MAKOR PROJECT – 1ST REVIEW

FPGA IMPLEMENTATION OF BOOTH

MULTIPLIER

PROJECT GUIDE BATCH-2

K Ashrith 1602-18-735-067
Mr. K Srikanth
Assistant Professor Ch Teja Sai 1602-18-735-113
JVS Avinash 1602-18-735-117

BATCH-2 PROJECT REVIEW | ECE | VCE | 2022

CONTENTS
⮚ LITERATURE SURVEY

⮚ WORKFLOW

⮚ VERILOG CODE

⮚ SIMULATION RESULTS

⮚ SCOPE FOR DEVELOPMENT

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Literature Survey
D.Govekar, Ameeta Amonkar Booth Multiplier with Hybrid Adder Area reduced by 4.8%
IEEE Delay reduced by 3.71%

Elisardo antelo Pipeline based array height reduction in Power reduction by 4%

partial product column. But huge circuitry and complex
implementation

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 WORKFLOW

Bitfile/Cycle
Verilog/ Map/ Level
Synthesize Netlist Place/ Simulation &
VHDL
Route Constraint File

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VERILOG CODE
`define width 4 always @ (x or y or inv_x)
begin
`timescale 1ns/1ps cc[0] = {y[1],y[0],1'b0};
module test_1 (p, x, y); for(kk=1;kk<N;kk=kk+1)
parameter width=`width; cc[kk] = {y[2*kk+1],y[2*kk],y[2*kk-1]};
for(kk=0;kk<N;kk=kk+1)
parameter N = `width/2; begin
input[width-1:0]x, y; case(cc[kk])
3'b001 , 3'b010 : pp[kk] = {x[width-1],x};
output[width+width-1:0]p; 3'b011 : pp[kk] = {x,1'b0};
reg [2:0] cc[N-1:0]; 3'b100 : pp[kk] = {inv_x[width-1:0],1'b0};
reg [width:0] pp[N-1:0]; 3'b101 , 3'b110 : pp[kk] = inv_x;
default : pp[kk] = 0;
reg [width+width-1:0] spp[N-1:0]; endcase
reg [width+width-1:0] prod; spp[kk] = $signed(pp[kk]);
for(ii=0;ii<kk;ii=ii+1)
wire [width:0] inv_x; spp[kk] = {spp[kk],2'b00}; //multiply by 2 to the power x or
integer kk,ii; shifting operation
assign inv_x = {~x[width-1],~x}+1; //2’s end //for(kk=0;kk<N;kk=kk+1)
prod = spp[0];
complement for(kk=1;kk<N;kk=kk+1)
prod = prod + spp[kk];
end
assign p = prod;
endmodule

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RESULTS - SIMULATION

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RESULTS – RTL SCHEMATIC

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BATCH-2 PROJECT REVIEW | ECE | VCE | 2022
RESULTS - SYNTHESIS

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BATCH-2 PROJECT REVIEW | ECE | VCE | 2022
BATCH-2 PROJECT REVIEW | ECE | VCE | 2022
RESULTS - IMPLEMENTAION

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BATCH-2 PROJECT REVIEW | ECE | VCE | 2022
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BATCH-2 PROJECT REVIEW | ECE | VCE | 2022
COMPARISION

Device utilization Radix-2 Radix-4

Number of Slices 52 15

Number of bonded IO 16 16

Power and Timing

Total On-Chip Power 20.98W 16.728W

Minimum Period 5.454ns 4.750ns

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Scope for Development

• Summation with different adders

Parameter Carry Look Ahead Adder Carry Save Adder

Delay 3.1ns 2.924

Gate Count 272 576

Power 0.312mW 1.082mW

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REFERENCES

• Ahmed Salman Tariq, Ruhul Amin, Md. Nazrul Islam Mondal, Md. Ali Hossain,
“Faster Implementation of Booth’s Algorithm Using FPGA” IEEE Xplore, IAN :
16757387

• Antonius Irianto Sukowati, Hendri Dwi Putra, Eri Prasetyo Wibowo , “Usage Area
and Speed Performance Analysis of Booth Multiplier on Its FPGA Implementation ”,
IEEE Xplore, IAN: 16836005

• Sukhmeet Kaur, Suman and Manpreet Singh Manna, “Implementation of Modified

Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2”,
Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 3,
Number 6 (2013), pp. 683-690
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