Department of EIE, KITSW U18CI 605 VLSI SYSTEM DESIGN

6ECI AY:2021-22
CDT21_LECTURE SUMMARY

CDT21 1. Scaling of MOS circuits

UNIT-1II
Topics Covered
VLSI fabrication technology is still in the process of evolution which is leading
Motivation
to smaller line widths and feature size and to higher packing density of circuitry
(Why you on a chip. The scaling down of feature size generally leads to improved
(students) should performance and it is important therefore to understand the effects of scaling.
learn these topics? )
There are also future limits to scaling down which may well be reached in the
next decade
Lecture Learning Outcomes (LLOs): After completion of this lecture, you should be able to…
LLO1
On topic
Calculate scaling factors for various device parameters
1

CDT21 – Lecture Summary – Key Takeaways

SCALING FACTORS FOR DEVICE PARAMETERS:

Gate Area Ag
Ag = L.W.
where L and Ware the channel length and width respectively. Both are scaled by 1/α. Thus Ag
is scaled by l/α2

Gate capacitance Per Unit Area Co or Cox

C = εox/D
where εox is the permittivity of the gate oxide (thinox) [=εins εo] and D is the gate oxide
thickness which is scaled by 1/β
Thus Cg is scaled by β( l/α2)= β /α2

Parasitic Capacitance Cx
Cx is proportional to Ax/d
where d is the depletion width around source or drain which is scaled by 1/ α, and Ax is the
area of the depletion region around source or drain which is scaled by 1/α 2.
Thus Cx is scaled by (1/α 2)/ (1/α)= 1/α

Prepared by: Prof. K.Sivani, Dept of EIE, KITSW Page 1 of 4

Department of EIE, KITSW U18CI 605 VLSI SYSTEM DESIGN
6ECI AY:2021-22
CDT21_LECTURE SUMMARY
Carrier Density in Channel Qon
Qon= Co.Vgs
where Qon is the average charge per unit area in the channel in the 'on' state. Note that C0 is
scaled by β and Vgs is scaled by 1/β
Thus-Qon is scaled by 1

Channel Resistance Ron

Gate Delay Td

Maximum Operating Frequency fo

Saturation Current Idss

Prepared by: Prof. K.Sivani, Dept of EIE, KITSW Page 2 of 4

Department of EIE, KITSW U18CI 605 VLSI SYSTEM DESIGN
6ECI AY:2021-22
CDT21_LECTURE SUMMARY
Current Density J

Switching Energy Per Gate Eg

Power Dissipation Per Gate Pg

Power-speed Product PT

Power Dissipation Per Unit Area Pa

Pa= Pg/Ag

Prepared by: Prof. K.Sivani, Dept of EIE, KITSW Page 3 of 4

Department of EIE, KITSW U18CI 605 VLSI SYSTEM DESIGN
6ECI AY:2021-22
CDT21_LECTURE SUMMARY

Prepared by: Prof. K.Sivani, Dept of EIE, KITSW Page 4 of 4