ESP32

Hardware Design Guidelines

Version 3.3
Espressif Systems
Copyright © 2022

www.espressif.com
About This Document
The guidelines outline recommended design practices when developing standalone or add-on systems based on
the ESP32 series of products, including ESP32 SoCs, ESP32 modules and ESP32 development boards.

Document Updates
Please always refer to the latest version on https://www.espressif.com/en/support/download/documents.

Revision History
For the revision history of this document, please refer to the last page.

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Contents

1 Overview 1

2 Schematic Checklist 2
2.1 Power Supply 3
2.1.1 Digital Power Supply 3
2.1.2 Analog Power Supply 5
2.1.3 RTC Power Supply 6
2.2 Power-on Sequence and System Reset 7
2.2.1 Power-on Sequence 7
2.2.2 Reset 8
2.3 Flash (compulsory) and SRAM (optional) 8
2.3.1 SiP Flash and SiP PSRAM 8
2.3.2 External Flash and External RAM 9
2.4 Clock Source 9
2.4.1 External Clock Source (compulsory) 9
2.4.2 RTC (optional) 10
2.5 RF 11
2.6 ADC 11
2.7 External Capacitor 12
2.8 UART 12
2.9 SDIO 13
2.10 Touch Sensor 13

3 PCB Layout Design 14

3.1 Standalone ESP32 Module 14
3.1.1 General Principles of PCB Layout 14
3.1.2 Positioning an ESP32 Module on a Base Board 15
3.1.3 Power Supply 16
3.1.4 Crystal Oscillator 18
3.1.5 RF 19
3.1.6 Flash & PSRAM 20
3.1.7 External RC 20
3.1.8 UART 20
3.1.9 Touch Sensor 21
3.2 ESP32 as a Slave Device 23
3.3 Typical Layout Problems and Solutions 24
3.3.1 Q: The current ripple is not large, but the TX performance of RF is rather poor. 24
3.3.2 Q: The power ripple is small, but RF TX performance is poor. 25
3.3.3 Q: When ESP32 sends data packages, the power value is much higher or lower than the target
power value, and the EVM is relatively poor. 25
3.3.4 Q: TX performance is not bad, but the RX sensitivity is low. 25

4 Hardware Development 26
5 Applications 27
5.1 ESP32 Smart Audio Platform 27
5.1.1 ESP32-LyraT Audio Development Board 27
5.1.2 ESP32-LyraTD-MSC Audio Development Board 28
5.2 ESP32 Touch Sensor Application—ESP32-Sense Kit 29
5.3 ESP-Mesh Application—ESP32-MeshKit 30

Revision History 31
List of Figures
1 ESP32 Schematics 2
2 Schematic for Quad 3.3 V SiP Flash 3
3 Schematic for 1.8 V VDD_SDIO Power Supply Pin 4
4 Schematic for 3.3 V VDD_SDIO Power Supply Pin 4
5 Schematic for VDD_SDIO Pin Powered by External Supply 5
6 ESP32 Analog Power Supply Pins 6
7 ESP32 RTC Power Supply 7
8 ESP32 Power-up and Reset Timing 7
9 ESP32 Crystal Oscillator 10
10 Schematic for ESP32’s External Crystal (RTC) 10
11 Schematic of External Oscillator 11
12 ESP32 RF Matching Schematics 11
13 ESP32 External Capacitor 12
14 ESP32 UART 13
15 ESP32 PCB Layout 14
16 ESP32 Module Antenna Position on Base Board 15
17 Keepout Zone for ESP32 Module’s Antenna on the Base Board 16
18 ESP32 Power Traces in a Four-layer PCB Design 17
19 Nine-Grid Design for EPAD 17
20 ESP32 Power Traces in a Two-layer PCB Design 18
21 ESP32 Crystal Oscillator Layout 19
22 ESP32 RF Layout in a Four-layer PCB Design 20
23 ESP32 RF Layout in a Two-layer PCB Design 20
24 ESP32 Flash and PSRAM Layout 21
25 ESP32 UART Design 21
26 A Typical Touch Sensor Application 22
27 Electrode Pattern Requirements 22
28 Sensor Track Routing Requirements 23
29 PAD/TV Box Layout 24
30 Top View of ESP32-LyraT 27
31 Bottom View of ESP32-LyraT 28
32 ESP32-LyraTD-MSC 29
33 ESP32-Sense Kit 29
34 ESP32-MeshKit-Light � 30
35 ESP32-MeshKit-Sense Development Board 30
1. OVERVIEW

1. Overview
ESP32 is a single 2.4 GHz Wi-Fi and Bluetooth combo chip designed with TSMC low-power 40 nm technology. It
is designed to achieve the best power and RF performance, robustness, versatility, and reliability in a wide variety
of applications and different power profiles.

ESP32 is a highly-integrated solution for Wi-Fi + Bluetooth applications in the IoT industry with around 20 external
components. ESP32 integrates the antenna switch, RF balun, power amplifier, low noise receive amplifier, filters,
and power management modules. As such, the entire solution occupies minimal Printed Circuit Board (PCB)
area.

ESP32 uses CMOS for single-chip fully-integrated radio and baseband, and also integrates advanced calibration
circuitries that allow the solution to dynamically adjust itself to remove external circuit imperfections or adjust to
changes in external conditions. As such, the mass production of ESP32 solutions does not require expensive and
specialized Wi-Fi test equipment.

The ESP32 series of chips includes ESP32-D0WD-V3, ESP32-D0WDR2-V3, ESP32-U4WDH, ESP32-S0WD (Not
Recommended For New Designs), ESP32-D0WD (Not Recommended For New Designs), ESP32-D0WDQ6 (Not
Recommended For New Designs), and ESP32-D0WDQ6-V3 (Not Recommended For New Designs), among
which, ESP32-D0WD-V3, ESP32-D0WDR2-V3, ESP32-U4WDH, and ESP32-D0WDQ6-V3 (Not Recommended
For New Designs), are based on chip revision v3.0 or v3.1.

For details of part number and ordering information, please refer to ESP32 Series Datasheet.

For details on chip revision v3.0 instructions, please refer to ESP32 Chip Revision v3.0 User Guide.

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2. SCHEMATIC CHECKLIST

4 3 2

2. Schematic Checklist
ESP32’s integrated circuitry requires only 20 resistors, capacitors and inductors, one crystal and one SPI flash
chip.

To better ensure the performance of ESP32, this chapter details ESP32 schematics design. ESP32 schematic is
shown in Figure 1.

GND
The values of C1 and C2 vary with GND GND
the selection of the crystal.

3
U1
The value of R2 varies with the actual C1 C2

GND

GND XOUT
PCB board. The initial value could be
TBD TBD
VDD33 0 ohm.

XIN
1

2
C3 C20

100pF 1uF GND

VDD33
TBD
40MHz(±10ppm)
GND
GND GND R1 20K(5%)

C9 C5 C6 GPIO21
R2

R3 499 U0TXD
0.1uF 10nF/6.3V(10%) 3.3nF/6.3V(10%) U0RXD
GPIO22
VDD33
GND
GND VDD_SDIO
L5 2.0nH
49

48
47
46
45
44
43
42
41
40
39

GND

8
C13 C11 C10 C21
VDDA
GND

CAP1
CAP2

XTAL_P

VDDA
XTAL_N

GPIO21
U0TXD
U0RXD
GPIO22

VDD
10uF 1uF 0.1uF NC C4 SCS/CMD 1 5 SDI/SD1
VDD33 /CS DI
0.1uF SCK/CLK 6 2 SDO/SD0
GND CLK DO
GND GND GND
ANT1 1 38 GPIO19 SHD/SD2 7 3 SWP/SD3

GND
1 RF_ANT L4 TBD LNA_IN 2 VDDA GPIO19 37 /HOLD /WP
2 3 LNA_IN VDD3P3_CPU 36 GPIO23
4 VDD3P3 GPIO23 35 GPIO18 U3 FLASH-3V3
C15 C14

4
PCB_ANT SENSOR_VP 5 VDD3P3 GPIO18 34 GPIO5
TBD TBD 6 SENSOR_VP GPIO5 33 SDI/SD1
7 SENSOR_CAPP SD_DATA_1 32 SDO/SD0 GND
SENSOR_VN 8 SENSOR_CAPN SD_DATA_0 31 SCK/CLK
EN 9 SENSOR_VN SD_CLK 30 SCS/CMD
GND GND GND
GPIO34 10 CHIP_PU SD_CMD 29 SWP/SD3 VDD_SDIO
GPIO35 11 VDET_1 SD_DATA_3 28 SHD/SD2
GPIO32 12 VDET_2 SD_DATA_2 27 GPIO17 VDD_SDIO
GPIO33 13 32K_XP GPIO17 26 R10
VDD3P3_RTC

GPIO25 14 32K_XN VDD_SDIO 25 GPIO16

GPIO25 GPIO16

8
The values of C15, L4 and C14 10K
GPIO26
GPIO27

vary with the actual PCB board.

VDD
GPIO2
GPIO0
GPIO4
MTMS

MTDO
MTCK

GPIO16 1 5 SDI/SD1
MTDI

VDD_SDIO CS SI/SIO0
NC: No component. R4 C24
PSRAM_CLK* 6 2 SDO/SD0
U2 ESP32 2K(NC) 1uF SCLK SO/SIO1
15
16
17
18
19
20
21
22
23
24

SHD/SD2 7 3 SWP/SD3

VSS
VDD33 SIO3 SIO2
GND GND
VDD33 R9 10K(NC) U4 PSRAM-3V3 (Optional)

4
C19
GPIO26
GPIO27
GPIO14
GPIO12

GPIO13
GPIO15
GPIO2
GPIO0
GPIO4

GND
0.1uF

PSRAM_CLK: SCK/CLK or GPIO17

GND

Figure 1: ESP32 Schematics

Notice:

• Figure 1 shows the connection for quad 3.3 V external flash/PSRAM. PSRAM CLK is from SCK/CLK or GPIO17.

• In cases when quad 1.8 V external flash/PSRAM is used, R9 should be populated.

• In cases when quad 3.3 V SiP PSRAM (such as ESP32-D0WDR2-V3) or an external flash is used, PSRAM CLK is
from SCK/CLK. See Figure 1.

• In cases when quad 3.3 V SiP flash (such as ESP32-U4WDH) is used, please refer to Figure 2 for its core schematic.

Title

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C
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XTAL_P
XTAL_N
VDDA
GPIO21
U0TXD
U0RXD
GPIO22
C4
2. SCHEMATIC CHECKLIST VDD33
0.1uF

38 GPIO19
GPIO19 37
VDD3P3_CPU 36 GPIO23 VDD_SDIO
GPIO23 35 GPIO18
GPIO18 34 GPIO5
GPIO5

8
33 SDI/SD1
SD_DATA_1 32 SDO/SD0

VDD
SD_DATA_0 31 SCK/CLK GPIO16 1 5 SDI/SD1
SD_CLK 30 SCS/CMD /CS DI
SD_CMD 29 SWP/SD3 SCK/CLK 6 2 GPIO17
SD_DATA_3 28 SHD/SD2 CLK DO
SD_DATA_2 27 GPIO17 SCS/CMD 7 3 SDO/SD0

GND
GPIO17 26 /HOLD /WP
VDD3P3_RTC

VDD_SDIO 25 GPIO16
GPIO16 U3 FLASH-3V3

4
GPIO2
GPIO0
GPIO4
MTDO
MTCK

C24
MTDI

VDD_SDIO GND
0.1uF
ESP32
19
20
21
22
23
24

VDD33
GND

C19
GPIO13
GPIO15
GPIO2
GPIO0
GPIO4

0.1uF

GND

Figure 2: Schematic for Quad 3.3 V SiP Flash

Any basic ESP32 circuit design may be broken down into 10 major sections:

• Power supply

• Power-on sequence and system reset

• Flash (compulsory) and SRAM (optional)

• Clock sources

• RF

• External capacitors

• ADC
Title
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• UART
Size Document Number
• SDIO A3 <Doc>

Date: Thursday, July 0

• Touch3Sensor 2

2.1 Power Supply

For further details of using the power supply pins, please refer to Section Power Scheme in ESP32 Series Datasheet.

2.1.1 Digital Power Supply

ESP32 has pin37 VDD3P3_CPU that supplies power for CPU IO, in a voltage range of 1.8 V ~ 3.6 V. It is recom-
mended to add an extra 0.1 µF decoupling capacitor close to this digital power supply pin.

Pin26 VDD_SDIO can serve as the power sullpy for the external device at either 1.8 V if GPIO12 is pulled high
during boot, or at 3.3 V if GPIO12 is pulled low during boot. By default, GPIO12 is pulled low.

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 GND GPIO22
stal.
GND

XTAL_P 44 4

U0TXD 40 3
ND U14
Hwith 2. SCHEMATIC CHECKLIST
the actual

49

48
CAP1 47
CAP2 46
VDDA 45

XTAL_N 43
VDDA 42
GPIO21 41

39
C63 C64

GND

XOUT
GND
1
value could be

GND

U0RXD
GPIO22
TBD TBD
• When VDD_SDIO operates at 1.8 V, it’s powered by ESP32’s internal LDO.
C51 The maximum current this LDO

GND
XIN
VDD33
can offer is 40 mA, and the output voltage range is 1.65 V ~ 2.0 V. When the VDD_SDIO outputs 1.8 V, it
0.1uF
ND is recommended that users add a 2 kΩ ground resistor and a 4.7 µF ground capacitor close to VDD_SDIO.

2
1 38 GPIO19
D LNA_IN VDDA
See 2Figure 3. GPIO19 37
3 LNA_IN VDD3P3_CPU 36 GPIO23
4 VDD3P3 GPIO23 35 GPIO18 therefore,
0 • When VDD_SDIO operates at 3.3 V, it isGND
driven directly by VDD3P3_RTC through a 6 Ω resistor,
5 VDD3P3 GPIO18 34

TBD
SENSOR_VP 40MHz(±10ppm) GPIO5
D there6 willSENSOR_VP
GND be some voltage drop from VDD3P3_RTC.
SENSOR_CAPP
WhenGPIO5 33
SD_DATA_1
the VDD_SDIO outputs 3.3 V, it SDI/SD1
is recommended
7 R24 20K(5%) 32 SDO/SD0
SENSOR_CAPN SD_DATA_0
SENSOR_VNthat 8users add a 1 µF filter capacitor close to VDD_SDIO. See Figure 31 4. SCK/CLK
ND EN 9 SENSOR_VN SD_CLK 30 SCS/CMD
C68 10 C69
GPIO34VDD_SDIO CHIP_PU SD_CMD 29 GPIO21
SWP/SD3
can also be driven by an external power supply as shown in Figure 5. 499
GPIO35 11 VDET_1 R22 SD_DATA_3 28
R23 U0TXD
SHD/SD2
10nF/6.3V(10%)
GPIO32 VDET_2
12 3.3nF/6.3V(10%) SD_DATA_2 27 U0RXD
GPIO17
GPIO33 13 32K_XP GPIO17 26 GPIO22

20 VDD3P3_RTC
GPIO25
GND 14 32K_XN VDD_SDIO 25 GPIO16
GPIO25 GPIO16
16 GPIO26
17 GPIO27
49

48
CAP1 47
CAP2 46
VDDA 45
44
43
VDDA 42
41
40
39
GPIO2
GPIO0
GPIO4
MTMS

MTDO
MTCK
GND
MTDI

R4 C24 VDD_SDIO(1.8V)
GND

XTAL_P
XTAL_N

GPIO21
U0TXD
U0RXD
GPIO22

U2 ESP32 2K 4.7uF
15

18
19

21
22
23
24
C66
VDD33
VDD33
0.1uF
GND GND
R9 10K
1VDD33 38 GPIO19
NA_IN 2 VDDA GPIO19 37
C19
GPIO26
GPIO27
GPIO14
GPIO12

GPIO13
GPIO15

3 LNA_IN VDD3P3_CPU 36
GPIO2
GPIO0
GPIO4

GPIO23
4 VDD3P3 GPIO23 35 0.1uF GPIO18
ENSOR_VP 5 VDD3P3 GPIO18 34 GPIO5
6 SENSOR_VP GPIO5 33 SDI/SD1
7 SENSOR_CAPP SD_DATA_1 32 GND SDO/SD0
ENSOR_VN 8 SENSOR_CAPN SD_DATA_0 31 SCK/CLK
N 9 SENSOR_VN Figure 3: Schematic for 1.8 VSD_CLK
VDD_SDIO
30 Power Supply Pin SCS/CMD
PIO34 10 CHIP_PU SD_CMD 29 SWP/SD3
PIO35 11 VDET_1 SD_DATA_3 28 SHD/SD2
PIO32 12 VDET_2 SD_DATA_2 27 GPIO17
PIO33 13 32K_XP GPIO17 26 Title
VDD3P3_RTC

PIO25 14 32K_XN VDD_SDIO 25 GPIO16 <Title>

GPIO25 GPIO16
Size Document Number
GPIO26
GPIO27

A4 <Doc>
GPIO2
GPIO0
GPIO4
MTMS

MTDO
MTCK

C24
MTDI

VDD_SDIO(3.3V)
Date: Thursday, July 07,
4 3
1uF 2
U2 ESP32
15
16
17
18
19
20
21
22
23
24

GND VDD33

C19
GPIO26
GPIO27
GPIO14
GPIO12

GPIO13
GPIO15
GPIO2
GPIO0
GPIO4

0.1uF

GND

Figure 4: Schematic for 3.3 V VDD_SDIO Power Supply Pin

Title
<Title>

Size Document Number

A4 <Doc>

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 7 SENSOR_CAPP SD_DATA_1 32 SDO/SD0
ENSOR_VN 8 SENSOR_CAPN SD_DATA_0 31 SCK/CLK
SENSOR_VN SD_CLK
N 2. 9SCHEMATIC CHECKLIST 30 SCS/CMD
PIO34 10 CHIP_PU SD_CMD 29 SWP/SD3
PIO35 11 VDET_1 SD_DATA_3 28 SHD/SD2
PIO32 12 VDET_2 SD_DATA_2 27 GPIO17
PIO33 13 32K_XP GPIO17 26

VDD3P3_RTC
PIO25 14 32K_XN VDD_SDIO 25 GPIO16
GPIO25 GPIO16

GPIO26
GPIO27

GPIO2
GPIO0
GPIO4
MTMS

MTDO
MTCK
C24

MTDI
VDD33
1uF
U2 ESP32

15
16
17
18
19
20
21
22
23
24
GND VDD33

C19
GPIO26
GPIO27
GPIO14
GPIO12

GPIO13
GPIO15
GPIO2
GPIO0
GPIO4
0.1uF

GND

Figure 5: Schematic for VDD_SDIO Pin Powered by External Supply

Title
<Title>
Notice:
Size the supply
When using VDD_SDIO as the power supply pin for the external 3.3 V flash/PSRAM, Document
voltageNumber
should be 3.0 V
A4 <Doc>
or above, so as to meet the requirements of flash/PSRAM’s working voltage.
Date: Thursday, July 07, 2022 She
3 2

2.1.2 Analog Power Supply

Pin1 VDDA, pin3 VDD3P3, pin4 VDD3P3, pin43 VDDA and pin46 VDDA are the analog power supply pins, working
at 2.3 V ~ 3.6 V.

It should be noted that the sudden increase in current draw, when ESP32 is in transmission mode, may cause a
power rail collapse. Therefore, it is highly recommended to add another 10 µF capacitor to the power trace, which
can work in conjunction with the 0.1 µF capacitor. LC filter circuit needs to be added near VDD3P3 pins so as to
suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and above. Refer to Figure
6 and place the appropriate decoupling capacitor near the other analog power pins.

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 U1

GND
2. SCHEMATIC CHECKLIST
C1
TBD

XIN
VDD33

2
C3 C20
GND
100pF 1uF R1 20K(5%)
R2 GND
GND GND C5 C6 0R 40MHz+/-10p
VDD33
10nF/6.3V(10%) 3.3nF/6.3V(10%) R3
C9
GND
0.1uF

49

48
47
46
45
44
43
42
41
40
39
VDD33 GND
L5 2.0nH

GND

CAP1
CAP2
VDDA
XTAL_P

VDDA
GPIO21
XTAL_N

U0TXD
U0RXD
GPIO22
C13 C12 C11 C10 C21
10uF NC 1uF 0.1uF NC

GND GND GND GND GND

ANT1 1
1 L4 TBD 2 VDDA
2 3 LNA_IN
C15 C14 C16 4 VDD3P3
PCB ANT SENSOR_VP 5 VDD3P3
TBD TBD 270pF(NC) 6 SENSOR_VP
SENSOR_CAPP
7 Pins
Figure 6: ESP32 Analog Power Supply
270pF(NC) SENSOR_VN8 SENSOR_CAPN
GND GND GND CHIP_PU 9 SENSOR_VN
C17 GPIO34 10 CHIP_PU
2.1.3 RTC Power Supply GPIO35 11 VDET_1
GPIO32 12 VDET_2
Pin19 VDD3P3_RTC of ESP32 is RTC and analog power GPIO33 13 32K_XP
pin. It is recommended to place a 0.1 µF decoupling

VDD3P3_RTC
GPIO25 14 32K_XN
capacitor near this power pin in the circuit. This power supply can not be used as a backup power since it is not
GPIO25
only for the RTC part.

GPIO26
GPIO27

GPIO2
GPIO0
GPIO4
MTMS

MTDO
MTCK
MTDI
U2
15
16
17
18
19
20
21
22
23
24
GPIO26
GPIO27
GPIO14
GPIO12

GPIO13
GPIO15
GPIO2
GPIO0
GPIO4

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 SD_CLK 30 SCS/CMD
SD_CMD 29 SWP/SD3
2. SCHEMATIC CHECKLIST
SD_DATA_3 28 SHD/SD2
SD_DATA_2 27 GPIO17
GPIO17 26
VDD3P3_RTC VDD_SDIO 25 GPIO16
GPIO16
GPIO26
GPIO27

GPIO2
GPIO0
GPIO4
MTDO
MTMS

MTCK
MTDI

R4 C24 VDD_SDIO

ESP32 2K(NC) 1uF

15
16
17
18
19
20
21
22
23
24

VDD33
GND GND
C)

C19
GPIO26
GPIO27
GPIO14
GPIO12

GPIO13
GPIO15
GPIO2
GPIO0
GPIO4

0.1uF

GND

Figure 7: ESP32 RTC Power Supply

Notice:

• When use the single power supply, the recommended power supply voltage for ESP32 is 3.3 V and the output
current should be no less than 500 mA.

• It is suggested that users add an ESD protection diode at the power entrance.

2.2 Power-on Sequence and System Reset

2.2.1 Power-on Sequence
ESP32 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized. This
is achieved by delaying the activation of CHIP_PU after the 3.3 V rails have been brought up.

Figure 8 shows the power-up and reset timing of ESP32. Details about the parameters are listed in Table 1.

t0 t1

VDD3P3_RTC Min

VDD

VIL_nRST
CHIP_PU

Figure 8: ESP32 Power-up and Reset Timing

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2. SCHEMATIC CHECKLIST

Table 1: Description of ESP32 Power-up and Reset Timing Parameters

Parameter Description Min (µs)

t0 Time between the 3.3 V rails being brought up and CHIP_PU being activated 50
t1 Duration of CHIP_PU signal level < VIL_nRST 50

Notice:
To ensure that stable power is supplied to the ESP32 chip during power-up, it is advised to add an RC delay circuit at the
CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 µF. However, specific
parameters should be adjusted based on the power supply features and the power-up timing and reset sequence timing
of the chip.

2.2.2 Reset
CHIP_PU serves as the reset pin of ESP32. The input level (VIL_nRST ) for resetting the chip should be no more than
0.6 V and remain at least 50 µs. More details can be found in Section Power Scheme in ESP32 Series Datasheet.
To avoid reboots caused by external interferences, the CHIP_PU trace should be as short as possible. A pull-up
resistor and a ground capacitor are highly recommended.

Notice:
CHIP_PU pin must not be left floating.

2.3 Flash (compulsory) and SRAM (optional)

ESP32 requires SiP flash or external flash to store application firmware and data. SiP PSRAM or external RAM is
optional.

2.3.1 SiP Flash and SiP PSRAM

SiP (System-in-Package) flash and SiP PSRAM refer to the flash and PSRAM that are integrated into the package,
depending on a chip variant. For the pin-to-pin mapping between the chip and SiP flash/PSRAM, please refer to
Table 2. The chip pins listed here are not recommended for other usage.

Table 2: Pin-to-Pin Mapping Between Chip and SiP Flash/PSRAM

ESP32-U4WDH SiP Flash (4 MB)

SD_DATA_1 IO0/DI
GPIO17 IO1/DO
SD_DATA_0 IO2/WP#
SD_CMD IO3/HOLD#
SD_CLK CLK
GPIO16 CS#
GND VSS
VDD_SDIO VDD
ESP32-D0WDR2-V3 SiP PSRAM (2 MB)
SD_DATA_1 SIO0/SI

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2. SCHEMATIC CHECKLIST

SD_DATA_0 SIO1/SO
SD_DATA_3 SIO2
SD_DATA_2 SIO3
SD_CLK SCLK
*
GPIO16 CE#
GND VSS
VDD_SDIO VDD

2.3.2 External Flash and External RAM

ESP32 can support up to 16 MB external flash and 8 MB external RAM. Make sure to select appropriate external
flash and RAM according to the power voltage on VDD_SDIO. It is recommended to add a 0 Ω series resistor on
the SPI communication lines to lower the driving current, reduce interference to RF, adjust timing, and better shield
from interference.

The ESP32 schematics for the external quad flash/PSRAM is shown in Figure 1.

Note:
For the supported flash chips, see Section SPI Flash API in ESP-IDF Programming Guide.

2.4 Clock Source

There are two clock sources for the ESP32, that is, an external crystal oscillator clock source and an RTC clock
source.

2.4.1 External Clock Source (compulsory)

Currently, the ESP32 Wi-Fi/Bluetooth firmware only supports 40 MHz crystal oscillator. In circuit design, capacitors
C1 and C2 which connect to the ground are added to the input and output terminals of the crystal oscillator
respectively. The specific capacitive values depend on further testing of, and adjustment to, the overall performance
of the whole circuit. It is recommended that users reserve a series resistor of 0 Ω on the XTAL_P clock trace to
reduce the drive strength of the crystal, as well as to minimize the impact of crystal harmonics on RF performance.
Note that the accuracy of the selected crystal is ±10 ppm. The schematic for crystal oscillator is shown in Figure
9.

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 pacitance of C1 and C2 varies
he selection of the crystal.
R1
N

2
1

3
3
R_VN
R_CAPN
R_CAPP
R_VP

6
3nF/6.3V(10%)
U
2. SCHEMATIC CHECKLIST

20K(5%)
48
5 CAP1 47 4
CAP2

TBD
46

C1
VDDA

GND
45
XTAL_P 44

0R 40MHz+/-10ppm
R2
RTC XTAL_N 43
VDDA

GND
42 1 4
GPIO21 41 XIN GND
U0TXD 40

U1
U0RXD

R3
39
GPIO22

GND
2 3
GND XOUT
VDD3P3_CPU
SD_DATA_2
SD_DATA_3

SD_DATA_0
SD_DATA_1
VDD_SDIO

499R

GND
SD_CMD
SD_CLK
GPIO16

GPIO17

GPIO18
GPIO23

GPIO19
GPIO5

TBD
C2
IPEX: C15=2.2pF,L4=1.2nH,C14=3.0pF,R2=51R(5%)
GND
PCB ANT: Figure 9: ESP32
C15=2.4pF,L4=2.0nH,C14=3.3pF,R2=51R(5%) Crystal Oscillator
25
26
27
28
29
30
31
32
33
34
35
36
37
38

0.1uF

3
GND U1 GND
C4

GND

GND XOUT
GND

Notice:
C1 C2
• If an oscillator is used, its output should be connected to XTAL_P on the chip through a DC blocking capacitor
GPIO16

GPIO17
SHD/SD2
SWP/SD3
SCS/CMD
SCK/CLK
SDO/SD0
SDI/SD1
GPIO5
GPIO18
GPIO23

GPIO19

GPIO22
U0RXD
U0TXD
GPIO21

XIN
VDD33 22pF/6.3V(10%) 22pF/6.3V(10%)
(about 10 pF). XTAL_N can be floating. Please make sure that the oscillator output is stable and its accuracy is
VDD33

2
C3 C20
within ±10 ppm. The amplitude into XTAL_P can not exceed 1.1 V. It is also recommended that the circuit design
100pF/6.3V(10%) 1uF/10V(20%)
for the oscillator is compatible with the use of crystal, in case that if there is a defect in the circuit design,
R2
users can
VDD33 GND GND
GND GND R1 20K(5%) 51R(5%)
still use the crystal. 40MHz+/-10ppm
SHD/SD2

SCK/CLK

SCS/CMD

C9 C5 C6
• Defects in the craftsmanship of the crystal oscillators (for example, frequency deviation more than ±10 ppm) and R
0.1uF/6.3V(10%) 10nF/6.3V(10%) 3.3nF/6.3V(10%)
unstable operating temperature may lead to the malfunction of ESP32, resulting in a decrease of the overall per-
VDD33 GND GND
formance. L5 2.0nH(±0.1nH)
49

48
47
46
45
44
43
42
41
40
39
7

IPEX C12 C11 C10 C21 G

R14 0R(5%)/NC C13
1
GND

CAP1
CAP2
VDDA
XTAL_P

GPIO22
XTAL_N
VDDA
GPIO21
U0TXD
U0RXD
U3
/HOLD

CLK

/CS

10uF/6.3V(10%) NC 1uF/10V(20%) 0.1uF/6.3V(10%) NC

J39
VDD_SDIO
2

4 2.4.2
GND
RTC
8 (optional)
GND GND GND GND GND
GND VCC
ANT1 1 38
R15 0R(5%) L4 VDDA GPIO19
ESP3212 supports an external 32.768 kHz 2.0nH(±0.1nH)
crystal or an external 32.768 kHz23 signal
LNA_IN(e.g., an oscillator) to act asVDD3P3_CPU
the 37
FLASH

36
/WP

VDD3P3 GPIO23
DO

C15 C14 4 35
RTC sleep clock.
DI

PCB ANT SENSOR_VP 5 VDD3P3 GPIO18 34

2.4pF±0.25pF 3.3pF±0.25pF 6 SENSOR_VP GPIO5 33
7 SENSOR_CAPP SD_DATA_1 32
3

Figure 10 shows the schematic for the external

GND GND
32.768 kHz crystal.
SENSOR_VN 8 SENSOR_CAPN SD_DATA_0 31
GND CHIP_PU 9 SENSOR_VN SD_CLK 30
GPIO34 10 CHIP_PU SD_CMD 29
VDET_1 SD_DATA_3
SWP/SD3

SDO/SD0

SDI/SD1

C17 TBD GPIO35 11 28

GPIO32 12 VDET_2 SD_DATA_2 27
GND 32K_XP GPIO17
GPIO33 13 26
VDD3P3_RTC

GPIO25 14 32K_XN VDD_SDIO 25

GPIO25 GPIO16
R18
GPIO26
GPIO27
1

GPIO2
GPIO0
GPIO4
MTMS

MTDO
MTCK
MTDI

X1
32.768kHz
2

TBD U2 ESP32-D0WD
15
16
17
18
19
20
21
22
23
24

GND G
CON1

J28

CON1

J25

CON1

J22
CON1

J19

CON1

J16
CON1

J13
CON1

J10

CON1

J7
CON1

J4

CON1

J1

C18 TBD
GPIO26
GPIO27
GPIO14
GPIO12

GPIO13
GPIO15
GPIO2
GPIO0
GPIO4
1

Figure 10: Schematic for ESP32’s External Crystal (RTC) G

SENSOR_VN

SENSOR_VP

CHIP_PU

Notice:
GPIO25

GPIO33

GPIO32

GPIO35

GPIO34

ESD3.3V88D-LCDN
D1

• Please note the requirements for the 32.768 kHz crystal.

– Equivalent series resistance (ESR) ⩽ 70 kΩ.
VDD33

– Load capacitance at both ends should be configured according to the crystal’s specification.
GND

• The parallel resistor R18 is used for biasing the crystal circuit (5 MΩ < R18 ⩽ 10 MΩ).
CON1

J29

CON1

J26

CON1

J23
CON1

J20

CON1

J17
CON1

J14
CON1

J11

CON1

J8
CON1

J5

CON1

J2
1

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S

S
2. SCHEMATIC CHECKLIST

• When ESP32-D0WD-V3 connects to an external 32.768 kHz crystal, the parallel resistor must be populated. For
other ESP32 series chips, the resistor can be reserved.

• If the RTC source is not required, then pin12 (32K_XP) and pin13 (32K_XN) can be used as GPIOs.

Figure 11 shows the schematic of the external signal.

32K_XN
32768 kHz signal

ESP32

32K_XP
C1

Figure 11: Schematic of External Oscillator

The value of C1 should be larger than 200 pF. The signal should meet the following requirements:

32K_XN input Amplitude (Vpp, unit: V)

Sine wave or square wave 0.6 < Vpp < VDD

2.5 RF
The output impedance of the RF pins of ESP32 (QFN 6*6) and ESP32 (QFN 5*5) are (30+j10) Ω and (35+j10) Ω,
respectively. A π-type matching network is essential for antenna matching in the circuit design. CLC structure is
recommended for the matching network. The schematic for ESP32 RF circuitry is shown in Figure 12.

ANT1 1
1 L4 TBD 2 VDDA
2 3 LNA_IN
C15 C14 4 VDD3P3
C16
SENSOR_VP 5 VDD3P3
PCB ANT
TBD TBD 270pF(NC) 6 SENSOR_VP
7 SENSOR_CAPP
270pF(NC) SENSOR_VN8 SENSOR_CAPN
GND GND GND CHIP_PU 9 SENSOR_VN
C17 GPIO34 10 CHIP_PU
GPIO35 11 VDET_1
Figure 12: ESP32 RF Matching Schematics VDET_2
GPIO32 12

Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.

2.6 ADC
It is recommended that users add a 0.1 µF filter capacitor to a pad when using the ADC function.

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• Pins SENSOR_VP or SENSOR_VN will trigger an input glitch lasting for 80 ns once SARADC1, or SARADC2,
or Hall sensor is initialized.

• Pins SENSOR_VP or SENSOR_VN is recommended for use as ADC.

• If SENSOR_VP and SENSOR_VN are used as GPIOs, while ADC is supported by other pins in the circuit
design, users need to do settings in software to avoid the input glitch.

• ADC1 is recommended over ADC2 as the latter cannot be used when Wi-Fi function is enabled.

• Currently, high-precision ADCs are not supported. The two 270 pF sampling resistors between SENSOR_VP
and SENSOR_CAPP, SENSOR_VN and SENSOR_CAPN, can be removed. In such case, the four pins can
be used as general ADCs or GPIOs.

• The recommended input voltage of the ADC is below 2450 mV, and preferably within the range of 100 to
950 mV for higher calibration accuracy. For details, please refer to Section ADC in ESP32 Series Datasheet.

2.7 External Capacitor

Figure 13 shows the schematic of components connected to pin47 CAP2 and pin48 CAP1. C5 (10 nF) that
connects to CAP1 should be of 10% tolerance and is required for proper operation of ESP32. RC circuit between
CAP1 and CAP2 pins may be omitted under certain conditions. This circuit is used when entering Deep-sleep
mode. During this process, to minimize power consumption, the voltage to power ESP32 internals is dropped
from 1.1 V to around 0.7 V. The RC circuit is used to minimize the period of the voltage drop. If removed, this
process will take longer and the power consumption in Deep-sleep will be higher. If particular application of ESP32
is not using Deep-sleep mode, or power consumption is less critical, then this circuit is not required.

GND
R1 20K(5%)

C5 C6
10nF/6.3V(10%) 3.3nF/6.3V(10%)

GND
49

48
47
46
CAP1
CAP2
GND

VDDA

Figure 13: ESP32 External Capacitor

2.8 UART
Users need to connect a 499 Ω resistor to the U0TXD line in order to suppress the 80 MHz harmonics. The
schematic for ESP32 UART is shown in Figure 14.

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R3 499R U0TXD
U0RXD
GPIO22

41
40
39
GPIO21

GPIO22
U0TXD
U0RXD
Figure 14: ESP32 UART

2.9 SDIO
There are two sets of GPIOs (slot0 and slot1) that can be assigned to SDIO on ESP32, as shown in the table below.
When ESP32 works as an SDIO host or slave, connect GPIOs in slot1 to signal lines.

CMD CLK DAT0 DAT1 DAT2 DAT3 Note

Used to connect flash by default. Not
Slot0 GPIO11 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10
recommended for other use.
Multiplexed with JTAG, touch, EMAC,
Slot1 GPIO15 GPIO14 GPIO2 GPIO4 GPIO12 GPIO13
and strapping functions.

Note that when connecting GPIOs in slot1:

• When ESP32 works as SDIO host, add pull-up resistors on used pins, unused pins can be used for other
purposes.

• When ESP32 works as an SDIO slave, add pull-up resistors on all pins, whether these pins are used for SDIO
or not; unused pins cannot be used for other purposes.

For more information on SDIO configuration, please refer to API References.

2.10 Touch Sensor

When using the touch function, it is recommended to reserve a series resistor at the chip side to reduce the coupling
noise and interference on the line, and to strengthen the ESD protection. The recommended resistance is 470 Ω
~ 2 kΩ, preferably 510 Ω. The specific value also depends on the testing of the product.

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3. PCB Layout Design

This chapter introduces the key points of designing ESP32 PCB layout with the example of ESP32-WROOM-
32D.

While the high level of integration makes the PCB design and layout process simple, the performance of the system
strongly depends on system design aspects. To achieve the best overall system performance, please follow the
guidelines specified in this document for circuit design and PCB layout. All the common rules associated with
good PCB design still apply and this document is not an exhaustive list of good design practices.

The PCB layout design guidelines are applicable to cases when the

• ESP32 module functions as a standalone device, and when the

• ESP32 functions as a slave device.

The ESP32 PCB layout design is shown in Figure 15.

Figure 15: ESP32 PCB Layout

3.1 Standalone ESP32 Module

3.1.1 General Principles of PCB Layout
We recommend a four-layer PCB design.

• The first layer is the TOP layer for signal traces and components.

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3. PCB LAYOUT DESIGN

• The second layer is the GND layer without signal traces being routed so as to ensure a complete GND plane.

• The third layer is the POWER layer where a GND plane should be applied to better isolate the RF and crystal
oscillator part. It is acceptable to route signal traces on this layer, provided that there is a complete GND
plane under the RF and crystal oscillator.

• The fourth layer is the BOTTOM layer, where power traces are routed. Placing any components on this layer
is not recommended.

Below are the suggestions for a two-layer PCB design.

• The first layer is the TOP layer for traces and components.

• The second layer is the BOTTOM layer. Please do not place any components on this layer and keep traces
to a minimum. Ideally, it should be a complete GND plane.

3.1.2 Positioning an ESP32 Module on a Base Board

If users adopt on-board design, they should pay attention to the layout of the module on the base board. The inter-
ference of the base board on the module’s antenna performance should be reduced as much as possible.

The module should be placed as close to the edge of the base board as possible. The PCB antenna area should
be placed outside the base board whenever possible. In addition, the feed point of the antenna should be closest
to the board, as Figure 16 shows.

If there is base board under the antenna area, it is recommended to cut it off to minimize its impact on the antenna.
When designing the whole device, pay attention to the impact of the device shell on the antenna. As shown in
Figure 16, positions 3 and 4 are highly recommended on the base board, while positions 1, 2, and 5 are not
recommended.

1 2 3 ✅

Base Board

5 4 ✅

Figure 16: ESP32 Module Antenna Position on Base Board

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3. PCB LAYOUT DESIGN

If the positions recommended are not suitable, please make sure that the module is not covered by any metal
shell. The antenna area of the module and the area 15 mm outside the antenna should be kept clean, (namely no
copper, routing, components on it) as shown in Figure 17.

Clearance

15 mm

15 mm

15 mm
Base Board

Figure 17: Keepout Zone for ESP32 Module’s Antenna on the Base Board

3.1.3 Power Supply

• Four-layer PCB design

– Four-layer PCB design is recommended over two-layer design. Route the power traces on the fourth
(bottom) layer whenever possible. Vias are required for the power traces to go through the layers and
get connected to the pins on the top layer. There should be at least two vias where the main power
traces cross layers. The drill diameter on other power traces should be no smaller than the width of the
power traces.

– The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 18. The width of the main
power traces should be greater than 25 mil. The width of the power traces for pin3 and pin4 should be
at least 20 mil. The width of other power traces should be within the range of 12 ~ 15 mil.

– As shown in Figure 18, an ESD protection diode is placed close to the power port (marked in red circle).
A 10 µF capacitor is required before the power trace connects the ESP32 chip, to be used in conjunction
with a 0.1 µF capacitor. Then the power routing is divided into two ways. The power rails of pin3 and
pin4 should be routed together to reduce the coupling between different power pins.

– It is required to place C (capacitor) and L (inductor) near the power pins pin3 and pin4. As shown in
Figure 18, C13 (10 µF) is placed at the entrance of the power, and C10, L5, and C21 are placed near
the chip’s analog power pins. When possible, add a 0.1 µF capacitor to each digital power supply pin.
Note that all decoupling capacitors should be placed close to the power pin, and ground vias should
be added adjacent to the ground pin for the decoupling capacitors to ensure a short return path.

– The ground pad at the bottom of the chip should be connected to the ground plane through at least
nine ground vias.

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3. PCB LAYOUT DESIGN

Note:
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ
a nine-grid on the EPAD, cover the gaps with ink, and place ground vias in the gaps, as shown in Figure 19. This
can avoid tin leakage when soldering the module EPAD to the substrate.

Figure 18: ESP32 Power Traces in a Four-layer PCB Design

Figure 19: Nine-Grid Design for EPAD

• Two-layer PCB design

In a two-layer PCB design, the 3.3 V power traces are routed as shown labelled with VDD33 in Figure 20.
In contrast to the design practices for a four-layer PCB design, the power traces in a two-layer PCB design
should be routed on the top layer, thus requiring a reduced size of a thermal pad in the center of the chip.
Route the power traces between the thermal pad and its surrounding signal pins. Employ vias only when the

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3. PCB LAYOUT DESIGN

power traces have to reach the bottom layer. The purpose of this practice is to maintain a complete ground
plane while reducing the surrounding area of the power traces.

Other good practices for routing power traces in four-layer PCB designs still apply to two-layer PCB designs.

Figure 20: ESP32 Power Traces in a Two-layer PCB Design

3.1.4 Crystal Oscillator

For design of the crystal oscillator section, please refer to Figure 21. In addition, the following should be noted:

• The crystal oscillator should be placed far from the clock pin. The recommended gap is 2.7 mm. It is good
practice to add high-density ground via stitching around the clock trace for containing the high-frequency
clock signal.

• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.

• When possible, the external regulating capacitor should be placed on the near left or right side of the crystal
oscillator, and at the end of the clock trace, to make sure the ground pad of the capacitor is close to that of
the crystal oscillator.

• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The vias on the power traces on both sides of the crystal clock trace
should be placed as far away from the clock trace as possible, and the two sides of the clock trace should
be surrounded by grounding copper.

• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example large inductance component, and ensure that there is a clean large-area
ground plane around the crystal oscillator.

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3. PCB LAYOUT DESIGN

Figure 21: ESP32 Crystal Oscillator Layout

3.1.5 RF
• Four-layer PCB design
In a four-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure 22. The characteristic
RF impedance must be 50 Ω. The ground plane on the adjacent layer needs to be complete. Make sure to
keep the width of the RF trace consistent, and do not branch the trace. The RF trace should be as short as
possible with dense ground via stitching around it for isolation.

However, there should be no vias for the RF trace. The RF trace should be routed at a 135° angle, or with
circular arcs if trace bends are required.

π-type matching circuitry should be reserved on the RF trace and placed close to the chip.

No high-frequency signal traces should be routed close to the RF trace. The RF antenna should be placed
away from high-frequency transmitting devices, such as crystal oscillators, DDR, and clocks (SDIO_CLK),
etc.

In addition, the USB port, USB-to-UART chip, UART signal lines (including traces, vias, test points, header
pins, etc.) must be as far away from the antenna as possible. It is good practice to add ground vias around
the UART signal line.

• Two-layer PCB design

In a two-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure 23. The width of the
RF trace should be greater than that of the RF trace in a four-layer board and is normally over 20 mil. The
actual width depends on the impedance formula where impedance-relevant parameters may vary depending
on the number of PCB layers.

Other good practices for routing RF traces in four-layer PCB designs still apply to two-layer board designs.

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3. PCB LAYOUT DESIGN

Figure 22: ESP32 RF Layout in a Four-layer PCB Design

Figure 23: ESP32 RF Layout in a Two-layer PCB Design

3.1.6 Flash & PSRAM

Route the SPI traces of the flash and PSRAM on the inner layer (e.g., the third layer) whenever possible. Add
ground vias around the clock and data traces of SPI separately. The layout of the flash and PSRAM on ESP32 is
shown in Figure 24.

3.1.7 External RC
External resistors and capacitors should be placed close to the chip pins, and there should be no vias around the
traces. Please ensure that 10 nF capacitors are placed close to the pins.

3.1.8 UART
The series resistor on the U0TXD line needs to be placed as close to the chip and away from the crystal oscillator
as possible. Figure 25 below shows an example of UART design.

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3. PCB LAYOUT DESIGN

Figure 24: ESP32 Flash and PSRAM Layout

Figure 25: ESP32 UART Design

3.1.9 Touch Sensor

ESP32 offers up to 10 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact or
proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows users to
use touch pads with smaller area to implement the touch detection function. Users can also use the touch panel
array to detect a larger area or more test points. Figure 26 depicts a typical touch sensor application.

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Figure 26: A Typical Touch Sensor Application

In order to prevent capacitive coupling and other electrical interference to the sensitivity of the touch sensor system,
the following factors should be taken into account.

Electrode Pattern

The proper size and shape of an electrode improves system sensitivity. Round, oval, or shapes similar to a hu-
man fingertip is commonly applied. Large size or irregular shape might lead to incorrect responses from nearby
electrodes.

Figure 27: Electrode Pattern Requirements

Note:
The examples illustrated in Figure 27 are not of actual scale. It is suggested that users use a human fingertip as reference.

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PCB Layout

The following are general guidelines to routing traces:

• The trace length should not exceed 300 mm.

• The trace width (W) can not be larger than 0.18 mm (7 mil).

• The alignment angle (R) should not be less than 90°.

• The trace-to-ground gap (S) should be in the range of 0.5 mm to 1 mm

• The electrode diameter (D) should be in the range of 8 mm to 15 mm.

• Hatched ground should be added around the electrodes and traces.

• The traces should be isolated well and routed away from the antenna.

Figure 28: Sensor Track Routing Requirements

Note:
For more details on the hardware design of ESP32 touch sensor, please refer to ESP32 Touch Sensor Application Note.

3.2 ESP32 as a Slave Device

When ESP32 works as a slave device in a system, the user needs to pay more attention to signal integrity in the
PCB design. It is important to keep ESP32 away from the interferences caused by the complexity of the system
and an increased number of high-frequency signals. We use the mainboard of a PAD or TV Box as an example
here to provide guidelines for the PCB layout and design.

The digital signals between the CPU and DDR are the main producers of the high-frequency noise that interferes
with Wi-Fi radio. Therefore, the following should be noted with regards to the PCB design.

• As can be seen in Figure 29, ESP32 should be placed near the edge of the PCB and away from the CPU
and DDR, the main high-frequency noise sources. The distance between the chip and the noise sources
decreases the interference and reduces the coupled noise.

• It is suggested that a series resistor be reserved on the six signal traces when ESP32 communicates with
the CPU via SDIO to decrease the drive current and any interference, and also to eliminate the sequencing
problem caused by the inconsistent length of the SDIO traces.

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Figure 29: PAD/TV Box Layout

• On-board PCB antenna is not recommended, as it receives much interference and coupling noise, both of
which impact the RF performance. We suggest that you use an external antenna which should be directed
away from the PCB board via a cable, in order to weaken the high frequency interference with Wi-Fi.

• The high-frequency signal traces between the CPU and associated memory should be routed strictly ac-
cording to the routing guidelines (please refer to the DDR trace routing guidelines). We recommend that you
add ground vias around the CLK traces separately, and around the parallel data or address buses.

• The GND of the Wi-Fi circuit and that of other high-power devices should be separated and connected
through wires if there are high-power components, such as motors, in the design.

• The antenna should be kept away from high-frequency noise sources, such as LCD, HDMI, Camera Sensor,
USB, etc.

3.3 Typical Layout Problems and Solutions

3.3.1 Q: The current ripple is not large, but the TX performance of RF is rather poor.
Analysis:

The current ripple has a strong impact on the RF TX performance. It should be noted that the ripple must be
tested when ESP32 is in the normal working mode. The ripple increases when the power gets high in a different
mode.

Generally, the peak-to-peak value of the ripple should be <80 mV when ESP32 sends MCS7@11n packets, and
<120 mV when ESP32 sends 11b/11m packets.

Solution:

Add a 10 µF filter capacitor to the branch of the power trace (the branch powering the ESP32 analog power
pin). The 10 µF capacitor should be as close to the analog power pin as possible for small and stable current
ripples.

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3.3.2 Q: The power ripple is small, but RF TX performance is poor.

Analysis:

The RF TX performance can be affected not only by power ripples, but also by the crystal oscillator itself. Poor
quality and big frequency offsets of the crystal oscillator decrease the RF TX performance. The crystal oscillator
clock may be corrupted by other interfering signals, such as high-speed output or input signals. In addition, high-
frequency signal traces, such as the SDIO trace and UART trace under the crystal oscillator, could also result in the
malfunction of the crystal oscillator. Besides, sensitive components or radiation components, such as inductors
and antennas, may also decrease the RF performance.

Solution:

This problem is caused by improper layout and can be solved by re-layout. Please see section 3 for details.

3.3.3 Q: When ESP32 sends data packages, the power value is much higher or lower
than the target power value, and the EVM is relatively poor.
Analysis:

The disparity between the tested value and the target value may be due to signal reflection caused by the impedance
mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance mismatch will
affect the working state of the internal PA, making the PA prematurely access the saturated region in an abnormal
way. The EVM becomes poor as the signal distortion happens.

Solution:

Match the antenna’s impedance with the reserved π-type circuit on the RF trace, so that impedance of the antenna
as seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.

3.3.4 Q: TX performance is not bad, but the RX sensitivity is low.

Analysis:

Good TX performance indicates proper RF impedance matching. External coupling to the antenna can affect the
RX performance. For instance, the crystal oscillator signal harmonics could couple to the antenna. If the TX and
RX traces of UART cross over with RF trace, then, they will affect the RX performance, as well. If ESP32 serves
as a slave device, there will be other high-frequency interference sources on the board, which may affect the Rx
performance.

Solution:

Keep the antenna away from crystal oscillators. Do not route high-frequency signal traces close to the RF trace.
High performance digital circuitry should be placed away from the RF block on large board designs. Please see
section 3 for details.

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4. HARDWARE DEVELOPMENT

4. Hardware Development
Espressif designs and manufactures a large variety of modules and boards to help users evaluate functionality of
the ESP32 family of chips.

For a list of the latest versions of ESP32 modules and development boards, please refer to ESP32 Modules and
Boards.

To review module reference designs please check Documentation section of Espressif website.

Notes on Using Modules

• The module uses one single pin as the power supply pin. Users can connect the module to a 3.3 V power
supply. The 3.3 V power supply works both for the analog circuit and the digital circuit.

• The EN pin is used for enabling the chip. Set the EN pin high for normal working mode. There is no RC
delay circuit on the module. It is recommended that users add an external RC delay circuit to the module.
For details please refer to Section 2.2.

• Lead the GND, RXD, TXD pins out and connect them to a USB-to-UART tool for firmware download, log-
printing and communication.

By default, the initial firmware has already been downloaded in the flash. If users need to re-download the firmware,
they should follow the steps below:

1. Set the module to UART Download mode by pulling IO0 (pulled up by default) and IO2 (pulled down by
default) low. The chip IOs are pulled down internally by default.

2. Power on the module and check through the serial terminal if the UART Download mode is enabled.

3. Download the firmware to flash, using the Flash Download Tool.

4. After downloading, pull IO0 high or just leave it floating and use the internal weak pull-up to enable the SPI
Boot mode.

5. Power on the module again. The chip will read and execute the firmware during initialization.

Notice:

• During the whole process, users can check the status of the chip with the log printed through UART. If the firmware
cannot be downloaded or executed, users can check if the working mode is normal during the chip initialization by
looking at the log.

• The serial tool cannot be used for both the log-print and flash-download tools simultaneously.

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5. APPLICATIONS

5. Applications

5.1 ESP32 Smart Audio Platform

5.1.1 ESP32-LyraT Audio Development Board
ESP32-LyraT is an open-source development board for Espressif Systems’ Audio Development Framework, ESP-ADF.
It is designed for smart speakers and smart-home applications. The dev board consists of the ESP32-WROVER/ESP32-
WROVER-B module, a Micro SD card, expansion interfaces, touch buttons and several function keys. It facilitates
the quick and easy development of dual-mode (Bluetooth + Wi-Fi) audio solutions , also supporting one-key
Wi-Fi configuration, a wake-up button, voice wake-up, voice recognition, cloud platform access, and an audio
player.

The ESP32-LyraT smart audio board has the following features:

• Various mainstream, both lossy and lossless, compressed audio formats, including M4A, AAC, FLAC, OGG,
OPUS, MP3, etc.

• One-key configuration and wake-up from the standby mode.

• SoftAP and Station mode.

• Various wireless protocols�Wi-Fi 802.11b/g/n, Classic Bluetooth and Bluetooth LE.

• A series of audio inputs, including Wi-Fi, Bluetooth-audio, DLNA, Line-in, etc.

• Bluetooth LE network configuration, and smart network configuration with apps, such as WeChat.

• Two microphones for the development of near-field and far-field voice recognition applications.

• Peripherals for differentiated demands.

Figure 30 and 31 show the top view and bottom view of ESP32-LyraT.

Figure 30: Top View of ESP32-LyraT

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5. APPLICATIONS

Figure 31: Bottom View of ESP32-LyraT

5.1.2 ESP32-LyraTD-MSC Audio Development Board

ESP32-LyraTD-MSC is designed for smart speakers and AI applications. This audio development board con-
sists of two parts: the upper board, which provides a three-microphone array, function keys and LED lights; and
the lower board, which integrates ESP32-WROVER-B, a MicroSemi Digital Signal Processing (DSP) chip, and
a power management module. ESP32-LyraTD-MSC facilitates the quick and easy development of dual-mode
(Bluetooth + Wi-Fi) audio solutions, as it supports one-key Wi-Fi network configuration, Acoustic Echo Cancel-
lation (AEC), near/far-field voice wake-up, cloud platform access, voice recognition, wake-up interrupt and audio
decoding.

The ESP32-LyraTD-MSC smart audio board has the following features:

• A lightweight, low-power and cost-effective smart audio solution.

• Access to multiple cloud platforms including DuerOS, Amazon, Tmall Genie, Turing, JD and iFLYTEK.

• HTTP live streaming, such as Internet radio and Ximalaya.

• Voice wake-up optimized with speech recognition and echo cancellation.

• Three digital MICs support far-field voice pick-up (from a distance of one to five meters).

• The dual-board design integrates an LED light strip and fully-functional buttons.

• Audio inputs over Wi-Fi, Bluetooth, DLNA, SD-Card.

• A variety of network configurations, such as Smartconfig, Bluetooth LE, and Air-kiss.

• Wi-Fi 802.11b/g/n, Classic Bluetooth and Bluetooth LE in the 2.4GHz band.

• Multiple audio formats including M4A, AAC, FLAC, OGG, OPUS, MP3, AMR.

ESP32-LyraTD-MSC’s layout is shown in Figure 32.

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5. APPLICATIONS

Figure 32: ESP32-LyraTD-MSC

Note:
Espressif provides design guidelines for audio products based on ESP32. For details please refer to
ESP32 Audio Design Guidelines.

5.2 ESP32 Touch Sensor Application—ESP32-Sense Kit

The ESP32 touch sensor development kit, ESP32-Sense Kit, is used for evaluating and developing ESP32 touch
sensor system. ESP32-Sense Kit consists of one motherboard and multiple daughterboards. The motherboard
contains a display unit, a main control unit and a debug unit. The daughterboards have touch electrodes in different
combinations or shapes, such as linear slider, wheel slider, matrix buttons and spring buttons, depending on the
application scenarios. Users can design and add their own daughterboards for special usage cases.

The following image shows the whole ESP32-Sense development kit.

Figure 33: ESP32-Sense Kit

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5. APPLICATIONS

5.3 ESP-Mesh Application—ESP32-MeshKit

ESP32-MeshKit is an all-in-one smart-light development kit, which is developed based on ESP-Mesh technology.
The development kit contains a number of ESP32-MeshKit-Lights and an ESP32-MeshKit-Sense board. ESP-
Mesh is developed upon ESP-MDF, Espressif Mesh Development Framework.

ESP32-MeshKit-Lights are smart lights besed on ESP-Mesh. Users can control the lights either with the ESP-Mesh
app, or the ESP32-MeshKit-Sense board that automatically switches on/off the lights by sensing the surrounding
temperature. ESP32-MeshKit-Lights also supports secondary development.

Figure 34 shows an ESP32-MeshKit-Light.

Figure 34: ESP32-MeshKit-Light �

ESP32-MeshKit-Sense is a development board with an ESP32 module at its core. It integrates a temperature and
humidity sensor and an ambient light sensor. The board can be connected to display screens. The integrated
sensors on the board can automatically switch on/off the ESP32-MeshKit-Lights by sensing the surrounding en-
vironment. Apart from smart lights, the development board can also form a mesh network with other devices.
In addition, the ESP32-MeshKit-Sense development board is a low-power sensing solution that can be used to
detect the current consumption of ESP32 modules in a normal operation state or in sleep mode, when connected
to different peripherals. Figure 35 shows an ESP32-MeshKit-Sense development board.

Figure 35: ESP32-MeshKit-Sense Development Board

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Revision History

Revision History

Date Version Release notes

Labelled ESP32-S0WD and ESP-D0WDQ6-V3 as (Not Recommended For New
Designs)
2022-10-13 v3.3
Updated Section 2.1, Section 2.2, and Section 2.3
Added Figure 2, Figure 3, Figure 4, Figure 5, Figure 8, and Table 1, Table 2
Removed ESP32-D2WD chip variant from this document
Labelled ESP32-DOWD and ESP-D0WDQ6 chip variants as (Not Recommended
For New Designs)
2021-08-09 v3.2
Updated R4 to R18 in Figure 10
Added a note below Figure 5
Updated Section 2.3
2021-04-30 V3.1 Added a note in Section 2.3 Flash (compulsory) and SRAM (optional)
Updated the C value of RC delay circuit in Section 2.2.1 from 0.1 µF to 1 µF
Added three chip variants ESP32-D0WD-V3, ESP32-D0WDQ6-V3, and ESP32-
U4WDH in Chapter 1
2020-09-25 V3.0 Added a note to EPAD in Chapter 3.1.3
Updated Chapter 2
Updated Chapter 4
Added documentation feedback link
Updated the note under Figure 16 about the recommended positions of ESP32 mod-
2019.10 V2.9
ules on the base board.
Changed the recommended minimum supply voltage of VDD_SDIO when powering
2019.09 V2.8
external 3.3 V flash/PSRAM to 3.0 V.
2019.04 V2.7 Updated Figure 10; added notes under the figure.
Added two-layer PCB design guidelines in Sections Power Supply and RF;
Updated Section UART;
2019.02 V2.6
Updated the modules supported on dev boards ESP32-LyraT and ESP32-LyraTD-
MSC according to the latest Espressif Product Ordering Information.
Updated Section Digital Power Supply: 2 kΩ resistor + 1 µF capacitor close to
2018.11 V2.5
VDD_SDIO when it outputs 1.8 V is changed to 2 kΩ resistor + 4.7 µF capacitor.
Updated Section 2.4.1: External Clock Source;
2018.09 V2.4
Updated Section 2.4.2: RTC.
2018.08 V2.3 Updated Section 2.7: External Capacitor.
Changed the official name of ESP-WROOM-32 into ESP32-WROOM-32;
Changed the official name of ESP-WROOM-32D into ESP32-WROOM-32D.
2018.07 V2.2
Updated Chapter 2: Schematic Checklist and PCB Layout Design;
Added new modules and applications based on ESP32.
Deleted sections introducing protocols, applications, block diagram and pin descrip-
tion of ESP32, for information of which please refer to ESP32 Series Datasheet;
Updated all figures and description of schematics and PCB layout in Chapter 2 ;
Added Section 2.6 ADC and 2.8 UART;

2018.03 V2.1
Espressif Systems 31 ESP32 Hardware Design Guidelines v3.3
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Revision History

Date Version Release notes

Updated Section 3, and added description about Positioning a ESP32 Module on a
Base Board in it.
Updated the value of current ripple in Section 3.3.1.
Updated Section ESP32-DevKitC Development Board.
Added Section ESP32-PICO-D4 Module.
Added Section ESP32-WROOM-32D Module.
Added Section ESP32-WROOM-32U Module.
Added Section ESP32-PICO-KIT Mini Development Kit.
Deleted orginal Section 2.1.6 ESP32-PICO-KIT Mini Development Kit.
Changed the transmitting power to +12 dBm; the sensitivity of NZIF receiver to -97
dBm in Section Bluetooth;
Added a note to Table Pin Description;
2017.08 V2.0 Added Section 3.1.9 Touch Sensor;
Updated Chapter 4 Hardware Development;
Updated Section 5.1.1.
Changed the input power supply range of CPU/RTC IO to 1.8V ~ 3.6V;
2017.06 V1.9
Updated Section 2.1.1 Digital Power Supply.
Updated Section 2.2.1 Power-on Sequence;
Updated Section 2.4.1 External Clock Source (Compulsory);
2017.06 V1.8
Added a link to ESP32 Pin Lists;
Added Documentation Change Notification.
2017.05 V1.7 Added a note to Section ESP32-WROOM-32 Overview.
Updated Figure ESP32-WROOM-32 Pin Layout;
2017.05 V1.6
Added a note in Section Strapping Pins.
2017.04 V1.5 Added the ESP-WROOOM-32 module’s dimensional tolerance.
Updated Section Strapping Pins;
Updated Figure ESP32 Pin Layout (for QFN 5*5);
2017.04 V1.4
Updated Figure ESP32-WROOM-32 Module;
Updated Figure ESP32-DevKitC Pin Layout.
Updated the notice to Table ESP32 Pin Description;
2017.03 V1.3
Added a note to Table ESP32-WROOM-32 Pin Definitions.
Updated Chapter Overview;
Updated Figure Function Block Diagram;
Updated Chapter Pin Definitions;
Updated Section Power Supply;
2017.03 V1.2
Updated Section RF;
Updated Figure ESP32-WROOM-32 Pin Layout;
Updated Table ESP32-WROOM-32 Pin Definitions;
Updated Section Notes.
2016.12 V1.1 Updated Table UART to Wi-Fi Smart Device.
2016.12 V1.0 First release.

Espressif Systems 32 ESP32 Hardware Design Guidelines v3.3

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INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
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