A560 A580 Quanta TWH DATWHMB18D0

5 4 3 2 1
TWH (15.6") Intel Huron River Platform Block Diagram 01

PCB 6L STACK UP PCB 8L STACK UP
D D
LAYER 1 : TOP LAYER 1 : TOP

VRAM DDR3 x 8
LAYER 2 : SGND LAYER 2 : SGND
Max 1GBs/2GBs LAYER 3 : IN1(High) LAYER 3 : IN1(High)
PAGE 19~20
LAYER 4 : IN2(Low) LAYER 4 : IN2(Low)
Intel Sandy Bridge
DDR3 SODIMM1 LAYER 5 : SVCC LAYER 5 : SGND1
DDR3 800 ~ 1333 MT/s
Maxima 4GBs Processor : Daul / Quad Core LCD Conn (15.6") LAYER 6 : BOT LAYER 6 : SVCC
Nvidia
PAGE 12 Dual Channel LAYER 7 : SGND2
Power : 35 / 45 (Watt) N12P-GS/N12E-GE (Ventura)
PCI-E Gen2 1366 x 768 PAGE 21 LAYER 8 : BOT
x 16 Lane
DDR3 SO-DIMM2 Package : rPGA998B Power : 25 / 35 (Watt)
DDR3 800 ~ 1333 MT/s
https://t.me/biosarchive
Maxima 4GBs Power Source

Size : 37.5 x 37.5 (mm) Package : FCBGA973/1005
PAGE 13 O2Micro OZ8681
PAGE 2~5 CRT Conn
Size : 29 x 29 (mm) System Charge Power (+BATCHG)
2048 x 1536
DMI x 4 FDI x 8 PAGE 14~18
PAGE 22
C C
BCLK133M 32.768KHz
DMI100M 27MHz
DP120M P2806
LVDS Interface HDMI Conn System Discharge Power
SATA - 1st HDD Intel Cougar Point
1920 x 1080 (+1.5V/+3V/+5V)
Power : SATA0 300MB/s
Platform Controller Hub PAGE 23
Package : 9.5 (mm) HDMI Interface
PAGE 29
Power : 3.5 Watt
https://t.me/biosarchive https://t.me/biosarchive
Ricktek RT8205
SATA - CD-ROM SATA1 300MB/s Package : FCBG989 CRT Interface System Power (+3VPCU/+5VPCU/
Power : +3VS5/+5VS5)
Size : 25 x 25 (mm)
Package : 12.7 (mm) USB2.0 Interface
PAGE 29 PAGE 6~11
Azalia
USB2.0 Port x 3 Camera Bluetooth Realtek RTS5138 NCP6131/NCP5911/RT8209/G9334

(Co-Layout With Power : Power : Processor Power (+VCC_CORE/
USB3.0 x 2) Package : Package :
Card Reader +1.05_VTT/+VCCSA)
B SPI Interface B
LPC Interface PCIE Gen 1 x 1 Lane Power :

Package : LQPF48 Richtek RT8207
System BIOS IT8158E Realtek ALC269 VIA VL801 Atheros AR8151 Intel Rambo Peak System Memory Power (+1.5VSUS/
Size : 7 x 7 (mm)
SPI ROM +0.75V_DDR_VTT)
Embedded Controller Audio Codec USB3.0 Controller LAN Controller Halt Mini Card PAGE 28
PAGE 25
Power : Power : Power : Power : WLAN / BT Combo
Package : LQPF128 Package : LQPF48 Package : QFN88 Package : OFN48 Power : Richtek RT8209/RT9025
Keyboard & PCH Power (+1.05/+1.8V)
Touch Pad Size : 14 x 14 (mm) Size : 7 x 7 (mm) Size : 9.15 x 9.15 (mm) Size : 6 x 6 (mm) Package :
PAGE 29 PAGE 32 PAGE 25 PAGE 24 PAGE 27
Size :
PAGE 31
FAN Controller Morden Conn USB3.0 Port x 3 25MHz O2Micro OZ8122
(Option) (Co-Layout With DGPU Power (+VGACORE/+3.3V_GFX/
A PAGE 25 PAGE 26 USB2.0) PAGE 24 +1.8_VGA/+1.5_GFX/+1.05_GFX) A
PROJECT : TWH
https://t.me/biosarchive Quanta Computer Inc.
Size Document Number Rev
A3 A
Block Diagram
NB5 Date: Tuesday, December 14, 2010 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (DMI,PEG,FDI)

U15A
PEG_ICOMPI J22
J21
PEG_COMP PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
Sandy Bridge Processor (CLK,MISC,JTAG)
U15B
3/26 DB for H/W modify.

02
PEG_ICOMPO PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.
[6] DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
[6] DMI_TXN1 B25 DMI_RX#[1] PEG_RX#[0..15] [14] BCLK A28 CLK_CPU_BCLKP [8]
A25 C26 A27
MISC
CLOCKS
[6] DMI_TXN2 DMI_RX#[2] [7] H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_BCLKN [8]
B24 K33 PEG_RX#0
[6] DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
M35 PEG_RX#1
PEG_RX#[1] PEG_RX#2 SKTOCC#
[6] DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34 SNB_IVB# N.A at SNB EDS #27637 0.7v1 TP22 AN34 SKTOCC#
D B26 J35 PEG_RX#3 A16 CLK_DPLL_SSCLKP_R D
[6] DMI_TXP1 DMI_RX[1] PEG_RX#[3] DPLL_REF_SSCLK
A24 J32 PEG_RX#4 A15 CLK_DPLL_SSCLKN_R
[6] DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RX#5 DPLL_REF_SSCLK#
DMI
[6] DMI_TXP3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_RX#6
PEG_RX#[6] PEG_RX#7 TP_CATERR#
[6] DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33 TP23 AL33 CATERR#
E22 G30 PEG_RX#8
[6] DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_RX#9 Placement close to EC.
D21 E34 PEG_RX#10
THERMAL
E32 PEG_RX#11 R276 43_4 H_PECI AN33 R8 CPU_DRAMRST#
PEG_RX#[11] [29] EC_PECI PECI SM_DRAMRST#
G22 D33 PEG_RX#12
[6] DMI_RXP0 DMI_TX[0] PEG_RX#[12]
D22 D31 PEG_RX#13
DDR3
MISC
[6] DMI_RXP1 DMI_TX[1] PEG_RX#[13]
F20 B33 PEG_RX#14
[6] DMI_RXP2 DMI_TX[2] PEG_RX#[14] PEG_RX#15
C21 C32 PEG_RX[0..15] [14] [29,39] H_PROCHOT# R167 56.2/F_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R134 140/F_4
[6] DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT# SM_RCOMP[0]
PCI EXPRESS* - GRAPHICS

A5 SM_RCOMP_1 R396 26.1/F_4
PEG_RX0 C1016 SM_RCOMP[1] SM_RCOMP_2 R395 200/F_4
PEG_RX[0] J33 SM_RCOMP[2] A4
L35 PEG_RX1 9/9 add for PDG update
PEG_RX[1] PEG_RX2 43P/50V_4
PEG_RX[2] K34 AN32 THERMTRIP# SM_RCOMP[0] W:20mils/S:20mils/L: 500mils,
A21 H35 PEG_RX3
[6] FDI_TXN0 FDI0_TX#[0] PEG_RX[3] PEG_RX4
SM_RCOMP[1] W:20mils/S:20mils/L: 500mils,
[6] FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32
E19 G34 PEG_RX5 R462 *0_4/S PM_THRMTRIP#_R SM_RCOMP[2] W:15mils/S:20mils/L: 500mils,
[6] FDI_TXN2 FDI0_TX#[2] PEG_RX[5] [9,29] PM_THRMTRIP#
F18 G31 PEG_RX6
[6] FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
B21 F33 PEG_RX7 AP29 XDP_PRDY#
[6] FDI_TXN4 TP72
Intel(R) FDI
FDI1_TX#[0] PEG_RX[7] PEG_RX8 PRDY# XDP_PREQ#

[6] FDI_TXN5 C20 FDI1_TX#[1] PEG_RX[8] F30 12/13 short PREQ# AP27 TP28 CPU XDP
D18 E35 PEG_RX9
[6] FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_RX10 11/12 short AR26 XDP_TCLK
[6] FDI_TXN7 FDI1_TX#[3] PEG_RX[10] TCK TP68
F32 PEG_RX11 AR27 XDP_TMS TP73
PWR MANAGEMENT
PEG_RX[11] TMS
JTAG & BPM

D34 PEG_RX12 [6] PM_SYNC R454 *0_4/S PM_SYNC_R AM34 AP30 XDP_TRST# TP71
PEG_RX[12] PEG_RX13 short0402 PM_SYNC TRST#
[6] FDI_TXP0 A22 FDI0_TX[0] PEG_RX[13] E31
G19 C33 PEG_RX14 8/31 reserved for "boot hang 47" issue C1001 *0.1U/10V_4 AR28 XDP_TDI_R TP27
[6] FDI_TXP1 FDI0_TX[1] PEG_RX[14] TDI
E20 B32 PEG_RX15 AP26 XDP_TDO TP74
C [6] FDI_TXP2 FDI0_TX[2] PEG_RX[15] TDO C
G18 [9] H_PWRGOOD R457 *0_4/S H_PWRGOOD_R AP33
[6] FDI_TXP3 FDI0_TX[3] UNCOREPW RGOOD
B20 M29 C_PEG_TX#0 R453 *1K_4 +3V
[6] FDI_TXP4 FDI1_TX[0] PEG_TX#[0]
C19 M32 C_PEG_TX#1 R456 10K_4
[6] FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 C_PEG_TX#2 AL35 XDP_DBRST#
[6] FDI_TXP6 FDI1_TX[2] PEG_TX#[2] DBR# XDP_DBRST# [6]
F17 L32 C_PEG_TX#3 3/26 DB del for DG update. PM_DRAM_PWRGD_R V8
[6] FDI_TXP7 FDI1_TX[3] PEG_TX#[3] SM_DRAMPW ROK
L29 C_PEG_TX#4
PEG_TX#[4] C_PEG_TX#5 XDP_BPM0
[6] FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 BPM#[0] AT28 TP30
J17 K28 C_PEG_TX#6 +1.05V_VTT R470 *75_4 AR29 XDP_BPM1 TP31
[6] FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] BPM#[1]
J30 C_PEG_TX#7 U18 XDP_BPM2
H20
PEG_TX#[7]
J28 C_PEG_TX#8 CPU RESET# 3 4 CPU_PLTRST# R460 *43_4 CPU_PLTRST#_R AR33
BPM#[2] AR30
AT30 XDP_BPM3
TP67
TP69
[6] FDI_INT FDI_INT PEG_TX#[8] C_PEG_TX#9 GND OUT RESET# BPM#[3] XDP_BPM4
PEG_TX#[9] H29 BPM#[4] AP32 TP25
J19 G27 C_PEG_TX#10 2 +3VS5 8/26 A-->B modify AR31 XDP_BPM5
[6] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] [8,14,24,26,27,29] PLTRST# IN C502 BPM#[5] TP66
H17 E29 C_PEG_TX#11 AT31 XDP_BPM6
[6] FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] BPM#[6] TP70
F27 C_PEG_TX#12 1 5 R459 AR32 XDP_BPM7
PEG_TX#[12] NC VCC BPM#[7] TP65
D28 C_PEG_TX#13
PEG_TX#[13] C_PEG_TX#14 *74LVC1G07GW 750/F_4
PEG_TX#[14] F26 8/26 A-->B modify *0.1U/10V_4
E25 C_PEG_TX#15 Sandy Bridge_rPGA_Rev0p61
eDP_COMP PEG_TX#[15] rpga989-47989-socket
A18 eDP_COMPIO
A17 M28 C_PEG_TX0 R463 1.5K/F_4 8/26 A-->B modify DGG^9000014
INT_eDP_HPD_Q eDP_ICOMPO PEG_TX[0] C_PEG_TX1 IC SOCKET RPGA 989P(P1.0,M/H3.0)
B16 M33
eDP_HPD PEG_TX[1]
PEG_TX[2] M30
L31
C_PEG_TX2
C_PEG_TX3
DDR3 DRAM RESET
PEG_TX[3] C_PEG_TX4 +3VS5 +3VS5
C15 eDP_AUX PEG_TX[4] L28
D15 K30 C_PEG_TX5 +1.5VSUS R41 1K_4 R42 *0_4
eDP_AUX# PEG_TX[5] C_PEG_TX6 +1.5V_CPU
PEG_TX[6] K27
J29 C_PEG_TX7
eDP
PEG_TX[7] C_PEG_TX8 R43 1K_4 CPU_DRAMRST#

C17 J27 3 1
F16
eDP_TX[0] PEG_TX[8]
H28 C_PEG_TX9 SM_DRAMPWROK R491 U19 C522
[12,13] DDR3_DRAMRST#
eDP_TX[1] PEG_TX[9] C_PEG_TX10 *10K_4 *0.1U/10V_4
C16
G15
eDP_TX[2] PEG_TX[10] G28
E28 C_PEG_TX11 Processor Input. 1 NC VCC 5
R488 CPU_DRAMRST#_R Q9
2
B eDP_TX[3] PEG_TX[11] C_PEG_TX12 PM_DRAM_PWRGD_PU 200/F_4 2N7002 B
PEG_TX[12] F28 2 IN
C18 D27 C_PEG_TX13 R39 *0_4/S
eDP_TX#[0] PEG_TX[13] [8] DRAMRST_CNTRL_PCH
E16 E26 C_PEG_TX14 3 4 PM_DRAM_PWRGD_C R123 130/F_4 PM_DRAM_PWRGD_R short0402 R40
eDP_TX#[1] PEG_TX[14] C_PEG_TX15 GND OUT R125 C37 4.99K/F_4
D16 eDP_TX#[2] PEG_TX[15] D25 3/26 DB del for
F15 R495 *74LVC1G07GW 11/12 short 0.047U/10V_4
eDP_TX#[3] DG update. *0_4 8/26 A-->B modify
3
10/11 change 39_4
Sandy Bridge_rPGA_Rev0p61 PM_DRAM_PWRGD [6]
rpga989-47989-socket
DGG^9000014 2 MAIN_ONG [4,36]
IC SOCKET RPGA 989P(P1.0,M/H3.0) R127 *0_4/S PM_DRAM_PWRGD_C
eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. R120 Q17 [6,7,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V
8/31 change to 0 ohm *3K/F_4 2N7002
eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils. [6,7,8,9,10,14,24,29,31,33,35,36,38] +3VS5
1
12/13 short 11/8 add [4,10,27] +1.5V_CPU
[4,29,33,34,38,39] +1.05V_VTT
8/26 A-->B modify
FDI disable PEG x16 disable (UMA only remove) Embedded Display PLL Clock DP & PEG Compensation Processor pull-up (CPU)
(DIS only stuff) [14] PEG_TX[0..15] [14] PEG_TX#[0..15]
Ra
3/26 DB change
Part reference. +1.05V_VTT R389 10K_4 INT_eDP_HPD_Q +1.05V_VTT
RP11
C_PEG_TX0 C504 0.1U/10V_4 PEG_TX0 C_PEG_TX#0 C505 0.1U/10V_4 PEG_TX#0 CLK_DPLL_SSCLKP_R 3 4 CLK_DPLL_SSCLKP [8] H_PROCHOT# R168 62_4
FDI_INT C_PEG_TX1 C500 0.1U/10V_4 PEG_TX1 C_PEG_TX#1 C503 0.1U/10V_4 PEG_TX#1 CLK_DPLL_SSCLKN_R 1 2 R390 24.9/F_4 eDP_COMP XDP_TDO R476 51_4
CLK_DPLL_SSCLKN [8] +1.05V_VTT
C_PEG_TX2 C499 0.1U/10V_4 PEG_TX2 C_PEG_TX#2 C501 0.1U/10V_4 PEG_TX#2 XDP_TMS R474 51_4
R71 *0_4 FDI_FSYNC0 C_PEG_TX3 C497 0.1U/10V_4 PEG_TX3 C_PEG_TX#3 C498 0.1U/10V_4 PEG_TX#3 0_4P2R_04 XDP_TDI_R R159 51_4
R69 *0_4 FDI_FSYNC1 C_PEG_TX4 C493 0.1U/10V_4 PEG_TX4 C_PEG_TX#4 C494 0.1U/10V_4 PEG_TX#4 eDP_COMPIO and ICOMPO signals should be shorted XDP_PREQ# R162 *51_4
A R70 *0_4 FDI_LSYNC0 C_PEG_TX5 C495 0.1U/10V_4 PEG_TX5 C_PEG_TX#5 C496 0.1U/10V_4 PEG_TX#5 Rb XDP_TCLK R163 51_4 A
FDI_LSYNC1 C_PEG_TX6 C488 0.1U/10V_4 PEG_TX6 C_PEG_TX#6 C490 0.1U/10V_4 PEG_TX#6 CLK_DPLL_SSCLKP_R R398 *0_4 near balls and routed with typical impedance <25 mohms XDP_TRST# R475 51_4
C_PEG_TX7 C489 0.1U/10V_4 PEG_TX7 C_PEG_TX#7 C492 0.1U/10V_4 PEG_TX#7 Rc
R68 *1K_4 C_PEG_TX8 C483 0.1U/10V_4 PEG_TX8 C_PEG_TX#8 C485 0.1U/10V_4 PEG_TX#8 CLK_DPLL_SSCLKN_R R397 *0_4 R67 24.9/F_4 PEG_COMP
+1.05V_VTT
R72 *1K_4 C_PEG_TX9 C486 0.1U/10V_4 PEG_TX9 C_PEG_TX#9 C487 0.1U/10V_4 PEG_TX#9
C_PEG_TX10 C478 0.1U/10V_4 PEG_TX10 C_PEG_TX#10 C481 0.1U/10V_4 PEG_TX#10
FDI_FSYNC can gang all these 4

C_PEG_TX11
C_PEG_TX12
C480
C479
0.1U/10V_4
0.1U/10V_4
PEG_TX11
PEG_TX12
C_PEG_TX#11
C_PEG_TX#12
C482
C475
0.1U/10V_4
0.1U/10V_4
PEG_TX#11
PEG_TX#12
Ra Rb Rc PEG_ICOMPI and RCOMPO signals PROJECT : TWH
signals together and tie them C_PEG_TX13
C_PEG_TX14
C474
C465
0.1U/10V_4
0.1U/10V_4
PEG_TX13
PEG_TX14
C_PEG_TX#13
C_PEG_TX#14
C476
C468
0.1U/10V_4
0.1U/10V_4
PEG_TX#13
PEG_TX#14
DIS NC Stuff Stuff
should be routed within 500 mils typical
impedance = 43 mohms PEG_ICOMPO
Quanta Computer Inc.
with only one 1K resistor to GND C_PEG_TX15 C466 0.1U/10V_4 PEG_TX15 C_PEG_TX#15 C469 0.1U/10V_4 PEG_TX#15 SG/UMA Stuff NC NC signals should be routed within 500 mils
(DG V0.5 Ch2.2.9). Size Document Number Rev
0.22uF AC coupling Caps for PCIE GEN1/2/3 0.22uF AC coupling Caps for PCIE GEN1/2/3 typical impedance = 14.5 mohms Custom
Processor 1/4 (Host/GPU) A
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (DDR3) 03

U15C U15D
D D
SA_CLK[0] AB6 M_A_CLKP0 [12] [13] M_B_DQ[63:0] SB_CLK[0] AE2 M_B_CLKP0 [13]
[12] M_A_DQ[63:0] SA_CLK#[0] AA6 M_A_CLKN0 [12] SB_CLK#[0] AD2 M_B_CLKN0 [13]
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
SA_DQ[0] SA_CKE[0] M_A_CKE0 [12] SB_DQ[0] SB_CKE[0] M_B_CKE0 [13]
M_A_DQ1 D5 M_B_DQ1 A7
M_A_DQ2 SA_DQ[1] M_B_DQ2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
M_A_DQ3 D2 M_B_DQ3 C8
D6 SA_DQ[4] SA_CLK[1] AA5 M_A_CLKP1 [12] A9 SB_DQ[4] SB_CLK[1] AE1 M_B_CLKP1 [13]
M_A_DQ5 C6 AB5 M_B_DQ5 A8 AD1
SA_DQ[5] SA_CLK#[1] M_A_CLKN1 [12] SB_DQ[5] SB_CLK#[1] M_B_CLKN1 [13]
M_A_DQ6 C2 V10 M_A_CKE1 [12] M_B_DQ6 D9 R10 M_B_CKE1 [13]
M_A_DQ7 SA_DQ[6] SA_CKE[1] M_B_DQ7 SB_DQ[6] SB_CKE[1]
C3 SA_DQ[7] D8 SB_DQ[7]
M_A_DQ8 F10 M_B_DQ8 G4
F8 SA_DQ[9] F4 SB_DQ[9]
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ[10] SA_CLK[2] M_B_DQ11 SB_DQ[10] SB_CLK[2]
G9 SA_DQ[11] SA_CLK#[2] AA4 G1 SB_DQ[11] SB_CLK#[2] AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
F7 SA_DQ[13] F5 SB_DQ[13]
M_A_DQ14 G8 M_B_DQ14 F2
G7 SA_DQ[15] G2 SB_DQ[15]
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ[16] SA_CLK[3] M_B_DQ17 SB_DQ[16] SB_CLK[3]
K5 SA_DQ[17] SA_CLK#[3] AA3 J8 SB_DQ[17] SB_CLK#[3] AB1
M_A_DQ18 K1 W 10 M_B_DQ18 K10 T10
J1 SA_DQ[19] K9 SB_DQ[19]
M_A_DQ20 J5 M_B_DQ20 J9
J4 SA_DQ[21] J10 SB_DQ[21]
M_A_DQ22 J2 AK3 M_A_CS#0 [12] M_B_DQ22 K8 AD3 M_B_CS#0 [13]
M_A_DQ23 SA_DQ[22] SA_CS#[0] M_B_DQ23 SB_DQ[22] SB_CS#[0]
K2 SA_DQ[23] SA_CS#[1] AL3 M_A_CS#1 [12] K7 SB_DQ[23] SB_CS#[1] AE3 M_B_CS#1 [13]
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ[24] SA_CS#[2] M_B_DQ25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
M_A_DQ26 N8 M_B_DQ26 N2
C M_A_DQ27 SA_DQ[26] M_B_DQ27 SB_DQ[26] C
N7 SA_DQ[27] N1 SB_DQ[27]
M_A_DQ28 M10 M_B_DQ28 M4
M9 SA_DQ[29] SA_ODT[0] AH3 M_A_ODT0 [12] N5 SB_DQ[29] SB_ODT[0] AE4 M_B_ODT0 [13]
DDR SYSTEM MEMORY B

M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A
SA_DQ[30] SA_ODT[1] M_A_ODT1 [12] SB_DQ[30] SB_ODT[1] M_B_ODT1 [13]
M_A_DQ31 M7 AG2 M_B_DQ31 M1 AD5
M_A_DQ32 SA_DQ[31] SA_ODT[2] M_B_DQ32 SB_DQ[31] SB_ODT[2]
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
M_A_DQ33 AG5 M_B_DQ33 AM6
AK6 SA_DQ[34] AR3 SB_DQ[34]
M_A_DQ35 AK5 M_B_DQ35 AP3
AH5 SA_DQ[36] M_A_DQSN[7:0] [12] AN3 SB_DQ[36] M_B_DQSN[7:0] [13]
M_A_DQ37 AH6 C4 M_A_DQSN0 M_B_DQ37 AN2 D7 M_B_DQSN0
M_A_DQ38 SA_DQ[37] SA_DQS#[0] M_A_DQSN1 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQSN1
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN1 SB_DQ[38] SB_DQS#[1] F3
M_A_DQ39 AJ6 J3 M_A_DQSN2 M_B_DQ39 AP2 K6 M_B_DQSN2
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
M_A_DQ41 AK8 AL6 M_A_DQSN4 M_B_DQ41 AN9 AN5 M_B_DQSN4
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT5 SB_DQ[42] SB_DQS#[5] AP9
M_A_DQ43 AK9 AR12 M_A_DQSN6 M_B_DQ43 AT6 AK12 M_B_DQSN6
AH8 SA_DQ[44] SA_DQS#[7] AM15 AP6 SB_DQ[44] SB_DQS#[7] AP15
M_A_DQ45 AH9 M_B_DQ45 AN8
AL9 SA_DQ[46] AR6 SB_DQ[46]
M_A_DQ47 AL8 M_B_DQ47 AR5
AP11 SA_DQ[48] M_A_DQSP[7:0] [12] AR9 SB_DQ[48] M_B_DQSP[7:0] [13]
M_A_DQ49 AN11 D4 M_A_DQSP0 M_B_DQ49 AJ11 C7 M_B_DQSP0
M_A_DQ50 SA_DQ[49] SA_DQS[0] M_A_DQSP1 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQSP1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
M_A_DQ51 AM12 K3 M_A_DQSP2 M_B_DQ51 AT9 J6 M_B_DQSP2
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
M_A_DQ53 AL11 AL5 M_A_DQSP4 M_B_DQ53 AR8 AN6 M_B_DQSP4
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
M_A_DQ55 AN12 AR11 M_A_DQSP6 M_B_DQ55 AH12 AK11 M_B_DQSP6
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
B M_A_DQ57 AH14 M_B_DQ57 AN14 B
AL15 SA_DQ[58] AR14 SB_DQ[58]
M_A_DQ59 AK15 M_B_DQ59 AT14
AL14 SA_DQ[60] M_A_A[15:0] [12] AT12 SB_DQ[60] M_B_A[15:0] [13]
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_A0
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ62 SB_DQ[61] SB_MA[0] M_B_A1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ63 AT15 R7 M_B_A2
SA_DQ[63] SA_MA[2] M_A_A3 SB_DQ[63] SB_MA[2] M_B_A3
SA_MA[3] W7 SB_MA[3] T6
V3 M_A_A4 T2 M_B_A4
SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
SA_MA[5] V2 SB_MA[5] T4
W3 M_A_A6 T3 M_B_A6
[12] M_A_BS#0 AE10 SA_BS[0] SA_MA[7] W6 [13] M_B_BS#0 AA9 SB_BS[0] SB_MA[7] R2
[12] M_A_BS#1 AF10 V1 M_A_A8 [13] M_B_BS#1 AA7 T5 M_B_A8
SA_BS[1] SA_MA[8] M_A_A9 SB_BS[1] SB_MA[8] M_B_A9
[12] M_A_BS#2 V6 SA_BS[2] SA_MA[9] W5 [13] M_B_BS#2 R6 SB_BS[2] SB_MA[9] R3
AD8 M_A_A10 AB7 M_B_A10
SA_MA[11] V4 SB_MA[11] R1
W4 M_A_A12 T1 M_B_A12
[12] M_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 [13] M_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
[12] M_A_RAS# AD9 V5 M_A_A14 [13] M_B_RAS# AB8 R5 M_B_A14
SA_RAS# SA_MA[14] M_A_A15 SB_RAS# SB_MA[14] M_B_A15
[12] M_A_WE# AF9 SA_W E# SA_MA[15] V7 [13] M_B_WE# AB9 SB_W E# SB_MA[15] R4
Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket rpga989-47989-socket
DGG^9000014 DGG^9000014
IC SOCKET RPGA 989P(P1.0,M/H3.0) IC SOCKET RPGA 989P(P1.0,M/H3.0)
A A
PROJECT : TWH
Custom A
Processor 2/4 (Memory)
5 4 3 2 1
5 4 3 2 1
9/4 all of these 22uF/6.3V capacitors are

repleaced by 10uF/6.3V in BOM
SNB: 55A
Sandy Bridge Processor (POWER)
+VCC_CORE
U15F
9/4 all of these 22uF/6.3V capacitors are
repleaced by 10uF/6.3V in BOM
Sandy Bridge Processor (GRAPHIC POWER)
22uF_8 x2 Socket TOP cavity U15G 3/26 DB Modify.
R136 100_4
04
+1.05V_VTT 22uF_8 x2 Socket BOT cavity +VCC_GFX
SNB: 8.5A 22uF_8 x4 Socket TOP edge
AG35 AT24 AK35
SENSE
LINES
VCC1 VAXG1 VAXG_SENSE VCC_AXG_SENSE [39]
AG34 VCC2 VCCIO1 AH13 22uF_8 x4 Socket BOT edge AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE [39]
AG33 VCC3 VCCIO2 AH10 470uF_7343 x2 AT21 VAXG3
AG32 AG10 AT20 R138 100_4
C48 C473 C127 VCC4 VCCIO3 C135 C137 C450 VAXG4
AG31 VCC5 VCCIO4 AC10 AT18 VAXG5
D 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AG30 Y10 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AT17 D
VCC6 VCCIO5 +VCC_GFX VAXG6
AG29 VCC7 VCCIO6 U10 SNB: 21.5A AR24 VAXG7
AG28 VCC8 VCCIO7 P10 AR23 VAXG8
AG27 VCC9 VCCIO8 L10 AR21 VAXG9
AG26 VCC10 VCCIO9 J14 AR20 VAXG10 CAD Note: +VDDR_REF_CPU should
AF35 J13 AR18 +VDDR_REF_CPU
VREF
VCC11 VCCIO10 C179 C138 C209 C472 C167 VAXG11 have 10 mil trace width
AF34 VCC12 VCCIO11 J12 AR17 VAXG12
C108 C92 C58 AF33 J11 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AP24 AL1 R157 *0_8 DDR_VTTREF [12,13,32]
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC13 VCCIO12 VAXG13 SM_VREF
AF32 VCC14 VCCIO13 H14 AP23 VAXG14
AF31 VCC15 VCCIO14 H12 AP21 VAXG15
AF30 VCC16 VCCIO15 H11 AP20 VAXG16 1 3
AF29 VCC17 VCCIO16 G14 AP18 VAXG17
AF28 G13 AP17 R165 Q19
VCC18 VCCIO17 C136 C148 C464 C193 C208 VAXG18 100K_4 2N7002
AF27 G12 AN24
2
VCC19 VCCIO18 *22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG19
AF26 VCC20 VCCIO19 F14 AN23 VAXG20
PEG AND DDR

C51 C28 C178 AD35 F13 AN21 MAIND MAIND [36]
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC21 VCCIO20 VAXG21
AD34 VCC22 VCCIO21 F12 AN20 VAXG22
AD33 F11 AN18
DDR3 -1.5V RAILS

VCC23 VCCIO22 VAXG23
AD32 VCC24 VCCIO23 E14 AN17 VAXG24 11/13 C516 mount for S3 black screen issue
AD31 E12 AM24 AF7 5/14 modify
GRAPHICS
VCC25 VCCIO24 C470 C142 C121 C192 C511 VAXG25 VDDQ1 +1.5V_CPU
AD30 VCC26 AM23 VAXG26 VDDQ2 AF4 SNB: 5A
AD29 E11 *22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AM21 AF1
VCC27 VCCIO25 VAXG27 VDDQ3
AD28 VCC28 VCCIO26 D14 AM20 VAXG28 VDDQ4 AC7
C206 C165 C49 AD27 D13 AM18 AC4
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC29 VCCIO27 VAXG29 VDDQ5
AD26 VCC30 VCCIO28 D12 AM17 VAXG30 VDDQ6 AC1
AC35 D11 AL24 Y7 C134 C152 C204 C153
VCC31 VCCIO29 VAXG31 VDDQ7 10U/6.3V_6 10U/6.3V_8 10U/6.3V_6 10U/6.3V_6
AC34 VCC32 VCCIO30 C14 5/14 modify AL23 VAXG32 VDDQ8 Y4
AC33 C13 C445 C120 C198 C207 C166 AL21 Y1
AC32 VCC34 VCCIO32 C12 22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 AL20 VAXG34 VDDQ10 U7 4/27: layout modify
AC31 VCC35 VCCIO33 C11 AL18 VAXG35 VDDQ11 U4 330uF x1, 10uF_8 x6 Socket BOT edge.
C AC30 B14 AL17 U1 C
1
C125 C477 C141 AC29 B12 AK24 P7
22U/6.3VS_8 *22U/6.3VS_8 22U/6.3VS_8 VCC37 VCCIO35 VAXG37 VDDQ13 + C516
AC28 VCC38 VCCIO36 A14 AK23 VAXG38 VDDQ14 P4
AC27 A13 AK21 P1 C173 C213 100U 16V(+-20%,6.3*5.8)
VCC39 VCCIO37 C446 C454 C158 C512 C169 VAXG39 VDDQ15 10U/6.3V_6 10U/6.3V_6
AC26 A12 AK20
2
VCC40 VCCIO38 *22U/6.3VS_8 22U/6.3VS_8 *22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG40
AA35 VCC41 VCCIO39 A11 AK18 VAXG41
AA34 VCC42 AK17 VAXG42 8/31 C516 FP changed from
AA33 VCC43 VCCIO40 J23 AJ24 VAXG43 330U_2.5V_5.0x5.9ESR10m to
AA32 VCC44 AJ23 VAXG44
C144 C147 C197 AA31 AJ21 220U/6.3V_6x4.5ESR18
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC45 VAXG45
AA30 VCC46 AJ20 VAXG46 3/26 DB change 10U FP to 0805.
AA29 C460 C457 C101 C168 C471 AJ18
VCC47 *22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3V_8 22U/6.3V_8 VAXG47
AA28 VCC48 AJ17 VAXG48 +VCCSA
AA27 VCC49 AH24 VAXG49 SNB: 6A
SA RAIL
AA26 VCC50 AH23 VAXG50
Y35 VCC51 AH21 VAXG51 VCCSA1 M27
Y34 VCC52 22uF_8 x7 Socket TOP cavity AH20 VAXG52 VCCSA2 M26
CORE SUPPLY
C157 C107 C151 Y33 5/4: add C8260/ C8322 AH18 L26
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC53 22uF_8 x5 Socket BOT cavity VAXG53 VCCSA3
Y32 VCC54 Ra R473 *0_4 AH17 VAXG54 VCCSA4 J26 C447 C31 C97 C24
Y31 22uF_8 x2 Socket TOP cavity (no stuff) J25 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8
VCC55 VCCSA5
Y30 VCC56
22uF_8 x5 Socket BOT cavity (no stuff) VCCSA6 J24
Y29 VCC57 330uF_7343 x2 DIS SG/UMA VCCSA7 H26
Y28 VCC58 VCCSA8 H25 330uF x1, 10uF_8 x1 Socket BOT edge,
Y27 VCC59 Ra Stuff NC 10uF_8 x2 Socket BOT cavity.
Y26
1.8V RAIL
C46 C467 C430 VCC60 +1.05V_VTT
V35 VCC61 3/26 DB change 10U FP to 0805.
*22U/6.3VS_8 *22U/6.3VS_8 22U/6.3VS_8 +1.8V
V34 VCC62 +1.05V_VTT_40
SNB: 1.5A
V33 R66 *0_4/S
VCC63
V32 VCC64 B6 VCCPLL1 VCCSA_SENSE H23 VCCUSA_SENSE_R R388 *0_4/S VCCUSA_SENSE [33]
V31 A6 short0402
MISC
B VCC65 VCCPLL2 B
V30 VCC66 A2 VCCPLL3
11/12 short
V29 AJ29 H_CPU_SVIDALRT# C42 C45 C44 + C432 R392 10K_4
SVID
VCC67 VIDALERT# H_CPU_SVIDCLK

V28 VCC68 VIDSCLK AJ30 10U/6.3V_8 1U/6.3V_4 1U/6.3V_4 330U/2V_7343
FC_C22 C22 H_FC_C22
C461 C29 C53 V27 AJ28 H_CPU_SVIDDAT C24 VCCSA_SEL [33]
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC69 VIDSOUT VCCSA_VID1
V26 VCC70
U35 330uF x1, 10uF_8 x1, 1uF_4 x2 R393 10K_4
VCC71
U34 VCC72 Socket BOT edge.
U33 Sandy Bridge_rPGA_Rev0p61
VCC73
U32 VCC74 3/26 DB change 10U FP to 0805. rpga989-47989-socket 5/11: Add for intel CRB
U31 DGG^9000014
VCC75 IC SOCKET RPGA 989P(P1.0,M/H3.0)
U30 VCC76
C41 C431 C47 U29
22U/6.3VS_8 22U/6.3VS_8 *22U/6.3VS_8 VCC77
U28 VCC78
U27 VCC79 9/8 delete JP1
U26 VCC80 Layout note: need routing Place PU resistor SVID CLK
R35 +1.5VSUS +1.5V_CPU +1.5VSUS
VCC81 together and ALERT need close to VR
R34 VCC82
22uF_8 x8 Socket TOP cavity R33 3/26 DB Modify. between CLK and DATA. R124 *54.9/F_4 +1.05V_VTT C515 0.1U/10V_4
VCC83 R128 100_4
22uF_8 x10 Socket BOT cavity R32 VCC84 +VCC_CORE Q40
SENSE LINES
R31 C517 0.1U/10V_4

22uF_8 x8 Socket TOP edge VCC85 H_CPU_SVIDCLK AON7410
R30 VCC86 VCC_SENSE AJ35 VCC_SENSE [39] VR_SVID_CLK [39]
470uF_7343 x4 R29 VCC87 VSS_SENSE AJ34 VSS_SENSE [39] 1 R170 C518 0.1U/10V_4
R28 3/26 DB Modify. 5 2 220_8
VCC88 R133 100_4 C514 0.1U/10V_4
3/26 DB change 10U FP to 0805. R27 VCC89 3
R26 +1.05V_VTT +1.05V_VTT
VCC90 SVID DATA
3
P35 VCC91 3/26 DB add for Intel.
P34 Placement close to CPU.
4
VCC92 MAIND
P33 VCC93 VCCP_SENSE [34]
P32 VCC94 VCCIO_SENSE B10 Place PU resistor Place PU resistor 2 MAIN_ONG [2,36]
P31 A10 VSSP_SENSE R121 R118
A VCC95 VSSIO_SENSE TP53 close to CPU close to VR A
P30 VCC96
130/F_4 *130/F_4 C262 Q20 5/6: modify
P29 *470P/50V_4 2N7002
VCC97 H_CPU_SVIDDAT
P28 Trace Route to Power IC area. VR_SVID_DATA [39]
CPU VDDQ
1
VCC98
P27 VCC99
P26 VCC100 3/26 DB Modify. 5/12: modify
Place PU resistor close to CPU SVID ALERT PROJECT : TWH
Sandy Bridge_rPGA_Rev0p61
rpga989-47989-socket
[2,10,12,13,32,33,38] +1.5VSUS +1.05V_VTT R158 75_4 Quanta Computer Inc.
[2,10,27] +1.5V_CPU 3/26 DB Modify.
DGG^9000014 [2,29,33,34,38,39] +1.05V_VTT
IC SOCKET RPGA 989P(P1.0,M/H3.0) [33] +VCCSA H_CPU_SVIDALRT# R166 43_4 VR_SVID_ALERT# [39] Size Document Number Rev
Custom A
Processor 3/4 (Power)
[39,40] +VCC_GFX
[39,40] +VCC_CORE NB5 Date: Tuesday, December 14, 2010 Sheet 4 of 40
5 4 3 2 1
5 4 3 2 1
AT35
U15H
Sandy Bridge Processor (GND)
AJ22
U15I
Sandy Bridge Processor (RESERVED, CFG)
U15E
05
VSS1 VSS81
AT32 VSS2 VSS82 AJ19 For CPU debug. RSVD28 L7
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22 RSVD29 AG7
AT27 AJ13 T34 F19 CFG0 AK28 AE7
VSS4 VSS84 VSS162 VSS235 TP20 CFG[0] RSVD30
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30 TP19 AK29 CFG[1] RSVD31 AK2
AT22 AJ7 T32 E27 CFG2 AL26 W8
VSS6 VSS86 VSS164 VSS237 CFG[2] RSVD32
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24 TP24 AL27 CFG[3]
D AT16 AJ3 T30 E21 CFG4 AK26 D
VSS8 VSS88 VSS166 VSS239 CFG5 CFG[4]
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18 AL29 CFG[5] RSVD33 AT26
AT10 AJ1 T28 E15 CFG6 AL30 AM33
VSS10 VSS90 VSS168 VSS241 CFG7 CFG[6] RSVD34
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AM31 CFG[7] RSVD35 AJ27
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10 AM32 CFG[8]
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AM30 CFG[9]
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8 AM28 CFG[10]
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AM26 CFG[11]
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6 AN28 CFG[12]
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5 AN31 CFG[13] RSVD37 T8
AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4 AN26 CFG[14] RSVD38 J16
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3 AM27 CFG[15] RSVD39 H16
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2 AK31 CFG[16] RSVD40 G16
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1 AN29 CFG[17]
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26 RSVD41 AR35
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20 AJ31 RSVD1 RSVD42 AT34
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17 AH31 RSVD2 RSVD43 AT33
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34 AJ33 RSVD3 RSVD44 AP35
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31 AH33 RSVD4 RSVD45 AR34
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25 AJ26 RSVD5
RESERVED
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1 RSVD46 B34
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22 [12] SMDDR_VREF_DQ0_M3 B4 RSVD6 RSVD47 A33
AN25 AE29 L4 B19 D1 A34
C AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
[13] SMDDR_VREF_DQ1_M3 RSVD7 RSVD48
RSVD49
RSVD50
B35
C35
C
AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13

AN13 AE9 K35 B11 R394 R387 F25
VSS41 VSS121 VSS199 VSS272 *1K_4 *1K_4 RSVD8
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9 F24 RSVD9
AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8 F23 RSVD10
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD51 AJ32
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD52 AK32
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3 G24 RSVD13
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2 E23 RSVD14
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35 D23 RSVD15
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32 C30 RSVD16 RSVD53 AH27
AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29 A31 RSVD17
AM10 VSS51 VSS131 AB33 H21 VSS209 VSS282 A26 B30 RSVD18
AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23 B29 RSVD19
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD54 AN35 TP63
AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3 B31 RSVD21 RSVD55 AM35 TP64
AM2 VSS55 VSS135 AB29 H10 VSS213 A30 RSVD22
AM1 VSS56 VSS136 AB28 H9 VSS214 C29 RSVD23 #27636 SNB EDS0.7v1 no function.
AL34 VSS57 VSS137 AB27 H8 VSS215
AL31 VSS58 VSS138 AB26 H7 VSS216
AL28 VSS59 VSS139 Y9 H6 VSS217 J20 RSVD24
AL25 VSS60 VSS140 Y8 H5 VSS218 B18 RSVD25 RSVD56 AT2
AL22 Y6 H4 R391 *0_4/S A19 AT1
VSS61 VSS141 VSS219 [34] H_VTTVID1 RSVD26 RSVD57
AL19 Y5 H3 short0402 AR1
VSS62 VSS142 VSS220 RSVD58
AL16 VSS63 VSS143 Y3 H2 VSS221
AL13 VSS64 VSS144 Y2 H1 VSS222
11/12 short J15 RSVD27 For rPGA socket, RSVD59 pin should be left NC.
AL10 VSS65 VSS145 W 35 G35 VSS223
AL7 VSS66 VSS146 W 34 G32 VSS224
AL4 VSS67 VSS147 W 33 G29 VSS225 KEY B1
B AL2 W 32 G26 B
VSS68 VSS148 VSS226
AK33 VSS69 VSS149 W 31 G23 VSS227
AK30 VSS70 VSS150 W 30 G20 VSS228
AK27 VSS71 VSS151 W 29 G17 VSS229
AK25 VSS72 VSS152 W 28 G11 VSS230
AK22 VSS73 VSS153 W 27 F34 VSS231
AK19 W 26 F31 Sandy Bridge_rPGA_Rev0p61
VSS74 VSS154 VSS232 rpga989-47989-socket
AK16 VSS75 VSS155 U9 F29 VSS233
AK13 U8 DGG^9000014
VSS76 VSS156 IC SOCKET RPGA 989P(P1.0,M/H3.0)
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2
Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket rpga989-47989-socket
DGG^9000014 DGG^9000014
IC SOCKET RPGA 989P(P1.0,M/H3.0) IC SOCKET RPGA 989P(P1.0,M/H3.0)
CFG[6:5] (PCIE Port Bifurcation Straps)

The CFG signals have a default value of '1' if not terminated on the board.
Processor Strapping 11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
1 0 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
(hh) TWH PEG bus is Lane Reversed
CFG2 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
A A
(PEG Static Lane Reversal) Normal Operation Lane Reversed CFG2 R155 1K_4
CFG4 CFG4 R156 *1K_4
(DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP CFG7 R153 *1K_4
PROJECT : TWH
CFG7 PEG train immediately following PEG wait for BIOS training CFG5 R141 *1K_4 Quanta Computer Inc.
(PEG Defer Training) xxRESETB de assertion CFG6 R152 *1K_4
Custom A
Processor 4/4 (Ground)
5 4 3 2 1
5 4 3 2 1
[2] DMI_RXN0
Cougar Point (DMI,FDI,PM)
BC24
U24C
BJ14
[21] PCH_LVDS_BLON
[21] PCH_DISP_ON
Cougar Point (LVDS,DDI)
J47
M45
U24D
L_BKLTEN SDVO_TVCLKINN AP43
AP45
06
DMI0RXN FDI_RXN0 FDI_TXN0 [2] L_VDD_EN SDVO_TVCLKINP
[2] DMI_RXN1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_TXN1 [2]
[2] DMI_RXN2 BG18 DMI2RXN FDI_RXN2 BE14 FDI_TXN2 [2] [21] PCH_DPST_PWM P45 L_BKLTCTL SDVO_STALLN AM42
[2] DMI_RXN3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_TXN3 [2] SDVO_STALLP AM40
BC12 [21] PCH_EDIDCLK PCH_EDIDCLK T40
FDI_RXN4 FDI_TXN4 [2] L_DDC_CLK
BE24 BJ12 PCH_EDIDDAT K47 AP39
[2] DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5 [2] [21] PCH_EDIDDATA L_DDC_DATA SDVO_INTN
[2] DMI_RXP1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_TXN6 [2] SDVO_INTP AP40
D BJ18 BG9 CTRL_CLK T45 D
[2] DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 [2] L_CTRL_CLK
[2] DMI_RXP3 BJ20 3/26 DB change net name. CTRL_DATA P39
DMI3RXP L_CTRL_DATA
FDI_RXP0 BG14 FDI_TXP0 [2]
AW 24 BB14 LVD_IBG AF37 P38
[2] DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1 [2] LVD_IBG SDVO_CTRLCLK SDVO_CLK [22]
[2] DMI_TXN1 AW 20 BF14 TP35 AF36 M39 SDVO_DATA [22]
DMI1TXN FDI_RXP2 FDI_TXP2 [2] LVD_VBG SDVO_CTRLDATA
[2] DMI_TXN2 BB18 DMI2TXN FDI_RXP3 BG13 FDI_TXP3 [2]
[2] DMI_TXN3 AV18 DMI3TXN FDI_RXP4 BE12 FDI_TXP4 [2] AE48 LVD_VREFH
INT. HDMI
FDI_RXP5 BG12 FDI_TXP5 [2] AE47 LVD_VREFL DDPB_AUXN AT49
DMI
FDI
[2] DMI_TXP0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_TXP6 [2] DDPB_AUXP AT47
[2] DMI_TXP1 AY20 BH9 AT40 DPB_HPD_Q
DMI1TXP FDI_RXP7 FDI_TXP7 [2] DDPB_HPD
[2] DMI_TXP2 AY18 [21] PCH_LA_CLK# PCH_LA_CLK# AK39
DMI2TXP PCH_LA_CLK LVDSA_CLK# DPB_LANE0_N
AU18 AK40 AV42
LVDS
[2] DMI_TXP3 DMI3TXP [21] PCH_LA_CLK LVDSA_CLK DDPB_0N
AW 16 AV40 DPB_LANE0_P
FDI_INT FDI_INT [2] DDPB_0P
[21] PCH_LA_DATAN0 PCH_LA_DATAN0 AN48 AV45 DPB_LANE1_N
PCH_LA_DATAN1 LVDSA_DATA#0 DDPB_1N DPB_LANE1_P
BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 [2] [21] PCH_LA_DATAN1 AM47 LVDSA_DATA#1 DDPB_1P AV46
PCH_LA_DATAN2 DPB_LANE2_N
Digital Display Interface

[21] PCH_LA_DATAN2 AK47 LVDSA_DATA#2 DDPB_2N AU48
+1.05V R563 49.9/F_4 DMI_COMP BG25 BC10 AJ48 AU47 DPB_LANE2_P
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [2] LVDSA_DATA#3 DDPB_2P DPB_LANE3_N
DDPB_3N AV47
R284 750/F_4 DMI_RBIAS BH21 AV14 PCH_LA_DATAP0 AN47 AV49 DPB_LANE3_P
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 [2] [21] PCH_LA_DATAP0 LVDSA_DATA0 DDPB_3P
[21] PCH_LA_DATAP1 PCH_LA_DATAP1 AM49
PCH_LA_DATAP2 LVDSA_DATA1
FDI_LSYNC1 BB10 FDI_LSYNC1 [2] [21] PCH_LA_DATAP2 AK49 LVDSA_DATA2
11/12 short AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
SUS_PWR_ACK_R R584 *0_4/S A18 DSWVREN PCH_LB_CLK# AF40
DSW VRMEN [21] PCH_LB_CLK# LVDSB_CLK#
short0402 R546 *0_4/S RSMRST# [21] PCH_LB_CLK PCH_LB_CLK AF39 AP47
System Power Management

LVDSB_CLK DDPC_AUXN
DDPC_AUXP AP49
R590 *0_4 SUSACK#_R C12 E22 R545 *0_4/S DPWROK 5/12: modify PCH_LB_DATAN0 AH45 AT38
[29] SUSACK# SUSACK# DPW ROK [21] PCH_LB_DATAN0 LVDSB_DATA#0 DDPC_HPD
12/13 short [21] PCH_LB_DATAN1 PCH_LB_DATAN1 AH47
XDP_DBRST# PCH_LB_DATAN2 LVDSB_DATA#1
[2] XDP_DBRST# [21] PCH_LB_DATAN2 AF49 LVDSB_DATA#2 DDPC_0N AY47
C K3 B9 PCIE_WAKE# AF45 AY49 C
SYS_RESET# W AKE# PCIE_WAKE# [24,26,27] LVDSB_DATA#3 DDPC_0P
10/11 add C2003 1U/10V_4 AY43
PCH_LB_DATAP0 DDPC_1N
(+3V) [21] PCH_LB_DATAP0 AH43 LVDSB_DATA0 DDPC_1P AY45
SYS_PWROK R630 *0_4/S SYS_PWROK_R P12 N3 CLKRUN# PCH_LB_DATAP1 AH49 BA47
SYS_PW ROK CLKRUN# / GPIO32 CLKRUN# [29] [21] PCH_LB_DATAP1 LVDSB_DATA1 DDPC_2N
short0402 [21] PCH_LB_DATAP2 PCH_LB_DATAP2 AF47 BA48
R312 *0_4 LVDSB_DATA2 DDPC_2P
(+3VS5) AF43 LVDSB_DATA3 DDPC_3N BB47
R336 *0_4/S EC_PWROK_R L22 G8 TP44 BB49
[29] EC_PWROK PW ROK SUS_STAT# / GPIO61 DDPC_3P
11/12 short
(+3VS5)
EC_PWROK_R R334 *0_4/S APWROK_R L10 N14 PCH_SUSCLK_L R294 *0_4/S R670 0_6 PCH_CRT_B N48 M43
APW ROK SUSCLK / GPIO62 PCH_SUSCLK [29] [22] PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
12/13 short short0402 R669 0_6 PCH_CRT_G P49 M36
[22] PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
(+3VS5) TP39 R671 0_6 PCH_CRT_R T49
PM_DRAM_PWRGD [22] PCH_CRT_R CRT_RED
[2] PM_DRAM_PWRGD B13 DRAMPW ROK SLP_S5# / GPIO63 D10 SLP_S5 [29]
DDPD_AUXN AT45
R673 0_6 T39 AT43
CRT
[22] PCH_DDCCLK CRT_DDC_CLK DDPD_AUXP
RSMRST# C21 H4 R330 *0_4/S R672 0_6 M40 BH41
[29] RSMRST# RSMRST# SLP_S4# SUSC# [29] [22] PCH_DDCDATA CRT_DDC_DATA DDPD_HPD
11/12 short (+3VS5) DDPD_0N BB43
[29] SUS_PWR_ACK R578 *0_4/S SUS_PWR_ACK_R K16 F4 R620 *0_4/S SUSB# [29] PCH_HSYNC_R R675 0_6 M47 BB45
short0402 SUSW ARN#/SUSPW RDNACK/GPIO30 SLP_S3# PCH_VSYNC_R R674 0_6 CRT_HSYNC DDPD_0P
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
[29] DNBSWON# R570 *0_4/S DNBSWON#_R E20 G10 R308 *0_4 SLP_A# [29] BF42
short0402 PW RBTN# SLP_A# DAC_IREF DDPD_2N
T43 DAC_IREF DDPD_2P BE42
(DSW) 9/9 remove in BOM C1013 6.8P/50V_4 PCH_CRT_B T42 BJ42
R269 *0_4 AC_PRESENT_R R574 *0_4 CRT_IRTN DDPD_3N
[29] AC_PRESENT H20 ACPRESENT / GPIO31 SLP_SUS# G16 SLP_SUS# [29] DDPD_3P BG42
C1014 6.8P/50V_4 PCH_CRT_G R227
(+3VS5) 1K/F_4 CougarPoint_Rev_0p7
8/26 A-->B modify PM_BATLOW# E10 AP14 PM_SYNC [2] C1015 6.8P/50V_4 PCH_CRT_R fcbga989-intel-cougarpoint
BATLOW # / GPIO72 PMSYNCH AJSLH9D0T13
(+3VS5) 9/8 EMI(near PCH) IC CTRL(989P)COUGARPOINT QMVY TOP B/S
B PM_RI# A10 K14 SLP_LAN# PCH PS - AJSLH9D0T13 B
RI# SLP_LAN# / GPIO29
CougarPoint_Rev_0p7 [7,10,21,22,23,27,28,36] +5V

fcbga989-intel-cougarpoint [2,7,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V
AJSLH9D0T13 [2,7,8,9,10,14,24,29,31,33,35,36,38] +3VS5
IC CTRL(989P)COUGARPOINT QMVY TOP B/S [7,21,27,28,29,30,31] +3VPCU
PCH PS - AJSLH9D0T13 [7,10] +3V_DSW
[7,10,29] +3V_RTC
PCH Pull-high/low(CLG) INT LVDS & CRT disable INT HDMI disable (DIS only remove) System PWR_OK(CLG) DPWROK FOR DSW
PM_RI# R610 10K_4

+3VS5 (DIS only remove)
3/26 DB change net name. DPB_LANE0_N
DPB_LANE0_P IN_D2#
IN_D2
[22]
[22]
+3VS5
C399 *0.1U/10V_4 ** 5/12: modify +3VPCU

+3VPCU
5
+3V R209 2.2K_4 CTRL_CLK DPB_LANE1_N
IN_D1# [22] +3V_DSW
PM_BATLOW# R350 *8.2K_4 R197 2.2K_4 CTRL_DATA DPB_LANE1_P 2 R554 R553
DPB_LANE2_N IN_D1 [22] SYS_PWROK IMVP_PWRGD [39]
4 *10K_4 *10K_4
IN_D0# [22]
PCIE_WAKE# R613 10K_4 R235 2.37K/F_4 LVD_IBG DPB_LANE2_P 1 EC_PWROK D21
IN_D0 [22]
DPB_LANE3_N +3VS5 DPWROK
IN_CLK# [22]
SLP_LAN# R268 *10K_4 DPB_LANE3_P U8
IN_CLK [22]
3
R204 33_4 PCH_HSYNC_R *TC7SH08FU *RB500V-40
[22] PCH_HSYNC
3
SUS_PWR_ACK R577 10K_4 R203 33_4 PCH_VSYNC_R R319 C595
[22] PCH_VSYNC
8/26 A-->B modify 100K_4 D20 *0.1U/10V_4
AC_PRESENT_R R270 10K_4 2 2 add cap to
INT HDMI Detect Function +3VPCU
*RB500V-40
timing tune
A +3V 4/29 modify R506 0_4 R320 0_4 Q48 Q49 A
PD Res place close to PCH
1
*PDTC144EU *2N7002
1
CLKRUN# R639 8.2K_4 PCH to Res routeing 50 ohm Impedance. 9/6 delete a short net in"EC_PWROK"
XDP_DBRST# R624 10K_4
Res to connector filter routeing 37.5ohm Impedance. DPB_HPD_Q 1 3 HDMI_HPD_CON [22]
R599 *1K_4 R202 150/F_4 PCH_CRT_B
Q45
+3V_RTC R565 330K_4 DSWVREN R568 *330K_4
PROJECT : TWH
2
RSMRST# R547 10K_4 R201 150/F_4 PCH_CRT_G R511 *2N7002 R496

*100K_4 *100K_4 On Die DSW VR Enable
SYS_PWROK R313 *100K_4 R200 150/F_4 PCH_CRT_R +5V
High = Enable (Default) Size Document Number Rev
9/10 change from 10K to 100K Low = Disable Custom A
PCH 1/6 (Host/Display)
9/28 change to NC NB5 Date: Tuesday, December 14, 2010 Sheet 6 of 40
5 4 3 2 1
5 4 3 2 1
RTC_X1
Cougar Point (HDA,JTAG,SATA)
A20
U24A
RTCX1 FW H0 / LAD0 C38

A38
4/29 DB change net name.
3/26 DB change net name.
LAD0 [27,29]
RTC Clock 32.768KHz 07
LPC
FW H1 / LAD1 LAD1 [27,29]
RTC_X2 C20 B37 LAD2 [27,29]
RTCX2 FW H2 / LAD2 C602 18P/50V_4 RTC_X1
FW H3 / LAD3 C37 LAD3 [27,29]
RTC_RST# D20 RTCRST#
2
1
FW H4 / LFRAME# D36 LFRAME# [27,29]
RTC
SRTC_RST# G22 SRTCRST# PCH_DRQ#0 Y5 R567
LDRQ0# E36 TP37
R281 1M_4 SM_INTRUDER# K22 K36 PCH_DRQ#1 32.768KHZ 10M_4
D
+3V_RTC INTRUDER# LDRQ1# / GPIO23 TP36 D
(+3V)
3
4
PCH_INVRMEN C17 V5 SERIRQ R324 8.2K_4 +3V C601 18P/50V_4 RTC_X2
INTVRMEN SERIRQ
SERIRQ [29]
AM3 SATA_RXN0_C
ACZ_BCLK SATA0RXN SATA_RXP0_C SATA_RXN0 [28]
N34 HDA_BCLK SATA0RXP AM1 SATA_RXP0 [28]
AP7 SATA_TXN0_C
SATA0TXN SATA_TXN0 [28] HDD0 (SATA3 6.0Gb/s)
SATA 6G
ACZ_SYNC L34 AP5 SATA_TXP0_C
HDA_SYNC SATA0TXP SATA_TXP0 [28]
SPKR T10 AM10 SATA_RXN1_C
[23] SPKR
ACZ_RST#
SPKR SATA1RXN
SATA1RXP AM8 SATA_RXP1_C
SATA_TXN1_C
SATA_RXN1 [28]
SATA_RXP1 [28]
RTC Circuitry(RTC) 30mils
K34 AP11
HDA_RST# SATA1TXN
AP10 SATA_TXP1_C SATA_TXN1 [28] ODD (SATA1 1.5Gb/s) +3V_RTC
SATA1TXP SATA_TXP1 [28]
R298
RTC_RST#
IHDA
[23] ACZ_SDIN0 E34 HDA_SDIN0 SATA2RXN AD7 8/26 A-->B modify 5/12: modify
SATA2RXP AD5
1
TP1004 G34 AH5 8/31 delete excess AC coupling C 20K/F_4
HDA_SDIN1 SATA2TXN R273 *0_6
SATA2TXP AH4 C635,C634,C409,C410 +3V_DSW FOR DSW
C34 C390 J2
HDA_SDIN2 C404,C405,C633,C632 1U/6.3V_4 *SOLDERJUMPER-2
9/3 delete net "ACZ_SDIN1" AB8
2
SATA3RXN R297
A34 HDA_SDIN3 SATA3RXP AB10
+3V_RTC_2
SATA
12/13 moved from p.26 AF3 +3VPCU R286 *0_6/S 20K/F_4
SATA3TXN SRTC_RST#
SATA3TXP AF1 DG recommended that AC coupling capacitors should be
+3VSUS ACZ_SDOUT A36 +3V_RTC_0 R275 1K_4 +3V_RTC_1
HDA_SDO close to the connector (<100 mils) for optimal signal quality.
1
SATA4RXN Y7
1
R5001 10K/F_4 (+3V) Y5 11/12 short
GPIO33 SATA4RXP CN17 D10 C389 C387 J1
C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3
AD1 BAT_CONN BAT54C 1U/6.3V_4 1U/6.3V_4 *SOLDERJUMPER-2
(+3VS5)
2
R652 *0_4/S SATA4TXP
[26] USB3_SMI# N32
2
HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
C C
11/12 short SATA5RXP Y1 RTC Power trace width 20mils. 4/20 DB add.
SATA5TXN AB3
TP47 PCH_JTAG_TCK_R J3 AB1 RTC_RST# R280 *0_6 SRTC_RST#
JTAG_TCK SATA5TXP
TP50 PCH_JTAG_TMS H7 Y11 3/26 DB modify for placement. 10/8 add for EMI
JTAG_TMS SATAICOMPO
JTAG
PCH_JTAG_TDI_R K5 Y10 SATA_COMP R302 37.4/F_4 R242 33_4 ACZ_BCLK

TP51 JTAG_TDI SATAICOMPI +1.05V [23] BIT_CLK_AUDIO
HDA Bus(CLG) PCH JTAG Debug(CLG)
TP52 PCH_JTAG_TDO_R H1 JTAG_TDO
SATA3RCOMPO AB12 C2001 5/3 : modify
10P/50V_4 R503 10K_4 Q46 +3VS5
+5V
2
AB13 SATA3_COMP R303 49.9/F_4 2N7002K
SATA3COMPI
[23] ACZ_SYNC_AUDIO R520 33_4 1 3 ACZ_SYNC

[29] PCH_SPI_CLK PCH_SPI_CLK T3 AH1 SATA3_RBIAS R606 750/F_4 4/29: modify
SPI_CLK SATA3RBIAS
PCH_SPI_CS0# Y14 R2005 10P/50V_4
[29] PCH_SPI_CS0# SPI_CS0#
SATA_LED# [27] 1M_4 C557 R347 R343 R358
+3VPCU R641 *10K_4 PCH_SPI_CS1# T1 *210/F_4 *210/F_4 *210/F_4
SPI_CS1#
SPI
P3 R640 10K_4 R522 33_4 ACZ_RST#

SATALED# +3V [23] ACZ_RST#_AUDIO
10/8 Intel PDG PCH_JTAG_TMS
PCH_SPI_SI (+3V) R321 10K_4 R535 33_4 ACZ_SDOUT PCH_JTAG_TDI_R
[29] PCH_SPI_SI V4 SPI_MOSI SATA0GP / GPIO21 V14 [23] ACZ_SDOUT_AUDIO
PCH_JTAG_TDO_R
PCH_SPI_SO (+3V) BBS_BIT0 PCH_JTAG_TCK_R
[29] PCH_SPI_SO U3 SPI_MISO SATA1GP / GPIO19 P1
9/3 delete MDC function support
CougarPoint_Rev_0p7
"ACZ_BCLK"-R246-"BIT_CLK_MDC" R331 R327 R346 R329
PCH PS - AJSLH9D0T13
fcbga989-intel-cougarpoint "ACZ_SYNC"-R214-"ACZ_SYNC_MDC" *100/F_4 *100/F_4 *100/F_4 *51_4
AJSLH9D0T13 "ACZ_RST#"-R527-"ACZ_RST#_MDC"
B
PCH Strap Table IC CTRL(989P)COUGARPOINT QMVY TOP B/S "ACZ_SDOUT"-R539-"ACZ_SDOUT_MDC" B
Pin Name Strap description Sampled Configuration Circuit

Different from 0 = Default (weak pull-down 20K) SPKR
Vender Size P/N 10/13 remove all R (Intel confirmed)
SPKR No reboot mode setting PWROK 1 = Setting to No-Reboot mode R636 *1K_4 +3V
Calpella EON 4MB AKE39FN0Q00 (EN25F32-100HIP)
0 = "top-block swap" mode R518 *1K_4
PCI_GNT3# [8]
PCH SPI ROM(CLG)
GNT3# / GPIO55 Top-Block Swap Override PWROK 1 = Default (weak pull-up 20K) +3V R514 10K_4 Bios request, for can't boot Capella 4/23. Winbond 4MB AKE391P0N00 (W25Q32BVSSIG)
PCH_INVRMEN
Socket DG008000031 +3V
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up R566 330K_4 +3V_RTC
Flash Descriptor Security 0 = Override 8/26 A-->B modify U22

HDA_DOCK_EN#/GPIO33 Only for Interposer PWROK 1 = Default (weak pull-up 20K) GPIO33 R540 *1K_4 PCH_SPI_CS0# 1 8
GPIO33_E [29] CE# VDD
PCH_SPI_CLK R603 *0_4 PCH_SPI1_CLK_R 6
PCH_SPI_SI R628 *0_4 PCH_SPI1_SI_R SCK
[Need external pull-down for LPC BIOS] 5 SI
GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK GNT1# GNT0# Boot Location Default weak pull-up on GNT0/1# PCH_SPI_SO R548 *0_4 PCH_SPI1_SO_R 2 7 R517 *3.3K_4
BBS_BIT0 SO HOLD#
1 1 SPI
Different from 0 0 LPC R602 *1K_4 3 4
R513 *1K_4 C645 W P# VSS C559
GPIO19 Calpella Boot BIOS Selection 0 [bit-0] PWROK BBS_BIT1 [8]
*22P/50V_4 *SPI Flash Socket *0.1U/10V_4
Should not be pull-down
GNT2# / GPIO53 ESI strap (Server only) PWROK (weak pull-up 20K) USE GPIO PIN
Intel Anti-Theft HDD protection +3V R549 *3.3K_4
NV_ALE Only for Interposer PWROK 0 = Disable (Internal pull-down 20kohm) +1.8V R608 *1K_4
NV_ALE [8]
4/29 modify R616 2.2K_4 R607 4.7K_4
NV_CLE DMI Termination voltage PWROK weak pull-down 20kohm +1.8V NV_CLE [8]N.A at CPT EDS 0.7
H_SNB_IVB# [2] [10] +V3.3A_1.5A_HDA_IO
A
[2,6,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V A
HDA_SYNC On-Die PLL VR Voltage Select RSMRST 0 = Support by 1.8V (weak pull-down)
+3VS5 R215 1K_4 ACZ_SYNC [6,21,27,28,29,30,31] +3VPCU
1 = Support by 1.5V
[6,10] +3V_DSW
0 = Override 8/26 A-->B modify [6,10,29] +3V_RTC
HDA_SDO Flash Descriptor Security PWROK 1 = Default (weak pull-up 20K) ACZ_SDOUT R544 *1K_4
[29] GPIO33_E +V3.3A_1.5A_HDA_IO [4,10,36,38] +1.8V
4/29 reserve.
GPIO8 Integrated Clock Chip Enable RSMRST# Should be pull-down (weak pull-up 20K) R611 *1K_4
ICC_EN# [9] PROJECT : TWH
Different from 0 = Disable
R617 *1K_4
GPIO28 Calpella On-die PLL Voltage Regulator RSMRST# 1 = Enable (Default) PLL_ODVR_EN [9]
0 = Default (weak pull-down 20K) Size Document Number Rev

SPI_MOSI iTPM function Disable APWROK 1 = Enable PCH_SPI_SI R604 1K_4 Custom A
PCH 2/6 (HDA/RTC/SATA/SPI)
+3V
NB5 Date: Wednesday, December 15, 2010 Sheet 7 of 40
5 4 3 2 1
5 4 3 2 1
11/8
change net name to "PCH_GPIO4"
delete "DGPU_IDLE_INT#" pull-hi
PCI/USBOC# Pull-up(CLG)
Cougar Point-M (PCI,USB,NVRAM)
BG26
U24E
NV_CE#0
NV_CE#1
AY7
AV7
AU3
[27]
[27]
PCIE_RXN1
PCIE_RXP1
Cougar Point-M (PCI-E,SMBUS,CLK)
BG34
BJ34
U24B
PERN1 (+3VS5)
E12 SMBALERT#
08
TP1 NV_CE#2 C385 0.1U/10V_4 PCIE_TXN1_C PERP1 SMBALERT# / GPIO11
+3V
BJ26
TP2 NV_CE#3
BG4 WLAN [27] PCIE_TXN1
C379 0.1U/10V_4 PCIE_TXP1_C
AV32
PETN1 SMB_PCH_CLK
BH25 [27] PCIE_TXP1 AU32 H14
TP3 PETP1 SMBCLK
BJ16 AT10
PCI_PIRQA# R198 8.2K_4 TP4 NV_DQS0 SMB_PCH_DAT
BG16 BC8 [24] PCIE_RXN2_LAN BE34 C9
PCI_PIRQB# R531 8.2K_4 TP5 NV_DQS1 PERN2 SMBDATA
AH38 [24] PCIE_RXP2_LAN BF34
PCI_PIRQC# R234 8.2K_4 TP6 C345 0.1U/10V_4 PCIE_TXN2_LAN_C PERP2
AH37 AU2 LAN [24] PCIE_TXN2_LAN BB32
SMBUS
PCI_PIRQD# R238 8.2K_4 TP7 NV_DQ0 / NV_IO0 C353 0.1U/10V_4 PCIE_TXP2_LAN_C PETN2
AK43
TP8 NV_DQ1 / NV_IO1
AT4 [24] PCIE_TXP2_LAN AY32
PETP2 (+3VS5)
D AK45 AT3 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH [2] D
TP9 NV_DQ2 / NV_IO2 SML0ALERT# / GPIO60
3/26 DB change C18
TP10 NV_DQ3 / NV_IO3
AT1 [26] PCIE_RXN3_USB3 BG36
PERN3
+3V N30 AY3 BJ36 C8 SMB_ME0_CLK
RP12
Part reference. TP11 NV_DQ4 / NV_IO4 [26] PCIE_RXP3_USB3
C355 0.1U/10V_4 PCIE_TXN3_USB3_C PERP3 SML0CLK
H3 AT5 AV34
10 1 PCH_GPIO4 AH12
AV3
USB3.0 [26]
[26]
PCIE_TXN3_USB3
PCIE_TXP3_USB3 C358 0.1U/10V_4 PCIE_TXP3_USB3_C AU34
PETN3
G12 SMB_ME0_DAT
MPC_PWR_CTRL# TP13 NV_DQ6 / NV_IO6 PETP3 SML0DATA
9 2 AM4 AV1
NVRAM
BT_COMBO_EN# TP14 NV_DQ7 / NV_IO7
8 3 AM5 BB1 BF36
TP15 NV_DQ8 / NV_IO8 PERN4
7 4 Y13
BA3 8/26 A-->B modify BE36
PERP4 (+3VS5)
LCD_BK 6 5 K24 BB5 AY34 C13 SML1ALERT#_R TP40
TP17 NV_DQ10 / NV_IO10 PETN4 SML1ALERT# / PCHHOT# / GPIO74
L24 BB3 BB34 (+3VS5)
10K_10P8R_6 TP18 NV_DQ11 / NV_IO11 PETP4 SMB_ME1_CLK
AB46 BB7 E14
TP19 NV_DQ12 / NV_IO12 SML1CLK / GPIO58
AB45 BE8 BG37 (+3VS5)
TP20 NV_DQ13 / NV_IO13 PERN5 SMB_ME1_DAT
3/26 DB change BD4 BH37 M16
RSVD
PCI-E*
+3VS5 NV_DQ14 / NV_IO14 PERP5 SML1DATA / GPIO75
Part reference. NV_DQ15 / NV_IO15 BF6 AY36 PETN5
RP13 BB36
USB_OC6# NV_ALE PETP5
10 1 B21 AV5 NV_ALE [7]
USB_OC4# USB_OC0# TP21 NV_ALE NV_CLE
9 2 M20 TP22 NV_CLE AY1 NV_CLE [7] BJ38 PERN6
USB_OC1# 8 3 USB_OC7# AY16 BG38
USB_OC2# USB_OC5# TP23 PERP6 CL_CLK_R
Controller
7 4 BG46 TP24 NV_RCOMP AV10 AU36 PETN6 CL_CLK1 M7 TP43
USB_OC3# 6 5 AV36 PETP6
NV_RB# AT8
Link
10K_10P8R_6 BG40 T11 CL_DAT_R TP48
PERN7 CL_DATA1
BE28 TP25 NV_RE#_WRB0 AY5 BJ40 PERP7
BC30 TP26 NV_RE#_WRB1 BA2 AY40 PETN7
BE32 BB40 P10 CL_RST#_R TP49
TP27 PETP7 CL_RST1#
MPC Switch Control BJ32 TP28 NV_WE#_CK0 AT12
BC28 TP29 NV_WE#_CK1 BF3 BE38 PERN8
Low = MPC ON BE30 TP30 BC38 PERP8
MPC_PWR_CTRL# High = MPC OFF (Default) BF32 TP31 8/26 A-->B modify AW38 PETN8
BG32 TP32 USBP0N C24 AY38 PETP8 (+3VS5)
AV26 A24 M10 CLK_PEGA_REQ#
MPC_PWR_CTRL# R521 *1K_4 TP33 USBP0P PEG_A_CLKRQ# / GPIO47
BB26 TP34 USBP1N C25 USBP1- [23]
AU28 B25 USBP1+ [23] USB2.0 EXTERNAL USB2.0 CLK_PCH_SRC0N Y40
C TP35 USBP1P CLK_PCH_SRC0P CLKOUT_PCIE0N CLK_PCH_PEGAN C
AY30 TP36 USBP2N C26 USBP2- [26] Y39 CLKOUT_PCIE0P CLKOUT_PEG_A_N AB37
AU26 A26 USBP2+ [26] USB2.0 USB2.0/USB3.0 COMBO AB38 CLK_PCH_PEGAP
TP37 USBP2P CLK_PCIE_REQ0# CLKOUT_PEG_A_P
AY26 TP38 USBP3N K28 J2 PCIECLKRQ0# / GPIO73
AV28 TP39 USBP3P H28
AW30 TP40 USBP4N E28 USBP4- [26] (+3VS5) CLKOUT_DMI_N AV22 CLK_CPU_BCLKN [2]
D28 USBP4+ [26] USB2.0 USB2.0/USB3.0 COMBO CLK_PCH_SRC2N AB49 AU22 CLK_CPU_BCLKP [2]
USBP4P CLK_PCH_SRC2P CLKOUT_PCIE1N CLKOUT_DMI_P
USBP5N C28 AB47 CLKOUT_PCIE1P
USBP5P A28
C29 CLK_PCIE_REQ1# M1
CLOCKS AM12
USBP6N PCIECLKRQ1# / GPIO18 CLKOUT_DP_N CLK_DPLL_SSCLKN [2]
PCI_PIRQA# USBP6P
B29 HM65 Port6 & Port7 CLKOUT_DP_P
AM13 CLK_DPLL_SSCLKP [2]
K40
PIRQA# USBP7N
N28 (+3V)
PCI_PIRQB# K38 M28 are disable AA48
PCI_PIRQC# PIRQB# USBP7P CLKOUT_PCIE2N CLK_BUF_PCIE_3GPLL#
H38 L30 TP1001 9/3 delete BT function (USB) AA47 BF18
PCI
PCI_PIRQD# PIRQC# USBP8N CLKOUT_PCIE2P CLKIN_DMI_N CLK_BUF_PCIE_3GPLL

G38
PIRQD# USBP8P
K30 TP1002 Bluetooth delete net "USB8+/-" CLK_PCIE_REQ2# CLKIN_DMI_P
BE18
G30 USBP9- [21] V10
BT_COMBO_EN# USBP9N PCIECLKRQ2# / GPIO20
[27] BT_COMBO_EN# C46
REQ1# / GPIO50 (+3V) USBP9P
E30 USBP9+ [21] Camera CLK_BUF_BCLK_N
C44 (+3V) C30 USBP10- [27] (+3V) BJ30
USB
REQ2# / GPIO52 USBP10N CLKIN_GND1_N CLK_BUF_BCLK_P

E40
REQ3# / GPIO54 (+3V) USBP10P
A30 USBP10+ [27] WLAN Y37
CLKOUT_PCIE3N CLKIN_GND1_P
BG30
USBP11N
L32 Y36
CLKOUT_PCIE3P 3/26 DB del external
BBS_BIT1 D47 K32
[7] BBS_BIT1 GNT1# / GPIO51 (+3V) USBP11P CLK_PCIE_REQ3# CLK_BUF_DREFCLK#
clock generator.
E42 G32 A8 G24
PCI_GNT3# GNT2# / GPIO53 (+3V) USBP12N USBP12- [25] PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLK_BUF_DREFCLK
[7] PCI_GNT3# F46
GNT3# / GPIO55 (+3V) USBP12P
E32 USBP12+ [25] Card Reader CLKIN_DOT_96P
E24
USBP13N
C32 (+3VS5)
MPC_PWR_CTRL# A32 Y43
LCD_BK USBP13P CLKOUT_PCIE4N CLK_BUF_DREFSSCLK#
[21] LCD_BK G42 (+3V) Y45 AK7
PIRQE# / GPIO2 CLKOUT_PCIE4P CLKIN_SATA_N CLK_BUF_DREFSSCLK
G40 (+3V) AK5
PCH_GPIO4 PIRQF# / GPIO3 USB_BIAS CLK_PCIE_REQ4# CLKIN_SATA_P
C42 (+3V) C33 L12
DGPU_IDLE_INT# PIRQG# / GPIO4 USBRBIAS# PCIECLKRQ4# / GPIO26
[17] DGPU_IDLE_INT# D44 (+3V)
PIRQH# / GPIO5 R541 CLK_PCH_14M
11/8 delete R2001 (+3VS5) REFCLK14IN
K45
B33 22.6/F_4 V45
PCI_PME# USBRBIAS CLKOUT_PCIE5N
Bios swap GPIO 4/23. TP46 K10
PME#
Bios swap GPIO 4/23. V46
CLKOUT_PCIE5P
H45 CLK_PCI_FB
PCI_PLTRST# USB_OC0# CLKIN_PCILOOPBACK C311
B C6 A14 [9] BOARD_ID0 L14 B
PLTRST# (+3VS5) OC0# / GPIO59
K20 USB_OC1# PCIECLKRQ5# / GPIO44 18P/50V_4
(+3VS5) OC1# / GPIO40
2
B17 USB_OC2# (+3VS5)
CLK_PCI_TPM_R H49
(+3VS5) OC2# / GPIO41
C16 USB_OC3# CLK_PCH_PEGBN AB42 R206 Y1 8/26 A-->B modify change FP
TP76 CLKOUT_PCI0 (+3VS5) OC3# / GPIO42 CLKOUT_PEG_B_N
TP34 CLK_PCI_CARD_R H43 L16 USB_OC4# CLK_PCH_PEGBP AB40 V47 XTAL25_IN 1M_4 25MHZ
CLK_PCI_FB R230 22_4 J48
CLKOUT_PCI1 (+3VS5) OC4# / GPIO43
A16 USB_OC5# CLKOUT_PEG_B_P XTAL25_IN
V49 XTAL25_OUT
1
K42
D14 USB_OC6# CLK_PEGB_REQ# E6
XTAL25_OUT C312
9/5 remove R213 in BOM CLK_PCI_FB_R H40
C14 USB_OC7# PEG_B_CLKRQ# / GPIO56 18P/50V_4
(+3VS5)
[27] CLK_33M_DEBUG R213 22_4 CLK_PCI_LPC_R 9/4 Change net name [27] INT_BT_COMBO_EN# V40
CougarPoint_Rev_0p7 CLKOUT_PCIE6N XCLK_RCOMP R502 90.9/F_4
"BOARD_ID1" to V42 Y47 +1.05V
R225 22_4 CLK_PCI_EC_R fcbga989-intel-cougarpoint CLKOUT_PCIE6P XCLK_RCOMP
[29] CLK_33M_KBC "INT_BT_COMBO_EN#" [9] BOARD_ID2
AJSLH9D0T13 T13
IC CTRL(989P)COUGARPOINT QMVY TOP B/S PCIECLKRQ6# / GPIO45
(+3VS5) (+3V)
C1011 C1012 PCH PS - AJSLH9D0T13 V38 K43 CLK_FLEX0 R211 22_4
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_48M_CR [25]
18P/50V_4 18P/50V_4 V37
FLEX CLOCKS
CLKOUT_PCIE7P (+3V) CLK_FLEX1 R205 22_4
F47 CLK_25M_USB3.0 [26]
CLKOUTFLEX1 / GPIO65
9/8 EMI(near PCH) SMBus/Pull-up(CLG) CLK_REQ/Strap Pin(CLG) K12
PCIECLKRQ7# / GPIO46 (+3V)
+3V H47 CLK_FLEX2
(+3VS5) CLKOUTFLEX2 / GPIO66 R3025 *22_4 C2002
10/10 R638 mount TP41 AK14
CLKOUT_ITPXDP_N (+3V) Rb
4/20 modify CLK_PCIE_REQ1# R638 10K_4 AK13 K49 CLK_FLEX3 10P/50V_4
TP38 CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 TP2002
2N7002 CLK_PCIE_REQ2# R323 10K_4 10/8 add for EMI
[13,17,29] MBCLK2 1 3 SMB_ME1_CLK CLK_PCH_ITPN Remove Ra, Rb for UMA & SG.
+3VS5 CLK_PCH_ITPP CougarPoint_Rev_0p7 AJSLH9D0T13 9/11 add R1015, exchange 27M net
Q50 R586 2.2K_4 fcbga989-intel-cougarpoint IC CTRL(989P)COUGARPOINT QMVY TOP B/S
27MHz support DIS only.
PCH PS - AJSLH9D0T13 10/8 remove 27M circuit
CLK_PCIE_REQ0# R597 10K_4
2
CLK_PCIE_REQ3# R612 10K_4 3/26 DB change Part reference.

+3V +3VS5
CLK_PCIE_REQ4# R287 10K_4 PCIE Clock CLK_PCH_SRC0N 12/13 delete RP7
PLTRST#(CLG) [27] CLK_PCIE_WLANN SMBus/Pull-up(CLG)
2
+3VS5 R587 2.2K_4 CLK_PCH_SRC0P +3VS5

CLK_PEGB_REQ# R360 *10K_4
WLAN [27] CLK_PCIE_WLANP
R621 *0_4/S CLK_PCIE_REQ0#
[27] PCIE_CLKREQ_WLAN#
C406 *0.1U/10V_4 [13,17,29] MBDATA2 1 3 SMB_ME1_DAT CLK_PEGA_REQ# Ra R344 *10K_4 R333 1K_4 DRAMRST_CNTRL_PCH
SG : Rb ; UMA : Ra 3/26 DB change Part reference. 12/13 short
5
Q51 CLK_PEGA_REQ# Rb R328 *10K_4 [24] CLK_PCIE_LANN RP6 3 4 CLK_PCH_SRC2N R282 10K_4 SMBALERT#
A CLK_PEGB_REQ# R1111 10K_4 A
2 2N7002 LAN [24] CLK_PCIE_LANP 0_4P2R_04 1 2 CLK_PCH_SRC2P R351 2.2K_4 SMB_PCH_CLK
4 PLTRST# [24] PCIE_CLKREQ_LAN# R637 *0_4/S CLK_PCIE_REQ1# R337 2.2K_4 SMB_PCH_DAT
PCI_PLTRST# 1 4/29 modify CLK_BUF_BCLK_N R556 10K_4 R634 2.2K_4 SMB_ME0_CLK
SMB_PCH_DAT 3 1 SMB_RUN_DAT [12,13] CLK_BUF_BCLK_P R558 10K_4 3/26 DB change Part reference. R292 2.2K_4 SMB_ME0_DAT
U9 [14] CLK_PCIE_VGA# RP5 2 1 CLK_PCH_PEGAN R289 10K_4 SML1ALERT#_R
3
*TC7SH08FU R338 Q44 CLK_BUF_PCIE_3GPLL# R291 10K_4 GPU [14] CLK_PCIE_VGA 0_4P2R_04 4 3 CLK_PCH_PEGAP
100K_4 2N7002 R487 4.7K_4 CLK_BUF_PCIE_3GPLL R295 10K_4 [14] PCIE_CLKREQ_VGA# R345 *0_4/S
CLK_PEGA_REQ#
2
R352
+3V
R486 4.7K_4
CLK_BUF_DREFCLK#
CLK_BUF_DREFCLK
R258
R262
10K_4
10K_4 PROJECT : TWH
2
0_4 CLK_BUF_DREFSSCLK# R315 10K_4 [26] CLK_PCIE_USB3N RP8 2 1 CLK_PCH_PEGBN

PLTRST# PLTRST# [2,14,24,26,27,29] CLK_BUF_DREFSSCLK R314 10K_4 USB3.0 [26] CLK_PCIE_USB3P 0_4P2R_04 4 3 CLK_PCH_PEGBP
SMB_PCH_CLK 3 1 SMB_RUN_CLK [12,13] CLK_PCH_14M R216 10K_4
11/11 delete R359 Size Document Number Rev
Q43 CLOCK TERMINATION for FCIM Custom A
[2,6,7,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V PCH 3/6 (Clock/PCI/PCIE/USB)
2N7002 [2,6,7,9,10,14,24,29,31,33,35,36,38] +3VS5 NB5 Date: Tuesday, December 14, 2010 Sheet 8 of 40
5 4 3 2 1
5 4 3 2 1
09
+3V
Cougar Point (GPIO,VSS_NCTF,RSVD) RF_PWR_OFF# [27]
Clock Gen Power OK (CLG)
9/6 add "RF_PWR_OFF#" control from PCH
U24F
S_GPIO R363 100_4 T7 C40 GPIO68 R529 *10K_4 +3V 5/11 stuff R9144 R3017
BMBUSY# / GPIO0 TACH4 / GPIO68
(+3V) (+3V) 10K/F_4
SIO_EXT_SMI# A42 B41 GPIO69 R525 1.5K/F_4 3/26 DB del external
[29] SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69
4/29 modify (+3V) (+3V)
R524 *1.5K/F_4 +3V clock generator.
[29] SIO_EXT_SCI# SIO_EXT_SCI# H36 C41 DGPU_OPT_DIS#
TACH2 / GPIO6 TACH6 / GPIO70 DGPU_OPT_DIS#
BT_OFF# (+3V) (+3V) GPIO71
9/3 delete net "BT_OFF#" TP1003 E38 TACH3 / GPIO7 TACH7 / GPIO71 A40 11/12 modify DGPU_OPT_DIS#:
R3018
D ICC_EN# (+3V) Delete net "GPIO70",connect DGPU optimus / discrete circuit High : Optimus. D
[7] ICC_EN# C10 GPIO8 (+3V) *10K/F_4
(+3VS5) Low: Discrete.
LAN_DISABLE#_R C4 LAN_PHY_PW R_CTRL / GPIO12
RF_OFF# (+3VS5)
[27] RF_OFF# G2 GPIO15 A20GATE P4 EC_A20GATE [29]
(+3VS5) PECI AU16
Reserve R627 *0_4 ODD_PRSNT#_R U2
CPU/MISC
[28] ODD_PRSNT# SATA4GP / GPIO16
P5 EC_RCIN#
RCIN# EC_RCIN# [29]
(+3V)
R676 0_4 D40 AY11
GPIO
[14,29,37] DGPU_PWROK TACH0 / GPIO17 PROCPW RGD H_PWRGOOD [2]
BIOS_REC (+3V) PCH_THRMTRIP# R311 390_4
8/26 A-->B modify T5 SCLOCK / GPIO22 THRMTRIP# AY10 PM_THRMTRIP# [2,29] MFG-TEST GPIO Pull-up/Pull-down(CLG)
R677 0_4 BOARD_ID5 E8
(+3V) T14
[14,29] DGPU_HOLD_RST# GPIO24 / MEM_LED INIT3_3V# +3V
GPIO27 (+3VS5) +3VS5
E16 GPIO27 20101012 modify:
MFG_MODE R626 10K_4
R618 0_4 PLL_ODVR_EN_R (DSW) 1. Delete TACH0. LAN_DISABLE#_R R595 10K_4
[7] PLL_ODVR_EN P8 GPIO28
(+3VS5) NC_1 AH8 2. GPIO70 connect DGPU optimus / discrete setting. R601 *0_4
BOARD_ID3 K1 STP_PCI# / GPIO34 +3V
(+3V) NC_2 AK11
BOARD_ID4 K4 GPIO35 SIO_EXT_SCI# R228 10K_4
(+3V) NC_3 AH10
R353 0_4 DGPU_PWR_EN_R V8 SIO_EXT_SMI# R523 10K_4
[29,37,38] DGPU_PWR_EN SATA2GP / GPIO36
AK10 BT_OFF# R512 10K_4
FDI_OVRVLTG (+3V) NC_4 R307 0_4 EC_A20GATE R325 10K_4
M5 SATA3GP / GPIO37 11/13
P37 Bios swap GPIO 4/23. EC_RCIN# R355 10K_4
MFG_MODE (+3V) NC_5 SATA5GP R605 10K_4 delete
N2 SLOAD / GPIO38
(+3V) "GPIO70"
C DGPU_PRSNT# M3 DG rev0.9 suggest to TS_VSS connect to GND 4/23. +3V GPIO71 R530 1.5K/F_4 C
SDATAOUT0 / GPIO39 ODD_PRSNT#_R R642 10K_4
and R528
TEST_SET_UP V13
(+3V) BG2 S_GPIO R365 10K_4 DGPU_PWROK R217 *10K_4
SDATAOUT1 / GPIO48 VSS_NCTF_15 R364 *0_4
SATA5GP (+3V) 10/10 double pull high
[29] SATA5GP V3 SATA5GP / GPIO49 VSS_NCTF_16 BG48
DGPU_PWROK R226 *10K_4
SV_DET (+3V) GPIO27 R296 10K_4
D6 GPIO57 VSS_NCTF_17 BH3
(+3VS5)
VSS_NCTF_18 BH47
9/3 update net name from 4/29 modify
A4 VSS_NCTF_1 VSS_NCTF_19 BJ4 "DGPU_VC_EN" to "DGPU_PWROK"
OPTIMUS POWER control pin
A44 VSS_NCTF_2 VSS_NCTF_20 BJ44
DGPU_PWROK GPIO17
A45 BJ45 +3VS5
VSS_NCTF_3 VSS_NCTF_21 +3V
DGPU_HOLD_RST# GPIO24
A46
NCTF BJ46 RF_OFF# R596 1K_4
VSS_NCTF_4 VSS_NCTF_22 R341 *0_4 BIOS_REC R354 10K_4
DGPU_PWR_EN GPIO36
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5
Intel ME Crypto Transport Layer
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 Security (TLS) cipher suite
BIOS RECOVERY High = Disable (Default)
B3 VSS_NCTF_7 VSS_NCTF_25 C2 Low = Disable (Default) Low = Enable
High = Enable
B47 VSS_NCTF_8 VSS_NCTF_26 C48
BD1 VSS_NCTF_9 VSS_NCTF_27 D1
BD49 VSS_NCTF_10 VSS_NCTF_28 D49

B BE1 E1 +3V +3VS5 B
VSS_NCTF_11 VSS_NCTF_29
BE49 E49 R339 *0_4 TEST_SET_UP R322 10K_4 R594 100K_4 SV_DET R619 *10K_4
VSS_NCTF_12 VSS_NCTF_30
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
SV_SET_UP TEST DETECT
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
High = Strong (Default) Low = Default
CougarPoint_Rev_0p7 IC CTRL(989P)COUGARPOINT QMVY TOP B/S
fcbga989-intel-cougarpoint
AJSLH9D0T13 PCH PS - AJSLH9D0T13
10/11 no need pull high

+3V +3V
BOARD ID SETTING DGPU_PWR_EN_R R340 *200K/F_4 R326 100K_4 FDI_OVRVLTG R342 *1K_4
[8] BOARD_ID0 BOARD_ID0
Board ID ID0 ID1 ID2 ID3 ID4 ID5 9/6 delete net "BOARD_ID1"
BOARD_ID2 Low = Tx, Rx terminated to
[8] BOARD_ID2
0=LG DMI TERMINATION FDI TERMINATION LOW - Tx, Rx terminated
LG VOLTAGE OVERRIDE
same voltage (DC Coupling Mode)
VOLTAGE OVERRIDE to same voltage
(DEFAULT)
1=CB
R632 *10K_4 BOARD_ID0 R631 10K_4
UMA/Dis. 0=UMA 1 +3VS5
1=Dis. x R356 *10K_4 BOARD_ID1 R357 *10K_4

0=QLH/TWH
15.6"/ 14"
A 1=QLC/SWH 0 R589 10K_4 BOARD_ID2 R609 *10K_4 A
0=YES GFX Present +3V

MDC x [2,6,7,8,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V
1=NO R598 *10K_4 BOARD_ID3 R623 *10K_4 +3V Rb
R600 *100K_4 DGPU_PRSNT#
Ra
R625 10K_4
[2,6,7,8,10,14,24,29,31,33,35,36,38] +3VS5
0=NO 0
Dobly
1=YES
R622 10K_4 BOARD_ID4 R635 *10K_4
SG UMA
PROJECT : TWH
x R348 *10K_4 BOARD_ID5 R349 *10K_4
1=YES +3VS5 Stuff Ra Rb
Optiums
0=NO 10/11 correct board ID
4/29 modify NC Rb Ra Size
Custom
Document Number Rev
A
PCH 4/6 (GPIO)
5 4 3 2 1
5 4 3 2 1
U3001
11/12 add for CRT +5V *G910T21U +3V_LDO
Cougar Point-M (POWER) wave noise 3 Vin Vout 1
10
GND
12/13 short
U24J +1.05V_VCCUSBCORE +1.05V 1.3 A (60mils)
COUGAR POINT (POWER) C3009
*1U/6.3V_4
2
+1.05V R508 *0_8
+VCCACLK AD49 N26 R543 *0_8/S +1.05V +1.05V_PCH_VCC U24G
R283 *0_4/S VCCACLK VCCIO[29] R301 +VCCA_DAC_1_2
+3VS5 +3V_LDO
VCCIO[30] P26
R288 *0_4 +VCCPDSW T16 C571 AA23 U48 +3V
+3V_DSW VCCDSW 3_3 VCCCORE[1] VCCADAC
3mA (10mils) P28 1U/6.3V_4 119mA (20mils) 0.002/F_1206 AC23 1mA (10mils) L24
C408 VCCIO[31] C350 C361 VCCCORE[2]
AD21
CRT
PCH_VCCDSW +3VS5 VCCCORE[3]
5/12: modify C383 V12 DCPSUSBYP VCCIO[32] T27 1U/6.3V_4 1U/6.3V_4 AD23 VCCCORE[4] VSSADAC U47 HCB1608KF-181T15/1.5A_6
D 0.1U/10V_4 AF21 D
*0.1U/10V_4 R267 *0_6/S VCCCORE[5] C523 10U/6.3VS_6
T29 AF23
VCC CORE
+3V_SUS_CLKF33 T38 VCCIO[33] VCCCORE[6]
VCC3_3[5] AG21 VCCCORE[7]
10/8 remove for leakage AG23 C525 0.1U/10V_4
+3V_VCCPUSB VCCCORE[8]
4/29: modify VCCSUS3_3[7] T23 C360 AG24 VCCCORE[9]
BH23 0.1U/10V_4 AG26 C524 0.01U/25V_4
+1.05V +VCCAPLL_CPY_PCH VCCAPLLDMI2 C370 C349 VCCCORE[10]
VCCSUS3_3[8] T24 AG27 VCCCORE[11]
L30 +VCCDPLL_CPY AL29 10U/6.3VS_6 1U/6.3V_4 AG29 1mA (10mils) R489 *0_8 12/9
VCCIO[14] VCCCORE[12]
USB
V23 R264 *0_6/S AJ23 0805 FP
VCCSUS3_3[9] VCCCORE[13] +VCCALVDS +3V
AJ26 VCCCORE[14]
*10uH/100mA_8 +VCCSUS1 AL24 V24 AJ27 Ra
C603 DCPSUS[3] VCCSUS3_3[10] C346 VCCCORE[15] R561 *0_4/S
AJ29 VCCCORE[16] VCCALVDS AK36
*10U/6.3V_6 P24 +3V_VCCAUBG 0.1U/10V_4 +1.05V +1.05V_PCH_VCCDPLL_EXP AJ31 Rb 12/13 short
C367 VCCSUS3_3[6] R274 VCCCORE[17] R562 *0_4
VSSALVDS AK37
+1.05V *1U/6.3V_4 AA19 VCCASW [1] +VCCAUPLL R259 *0_6/S
VCCIO[34] T26 +1.05V 60mA (10mils)
R569 *0_6/S AA21 *0_6/S Ra
VCCASW [2] +VCC_TX_LVDS L29 +1.8V
VCCTX_LVDS[1] AM37
AA24 M26 +5V_PCH_VCC5REFSUS +1.05V +1.05V_VCCAPLL_EXP AN19 0.1uH/250mA_8
VCCASW [3] V5REF_SUS L31 VCCIO[28]
AM38
LVDS
+1.05V +1.05V_VCCEPW VCCTX_LVDS[2]
1.01A (60mils) AA26 VCCASW [4] Rb
R249 AN23 +VCCA_USBSUS C365 *1U/6.3V_4 AP36 R551 *0_4
DCPSUS[4] *1uH/25mA_6 VCCTX_LVDS[3]
AA27 VCCASW [5]
AN24 +3V_VCCPSUS C604 AP37 C584 22U/6.3VS_8
Clock and Miscellaneous

0.002/F_1206 VCCSUS3_3[1] *10U/6.3V_6 VCCTX_LVDS[4]
AA29 VCCASW [6] BJ22 VCCAPLLEXP
C351 C369 C352 SG & UMA : Ra C581 0.01U/25V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 AA31 VCCASW [7] DIS : Rb C582 0.01U/25V_4
AC26 P34 +5V_PCH_VCC5REF
VCCASW [8] V5REF +1.05V +1.05V_VCCIO AN16 VCCIO[15]
C AC27 11/12 short R257 2.925 A (140mils) +3V_VCC_GIO +3V C
VCCASW [9]
VCCSUS3_3[2] N20 AN17 VCCIO[16]
PCI/GPIO/LPC
AC29 V33 R243 *0_6/S
HVCMOS
C340 C341 VCCASW [10] 0.002/F_1206 VCC3_3[6]
VCCSUS3_3[3] N22 119mA (15mils)
22U/6.3VS_8 22U/6.3VS_8 AC31 C330 C334 AN21 V34
VCCASW [11] +3V_VCCPSUS R290 *0_6/S 1U/6.3V_4 1U/6.3V_4 VCCIO[17] VCC3_3[7] C333
VCCSUS3_3[4] P20 +3VS5
11/12 short AD29 AN26 0.1U/10V_4
VCCASW [12] VCCIO[18]
VCCSUS3_3[5] P22
AD31 C366 AN27 42mA (10mils)
VCCASW [13] 1U/6.3V_4 VCCIO[19]
VCCIO
W 21 AA16 266mA (20mils) AP21 AT16 +VCCAFDI_VRM +1.1V_VCC_DMI +1.05V
VCCASW [14] VCC3_3[1] C329 C356 C344 VCCIO[20] VCCVRM[3]
W 23 W 16 +3V_VCCPCORE R332 *0_6/S 10U/6.3VS_6 1U/6.3V_4 1U/6.3V_4 AP23 AT20 R279 *0_4/S
DMI
VCCASW [15] VCC3_3[8] +3V VCCIO[21] VCCDMI[1]
W 24 T34 AP24 +1.1V_VCC_DMI_CCI
VCCASW [16] VCC3_3[4] +3V VCCIO[22]
C403 C376
W 26 0.1U/10V_4 AP26 AB36 1U/6.3V_4
VCCASW [17] C400 +3V +3V_VCC_EXP VCCIO[23] VCCCLKDMI
W 29 0.1U/10V_4 AT24
VCCASW [18] R564 0_8 VCCIO[24] C616 C619
W 31 AJ2 +3V 1U/6.3V_4 *10U/6.3V_6
R335 *0_6/S VCCASW [19] VCC3_3[2]
+1.05V AN33 VCCIO[25]
W 33 C600
VCCASW [20] C338 0.1U/10V_4 AN34 VCCIO[26]
C407 0.1U/10V_4 190 mA (15mils)
1U/6.3V_4 C388 +VCCRTCEXT N16 AF13 160mA (15mils) AG16
0.1U/10V_4 DCPRTC VCCIO[5] VCCPNAND[1] +VCCP_NAND +1.8V
BH29 11/12 short
NAND / SPI
+V1.05S_SATA3 R318 *0_8/S +VCCAFDI_VRM VCC3_3[3]
VCCIO[12] AH13 +1.05V (Mobile 1.5V)
R504 *0_6/S +VCCAFDI_VRM Y49 AG17 R317 *0_8/S
+1.05V VCCVRM[4] VCCPNAND[2]
160mA (20mils) AH14 +1.5V_CPU R500 *0_6/S
B VCCIO[13] C402 B
C542 +1.05V_VCCA_A_DPL BD47 AF14 1U/6.3V_4 R501 *0_6 +VCCAFDI_VRM AP16 AJ16 C401
VCCADPLLA VCCIO[6] +1.05V VCCVRM[2] VCCPNAND[3]
SATA
1U/6.3V_4 65mA (10mils) 0.1U/10V_4

+1.05V_VCCAPLL_FDI
+1.05V_VCCA_B_DPL BF47 AK1 +V1.1LAN_VCCAPLL L35 AJ17
VCCADPLLB VCCAPLLSATA +1.05V VCCPNAND[4]
+1.05V R557 *0_6/S 8mA (10mils) *10uH/100mA_8 +1.05V R316 *0_8 BG6
+VCCAFDI_VRM VccAFDIPLL
AF11 20mA (10mils)
FDI
+VCCDIFFCLK VCCVRM[1] C652 R304 *0_8/S
AF17 VCCIO[7] 12/13 short AP17 VCCIO[27]
C592 +VCCDIFFCLKN AF33 *10U/6.3V_6 +3V_VCCME_SPI +3V
1U/6.3V_4 VCCDIFFCLKN[1] +1.05V_VCCDPLL_FDI
55mA (10mils) AF34 VCCDIFFCLKN[2] VCCIO[2] AC16
AG34 V1 R643 *0_6/S
VCCDIFFCLKN[3] +1.05V_VCCIO1 R362 *0_6/S VCCSPI
VCCIO[3] AC17 +1.05V +1.05V AU20 VCCDMI[2]
+V1.05V_SSCVCC AG33 AD17 C646
R293 *0_6 VCCSSC VCCIO[4] C412 CougarPoint_Rev_0p7 1U/6.3V_4
+1.05V 95mA (10mils)
1.01A (60mils) 1U/6.3V_4 fcbga989-intel-cougarpoint PCH PS - AJSLH9D0T13
C384 +VCCSST V16 AJSLH9D0T13
C374 0.1U/10V_4 DCPSST +1.05V_VCCEPW +1.05V IC CTRL(989P)COUGARPOINT QMVY TOP B/S
65mA (10mils)
*1U/6.3V_4 +5V_PCH_VCC5REF R241 10_4 +5V
T17 T21 L25 +1.05V_VCCA_A_DPL C543 1U/6.3V_4
+V1.05M_VCCSUS DCPSUS[1] VCCASW [22] 10uH/100MA_8 D9 RB500V-40
V19 DCPSUS[2] V5REF= 1mA +3V
C540 *220U/2.5V_3528 C332
+
MISC
+1.05V R588 *0_4/S +VTT_VCCPCPU V21 8mA (10mils) 1U/6.3V_4

short0402 VCCASW [23]
10mA (10mils)
CPU
V_PROC_IO=1mA BJ8 L27 +1.05V_VCCA_B_DPL C586 1U/6.3V_4

C621 C617 C613 V_PROC_IO +V3.3A_1.5A_HDA_IO 10uH/100MA_8
(10mils) VCCASW [21] T19
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 C576 +5V_PCH_VCC5REFSUS
+
*220U/2.5V_3528 R560 10_4 +5VS5
R550 *0_4 +1.5VSUS
5/14 modify VCC5REFSUS=1mA D22 RB500V-40
RTC
+3V +3VS5
A22 P32 R552 *0_4/S 20mA (10mils) C589
HDA
A
+3V_RTC VCCRTC VCCSUSHDA +3VS5 A
0.1U/10V_4
VCCRTC<1mA 12/13 short R536 *0_6 +3V_SUS_CLKF33 C568 1U/6.3V_4
C386 C382 C375 CougarPoint_Rev_0p7 C580 C575
(10mils) 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 fcbga989-intel-cougarpoint 0.1U/10V_4 *1U/6.3V_4 R537 1/F_4 +3V_SUS_CLKF33_R C567 10U/6.3VS_6
AJSLH9D0T13 L28
IC CTRL(989P)COUGARPOINT QMVY TOP B/S 10uH/100MA_8
PCH PS - AJSLH9D0T13 20mA (10mils) PROJECT : TWH
[6,7,21,22,23,27,28,36] +5V
+1.05V +VCC_DMI_CCI +1.1V_VCC_DMI_CCI Quanta Computer Inc.
[21,23,26,31,32,33,34,35,36,37,38,39,40] +5VS5
[4,7,36,38] +1.8V [2,6,7,8,9,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V R591 *1/F_4
[2,4,12,13,32,33,38] +1.5VSUS [2,6,7,8,9,14,24,29,31,33,35,36,38] +3VS5 L33 Size Document Number Rev
R592 *0_4/S *10uH/100mA_8 Custom A
PCH 5/6 (Power)
[6,7,8,26,35] +1.05V [6,7] +3V_DSW
[6,7,29] +3V_RTC 12/13 short NB5 Date: Tuesday, December 14, 2010 Sheet 10 of 40
5 4 3 2 1
5 4 3 2 1
IBEX PEAK-M (GND)

U24I
IBEX PEAK-M (GND)
U24H
11
AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26 H5 VSS[0]
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46 AA17 VSS[1] VSS[80] AK38
B15 VSS[164] VSS[264] K7 AA2 VSS[2] VSS[81] AK4
D B19 L18 AA3 AK42 D
VSS[165] VSS[265] VSS[3] VSS[82]
B23 VSS[166] VSS[266] L2 AA33 VSS[4] VSS[83] AK46
B27 VSS[167] VSS[267] L20 AA34 VSS[5] VSS[84] AK8
B31 VSS[168] VSS[268] L26 AB11 VSS[6] VSS[85] AL16
F45 VSS[172] VSS[272] M12 AB43 VSS[10] VSS[89] AL21
BB12 VSS[173] VSS[273] P16 AB5 VSS[11] VSS[90] AL23
BB16 VSS[174] VSS[274] M18 AB7 VSS[12] VSS[91] AL26
BB20 VSS[175] VSS[275] M22 AC19 VSS[13] VSS[92] AL27
BB38 VSS[180] VSS[280] M38 AC34 VSS[18] VSS[97] AM11
BB4 VSS[181] VSS[281] M4 AC48 VSS[19] VSS[98] AM14
BB46 VSS[182] VSS[282] M42 AD10 VSS[20] VSS[99] AM36
BC14 VSS[183] VSS[283] M46 AD11 VSS[21] VSS[100] AM39
BC18 VSS[184] VSS[284] M8 AD12 VSS[22] VSS[101] AM43
BC2 VSS[185] VSS[285] N18 AD13 VSS[23] VSS[102] AM45
BC22 VSS[186] VSS[286] P30 AD19 VSS[24] VSS[103] AM46
BC26 VSS[187] VSS[287] N47 AD24 VSS[25] VSS[104] AM7
BC32 VSS[188] VSS[288] P11 AD26 VSS[26] VSS[105] AN2
BC36 VSS[190] VSS[290] T33 AD33 VSS[28] VSS[107] AN3
BC42 VSS[192] VSS[292] P43 AD36 VSS[30] VSS[109] AP12
BC48 VSS[193] VSS[293] P47 AD37 VSS[31] VSS[110] AP19
BD46 VSS[194] VSS[294] P7 AD38 VSS[32] VSS[111] AP28
C BD5 R2 AD39 AP30 C
VSS[195] VSS[295] VSS[33] VSS[112]
BE22 VSS[196] VSS[296] R48 AD4 VSS[34] VSS[113] AP32
BE26 VSS[197] VSS[297] T12 AD40 VSS[35] VSS[114] AP38
BE40 VSS[198] VSS[298] T31 AD42 VSS[36] VSS[115] AP4
BF10 VSS[199] VSS[299] T37 AD43 VSS[37] VSS[116] AP42
BF12 VSS[200] VSS[300] T4 AD45 VSS[38] VSS[117] AP46
BF16 VSS[201] VSS[301] W 34 AD46 VSS[39] VSS[118] AP8
BF20 VSS[202] VSS[302] T46 AD8 VSS[40] VSS[119] AR2
BF22 VSS[203] VSS[303] T47 AE2 VSS[41] VSS[120] AR48
BF24 VSS[204] VSS[304] T8 AE3 VSS[42] VSS[121] AT11
BF26 VSS[205] VSS[305] V11 AF10 VSS[43] VSS[122] AT13
BD3 VSS[207] VSS[307] V26 AD14 VSS[45] VSS[124] AT22
BF30 VSS[208] VSS[308] V27 AD16 VSS[46] VSS[125] AT26
BG17 VSS[212] VSS[312] V39 AF26 VSS[50] VSS[129] AT34
BG44 VSS[215] VSS[315] W 17 AF31 VSS[53] VSS[132] AT46
BG8 VSS[216] VSS[316] W 19 AF38 VSS[54] VSS[133] AT7
BH11 VSS[217] VSS[317] W2 AF4 VSS[55] VSS[134] AU24
BH15 VSS[218] VSS[318] W 27 AF42 VSS[56] VSS[135] AU30
BH17 VSS[219] VSS[319] W 48 AF46 VSS[57] VSS[136] AV16
BH19 VSS[220] VSS[320] Y12 AF5 VSS[58] VSS[137] AV20
H10 VSS[221] VSS[321] Y38 AF7 VSS[59] VSS[138] AV24
BH27 VSS[222] VSS[322] Y4 AF8 VSS[60] VSS[139] AV30
BH31 VSS[223] VSS[323] Y42 AG19 VSS[61] VSS[140] AV38
BH33 VSS[224] VSS[324] Y46 AG2 VSS[62] VSS[141] AV4
B BH35 Y8 AG31 AV43 B
VSS[225] VSS[325] VSS[63] VSS[142]
BH39 VSS[226] VSS[328] BG29 AG48 VSS[64] VSS[143] AV8
BH43 VSS[227] VSS[329] N24 AH11 VSS[65] VSS[144] AW 14
BH7 VSS[228] VSS[330] AJ3 AH3 VSS[66] VSS[145] AW 18
D3 VSS[229] VSS[331] AD47 AH36 VSS[67] VSS[146] AW 2
D12 VSS[230] VSS[333] B43 AH39 VSS[68] VSS[147] AW 22
D16 VSS[231] VSS[334] BE10 AH40 VSS[69] VSS[148] AW 26
D18 VSS[232] VSS[335] BG41 AH42 VSS[70] VSS[149] AW 28
D22 VSS[233] VSS[337] G14 AH46 VSS[71] VSS[150] AW 32
D24 VSS[234] VSS[338] H16 AH7 VSS[72] VSS[151] AW 34
D26 VSS[235] VSS[340] T36 AJ19 VSS[73] VSS[152] AW 36
D30 VSS[236] VSS[342] BG22 AJ21 VSS[74] VSS[153] AW 40
D32 VSS[237] VSS[343] BG24 AJ24 VSS[75] VSS[154] AW 48
D34 VSS[238] VSS[344] C22 AJ33 VSS[76] VSS[155] AV11
D38 VSS[239] VSS[345] AP13 AJ34 VSS[77] VSS[156] AY12
D42 VSS[240] VSS[346] M14 AK12 VSS[78] VSS[157] AY22
D8 VSS[241] VSS[347] AP3 AK3 VSS[79] VSS[158] AY28
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
G20 BG28 CougarPoint_Rev_0p7
VSS[245] VSS[351]
G26 VSS[246] VSS[352] BJ28 PCH PS - AJSLH9D0T13
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
A H30 A
VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
CougarPoint_Rev_0p7 PROJECT : TWH

PCH PS - AJSLH9D0T13 Quanta Computer Inc.
Custom A
PCH 6/6 (Ground)
5 4 3 2 1
5 4 3 2 1
[3] M_A_A[15:0] M_A_A0

M_A_A1
M_A_A2
M_A_A3
98
97
96
95
JDIM1A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
17
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ6
M_A_DQ[63:0] [3]
2.48A +1.5VSUS
75
76
81
JDIM1B
VDD1
VDD2
VSS16
VSS17
44
48
49
12
M_A_A4 A3 DQ3 M_A_DQ1 VDD3 VSS18
92 A4 DQ4 4 82 VDD4 VSS19 54
M_A_A5 91 6 M_A_DQ0 87 55
90 A6 DQ6 16 88 VDD6 VSS21 60
M_A_A7 86 18 M_A_DQ2 93 61
89 A8 DQ8 21 94 VDD8 VSS23 65
M_A_A9 85 23 M_A_DQ8 99 66
D M_A_A10 A9 DQ9 M_A_DQ15 VDD9 VSS24 D
107 A10/AP DQ10 33 100 VDD10 VSS25 71
M_A_A11 84 35 M_A_DQ10 105 72
PC2100 DDR3 SDRAM SO-DIMM

83 A12/BC# DQ12 22 106 VDD12 VSS27 127
M_A_A13 119 24 M_A_DQ13 111 128
80 A14 DQ14 34 112 VDD14 VSS29 133
M_A_A15 78 36 M_A_DQ11 117 134
A15 DQ15 M_A_DQ21 VDD15 VSS30

DQ16 39 118 VDD16 VSS31 138
109 41 M_A_DQ16 123 139
[3] M_A_BS#0 BA0 DQ17 VDD17 VSS32
108 51 M_A_DQ19 124 144
[3] M_A_BS#1 BA1 DQ18 VDD18 VSS33
79 53 M_A_DQ18 145
[3] M_A_BS#2 BA2 DQ19 VSS34
114 40 M_A_DQ20 199 150
[3] M_A_CS#0 S0# DQ20 +3V VDDSPD VSS35
121 42 M_A_DQ17 151
[3] M_A_CS#1 S1# DQ21 M_A_DQ23 VSS36
[3] M_A_CLKP0 101 CK0 DQ22 50 77 NC1 VSS37 155
103 52 M_A_DQ22 122 156
[3] M_A_CLKN0 CK0# DQ23 NC2 VSS38
102 57 M_A_DQ25 R177 10K_4 125 161
[3] M_A_CLKP1 CK1 DQ24 M_A_DQ24 +3V NCTEST VSS39
[3] M_A_CLKN1 104 CK1# DQ25 59 VSS40 162
73 67 M_A_DQ30 [13] PM_EXTTS#0 PM_EXTTS#0 198 167
[3] M_A_CKE0 CKE0 DQ26 M_A_DQ26 EVENT# VSS41
[3] M_A_CKE1 74 CKE1 DQ27 69 [2,13] DDR3_DRAMRST# 30 RESET# VSS42 168
115 56 M_A_DQ28 172
[3] M_A_CAS# CAS# DQ28 VSS43
110 58 M_A_DQ29 173
[3] M_A_RAS# RAS# DQ29 M_A_DQ31 SMDDR_VREF_DQ0_M1 R36 +SMDDR_VREF_DQ0 VSS44
113 68 *0_6/S 1 178
[3] M_A_WE# W E# DQ30 VREF_DQ VSS45
R160 10K_4 DIMM0_SA0 197 70 M_A_DQ27 SMDDR_VREF_DQ0_M3 R32 *0_6 +SMDDR_VREF_DIMM 126 179
SA0 DQ31 [5] SMDDR_VREF_DQ0_M3 VREF_CA VSS46
R164 10K_4 DIMM0_SA1 201 129 M_A_DQ36 184
SMB_RUN_CLK SA1 DQ32 M_A_DQ37 VSS47
[8,13] SMB_RUN_CLK 202 SCL DQ33 131 12/13 short VSS48 185
SMB_RUN_DAT 200 141 M_A_DQ34 2 189
[8,13] SMB_RUN_DAT SDA DQ34 VSS1 VSS49
143 M_A_DQ38 3 190
DQ35 M_A_DQ32 VSS2 VSS50
116 130 8 195
(204P)
[3] M_A_ODT0 ODT0 DQ36 M_A_DQ33 VSS3 VSS51
[3] M_A_ODT1 120 ODT1 DQ37 132 9 VSS4 VSS52 196
140 M_A_DQ35 13
M_A_DM1 DQ38 M_A_DQ39 VSS5
11 DM0 DQ39 142 14 VSS6
C 28 147 M_A_DQ41 19 C
DM1 DQ40 M_A_DQ45 VSS7
46 149 20
(204P)
DM2 DQ41 M_A_DQ47 VSS8
63 DM3 DQ42 157 25 VSS9
M_A_DM2 136 159 M_A_DQ46 26 203
DM4 DQ43 VSS10 VTT1 +0.75V_DDR_VTT
153 146 M_A_DQ40 31 204
DM5 DQ44 M_A_DQ44 VSS11 VTT2
170 DM6 DQ45 148 32 VSS12
187 158 M_A_DQ42 37 205
DM7 DQ46 M_A_DQ43 VSS13 GND
[3] M_A_DQSP[7:0] DQ47 160 38 VSS14 GND 206
M_A_DQSP0 12 163 M_A_DQ49 43
M_A_DQSP1 DQS0 DQ48 M_A_DQ48 VSS15
29 DQS1 DQ49 165
M_A_DQSP2 47 175 M_A_DQ54
M_A_DQSP3 DQS2 DQ50 M_A_DQ55 DDR3-DIMM0_H=5.2_RVS
64 DQS3 DQ51 177
M_A_DQSP4 137 164 M_A_DQ53 DDR-78279-001-RVS-204P
M_A_DQSP5 DQS4 DQ52 M_A_DQ52 DGMK4000028
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ50 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)
M_A_DQSP7 DQS6 DQ54 M_A_DQ51
[3] M_A_DQSN[7:0] 188 DQS7 DQ55 176
M_A_DQSN0 10 181 M_A_DQ61
M_A_DQSN1 DQS#0 DQ56 M_A_DQ60
27 DQS#1 DQ57 183
M_A_DQSN2 45 191 M_A_DQ62
62 DQS#3 DQ59 193
M_A_DQSN4 135 180 M_A_DQ56
152 DQS#5 DQ61 182
M_A_DQSN6 169 192 M_A_DQ59
186 DQS#7 DQ63 194
DDR3-DIMM0_H=5.2_RVS
DDR-78279-001-RVS-204P
DGMK4000028
IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)
B B
+1.5VSUS
Place these Caps near So-Dimm0. VREF DQ0 M1 Solution

+1.5VSUS +0.75V_DDR_VTT
Remove M2 Solution (Intel 436996 Doc) R34
C126 1U/6.3V_4 C287 1U/6.3V_4 1K/F_4
+1.5VSUS
C171 1U/6.3V_4 C288 1U/6.3V_4 DDR_VTTREF R33 *0_6 SMDDR_VREF_DQ0_M1
C177 1U/6.3V_4 C286 1U/6.3V_4 R115

10K_4
C163 1U/6.3V_4 C285 1U/6.3V_4 R35
1K/F_4
C155 10U/6.3VS_6 C284 10U/6.3V_6
[4,13,32] DDR_VTTREF R119 *0_6 +SMDDR_VREF_DIMM
C139 10U/6.3VS_6 C289 *10U/6.3V_6
C119 10U/6.3VS_6
+SMDDR_VREF_DIMM R111 C180
C124 10U/6.3VS_6 10K_4 470P/50V_4
C181 0.1U/10V_4
C61 10U/6.3VS_6
C164 2.2U/6.3V_6
C123 10U/6.3VS_6
A C146 *10U/6.3V_6 +SMDDR_VREF_DQ0 A

[2,6,7,8,9,10,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V
[6,7,21,27,28,29,30,31] +3VPCU
C140 10U/6.3V_8 C26 0.1U/10V_4 [2,4,10,13,32,33,38] +1.5VSUS
[13,32,36] +0.75V_DDR_VTT
C149 10U/6.3V_8 C23 2.2U/6.3V_6
8/31 C513 FP changed from

+3V PROJECT : TWH
330U_2.5V_5.0x5.9ESR10m to 220U/6.3V_6x4.5ESR18
C273 0.1U/10V_4
11/13 delete C513
C265 2.2U/6.3V_6 Size Document Number Rev
4/27: layout modify Custom A
System Memory 1/2 (5.2H)
5 4 3 2 1
5 4 3 2 1
[3] M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
98
97
96
JDIM2A
A0
A1
DQ0
DQ1
5
7
15
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ[63:0] [3]
+1.5VSUS
75
76
81
JDIM2B
VDD1
VDD2
VSS16
VSS17
44
48
49
13
M_B_A3 A2 DQ2 M_B_DQ2 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 M_B_DQ12
D M_B_A9
89
85
A8 DQ8 21
23 M_B_DQ13
2.48A 99
100
VDD9 VSS24 66
71 D
107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ10

84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ8 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ9 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ11 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ20

DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ21 124 144
[3] M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ18 145
[3] M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ22 +3V 199 150
[3] M_B_BS#2 BA2 DQ19 VDDSPD VSS35
114 40 M_B_DQ17 151
[3] M_B_CS#0 S0# DQ20 M_B_DQ16 VSS36
[3] M_B_CS#1 121 S1# DQ21 42 10/10 double pull high 77 NC1 VSS37 155
101 50 M_B_DQ19 122 156
[3] M_B_CLKP0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 R175 *10K_4 125 161
[3] M_B_CLKN0 CK0# DQ23 M_B_DQ25 +3V NCTEST VSS39
[3] M_B_CLKP1 102 CK1 DQ24 57 VSS40 162
104 59 M_B_DQ29 PM_EXTTS#0 198 167
[3] M_B_CLKN1 CK1# DQ25 M_B_DQ27 EVENT# VSS41
[3] M_B_CKE0 73 CKE0 DQ26 67 [2,12] DDR3_DRAMRST# 30 RESET# VSS42 168
74 69 M_B_DQ26 172
[3] M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 173
[3] M_B_CAS# CAS# DQ28 M_B_DQ24 SMDDR_VREF_DQ1_M1 R38 +SMDDR_VREF_DQ1 VSS44
110 58 *0_6/S 1 178
[3] M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ31 SMDDR_VREF_DQ1_M3 R37 *0_6 126 179
[3] M_B_WE# W E# DQ30 [5] SMDDR_VREF_DQ1_M3 +SMDDR_VREF_DIMM VREF_CA VSS46
R174 10K_4 DIMM1_SA0 197 70 M_B_DQ30 184
R176 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ36 VSS47
+3V 201 SA1 DQ32 129 VSS48 185
202 131 M_B_DQ37 12/13 short 2 189
[8,12] SMB_RUN_CLK SCL DQ33 VSS1 VSS49
[8,12] SMB_RUN_DAT 200 141 M_B_DQ35 3 190
SDA DQ34 M_B_DQ34 VSS2 VSS50
143 8 195
(204P)
DQ35 M_B_DQ33 VSS3 VSS51
[3] M_B_ODT0 116 ODT0 DQ36 130 9 VSS4 VSS52 196
[3] M_B_ODT1 120 132 M_B_DQ32 13
ODT1 DQ37 M_B_DQ39 VSS5
DQ38 140 14 VSS6
C M_B_DM1 11 142 M_B_DQ38 19 C
DM0 DQ39 M_B_DQ44 VSS7
28 DM1 DQ40 147 20 VSS8
46 149 M_B_DQ40 25
(204P)
DM2 DQ41 M_B_DQ42 VSS9
63 DM3 DQ42 157 26 VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM2 136 159 M_B_DQ43 31 204
DM4 DQ43 M_B_DQ45 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
170 148 M_B_DQ41 37 205
DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 43
[3] M_B_DQSP[7:0] DQ47 VSS15
M_B_DQSP0 12 163 M_B_DQ49
M_B_DQSP1 DQS0 DQ48 M_B_DQ48
29 DQS1 DQ49 165
M_B_DQSP2 47 175 M_B_DQ54 DDR3-DIMM1_H=9.2_RVS
M_B_DQSP3 DQS2 DQ50 M_B_DQ55 DDR-AS0A626-UARN-7F-204P
64 DQS3 DQ51 177
M_B_DQSP4 137 164 M_B_DQ52 DGMK4000029
M_B_DQSP5 DQS4 DQ52 M_B_DQ53 IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS)
154 DQS5 DQ53 166
M_B_DQSP6 171 174 M_B_DQ50
M_B_DQSP7 DQS6 DQ54 M_B_DQ51
[3] M_B_DQSN[7:0] 188 DQS7 DQ55 176
M_B_DQSN0 10 181 M_B_DQ61
M_B_DQSN1 DQS#0 DQ56 M_B_DQ56
27 DQS#1 DQ57 183
M_B_DQSN2 45 191 M_B_DQ62
62 193
M_B_DQSN4 135
DQS#3 DQ59
180 M_B_DQ57 DDR3 Thermal Sensor 10/13 remove
152 DQS#5 DQ61 182
M_B_DQSN6 169 192 M_B_DQ59 U23 C577 *0.01U/25V_4
186 DQS#7 DQ63 194
MBCLK2 8 1
[8,17,29] MBCLK2 SCLK VCC +3V
DDR3-DIMM1_H=9.2_RVS [8,17,29] MBDATA2 MBDATA2 7 2 DDR_THERMDA
DDR-AS0A626-UARN-7F-204P SDA DXP
3
DGMK4000029 [12] PM_EXTTS#0 PM_EXTTS#0 6 3
B IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS) ALERT# DXN C588 Q47 B
2
PM_EXTTS#0_EC 4 5 *2200P/50V_4 *MMBT3904-7-F
OVERT# GND
1
DDR_THERMDC
+3V R555 *10K_4 *G780P81U
Place these Caps near So-Dimm1. VREF DQ1 M1 Solution

+1.5VSUS
Remove M2 Solution (Intel 436996 Doc)
+1.5VSUS +0.75V_DDR_VTT +SMDDR_VREF_DIMM
C170 1U/6.3V_4 C281 1U/6.3V_4 C200 0.1U/10V_4 R28

1K/F_4
C87 1U/6.3V_4 C282 1U/6.3V_4 C191 2.2U/6.3V_6
C184 1U/6.3V_4 C280 1U/6.3V_4 R30 *0_6 SMDDR_VREF_DQ1_M1

[4,12,32] DDR_VTTREF
C159 1U/6.3V_4 C283 1U/6.3V_4 +SMDDR_VREF_DQ1
R29
C113 10U/6.3VS_6 C290 10U/6.3V_6 C30 0.1U/10V_4 1K/F_4
C182 10U/6.3VS_6 C279 *10U/6.3V_6 C27 2.2U/6.3V_6
C122 10U/6.3VS_6
A C102 10U/6.3VS_6 +3V A

[2,6,7,8,9,10,12,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V
[6,7,21,27,28,29,30,31] +3VPCU
C154 10U/6.3VS_6 C264 0.1U/10V_4 [2,4,10,12,32,33,38] +1.5VSUS
[12,32,36] +0.75V_DDR_VTT
C145 10U/6.3VS_6 C278 2.2U/6.3V_6
C174 *10U/6.3V_6
PROJECT : TWH
C103 10U/6.3V_8 Quanta Computer Inc.
C133 10U/6.3V_8
Custom A
System Memory 2/2 (9.2H)
5 4 3 2 1
1 2 3 4 5 6 7 8
14
+3V_GFX
For Discrete +3V_GFX
R433 10K/F_4
+1.05V_GFX
500mA +3VS5
Power Sequence
C114 22U/6.3V_8 R430
C186 10U/6.3V_6 U17A
11/10 add 10K/F_4 R441
PCIE_CLKREQ_VGA# [8]
3
C130 4.7U/6.3V_6 AK16 AP17 PEG_TX15 PEG_TX15 [2] *10K/F_4
C112 1U/6.3V_4 PEX_IOVDD_1 PEX_RX0 PEG_TX#15
AK17 AN17
C60 1U/6.3V_4 AK21
PEX_IOVDD_2 [PEG Interface] PEX_RX0_N
AN19 PEG_TX14
PEG_TX#15 [2]
PEG_TX14 [2] [9,29,37] DGPU_PW ROK R429 2 Q34
C59 0.1U/10V_4 PEX_IOVDD_3 PEX_RX1 PEG_TX#14 *0_4/S DTC144EUA
AK24 PEX_IOVDD_4 PEX_RX1_N AP19 PEG_TX#14 [2]
3
C217 0.1U/10V_4 AK27 AR19 PEG_TX13 PEG_TX13 [2] 12/13 short
PEX_IOVDD_5 PEX_RX2 PEG_TX#13
AR20 PEG_TX#13 [2]
1
PEX_RX2_N PEG_TX12 PEX_CLKREQ# Q35
AP20 2
A
+1.05V_GFX
1600mA AG11
PEX_RX3
AN20 PEG_TX#12
PEG_TX12 [2]
PEG_TX#12 [2] *DTC144EUA
A
C115 22U/6.3V_8 PEX_IOVDDQ_1 PEX_RX3_N PEG_TX11

AG12 PEX_IOVDDQ_2 PEX_RX4 AN22 PEG_TX11 [2]
C131 10U/6.3V_6 AG13 AP22 PEG_TX#11 PEG_TX#11 [2]
1
C129 4.7U/6.3V_6 PEX_IOVDDQ_3 PEX_RX4_N PEG_TX10
AG15 PEX_IOVDDQ_4 PEX_RX5 AR22 PEG_TX10 [2]
C231 1U/6.3V_4 AG16 AR23 PEG_TX#10 PEG_TX#10 [2]
C212 1U/6.3V_4 PEX_IOVDDQ_5 PEX_RX5_N PEG_TX9
AG17 PEX_IOVDDQ_6 PEX_RX6 AP23 PEG_TX9 [2]
C100 0.1U/10V_4 AG18 AN23 PEG_TX#9 PEG_TX#9 [2]
C199 0.1U/10V_4 PEX_IOVDDQ_7 PEX_RX6_N PEG_TX8
AG22 PEX_IOVDDQ_8 PEX_RX7 AN25 PEG_TX8 [2]
C236 0.1U/10V_4 AG23 AP25 PEG_TX#8 PEG_TX#8 [2]
C89 0.1U/10V_4 PEX_IOVDDQ_9 PEX_RX7_N PEG_TX7 +3V
AG24 PEX_IOVDDQ_10 PEX_RX8 AR25 PEG_TX7 [2]
C88 0.1U/10V_4 AG25 AR26 PEG_TX#7
C98
C104
0.1U/10V_4
0.1U/10V_4
AG26
AJ14
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_RX8_N
PEX_RX9 AP26
AN26
PEG_TX6
PEG_TX#6
PEG_TX#7 [2]
PEG_TX6 [2] For Discrete C143 0.1U/10V_4
PEX_IOVDDQ_13 PEX_RX9_N PEG_TX#6 [2]
AJ15 AN28 PEG_TX5 PEG_TX5 [2] 12/13 short
PEX_IOVDDQ_14 PEX_RX10
5
AJ19 AP28 PEG_TX#5 PEG_TX#5 [2]
PEX_IOVDDQ_15 PEX_RX10_N PEG_TX4 R81
AJ21 PEX_IOVDDQ_16 PEX_RX11 AR28 PEG_TX4 [2] [2,8,24,26,27,29] PLTRST# 2
AJ22 AR29 PEG_TX#4 PEG_TX#4 [2] *0_4/S 4 PEGX_RST#
PEX_IOVDDQ_17 PEX_RX11_N PEG_TX3
AJ24 PEX_IOVDDQ_18 PEX_RX12 AP29 PEG_TX3 [2] [9,29] DGPU_HOLD_RST# 1
AJ25 AN29 PEG_TX#3 PEG_TX#3 [2]
PEX_IOVDDQ_19 PEX_RX12_N PEG_TX2 U5 R109
AJ27 AN31 PEG_TX2 [2]
3
PEX_IOVDDQ_20 PEX_RX13 PEG_TX#2 MC74VHC1G08DFT2G
AK18 PEX_IOVDDQ_21 PEX_RX13_N AP31 PEG_TX#2 [2]
AK20 AR31 PEG_TX1 PEG_TX1 [2] 100K/F_4
PEX_IOVDDQ_22 PEX_RX14 PEG_TX#1
AK23 PEX_IOVDDQ_23 PEX_RX14_N AR32 PEG_TX#1 [2]
AK26 AR34 PEG_TX0 PEG_TX0 [2]
PEX_IOVDDQ_24 PEX_RX15 PEG_TX#0
AL16 PEX_IOVDDQ_25 PEX_RX15_N AP34 PEG_TX#0 [2]
+3V_GFX R98
C91 4.7U/6.3V_6 J9 AL17 C_PEG_RX15 C161 0.1U/10V_4 PEG_RX15 [2] *0_4
B C194 1U/6.3V_4 VDD33_1 PEX_TX0 C_PEG_RX#15 C175 0.1U/10V_4 B
J10 VDD33_2 PEX_TX0_N AM17 PEG_RX#15 [2]
C185 0.1U/10V_4 J11 AM18 C_PEG_RX14 C162 0.1U/10V_4 PEG_RX14 [2]
C201 0.1U/10V_4 VDD33_3 PEX_TX1 C_PEG_RX#14 C176 0.1U/10V_4
J12 VDD33_4 PEX_TX1_N AM19 PEG_RX#14 [2]
C99 0.1U/10V_4 J13 AL19 C_PEG_RX13 C195 0.1U/10V_4 PEG_RX13 [2]
VDD33_5 PEX_TX2 C_PEG_RX#13 C187 0.1U/10V_4
PEX_TX2_N AK19 PEG_RX#13 [2]
AL20 C_PEG_RX12 C196 0.1U/10V_4 PEG_RX12 [2]
L10 0_6 PEX_TX3 C_PEG_RX#12 C188 0.1U/10V_4
+3V_GFX AG19 PEX_SVDD_3V3_2 PEX_TX3_N AM20 PEG_RX#12 [2]
C132 4.7U/6.3V_6 F7 AM21 C_PEG_RX11 C202 0.1U/10V_4 PEG_RX11 [2]
C224 0.1U/10V_4 PEX_SVDD_3V3_NC PEX_TX4 C_PEG_RX#11 C210 0.1U/10V_4
PEX_TX4_N AM22 PEG_RX#11 [2]
C128 0.01U/16V_4 AL22 C_PEG_RX10 C211 0.1U/10V_4 PEG_RX10 [2]
PEX_TX5 C_PEG_RX#10 C203 0.1U/10V_4
AA4 NC_1 PEX_TX5_N AK22 PEG_RX#10 [2]
AA8 AL23 C_PEG_RX9 C222 0.1U/10V_4
12~16 mils width AA28
NC_2 PEX_TX6
AM23 C_PEG_RX#9 C215 0.1U/10V_4
PEG_RX9 [2]
PEG_RX#9 [2]
NC_3 PEX_TX6_N C_PEG_RX8 C223 0.1U/10V_4
AB4 NC_4 PEX_TX7 AM24 PEG_RX8 [2]
AB5 AM25 C_PEG_RX#8 C216 0.1U/10V_4 PEG_RX#8 [2]
NC_5 PEX_TX7_N C_PEG_RX7 C229 0.1U/10V_4
AB7 NC_6 PEX_TX8 AL25 PEG_RX7 [2]
AC5 AK25 C_PEG_RX#7 C226 0.1U/10V_4
AD6
AD28
NC_7
NC_8
PEX_TX8_N
PEX_TX9 AL26
AM26
C_PEG_RX6
C_PEG_RX#6
C227
C230
0.1U/10V_4
0.1U/10V_4
PEG_RX#7 [2]
PEG_RX6 [2] NVVDD Settling Time
NC_9 PEX_TX9_N PEG_RX#6 [2]
AD29 AM27 C_PEG_RX5 C233 0.1U/10V_4 PEG_RX5 [2]
NC_10 PEX_TX10 C_PEG_RX#5 C238 0.1U/10V_4
AE29 NC_11 PEX_TX10_N AM28 PEG_RX#5 [2]
AF6 AL28 C_PEG_RX4 C234 0.1U/10V_4 PEG_RX4 [2]
AG6 NC_13 PEX_TX11_N AK28 PEG_RX#4 [2]
AG29 AK29 C_PEG_RX3 C247 0.1U/10V_4 PEG_RX3 [2]
AH12 NC_15 PEX_TX12_N AL29 PEG_RX#3 [2]
AH24 AM29 C_PEG_RX2 C248 0.1U/10V_4 PEG_RX2 [2]
AH25 NC_17 PEX_TX13_N AM30 PEG_RX#2 [2]
AH26 AM31 C_PEG_RX1 C259 0.1U/10V_4 PEG_RX1 [2]
AH29 NC_19 PEX_TX14_N AM32 PEG_RX#1 [2]
C C_PEG_RX0 C257 0.1U/10V_4 C
AJ5 NC_20 PEX_TX15 AN32 PEG_RX0 [2]
AK15 AP32 C_PEG_RX#0 C254 0.1U/10V_4 PEG_RX#0 [2]
NC_21 PEX_TX15_N
AL7 NC_22
A2 NC_23
C5 AR16 CLK_PCIE_VGA CLK_PCIE_VGA [8]
NC_24 PEX_REFCLK CLK_PCIE_VGA#
E7 NC_25 PEX_REFCLK_N AR17 CLK_PCIE_VGA# [8]
G11 NC_26
G12 NC_27
G14 AJ17 PEX_TSTCLK R110 *200_4
NC_28 PEX_TSTCLK_OUT PEX_TSTCLK#
G15 NC_29 PEX_TSTCLK_OUT_N AJ18
G24 NC_30
G25 NC_31
G27 AM16 VGA_RST# R108 0_4 PEGX_RST#
NC_32 PEX_RST_N
G28 NC_33
H10 NC_34
H11 AR13 PEX_CLKREQ# R436 10K/F_4 +3V_GFX
NC_35 PEX_CLKREQ_N
H12 NC_36
H15
H21
NC_37
AG21 PEX_TERMP R106 2.49K/F_4 PEX_RST timing
NC_38 PEX_TERMP R107 *0_4/S
H24 NC_39 (NC) PEX_TERMP AH21
H25 NC_40
H26 AP35 TESTMODE R482 10K/F_4
NC_41 TESTMODE
H32 NC_42
J25 NC_43
11/12 short I/O 3.3V
J26 AG14 L9 PBY160808T-301Y-N_6 +1.05V_GFX
NC_44 PEX_PLLVDD R122 *0_4/S C106 4.7U/6.3V_6
L8 AH15
L29
NC_45 PEX_PLLVDD (NC)
AG20 C111 1U/6.3V_4 110mA PEX_RST
NC_46 PEX_PLL_HVDD_NC C110 0.1U/10V_4
M29
D P6
NC_47
10/12 for N12E 12~16 mils width D
NC_48
P29 NC_49 VDD_SENSE_1 AD20
R28 NC_50 VDD_SENSE_2 D35 VGPU_CORE_SENSE [37]
R29 NC_51 VDD_SENSE_3 P7 Trise >= 1uS Tfail <=500nS
U7 NC_52
V6 NC_53
Y4 NC_54 GND_SENSE_1 AD19
E35
PROJECT : TWH
GND_SENSE_2
GND_SENSE_3 R7
VSS_GPU_SENSE [37]
N12x
N12P AJ0N12P0T04 [15,16,37,38] +1.05V_GFX A3 A
DGPU 1/5 (PEG)
[16,17,22,37,38] +3V_GFX
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
15
U17B U17C
A FBA_CMD0 U30 L32 VMA_DQ0 FBC_CMD0 F18 B13 VMC_DQ0 A
[19] FBA_CMD[30:0] FBA_CMD0 (FBA_CMD25) FBA_D00 [20] FBC_CMD[30:0] FBB_CMD0 (FBC_CMD25) FBC_D00
FBA_CMD1 VMA_DQ1 FBC_CMD1 VMC_DQ1
FBA_CMD2
V30 FBA_CMD1 (FBA_CMD23) [MEMORY I/F A] FBA_D01 N33
VMA_DQ2 FBC_CMD2
E19 FBB_CMD1 (FBC_CMD23) FBC_D01 D13
VMC_DQ2 FBA_CMD2 R498 10K/F_4
U31 L33 D18 A13
FBA_CMD3 V32
FBA_CMD2 FBA_D02
N34 VMA_DQ3 FBC_CMD3 C17
FBC_CMD2 MEMORY I/F C FBC_D02
A14 VMC_DQ3
FBA_CMD4 FBA_CMD3 (FBA_CMD0) FBA_D03 VMA_DQ4 FBC_CMD4 FBB_CMD3 (FBC_CMD0) FBC_D03 VMC_DQ4 FBA_CMD3 R181 10K/F_4
T35 FBA_CMD4 (FBA_CMD10) FBA_D04 N35 F19 FBB_CMD4 (FBC_CMD10) FBC_D04 C16
FBA_CMD5 U33 P35 VMA_DQ5 FBC_CMD5 C19 B16 VMC_DQ5
W32 FBA_CMD6 (FBA_CMD14) FBA_D06 P33 B17 FBB_CMD6 (FBC_CMD14) FBC_D06 A17
FBA_CMD7 W33 P34 VMA_DQ7 FBC_CMD7 E20 D16 VMC_DQ7
FBA_CMD8 FBA_CMD7 FBA_D07 VMA_DQ8 FBC_CMD8 FBC_CMD7 FBC_D07 VMC_DQ8 FBA_CMD18 R516 10K/F_4
W31 FBA_CMD8 (FBA_CMD1) FBA_D08 K35 B19 FBB_CMD8 (FBC_CMD1) FBC_D08 C13
FBA_CMD9 W34 K33 VMA_DQ9 FBC_CMD9 D20 B11 VMC_DQ9
U34 FBA_CMD10 (FBA_CMD20) FBA_D10 K34 A19 FBB_CMD10 (FBC_CMD20) FBC_D10 C11
FBA_CMD11 U35 H33 VMA_DQ11 FBC_CMD11 D19 A11 VMC_DQ11
FBA_CMD12 FBA_CMD11 (FBA_CMD24) FBA_D11 VMA_DQ12 FBC_CMD12 FBB_CMD11 (FBC_CMD24) FBC_D11 VMC_DQ12 FBC_CMD2 R438 10K/F_4
U32 FBA_CMD12 (FBA_CMD18) FBA_D12 G34 C20 FBB_CMD12 (FBC_CMD18) FBC_D12 C10
FBA_CMD13 T34 G33 VMA_DQ13 FBC_CMD13 F20 C8 VMC_DQ13
T33 FBA_CMD14 (FBA_CMD29) FBA_D14 E34 B20 FBB_CMD14 (FBC_CMD29) FBC_D14 B8
FBA_CMD15 W30 E33 VMA_DQ15 FBC_CMD15 G21 A8 VMC_DQ15
AB30 FBA_CMD16 (FBA_CMD27) FBA_D16 G31 F22 FBB_CMD16 (FBC_CMD27) FBC_D16 E8
FBA_CMD17 AA30 F30 VMA_DQ17 FBC_CMD17 F24 F8 VMC_DQ17
AB31 FBA_CMD18 (FBA_CMD11) FBA_D18 G30 F23 FBB_CMD18 (FBC_CMD11) FBC_D18 F10
FBA_CMD19 AA32 G32 VMA_DQ19 FBC_CMD19 C25 F9 VMC_DQ19
AB33 FBA_CMD20 (FBA_CMD28) FBA_D20 K30 C23 FBB_CMD20 (FBC_CMD28) FBC_D20 F12
FBA_CMD21 Y32 K32 VMA_DQ21 FBC_CMD21 F21 D8 VMC_DQ21
FBA_CMD22 FBA_CMD21 (FBA_CMD3) FBA_D21 VMA_DQ22 FBC_CMD22 FBB_CMD21 (FBC_CMD3) FBC_D21 VMC_DQ22
FBA_CMD23
Y33 FBA_CMD22 (FBA_CMD17) FBA_D22 H30
VMA_DQ23 FBC_CMD23
E22 FBB_CMD22 (FBC_CMD17) FBC_D22 D11
VMC_DQ23
For Fermi
AB34 FBA_CMD23 (FBA_CMD5) FBA_D23 K31 D21 FBB_CMD23 (FBC_CMD5) FBC_D23 E11
FBA_CMD24 AB35 L31 VMA_DQ24 FBC_CMD24 A23 D12 VMC_DQ24
FBA_CMD25 FBA_CMD24 (FBA_CMD4) FBA_D24 VMA_DQ25 FBC_CMD25 FBB_CMD24(FBC_CMD4) FBC_D24 VMC_DQ25
Y35 FBA_CMD25 (FBA_CMD21) FBA_D25 L30 D22 FBB_CMD25 (FBC_CMD21) FBC_D25 E13
FBA_CMD26 W35 M32 VMA_DQ26 FBC_CMD26 B23 F13 VMC_DQ26 VMA_DQ[63:0]
FBA_CMD26 (FBA_CMD6) FBA_D26 FBB_CMD26 (FBC_CMD6) FBC_D26 VMA_DQ[63:0] [19]
FBA_CMD27 Y34 N30 VMA_DQ27 FBC_CMD27 C22 F14 VMC_DQ27
FBA_CMD28 FBA_CMD27 (FBA_CMD13) FBA_D27 VMA_DQ28 FBC_CMD28 FBB_CMD27 (FBC_CMD13) FBC_D27 VMC_DQ28 VMC_DQ[63:0]
Y31 FBA_CMD28 (FBA_CMD19) FBA_D28 M30 B22 FBB_CMD28 (FBC_CMD19) FBC_D28 F15 VMC_DQ[63:0] [20]
B FBA_CMD29 Y30 P31 VMA_DQ29 FBC_CMD29 A22 E16 VMC_DQ29 B
FBA_CMD30 FBA_CMD29 (FBA_CMD12) FBA_D29 VMA_DQ30 FBC_CMD30 FBB_CMD29 (FBC_CMD12) FBC_D29 VMC_DQ30
W29 FBA_CMD30 FBA_D30 R32 A20 FBC_CMD30 FBC_D30 F16
Y29 R30 VMA_DQ31 G20 F17 VMC_DQ31
FBA_CMD31 (NC) FBA_D31 VMA_DQ32 FBC_CMD31 (NC) FBC_D31 VMC_DQ32
FBA_D32 AG30 FBC_D32 D29
AG32 VMA_DQ33 F27 VMC_DQ33
VMA_DM0 FBA_D33 VMA_DQ34 VMC_DM0 FBC_D33 VMC_DQ34
[19] VMA_DM[7:0] P32 FBA_DQM0 FBA_D34 AH31 [20] VMC_DM[7:0] A16 FBC_DQM0 FBC_D34 F28
VMA_DM1 H34 AF31 VMA_DQ35 VMC_DM1 D10 E28 VMC_DQ35
VMA_DM2 FBA_DQM1 FBA_D35 VMA_DQ36 VMC_DM2 FBC_DQM1 FBC_D35 VMC_DQ36
J30 FBA_DQM2 FBA_D36 AF30 F11 FBC_DQM2 FBC_D36 D26
VMA_DM3 P30 AE30 VMA_DQ37 VMC_DM3 D15 F25 VMC_DQ37
AF32 FBA_DQM4 FBA_D38 AC32 D27 FBC_DQM4 FBC_D38 D24
VMA_DM5 AL32 AD30 VMA_DQ39 VMC_DM5 D34 E25 VMC_DQ39
AL34 FBA_DQM6 FBA_D40 AN33 A34 FBC_DQM6 FBC_D40 E32
VMA_DM7 AF35 AL31 VMA_DQ41 VMC_DM7 D28 F32 VMC_DQ41
FBA_DQM7 FBA_D41 VMA_DQ42 FBC_DQM7 FBC_D41 VMC_DQ42
FBA_D42 AM33 FBC_D42 D33
AL33 VMA_DQ43 E31 VMC_DQ43
VMA_W DQS0 FBA_D43 VMA_DQ44 VMC_W DQS0 FBC_D43 VMC_DQ44
[19] VMA_W DQS[7:0] L34 FBA_DQS_WP0 FBA_D44 AK30 [20] VMC_W DQS[7:0] C14 FBC_DQS_WP0 FBC_D44 C33
VMA_W DQS1 H35 AK32 VMA_DQ45 VMC_W DQS1 A10 F29 VMC_DQ45
VMA_W DQS2 FBA_DQS_WP1 FBA_D45 VMA_DQ46 VMC_W DQS2 FBC_DQS_WP1 FBC_D45 VMC_DQ46
J32 FBA_DQS_WP2 FBA_D46 AJ30 E10 FBC_DQS_WP2 FBC_D46 D30
VMA_W DQS3 N31 AH30 VMA_DQ47 VMC_W DQS3 D14 E29 VMC_DQ47
AE31 FBA_DQS_WP4 FBA_D48 AH33 E26 FBC_DQS_WP4 FBC_D48 B29
VMA_W DQS5 AJ32 AH35 VMA_DQ49 VMC_W DQS5 D32 C31 VMC_DQ49
AJ34 FBA_DQS_WP6 FBA_D50 AH34 A32 FBC_DQS_WP6 FBC_D50 C29
VMA_W DQS7 AC33 AH32 VMA_DQ51 VMC_W DQS7 B26 B31 VMC_DQ51
FBA_DQS_WP7 FBA_D51 VMA_DQ52 FBC_DQS_WP7 FBC_D51 VMC_DQ52
FBA_D52 AJ33 FBC_D52 C32
AL35 VMA_DQ53 B32 VMC_DQ53
VMA_RDQS0 FBA_D53 VMA_DQ54 VMC_RDQS0 FBC_D53 VMC_DQ54
[19] VMA_RDQS[7:0] L35 FBA_DQS_RN0 FBA_D54 AM34 [20] VMC_RDQS[7:0] B14 FBC_DQS_RN0 FBC_D54 B35
VMA_RDQS1 G35 AM35 VMA_DQ55 VMC_RDQS1 B10 B34 VMC_DQ55
VMA_RDQS2 FBA_DQS_RN1 FBA_D55 VMA_DQ56 VMC_RDQS2 FBC_DQS_RN1 FBC_D55 VMC_DQ56
H31 FBA_DQS_RN2 FBA_D56 AF33 D9 FBC_DQS_RN2 FBC_D56 A29
VMA_RDQS3 N32 AE32 VMA_DQ57 VMC_RDQS3 E14 B28 VMC_DQ57
C VMA_RDQS4 FBA_DQS_RN3 FBA_D57 VMA_DQ58 VMC_RDQS4 FBC_DQS_RN3 FBC_D57 VMC_DQ58 C
AD32 FBA_DQS_RN4 FBA_D58 AF34 F26 FBC_DQS_RN4 FBC_D58 A28
VMA_RDQS5 AJ31 AE35 VMA_DQ59 VMC_RDQS5 D31 C28 VMC_DQ59
VMA_RDQS6 FBA_DQS_RN5 FBA_D59 VMA_DQ60 VMC_RDQS6 FBC_DQS_RN5 FBC_D59 VMC_DQ60
AJ35 FBA_DQS_RN6 FBA_D60 AE34 A31 FBC_DQS_RN6 FBC_D60 C26
VMA_RDQS7 AC34 AE33 VMA_DQ61 VMC_RDQS7 A26 D25 VMC_DQ61
FBA_DQS_RN7 FBA_D61 VMA_DQ62 FBC_DQS_RN7 FBC_D61 VMC_DQ62
FBA_D62 AB32 FBC_D62 B25
AC35 VMA_DQ63 A25 VMC_DQ63
FBA_D63 FBC_D63
+1.5V_GFX AA27 FBVDDQ_1 +1.5V_GFX J16 FBVDDQ_20
AA29 FBVDDQ_2 J17 FBVDDQ_21
AA31 T32 VMA_CLK0 VMA_CLK0 [19] J20 E17 VMC_CLK0 VMC_CLK0 [20]
FBVDDQ_3 FBA_CLK0 VMA_CLK0# FBVDDQ_22 FBC_CLK0 VMC_CLK0#
AB27 FBVDDQ_4 FBA_CLK0_N T31 VMA_CLK0# [19] J21 FBVDDQ_23 FBC_CLK0_N D17 VMC_CLK0# [20]
AB29 AC31 VMA_CLK1 VMA_CLK1 [19] J22 D23 VMC_CLK1 VMC_CLK1 [20]
FBVDDQ_5 FBA_CLK1 VMA_CLK1# FBVDDQ_24 FBC_CLK1 VMC_CLK1#
AC27 FBVDDQ_6 FBA_CLK1_N AC30 VMA_CLK1# [19] J23 FBVDDQ_25 FBC_CLK1_N E23 VMC_CLK1# [20]
AD27 FBVDDQ_7 15mils width J24 FBVDDQ_26
C256 4.7U/6.3V_6 AE27 J29
C243 4.7U/6.3V_6 FBVDDQ_8 FBA_DEBUG R151 *10K/F_4 FBVDDQ_27 FBC_DEBUG R137 *10K/F_4
AJ28 FBVDDQ_9 (FBA_DEBUG) FBA_DEBUG0 T30 +1.5V_GFX N27 FBVDDQ_28 (FBC_DEBUG) FBB_DEBUG0 G19 +1.5V_GFX
C240 1U/6.3V_4 B18 T29 FBA_DEBUG1 R147 *10K/F_4 +1.5V_GFX P27 G16 FBC_DEBUG1 R129 *10K/F_4 +1.5V_GFX
C205 1U/6.3V_4 FBVDDQ_10 (NC) FBA_DEBUG1 +FB_VREF1 TP32 FBVDDQ_29 (NC) FBB_DEBUG1
E21 FBVDDQ_11 FB_VREF_NC J27 R27 FBVDDQ_30
C218 0.1U/10V_4 G17 15mils width T27
C235 0.1U/10V_4 FBVDDQ_12 FBVDDQ_31 FB_CAL_PD_VDDQ R139 40.2/F_4
G18 FBVDDQ_13 U27 FBVDDQ_32 FB_CAL_PD_VDDQ K27 +1.5V_GFX
C246 0.1U/10V_4 G22 AG27 +FB_DLLAVDD L12 PBY160808T-30Y-N_6 +1.05V_GFX U29 K28 R144 *0_4/S
C314 0.1U/10V_4 FBVDDQ_14 FB_DLLAVDD1 R149 *0_4/S FBVDDQ_33 (NC) FB_CAL_PD_VDDQ FB_CAL_PU_GND R140 40.2/F_4
G8 FBVDDQ_15 (NC) FB_DLLAVDD2 AF28 V27 FBVDDQ_34 FB_CAL_PU_GND L27
C241 0.1U/10V_4 G9 J19 R135 *0_4/S C260 10U/6.3V_6 V29 L28 R145 *0_4/S
C317 0.1U/10V_4 FBVDDQ_16 (NC) FB_DLLAVDD3 C275 1U/6.3V_4 FBVDDQ_35 (NC) FB_CAL_PU_GND
H29 FBVDDQ_17 V34 FBVDDQ_36
C245 0.1U/10V_4 J14 AF27 +FB_PLLAVDD C268 0.1U/10V_4 W27
C244 0.1U/10V_4 FBVDDQ_18 FB_PLLAVDD1 R148 *0_4/S C270 0.1U/10V_4 FBVDDQ_37 FB_CAL_TERM_GND R142 60.4/F_4
J15 FBVDDQ_19 (NC) FB_PLLAVDD2 AE28 Y27 FBVDDQ_38 FB_CAL_TERM_GND M27
J18 R132 *0_4/S C272 0.1U/10V_4 M28 R146 *0_4/S
(NC) FB_PLLAVDD3 (NC) FB_CAL_TERM_GND
N12x N12x 12/9 change to 60.4 ohm
D 10/12 for N12E 10/12 for N12E D
N12P AJ0N12P0T04 11/12 short
N12P AJ0N12P0T04 11/12 short
PROJECT : TWH
[14,16,37,38] +1.05V_GFX A3 A
DGPU 2/5 (Memory)
[19,20,37,38] +1.5V_GFX
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R93 10K/F_4 IFPAB_PLLVDD AK9

U17D
AM11
16
IFPAB_PLLVDD IFPA_TXC
[IFPA/B_LVDS] IFPA_TXC_N AM12
IFPA_TXD0 AM8
IFPAB_IOVDD AG9 AL8
R102 *0_4/S IFPA_IOVDD IFPA_TXD0_N
AH10 IFPA_IOVDD (NC) IFPA_TXD1 AM10
AG10 IFPB_IOVDD IFPA_TXD1_N AM9
A R104 10K/F_4 R103 *0_4/S AH11 AK10 A
IFPB_IOVDD (NC) IFPA_TXD2
IFPA_TXD2_N AL10
IFPA_TXD3 AK11
11/12 for N12E, short AJ11 IFPAB_RSET IFPA_TXD3_N AL11
IFPB_TXC AP13
IFPB_TXC_N AN13 10/8 remove 27M clcok buffer circuit
IFPB_TXD4 AN8
IFPB_TXD4_N AP8
IFPB_TXD5 AP10
IFPB_TXD5_N AN10
IFPB_TXD6 AR11
IFPB_TXD6_N AR10
IFPB_TXD7 AN11
IFPB_TXD7_N AP11
AJ9 IFPC_PLLVDD IFPC_AUX_I2CW_SCL AP2

R74 10K/F_4 IFPCD_PLLVDD AC6 [IFPC/D_TMDS]IFPC_AUX_I2CW_SDA_N AN3
IFPD_PLLVDD
IFPC_L0 AM7
IFPC_L0_N AM6
AJ8 IFPC_IOVDD IFPC_L1 AL5
R92 10K/F_4 IFPCD_IOVDD AK8 AM5
IFPD_IOVDD IFPC_L1_N
IFPC_L2 AM3
IFPC_L2_N AM4
AK7 IFPC_RSET IFPC_L3 AP1
AB6 IFPD_RSET IFPC_L3_N AR2
AP4
B IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N AN4
AR8
VENTURA Function(N12E Only) B
IFPD_L0
IFPD_L0_N AR7
IFPD_L1 AP7
IFPD_L1_N AN7
IFPD_L2 AN5
IFPD_L2_N AP5
IFPD_L3 AR5
IFPD_L3_N AR4
R435 10K/F_4 IFPEF_PLLVDD AJ6 AE4

IFPEF_PLLVDD IFPE_AUX_I2CY_SCL
[IFPE/F_DP] IFPE_AUX_I2CY_SDA_N AD4
IFPE_L0 AH6
AE7 IFPE_IOVDD IFPE_L0_N AH5
R400 10K/F_4 IFPEF_IOVDD AD7 AH4
IFPF_IOVDD IFPE_L1
IFPE_L1_N AG4 9/28
IFPE_L2 AF4 Nvidia announce - N12E no support Ventura
AL1 IFPEF_RSET IFPE_L2_N AF5
AE6 N12E only support Dual Core CPU (35W)
IFPE_L3
IFPE_L3_N AE5
IFPF_AUX_I2CZ_SCL AF3
IFPF_AUX_I2CZ_SDA_N AF2
IFPF_L0 AL2 10/7
IFPF_L0_N AL3 remove all ventura circuit
IFPF_L1 AJ3
IFPF_L1_N AJ2
IFPF_L2 AJ1
C C
IFPF_L2_N AH1
IFPF_L3 AH2
IFPF_L3_N AH3
R94 10K/F_4 DACA_VDD AJ12 AM15

DACA_VDD DACA_RED
[DACA/B_CRT] DACA_GREEN AM14
DACA_BLUE AL14
AK12 DACA_VREF
DACA_HSYNC AM13
AK13 DACA_RSET DACA_VSYNC AL13
R432 10K/F_4 DACB_VDD AG7 G1 I2CA_SCL R3001 2.2K_4 +3V_GFX

DACB_VDD I2CA_SCL I2CA_SDA R3002 2.2K_4
I2CA_SDA G4
AK6 DACB_VREF
DACB_RED AK4 11/10 add R3001,R3002 for NV
DACB_GREEN AL4
AH7 DACB_RSET DACB_BLUE AJ4
+1.05V_GFX L6 PBY160808T-30Y-N_6 NV_PLLVDD AE9 AM1

C90 10U/6.3V_6 R76 *0_4/S PLLVDD DACB_HSYNC
AE8 PLLVDD (NC) DACB_VSYNC AM2
C95 0.1U/10V_4
C109 0.1U/10V_4
C94 0.1U/10V_4 SP_PLLVDD AF9 G3 N12E_SCL R417 2.2K_4 +3V_GFX
C96 0.1U/10V_4 R75 *0_4/S SP_PLLVDD I2CB_SCL N12E_SDA R416 2.2K_4
D AF8 SP_PLLVDD (NC) I2CB_SDA G2 9/11 min stub D
VID_PLLVDD AD9 B1 CLK_27M_VGA_2

R402 *0_4/S VID_PLLVDD XTAL_IN XTALOUT Y4 27MHZ
AD8 VID_PLLVDD (NC) XTAL_OUT B2
[XTAL IN] D1 R420 10K/F_4 2 1 10/8 remove R1016
XTAL_OUTBUFF
XTAL_SSIN D2 R421 10K/F_4
C439 C442 PROJECT : TWH
10/12 for N12E N12x
18P/50V_4 18P/50V_4
11/12 short N12P AJ0N12P0T04 [14,15,37,38] +1.05V_GFX
[14,17,22,37,38] +3V_GFX A3
9/11 stuff XTAL solution A
DGPU 3/5 (Display)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
N11P-GS ES N11P-GS QS
U17E
Strap2 = 35K Pull High
ROM_CLK=15k Pull High
Strap2 = 5K Pull down
ROM_CLK=15k Pull High 17
MIOA_VDDQ P9 N4 MIOA_CLKIN R413 10K/F_4 Logical Strap Bit Mapping +3V_GFX +3V_GFX
MIOA_VDDQ1_NC MIOA_CLKIN_NC
R9 MIOA_VDDQ2_NC [MIOA] MIOA_CLKOUT_NC R4
PU-VDD PD
T9 MIOA_VDDQ3_NC MIOA_CLKOUT_NC_N T4
R90 10K/F_4 U9 MIOA_VDDQ4_NC R407 R403 R405
A N1 DGPU_IDLE# 1 3 DGPU_IDLE_INT# [8]
5K 1000 0000 R418 A
MIOA_D0_NC R422 R82
N5 P4
MIOA_VREF_NC MIOA_D1_NC
P1 Q38 10K 1001 0001 *4.99K/F_4 *4.99K/F_4 45.3K/F_4
MIOA_D2_NC 2N7002 *35.7K/F_4 *35.7K/F_4
P2
15K 1010 0010
2
MIOA_D3_NC ROM_SI 15K/F_4 STRAP0
U5 MIOA_CAL_PD_VDDQ_NC MIOA_D4_NC P3
T5 T3 ROM_SI ROM_SO STRAP1
MIOA_CAL_PU_GND_NC MIOA_D5_NC
MIOA_D6_NC T2 20K 1011 0011 ROM_SCLK STRAP2
T1 +3V_GFX Hynix 64Mx16 -->15K PD
MIOA_D7_NC
U4 Samsung 64Mx16 -->20K PD
25K 1100 0100 R399 R78 R419 R408 R404
MIOA_D8_NC
U1
MIOA_D9_NC
U2 Hynix 128Mx16 -->35K PD 30K 1101 0101 R406
MIOA_D10_NC 25.5K/F_4
U3
MIOA_D11_NC
R6
Samsung 128Mx16 -->45K PD 35K 1110 0110 20K/F_4 10K/F_4 *15K/F_4 *2K/F_4 35.7K/F_4
MIOA_D12_NC
T6
MIOA_D13_NC
N6 ROM_SO 45K 1111 0111
MIOA_D14_NC
Default: Hynix VRAM
--> 10K PD 4.99K/F_4: CS24992FB26 [RES CHIP 4.99K 1/16W +1%(0402)]
MIOA_HSYNC_NC N3 10K/F_4: CS31002FB26 [RES CHIP 10K 1/16W +1% (0402)]
MIOA_VSYNC_NC L3 ROM_SCLK 15K/F_4: CS31502FB24 [RES CHIP 15K 1/16W +1% (0402)]
MIOA_CTL3_NC P5 20K/F_4: CS32002FB29 [RES CHIP 20K 1/16W +-1%(0402)]
N2 N11P-GS (DID=0DF0) ---> 15k PU 30.1K/F_4: CS33012FB18 [RES CHIP 30.1K 1/16W +-1%(0402)]
MIOA_DE_NC
N12P-GS (DID=0DF4) --->15K PU 35.7K/F_4: CS33572FB13 [RES CHIP 35.7K 1/16W +-1%(0402)]
45.3K/F_4: CS34532FB18 [RES CHIP 45.3K 1/16W +-1% (0402)] 20K/F_4: CS32002FB29 RES CHIP 20K 1/16W +-1%(0402)
MIOB_VDDQ AA9 MIOB_VDDQ1_NC MIOB_CLKIN_NC AE1 MIOB_CLKIN R401 10K/F_4 N12E-GE (DID=0DCE) --->15K PD
AB9 MIOB_VDDQ2_NC [MIOB] MIOB_CLKOUT_NC V4 Logical Logical Logical Logical
W9 MIOB_VDDQ3_NC MIOB_CLKOUT_NC_N W4 Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
R91 10K/F_4 Y9 MIOB_VDDQ4_NC
STRAP0 ROM_SO NB10X XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE 0001
MIOB_D0_NC Y1
B AF1 Y2 -->45K PU ROM_SCLK PCI_DEVIDE[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM 0010 B
MIOB_VREF_NC MIOB_D1_NC
MIOB_D2_NC Y3
MIOB_D3_NC AB3 STRAP1 ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] XXXX
AA7 MIOB_CAL_PD_VDDQ_NC MIOB_D4_NC AB2
AA6 AB1 N11P-GS -->35K PD STRAP2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] 1000
MIOB_CAL_PU_GND_NC MIOB_D5_NC
MIOB_D6_NC AC4 N12P-GS waiting PUN update
MIOB_D7_NC AC1 STRAP1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0] 0001
MIOB_D8_NC AC2 N12E-GE waiting PUN update
MIOB_D9_NC AC3 STRAP0 USER[3] USER[2] USER[1] USER[0] 1111
MIOB_D10_NC AE3 STRAP2
MIOB_D11_NC AE2 VRAM Configuration Table
U6 N11P-GS (DID=0DF0) ---> 5k PD
MIOB_D12_NC
MIOB_D13_NC W6 N12P-GS (DID=0DF4) --->25K PD RAMCFG
MIOB_D14_NC Y6 [3:0] DESCRIPTION Vendor Vendor P/N ROM_SI
N12E-GE (DID=0DCE)--->35K PU
0000 Reserved
MIOB_HSYNC_NC W1 AKD58GGT^01 0001 DDR3 64Mx16x8, 128bit, 1GB,800MHz Qimonda IDGH1G-04A1F1C-16X PD 10K
MIOB_VSYNC_NC W2 AKD5LZGTW00 0010 DDR3 64Mx16x8, 128bit, 1GB,800MHz Hynix H5TQ1G63BFR-12C PD 15K
MIOB_CTL3_NC W3 AKD5LGGT502 0011 DDR3 64Mx16x8, 128bit, 1GB,800MHz Samsung K4W1G1646E-HC12 PD 20K
MIOB_DE_NC Y5 0101 Reserved
0110
XXXX DDR3 64Mx16x8, 128bit, 1GB,667MHz Hynix H5TQ1G63AFR-14C
TP60 JTAG_TCK AP14 K1 TP58 XXXX DDR3 64Mx16x8, 128bit, 1GB,667MHz Samsung K4W1G1646D-EC12
TP62 JTAG_TMS JTAG_TCK GPIO0 TP57
TP15 JTAG_TDI
AR14 JTAG_TMS [MISC_GPIO/I2C/JTAG/THER] GPIO1 K2
DGPU_DPST_PW M TP54
AN14 JTAG_TDI GPIO2 K3
TP61 JTAG_TDO AN16 H3 DGPU_DISP_ON TP3
TP59 JTAG_TRST
JTAG_TRST# AP16
JTAG_TDO
JTAG_TRST_N
GPIO3
GPIO4
GPIO5
H2
H1
H4
DGPU_LVDS_BLON
GFx_CORE_CNTRL0
GFx_CORE_CNTRL1
TP5
GFx_CORE_CNTRL0 [37] +3V_GFX
GPIO ASSIGNMENTS
GPIO6 GFx_CORE_CNTRL1 [37]
C +3V_GFX R87 2.2K_4 DGPU_EDIDCLK E3 H5 TP12 C
R86 2.2K_4 DGPU_EDIDDATA I2CC_SCL GPIO7 VGA_OVT# JTAG_TMS R440 *10K/F_4
E4
F4
I2CC_SDA GPIO8 H6
J7 ALERT TP1
DGPU_OVT# [29] GPIO I/O ACTIVE USAGE
NC (I2CD_SCL_NC) GPIO9 TP7 JTAG_TDI R442 *10K/F_4
G5 NC (I2CD_SDA_NC GPIO10 K4
TP16
D5
E5
NC (I2CE_SCL_NC) GPIO11 K5
H7 R88 10K/F_4 VGA_OVT# R84 10K/F_4
0 N/A N/A
NC (I2CE_SDA_NC) GPIO12 +3V_GFX
R83 2.2K_4 HDCP_SCL TP10
+3V_GFX
R85 2.2K_4 HDCP_SDA
F6
G6
I2CH_SCL GPIO13 J4
J6 TP8 ALERT R89 10K/F_4
1 IN N/A Hot plug detect for IFP link C
GFx_SCL I2CH_SDA GPIO14 TP56
GFx_SDA
E2
E1
I2CS_SCL GPIO15 L1
L2 TP55 JTAG_TCK R439 *10K/F_4
2 OUT HIGH PANEL BACKLIGHT PWM
I2CS_SDA GPIO16 TP2
GPIO17 L4
M4 DGPU_IDLE# R414 10K/F_4 JTAG_TRST# R443 *10K/F_4
3 OUT HIGH PANEL POWER ENABLE
GPIO18 +3V_GFX
TP11 THERM+ TP18
TP6 THERM-
B5
B4
THERMDP GPIO19 L7
L5 TP9 DGPU_DPST_PW M R415 *2K/F_4
4 OUT HIGH PANEL BACKLIGHT ENABLE
THERMDN GPIO20 TP4
GPIO21 K6
L6 TP17
5 OUT N/A NVVDD VID0
GPIO22 TP13
GPIO23 M6
M7 TP14
6 OUT N/A NVVDD VID1
(NC) GPIO24
A7
B7
C7
NC
NC
(HDA_SYNC_NC)
(HDA_SDO_NC) [MISC2_ROM]
ROM_SCLK
ROM_CS_N
D4
C3
D3
ROM_SCLK
ROM_SI
GFx SMBus Isolation
R483 *0_4
** 7
8
9
OUT
I/O
I/O
N/A
LOW
LOW
NVVDD VID2 11/13
OVERT
ALERT
NC (HDA_SDI_NC) ROM_SI ROM_SO
11/8 for N12E D6 NC (HDA_RST_N_NC) ROM_SO C4
GFx_SCL
11/12 short
D7 NC (HDA_BCLK_NC) 1 3 MBCLK2 [8,13,29] 10 OUT N/A FBVREF SELECT
SPDIF_VGA R77 *36K/F_4 R481 Q41
R410 40.2K/F_4 STRAP_REF0 N9
SPDIF_NC A5
4.7K_4 2N7002
11 OUT N/A SLI SYNC0
2
MULTI_STRAP_REF0_GND
R409
R412
*0_4/S
*0_4/S
R8
M8
MULTI_STRAP_REF0_GND (NC)
A4
12 IN N/A PWR_LEVEL 11/13
D MULTI_STRAP_REF1_GND (NC) BUFRST_N +3V_GFX D
R411 40.2K/F_4 STRAP_REF1
STRAP0
M9
W5
MULTI_STRAP_REF1_GND R485
13 OUT N/A MEM_VID or power supply control
STRAP1 STRAP0 4.7K_4
2
Q42
STRAP2
W7
V7
STRAP1 GND K9
K8 R79 *0_4/S 2N7002
14 OUT N/A PS CONTROL
STRAP2 (NC) HDA_FUSE_SRC GFx_SDA 1 3 MBDATA2 [8,13,29]
N12x
11/11 for N12E PROJECT : TWH
11/12 short R484 *0_4 Quanta Computer Inc.
N12P AJ0N12P0T04
11/8 change for GPU temp detect Size Document Number Rev
Custom A
DGPU 4/5 (MIO/GPIO)
NB5 Date: W ednesday, December 15, 2010 Sheet 17 of 40
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
U17G
18
AA2 E9
AA5
AA11
GND_1
GND_2 [GPU GND]
GND_97
GND_98 E12
E15
N12P-GS (GB2-128) Stuff
GND_3 GND_99
AA12 GND_4 GND_100 E18
+VGACORE AA13 E24 +VGACORE
U17F GND_5 GND_101
A AA14 GND_6 GND_102 E27 A
AB11 VDD_001 VDD_057 P21 AA15 GND_7 GND_103 E30
AB13 VDD_002 [GPU VDD] VDD_058 P23 AA16 GND_8 GND_104 F2
AB15 VDD_003 VDD_059 P25 AA17 GND_9 GND_105 F5
AB17 VDD_004 VDD_060 R11 AA18 GND_10 GND_106 F31
AB19 R12 AA19 F34 C693 C694 C695 C696 C697 C698 C699 C700 C701 C702 C703
VDD_005 VDD_061 GND_11 GND_107
AB21 VDD_006 VDD_062 R13 AA20 GND_12 GND_108 J2
AB23 R14 AA21 J5 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.022U/16V_4 0.022U/16V_4 0.022U/16V_4
AB25 VDD_008 VDD_064 R15 AA22 GND_14 GND_110 J31
AC11 VDD_009 VDD_065 R16 AA23 GND_15 GND_111 J34
AC12 VDD_010 VDD_066 R17 AA24 GND_16 GND_112 L9
AC13 VDD_011 VDD_067 R18 AA25 GND_17 GND_113 M2
AC14 VDD_012 VDD_068 R19 AA34 GND_18 GND_114 M5
AC15 R20 AB12 M11 +VGACORE
AC16 VDD_014 VDD_070 R21 AB14 GND_20 GND_116 M13
2
AC21 T12 AB24 M23 C704 C705 C706 C707 C708 C709
VDD_019 VDD_075 GND_25 GND_121 C710
AC22 VDD_020 VDD_076 T14 AC9 GND_26 GND_122 M25
AC23 T16 AD11 M31 0.47U/10V_4 0.47U/10V_4 0.47U/10V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 22U/6.3V_8
1
AC24 VDD_022 VDD_078 T18 AD13 GND_28 GND_124 M34
AC25 VDD_023 VDD_079 T20 AD15 GND_29 GND_125 N11
AD12 VDD_024 VDD_080 T22 AD17 GND_30 GND_126 N12
AD14 VDD_025 VDD_081 T24 AD2 GND_31 GND_127 N13
AD16 VDD_026 VDD_082 V11 AD5 GND_32 GND_128 N14
B AD24 V17 AD25 N17 B
L11 VDD_030 VDD_086 V19 AD31 GND_36 GND_132 N18 N12E-GE : C395, C396, C397, C398, C399, C400, C401, C402, C403, C404, C405, C406, C407, C408, C409, C410, C411 stuff 0.1U/10V_4.
L12 VDD_031 VDD_087 V21 AD34 GND_37 GND_133 N19 N12E-GE : C412 Stuff 47U/6.3V_8
L13 VDD_032 VDD_088 V23 AE11 GND_38 GND_134 N20
L14 VDD_033 VDD_089 V25 AE12 GND_39 GND_135 N21
L15 W11 AE13 N22
L16
L17
VDD_034
VDD_035
VDD_090
VDD_091 W12
W13
AE14
AE15
GND_40
GND_41
GND_136
GND_137 N23
N24
N12E-GE (GB3-128) Stuff
L18 VDD_037 VDD_093 W14 AE16 GND_43 GND_139 N25
L19 VDD_038 VDD_094 W15 AE17 GND_44 GND_140 P12
L20 W16 AE18 P14 +VGACORE
M12 W22 AE24 R2 C711 C712 C713 C714 C715
M14 VDD_046 VDD_102 W23 AE25 GND_52 GND_148 R5
M16 W24 AG2 R31 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *1U/6.3V_4 *1U/6.3V_4
M18 VDD_048 VDD_104 W25 AG31 GND_54 GND_150 R34
M20 VDD_049 VDD_105 Y12 AG34 GND_55 GND_151 T11
M22 VDD_050 VDD_106 Y14 AK2 GND_56 GND_152 T13
M24 VDD_051 VDD_107 Y16 AG5 GND_57 GND_153 T15
P11 VDD_052 VDD_108 Y18 AK31 GND_58 GND_154 T17
P13 Y20 AK34 T19 +VGACORE
P19 VDD_056 AL6 GND_62 GND_158 T25
AL9 GND_63 GND_159 U11
C N12x C
AL12 GND_64 GND_160 U12
AL15 U13 C716 C717 C718 C719 C720 C721 C722
GND_65 GND_161
AL18 GND_66 GND_162 U14
AL21 U15 *1U/6.3V_4 *1U/6.3V_4 *1U/6.3V_4 *1U/6.3V_4 *1U/6.3V_4 *4.7U/6.3V_6 *4.7U/6.3V_6
N12P AJ0N12P0T04 AL24
GND_67 GND_163
U16
GND_68 GND_164
AL27 GND_69 GND_165 U17
AL30 GND_70 GND_166 U18
AN2 GND_71 GND_167 U19
AN34 GND_72 GND_168 U20
+VGACORE AP3 U21
GND_73 GND_169
AP6 GND_74 GND_170 U22
AP9 GND_75 GND_171 U23
AP12 GND_76 GND_172 U24
AP15 GND_77 GND_173 U25
AP18 GND_78 GND_174 V2 9/28 need check for N12E
C723 C724 C725 C726 AP21 V5
GND_79 GND_175
AP24 GND_80 GND_176 V9
0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 4.7U/6.3V_6 AP27 V12
GND_81 GND_177
AP30 GND_82 GND_178 V14
AP33 GND_83 GND_179 V16
B3 GND_84 GND_180 V18
B6 GND_85 GND_181 V20
B9 GND_86 GND_182 V22
+VGACORE B12 V24
GND_87 GND_183
B15 GND_88 GND_184 V31
B21 GND_89 GND_185 Y11
B24 GND_90 GND_186 Y13
B27 GND_91 GND_187 Y15
D B30 GND_92 GND_188 Y17 D
C727 C728 C729 B33 Y19
GND_93 GND_189
C2 GND_94 GND_190 Y21
10U/6.3V_8 10U/6.3V_8 47U/6.3V_8 C34 Y23
GND_95 GND_191
E6 GND_96 GND_192 Y25
N12x
PROJECT : TWH
N12P AJ0N12P0T04 Quanta Computer Inc.
A3 A
DGPU 5/5 (Power/Ground)
[37] +VGACORE
1 2 3 4 5 6 7 8
5 4 3 2 1
[15] VMA_DQ[63..0]
[15] VMA_DM[7..0]
[15] VMA_WDQS[7..0]
[15] VMA_RDQS[7..0] CHANNEL A: 256MB/512MB DDR3
19
VRAM3 VRAM8 VRAM4 VRAM7
VREFC_VMA1 M8 E3 VMA_DQ16 VREFC_VMA1 M8 E3 VMA_DQ30 VREFC_VMA3 M8 E3 VMA_DQ45 VREFC_VMA3 M8 E3 VMA_DQ58

VREFD_VMA1 VREFCA DQL0 VMA_DQ22 VREFD_VMA1 VREFCA DQL0 VMA_DQ26 VREFD_VMA3 VREFCA DQL0 VMA_DQ43 VREFD_VMA3 VREFCA DQL0 VMA_DQ63
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMA_DQ18 F2 VMA_DQ29 F2 VMA_DQ44 F2 VMA_DQ56
FBA_CMD9 DQL2 VMA_DQ23 FBA_CMD9 DQL2 VMA_DQ28 FBA_CMD9 DQL2 VMA_DQ41 FBA_CMD9 DQL2 VMA_DQ61
D [15] FBA_CMD9 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 D
FBA_CMD11 P7 H3 VMA_DQ19 FBA_CMD11 P7 H3 VMA_DQ31 FBA_CMD11 P7 H3 VMA_DQ47 FBA_CMD11 P7 H3 VMA_DQ59
[15] FBA_CMD11 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
FBA_CMD25 N2 G2 VMA_DQ17 FBA_CMD25 N2 G2 VMA_DQ27 FBA_CMD25 N2 G2 VMA_DQ46 FBA_CMD25 N2 G2 VMA_DQ60
FBA_CMD24 P2 FBA_CMD24 P2 FBA_CMD24 P2 FBA_CMD24 P2
[15] FBA_CMD24 A5 A5 A5 A5
FBA_CMD22 R8 FBA_CMD22 R8 FBA_CMD22 R8 FBA_CMD22 R8
[15] FBA_CMD22 A6 A6 A6 A6
FBA_CMD7 R2 D7 VMA_DQ7 FBA_CMD7 R2 D7 VMA_DQ12 FBA_CMD7 R2 D7 VMA_DQ36 FBA_CMD7 R2 D7 VMA_DQ51
[15] FBA_CMD7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
FBA_CMD21 T8 C3 VMA_DQ2 FBA_CMD21 T8 C3 VMA_DQ10 FBA_CMD21 T8 C3 VMA_DQ39 FBA_CMD21 T8 C3 VMA_DQ53
FBA_CMD6 R3 C8 VMA_DQ5 FBA_CMD6 R3 C8 VMA_DQ15 FBA_CMD6 R3 C8 VMA_DQ32 FBA_CMD6 R3 C8 VMA_DQ50
FBA_CMD29 L7 C2 VMA_DQ1 FBA_CMD29 L7 C2 VMA_DQ8 FBA_CMD29 L7 C2 VMA_DQ38 FBA_CMD29 L7 C2 VMA_DQ52
[15] FBA_CMD29 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
FBA_CMD23 R7 A7 VMA_DQ6 FBA_CMD23 R7 A7 VMA_DQ13 FBA_CMD23 R7 A7 VMA_DQ33 FBA_CMD23 R7 A7 VMA_DQ48
FBA_CMD28 N7 A2 VMA_DQ0 FBA_CMD28 N7 A2 VMA_DQ11 FBA_CMD28 N7 A2 VMA_DQ37 FBA_CMD28 N7 A2 VMA_DQ54
[15] FBA_CMD28 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
FBA_CMD20 T3 B8 VMA_DQ4 FBA_CMD20 T3 B8 VMA_DQ14 FBA_CMD20 T3 B8 VMA_DQ34 FBA_CMD20 T3 B8 VMA_DQ49
FBA_CMD4 T7 A3 VMA_DQ3 FBA_CMD4 T7 A3 VMA_DQ9 FBA_CMD4 T7 A3 VMA_DQ35 FBA_CMD4 T7 A3 VMA_DQ55
FBA_CMD14 M7 FBA_CMD14 M7 FBA_CMD14 M7 FBA_CMD14 M7
[15] FBA_CMD14 A15 A15 A15 A15
FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2

[15] FBA_CMD12 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2
FBA_CMD27 N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9
[15] FBA_CMD27 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
FBA_CMD26 M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7
[15] FBA_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#K2 K2 VDD#K2 K2 VDD#K2 K2 VDD#K2 K2
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
[15] VMA_CLK0 VMA_CLK0 J7 N9 VMA_CLK0 J7 N9 [15] VMA_CLK1 VMA_CLK1 J7 N9 VMA_CLK1 J7 N9
VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 VMA_CLK1# CK VDD#N9 VMA_CLK1# CK VDD#N9
[15] VMA_CLK0# K7 R1 K7 R1 [15] VMA_CLK1# K7 R1 K7 R1
FBA_CMD3 CK VDD#R1 FBA_CMD3 CK VDD#R1 FBA_CMD19 CK VDD#R1 FBA_CMD19 CK VDD#R1 +1.5V_GFX
[15] FBA_CMD3 K9 CKE VDD#R9 R9 K9 CKE VDD#R9 R9 [15] FBA_CMD19 K9 CKE VDD#R9 R9 K9 CKE VDD#R9 R9
+1.5V_GFX
FBA_CMD2 K1 A1 FBA_CMD2 K1 A1 FBA_CMD18 K1 A1 FBA_CMD18 K1 A1

[15] FBA_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 [15] FBA_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
C FBA_CMD0 L2 A8 FBA_CMD0 L2 A8 FBA_CMD16 L2 A8 FBA_CMD16 L2 A8 C
[15] FBA_CMD0 CS VDDQ#A8 CS VDDQ#A8 [15] FBA_CMD16 CS VDDQ#A8 CS VDDQ#A8
FBA_CMD30 J3 C1 FBA_CMD30 J3 C1 FBA_CMD30 J3 C1 FBA_CMD30 J3 C1
[15] FBA_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
[15] FBA_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2
[15] FBA_CMD13 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMA_WDQS2 F3 H2 VMA_WDQS3 F3 H2 VMA_WDQS5 F3 H2 VMA_WDQS7 F3 H2
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS5 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2
G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9
VMA_DM2 E7 A9 VMA_DM3 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 DML VSS#A9 VMA_DM1 DML VSS#A9 VMA_DM4 DML VSS#A9 VMA_DM6 DML VSS#A9
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMA_WDQS0 VSS#G8 VMA_WDQS1 VSS#G8 VMA_WDQS4 VSS#G8 VMA_WDQS6 VSS#G8
C7 J2 C7 J2 C7 J2 C7 J2
VMA_RDQS0 DQSU VSS#J2 VMA_RDQS1 DQSU VSS#J2 VMA_RDQS4 DQSU VSS#J2 VMA_RDQS6 DQSU VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
P1 P1 P1 P1
FBA_CMD5 VSS#P1 FBA_CMD5 VSS#P1 FBA_CMD5 VSS#P1 FBA_CMD5 VSS#P1
[15] FBA_CMD5 T2 P9 T2 P9 T2 P9 T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R185 VSSQ#B9 R490 VSSQ#B9 R180 VSSQ#B9 R497 VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
243/F_4 D8 243/F_4 D8 243/F_4 D8 243/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
B NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 B
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VRAM _DDR3 VRAM _DDR3 VRAM _DDR3 VRAM _DDR3
+1.5V_GFX +1.5V_GFX FBA_CMD17 TP29 +1.5V_GFX +1.5V_GFX

[15] FBA_CMD17
FBA_CMD1 TP33
[15] FBA_CMD1
VMA_CLK0 R505 R188 R187 R507
1.33K/F_4 1.33K/F_4 1.33K/F_4 1.33K/F_4
R178 VMA_CLK1
160/F_4 VREFC_VMA1 VREFD_VMA1 R183 VREFC_VMA3 VREFD_VMA3

VMA_CLK0# 160/F_4
Fermi : Change to 160 ohm R499 C530 R182 VMA_CLK1# R186 C297 R515 C544
1.33K/F_4 1.33K/F_4 C295 1.33K/F_4 1.33K/F_4
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) 0.1U/10V_4 0.1U/10V_4 Fermi : Change to 160 ohm 0.1U/10V_4 0.1U/10V_4
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) 1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)
+1.5V_GFX
A +1.5V_GFX A
C527 10U/6.3V_8 C291 10U/6.3V_8 +1.5V_GFX

Samsung 900MHz 1G AKD5LGHT500 [15,20,37,38] +1.5V_GFX
+1.5V_GFX C556 0.1U/10V_4 C539 10U/6.3V_8 C532 10U/6.3V_8
C551 0.1U/10V_4
+1.5V_GFX C531
C554
10U/6.3V_8
0.1U/10V_4
C296 0.1U/10V_4 C292
C293
0.1U/10V_4
0.1U/10V_4
C538 10U/6.3V_8
PROJECT : TWH
C528
C555
1U/10V_4
1U/10V_4
C316
C553
0.1U/10V_4
0.1U/10V_4
C535
C537
0.1U/10V_4
0.1U/10V_4
C301 0.1U/10V_4
C541 0.1U/10V_4
C318 1U/10V_4 C521 0.1U/10V_4 C300 0.1U/10V_4 C520 0.1U/10V_4 C552 0.1U/10V_4
C519 1U/10V_4 C294 0.1U/10V_4 C529 0.1U/10V_4 C315 0.1U/10V_4 C526 0.1U/10V_4 Size Document Number Rev
Custom A
DGPU Memory 1/2 (DDR3)
5 4 3 2 1
5 4 3 2 1
[15] VMC_DQ[63..0]
[15] VMC_DM[7..0]
[15] VMC_WDQS[7..0]
[15] VMC_RDQS[7..0] CHANNEL B: 256MB/512MB DDR3 20
VRAM5 VRAM1 VRAM2 VRAM6
VREFC_VMC1 M8 E3 VMC_DQ22 VREFC_VMC1 M8 E3 VMC_DQ24 VREFC_VMC3 M8 E3 VMC_DQ36 VREFC_VMC3 M8 E3 VMC_DQ49

VREFD_VMC1 VREFCA DQL0 VMC_DQ21 VREFD_VMC1 VREFCA DQL0 VMC_DQ30 VREFD_VMC3 VREFCA DQL0 VMC_DQ34 VREFD_VMC3 VREFCA DQL0 VMC_DQ48
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMC_DQ23 F2 VMC_DQ26 F2 VMC_DQ39 F2 VMC_DQ55
FBC_CMD9 DQL2 VMC_DQ16 FBC_CMD9 DQL2 VMC_DQ28 FBC_CMD9 DQL2 VMC_DQ32 FBC_CMD9 DQL2 VMC_DQ53
D [15] FBC_CMD9 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 D
FBC_CMD11 P7 H3 VMC_DQ20 FBC_CMD11 P7 H3 VMC_DQ25 FBC_CMD11 P7 H3 VMC_DQ37 FBC_CMD11 P7 H3 VMC_DQ52
[15] FBC_CMD11 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
FBC_CMD25 N2 G2 VMC_DQ18 FBC_CMD25 N2 G2 VMC_DQ27 FBC_CMD25 N2 G2 VMC_DQ38 FBC_CMD25 N2 G2 VMC_DQ54
FBC_CMD24 P2 FBC_CMD24 P2 FBC_CMD24 P2 FBC_CMD24 P2
[15] FBC_CMD24 A5 A5 A5 A5
FBC_CMD22 R8 FBC_CMD22 R8 FBC_CMD22 R8 FBC_CMD22 R8
[15] FBC_CMD22 A6 A6 A6 A6
FBC_CMD7 R2 D7 VMC_DQ3 FBC_CMD7 R2 D7 VMC_DQ8 FBC_CMD7 R2 D7 VMC_DQ42 FBC_CMD7 R2 D7 VMC_DQ61
[15] FBC_CMD7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
FBC_CMD21 T8 C3 VMC_DQ6 FBC_CMD21 T8 C3 VMC_DQ14 FBC_CMD21 T8 C3 VMC_DQ47 FBC_CMD21 T8 C3 VMC_DQ58
FBC_CMD6 R3 C8 VMC_DQ0 FBC_CMD6 R3 C8 VMC_DQ9 FBC_CMD6 R3 C8 VMC_DQ41 FBC_CMD6 R3 C8 VMC_DQ62
FBC_CMD29 L7 C2 VMC_DQ7 FBC_CMD29 L7 C2 VMC_DQ12 FBC_CMD29 L7 C2 VMC_DQ45 FBC_CMD29 L7 C2 VMC_DQ59
[15] FBC_CMD29 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
FBC_CMD23 R7 A7 VMC_DQ1 FBC_CMD23 R7 A7 VMC_DQ11 FBC_CMD23 R7 A7 VMC_DQ44 FBC_CMD23 R7 A7 VMC_DQ60
FBC_CMD28 N7 A2 VMC_DQ5 FBC_CMD28 N7 A2 VMC_DQ13 FBC_CMD28 N7 A2 VMC_DQ43 FBC_CMD28 N7 A2 VMC_DQ56
[15] FBC_CMD28 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
FBC_CMD20 T3 B8 VMC_DQ2 FBC_CMD20 T3 B8 VMC_DQ10 FBC_CMD20 T3 B8 VMC_DQ40 FBC_CMD20 T3 B8 VMC_DQ63
FBC_CMD4 T7 A3 VMC_DQ4 FBC_CMD4 T7 A3 VMC_DQ15 FBC_CMD4 T7 A3 VMC_DQ46 FBC_CMD4 T7 A3 VMC_DQ57
FBC_CMD14 M7 FBC_CMD14 M7 FBC_CMD14 M7 FBC_CMD14 M7
[15] FBC_CMD14 A15 A15 A15 A15
FBC_CMD12 M2 B2 FBC_CMD12 M2 B2 FBC_CMD12 M2 B2 FBC_CMD12 M2 B2

[15] FBC_CMD12 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2
FBC_CMD27 N8 D9 FBC_CMD27 N8 D9 FBC_CMD27 N8 D9 FBC_CMD27 N8 D9
[15] FBC_CMD27 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
FBC_CMD26 M3 G7 FBC_CMD26 M3 G7 FBC_CMD26 M3 G7 FBC_CMD26 M3 G7
[15] FBC_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
[15] VMC_CLK0 VMC_CLK0 J7 N9 VMC_CLK0 J7 N9 [15] VMC_CLK1 VMC_CLK1 J7 N9 VMC_CLK1 J7 N9
VMC_CLK0# CK VDD#N9 VMC_CLK0# CK VDD#N9 VMC_CLK1# CK VDD#N9 VMC_CLK1# CK VDD#N9
[15] VMC_CLK0# K7 R1 K7 R1 [15] VMC_CLK1# K7 R1 K7 R1
FBC_CMD3 CK VDD#R1 FBC_CMD3 CK VDD#R1 +1.5V_GFX FBC_CMD19 CK VDD#R1 FBC_CMD19 CK VDD#R1 +1.5V_GFX
[15] FBC_CMD3 K9 CKE VDD#R9 R9 K9 CKE VDD#R9 R9 [15] FBC_CMD19 K9 CKE VDD#R9 R9 K9 CKE VDD#R9 R9
FBC_CMD2 K1 A1 FBC_CMD2 K1 A1 FBC_CMD18 K1 A1 FBC_CMD18 K1 A1

[15] FBC_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 [15] FBC_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
C FBC_CMD0 L2 A8 FBC_CMD0 L2 A8 FBC_CMD16 L2 A8 FBC_CMD16 L2 A8 C
[15] FBC_CMD0 CS VDDQ#A8 CS VDDQ#A8 [15] FBC_CMD16 CS VDDQ#A8 CS VDDQ#A8
FBC_CMD30 J3 C1 FBC_CMD30 J3 C1 FBC_CMD30 J3 C1 FBC_CMD30 J3 C1
[15] FBC_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
FBC_CMD15 K3 C9 FBC_CMD15 K3 C9 FBC_CMD15 K3 C9 FBC_CMD15 K3 C9
[15] FBC_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
FBC_CMD13 L3 D2 FBC_CMD13 L3 D2 FBC_CMD13 L3 D2 FBC_CMD13 L3 D2
[15] FBC_CMD13 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMC_WDQS2 F3 H2 VMC_WDQS3 F3 H2 VMC_WDQS4 F3 H2 VMC_WDQS6 F3 H2
VMC_RDQS2 DQSL VDDQ#H2 VMC_RDQS3 DQSL VDDQ#H2 VMC_RDQS4 DQSL VDDQ#H2 VMC_RDQS6 DQSL VDDQ#H2
G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9
VMC_DM2 E7 A9 VMC_DM3 E7 A9 VMC_DM4 E7 A9 VMC_DM6 E7 A9

VMC_DM0 DML VSS#A9 VMC_DM1 DML VSS#A9 VMC_DM5 DML VSS#A9 VMC_DM7 DML VSS#A9
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMC_WDQS0 VSS#G8 VMC_WDQS1 VSS#G8 VMC_WDQS5 VSS#G8 VMC_WDQS7 VSS#G8
C7 J2 C7 J2 C7 J2 C7 J2
VMC_RDQS0 DQSU VSS#J2 VMC_RDQS1 DQSU VSS#J2 VMC_RDQS5 DQSU VSS#J2 VMC_RDQS7 DQSU VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
M9 M9 M9 M9
P1 P1 P1 P1
FBC_CMD5 VSS#P1 FBC_CMD5 VSS#P1 FBC_CMD5 VSS#P1 FBC_CMD5 VSS#P1
[15] FBC_CMD5 T2 P9 T2 P9 T2 P9 T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMC_ZQ1 VSS#T1 VMC_ZQ2 VSS#T1 VMC_ZQ3 VSS#T1 VMC_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R426 VSSQ#B9 R116 VSSQ#B9 R171 VSSQ#B9 R131 VSSQ#B9
D1 D1 D1 D1
243/F_4 D8 243/F_4 D8 243/F_4 D8 243/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
B NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 B
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VRAM _DDR3 VRAM _DDR3 VRAM _DDR3 VRAM _DDR3
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
VMC_CLK0 R101 R434 VMC_CLK1 R479 R478

1.33K/F_4 1.33K/F_4 1.33K/F_4 1.33K/F_4
R61 R173
160/F_4 160/F_4
VREFC_VMC1 VREFD_VMC1 VREFC_VMC3 VREFD_VMC3
VMC_CLK0# VMC_CLK1#
Fermi : Change to 160 ohm R97 R427 Fermi : Change to 160 ohm R480 R477 C507
1.33K/F_4 C189 1.33K/F_4 C453 1.33K/F_4 C510 1.33K/F_4
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) 0.1U/10V_4 0.1U/10V_4 1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) 0.1U/10V_4 0.1U/10V_4
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) 2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)
A +1.5V_GFX A
FBC_CMD17 TP26
[15] FBC_CMD17
C491 10U/6.3V_8 [15,19,37,38] +1.5V_GFX
+1.5V_GFX +1.5V_GFX FBC_CMD1 TP21
[15] FBC_CMD1
C225 10U/6.3V_8 C160 0.1U/10V_4 C219 0.1U/10V_4
+1.5V_GFX C459 10U/6.3V_8
C274
C172
0.1U/10V_4
0.1U/10V_4
C443
C508
0.1U/10V_4
0.1U/10V_4 PROJECT : TWH
C276 1U/10V_4 C436 0.1U/10V_4
C441
C253
0.1U/10V_4
0.1U/10V_4
C271
C56
0.1U/10V_4
0.1U/10V_4
C455 1U/10V_4 C267 0.1U/10V_4 C456 0.1U/10V_4 C437 0.1U/10V_4
C509 1U/10V_4 C484 0.1U/10V_4 C277 0.1U/10V_4 C506 0.1U/10V_4 Size Document Number Rev
C57 1U/10V_4 C269 0.1U/10V_4 C220 0.1U/10V_4
Samsung 900MHz 1G AKD5LGHT500 Custom A
DGPU Memory 2/2 (DDR3)
5 4 3 2 1
5 4 3 2 1
R13 2.2K_4
21
+3V
R12 2.2K_4
USB Camera Connector EDIDCLK

[6] PCH_EDIDCLK
[6] PCH_EDIDDATA EDIDDATA
+5V CN7
R14 *0_6 +3V
G_0
U1 R8 *0_6/S +5V +3VLCD_CON 1
3 VIN VOUT 4 +3.6V_CAM 2
C10 1000P/50V_4
3
12/13 short +3V 4
C15 EDIDCLK
EDIDDATA 5
1
D SHDN R1 R15 6 D
*1U/6.3V_4 *215K/F/04 TXLOUT0- 7

[6] PCH_LA_DATAN0 8
C14 [6] PCH_LA_DATAP0 TXLOUT0+
9
2 GND SET 5 10 G_1
*4.7U/6.3V_6 [6] PCH_LA_DATAN1 TXLOUT1-
*IC(5P) G913C (SOT23-5)EP TXLOUT1+ 11
[6] PCH_LA_DATAP1 12
R16 TXLOUT2- 13
Vout=1.25(1+R1/R2) R2 *100K/F_4
[6] PCH_LA_DATAN2
[6] PCH_LA_DATAP2 TXLOUT2+ 14
15
TXLCLKOUT- 16
[6] PCH_LA_CLK# 17
[6] PCH_LA_CLK TXLCLKOUT+
18 G_2
TXUOUT0- 19
[6] PCH_LB_DATAN0 20
TXUOUT0+
MIC [6] PCH_LB_DATAP0 21
L23 SBK160808T-301Y-N DIGITAL_D1_R TXUOUT1- 22
[23] DIGITAL_D1 [6] PCH_LB_DATAN1 23
[23] DIGITAL_CLK L22 SBK160808T-301Y-N DIGITAL_CLK_R [6] PCH_LB_DATAP1 TXUOUT1+
24 G_3
CON_USBP9- TXUOUT2- 25
[8] USBP9- 2 1 [6] PCH_LB_DATAN2 26
3 4 CON_USBP9+ [6] PCH_LB_DATAP2 TXUOUT2+
[8] USBP9+ 27
L21 TXUCLKOUT- 28
CAMERA 8/26 A-->B modify [6] PCH_LB_CLK# 29
W CM2012-90 [6] PCH_LB_CLK TXUCLKOUT+
DIGITAL_D1_R 30
DIGITAL_CLK_R 31 G_4
8/26 A-->B modify 32
[6] PCH_DPST_PW M DPST_PW M_R +3.6V_CAM
C11 0.01U/16V_4 CON_USBP9- 33
+3.6V_CAM 34
C C16 *4.7U/6.3V_6 8/26 A-->B modify CON_USBP9+ C
35
11/11 changed from +3VPCU 36
[29] PW M_VADJ R10 *0_4 DPST_PW M_R
C422 *10P/50V_4 CON_USBP9- BLON_CON 37
8/26 A-->B modify 38
C421 *10P/50V_4 CON_USBP9+ C13 *4.7U/6.3V_6 +VIN_BLIGHT
C424 33P/50V_4 DIGITAL_D1 +5VS5 +12VALW +3V C12 *0.1U/10V_4 39
14.5v
G_5
C423 33P/50V_4 DIGITAL_CLK 40
AO3404 ID
2
current C1 0.1U/10V_4
R1 5.8A GS12401-1011-9F
330K_6
3
Q1 +3VLCD +3VLCD_CON
1
R9 AO3404
100K/F_4 LCDONG 2 L1
PBY201209T-4A/08
1
C8 *0.01U/16V_4
3
R6 C9 0.1U/10V_4
C4 *10U/6.3V_8 +VIN_BLIGHT
1
22_8
2
2
1
Q3 C2 LCDDISCHG +VIN L2 FBM2125 HM330-T +VIN_BLIGHT
2N7002 0.027U/25V_6
3
1
Q5 C5 C420 *10U/25V_12
3
DTC144EUA 0.1U/50V_6 C6 0.1U/50V_6
LCDON# 2 Q4 C7 0.01U/25V_4
B [6] PCH_DISP_ON DISP_ON 2 2N7002 B
1
1
R11 100K/F_4
R5 100K/F_4
C3 22P/50V_4
D2 RB501V-40
[29] LID_CONTROL R3 0_4 PN_BLON BLON_CON
R7 47K_4 +3VPCU
[6] PCH_LVDS_BLON LVDS_BLON R2 1K/F_4 D1 *RB501V-40

LID_EC# [28,29]
A A
R4 100K/F_4
3
2
PROJECT : TWH
[8] LCD_BK
Q2
*DTC144EUA
[2,6,7,8,9,10,12,13,14,22,23,24,25,26,27,28,29,34,36,37,39] +3V
[6,7,27,28,29,30,31] +3VPCU
1

[6,7,10,22,23,27,28,36] +5V Custom A
LCD Connector (LVDS)
[30,31,32,33,34,35,36,37,38,40] +VIN
5 4 3 2 1
5 4 3 2 1
CRT PORT
22
16
40 MIL 6
[6] PCH_CRT_R L4 NBQ160808T-470Y-N CRT_R_CON 1 11
40 mils 7
D F1 2 1 +5VCRT +5VCRT [6] PCH_CRT_G L5 NBQ160808T-470Y-N CRT_G_CON 2 12 CRT_DDCDATA_CON C33 *470P/50V_4 D
+5V
FUSE1A6V_POLY 8
C20 0.1U/10V_4 [6] PCH_CRT_B L3 NBQ160808T-470Y-N CRT_B_CON 3 13 CRT_HSYNC_CON C32 *47P/50V_6
+5VCRT 9
SSM14 spec is 40V 1A 4 14 CRT_VSYNC_CON C25 *47P/50V_6
R44 R45 R46 C43 C39 C40 10
C34 C36 C38 5 15 CRT_DDCCLK_CON C22 *470P/50V_4
150/F_4 *6.8P/50V_4 6.8P/50V_4

150/F_4 *6.8P/50V_4 6.8P/50V_4 CRT CONN
17
150/F_4 *6.8P/50V_4 6.8P/50V_4 CN9
EMI
Isolation R48 *0_4

Driven Strong U3 M74VHC1GT125DF2G
Q10 2N7002
[6] PCH_VSYNC CRT_VSYNC 2 4 CRT_VSYNC_CON
[6] PCH_DDCCLK CRT_DDCCLK 1 3 R51 *0_4/S CRT_DDCCLK_CON
short0402
+5V R47 2.2K_4 R50 4.7K_4
C35
C C
5 5
1 1
2
+3V +5VCRT 2 1+5VCRT2
D3 RB501V-40
2
R56 2.2K_4 R52 4.7K_4
0.1U/10V_4
[6] PCH_HSYNC CRT_HSYNC 2 4 CRT_HSYNC_CON [6] PCH_DDCDATA CRT_DDCDATA 1 3 R53 *0_4/S CRT_DDCDATA_CON
short0402
U4 M74VHC1GT125DF2G Q13 2N7002
R57 *0_4
HDMI PORT
12/13 change to 4 ground pin connector for EMI
CN5002
+5V_HDMIC SHELL3 22
+3V IN_D2 C266 0.1U/10V_4 C_TX2_HDMI+ SHELL1 20
1 D2+
HDMI SMBus Isolation +3V
EMI Solution [6] IN_D2
IN_D2# C261 0.1U/10V_4 C_TX2_HDMI-
2 D2 Shield
3 D2-
[6] IN_D2#
B [6] IN_D1 IN_D1 C258 0.1U/10V_4 C_TX1_HDMI+ 4 D1+ B
R126 C221 C_TX2_HDMI+ R169 150 C_TX2_HDMI- 5 D1 Shield
*0.01U/16V_4 C_TX1_HDMI+ R161 150 C_TX1_HDMI- [6] IN_D1# IN_D1# C255 0.1U/10V_4 C_TX1_HDMI- 6 D1-
2
2.2K_4 C_TX0_HDMI+ R154 150 C_TX0_HDMI- [6] IN_D0 IN_D0 C252 0.1U/10V_4 C_TX0_HDMI+ 7 D0+
C_TXC_HDMI+ R143 150 C_TXC_HDMI- 8 D0 Shield
[6] SDVO_CLK HDMI_SCL_R 1 3 HDMI_SCLK [6] IN_D0# IN_D0# C249 0.1U/10V_4 C_TX0_HDMI- 9
[6] IN_CLK IN_CLK C242 0.1U/10V_4 C_TXC_HDMI+ 10 D0-
Q16 CK+
for EMI request 11 CK Shield
FDV301N [6] IN_CLK# IN_CLK# C237 0.1U/10V_4 C_TXC_HDMI- 12
+3V CH751H-40GP CK-
13 CE Remote
+3V D19 2 1 5V_HSMBCK R468 2.2K_4 14 NC
+5V
2 1 5V_HSMBDT R467 2.2K_4 HDMI_SCLK 15 DDC CLK
D18 CH751H-40GP HDMI_SDATA 16 DDC DATA
R112 C228 *10P/50V_4 17 GND
Q15 C232 *10P/50V_4 18 +5V
2
2.2K_4 FDV301N 12/13 short 19 HP DET

R449 *0_4/S F2 2 1 +5V_HDMIC
HDMI_SDA_R HDMI_SDATA
+3V +5V
FUSE1A6V_POLY SHELL2 21
[6] SDVO_DATA 1 3 SHELL4 23
[29] HDMI_HPD HDMI_DET_N HDMI_DET_C
R450 *0_4 +3V_GFX R114 10K/F_4 L11 BLM18BA470SN1D
C214 HDMI CONN_4 pin GND
D4
R451 10/8 add for EMI
3
Q39 150K/F_4 +3V 220P/50V_4

MMBT3904-7-F HDMI_DET_P HDMI_HPD 1
2 2 1 3
11/11 pin 13,17 -> NC
for HDMI 7-13 test issue
R113
1
2
1
[6] HDMI_HPD_CON HDMI_HPD_3V

DGPU_CL_HDMIP R472 680/F_4 C_TX2_HDMI+ R452 110K/F_4 BAV99W
A
R471 680/F_4 C_TX2_HDMI- *348K/F_4 A
R465
3
+3V R469 680/F_4 C_TX1_HDMI+ 10K_4 B-stage change

2
Q18 R466 680/F_4 C_TX1_HDMI-

2N7002
2 R464 680/F_4 C_TX0_HDMI+
R461 680/F_4 C_TX0_HDMI-
PROJECT : TWH
R458
R455
680/F_4
680/F_4
C_TXC_HDMI+
C_TXC_HDMI-
1
9/1 change to 680ohm Size Document Number Rev

Custom A
CRT/HDMI Connector
8/31UMA/OPTIMUS-680 ohm, DISCRETE-499 ohm
5 4 3 2 1
A B C D E
+5V
L36
HCB1608K-181T15
5V_AMP_PWR39
C690
C685
0.1U/10V_4
5V_AMP_PWR39 +5V_AVDD
+5V_AVDD L34 HCB1608K-181T15
+5V
Internal Speaker 23
INT SPEAKER CONN
4.7U/6.3V_6 5V_AMP_PWR46 C618 C615 L_SPK+ L20 SBK160808T-221Y-N L_SPK+_R
+3V 1
+5V C673 C659 C631 C644 C639 1U/10V_4 10U/6.3V_8 L_SPK- L19 SBK160808T-221Y-N L_SPK-_R
1U/10V_4 *0.1U/10V_4 4.7U/6.3V_6 1U/10V_4 *0.1U/10V_4 R_SPK- L18 SBK160808T-221Y-N R_SPK-_R 2
3
1
C689 C688 R_SPK+ L17 SBK160808T-221Y-N R_SPK+_R
L37 5V_AMP_PWR46 4
4 +5V_AVDD CN19 4
HCB1608K-181T15 4.7U/6.3V_6 0.1U/10V_4
2
C416 C417
AGND C418
C691 C686 +3V 680P/50V_4 680P/50V_4 C419
4.7U/6.3V_6 0.1U/10V_4 AGND 680P/50V_4
680P/50V_4
9/8 EMI need change to 680p
46
39
38
25
9
1
U28
DVDD1
DVDD-IO
PVDD2
PVDD1
AVDD2
AVDD1
36 ALC269_CBP
C664 *10P/50V_4 CBP
35 ALC269_CBN
ACZ_SDOUT_AUDIO CBN C670 2.2U/10V_6
[7] ACZ_SDOUT_AUDIO 5 SDATA-OUT
33 EARP_R1 R375 30_4 EARP_R
BIT_CLK_AUDIO HP-OUT-R EARP_L1 R374 30_4 EARP_L
[7] BIT_CLK_AUDIO 6 BIT-CLK HP-OUT-L 32
C663 *10P/50V_4
[7] ACZ_SDIN0 R645 22_4 HD_SDIN0 8 31 VREFOUT_AL R371 4.7K_4 EXT_MIC_L C1002 C1003
SDATA-IN MIC1_VREF_L
Digital
[7] ACZ_SYNC_AUDIO ACZ_SYNC_AUDIO 10 30 VREFOUT_AR R661 4.7K_4 EXT_MIC_R
SYNC MIC1-VREFO-R 150P/50V_4 150P/50V_4
Analog
C655 *10P/50V_4
[7] ACZ_RST#_AUDIO ACZ_RST#_AUDIO 11 29
RESET# MIC2-VREFO
27 ALC269_VREF AGND
VREF
1 2
L_SPK+ 40 24 C653 4.7U/6.3V_6 AGND
L_SPK- SPK-L+ LINE1-R C656 1U/10V_4
3 41 SPK-L- LINE1-L 23 9/5 add de-pop circuit, add 3
R384 0_4 C1002,C1003,C1004
R668 0_4 R_SPK- 44
R579 0_4 R_SPK+ SPK-R- EXT_MIC_R1 C411 2.2U/6.3V_6 EXT_MIC_R2 R660 1K_4 EXT_MIC_R
Q1005,Q1006,Q1007
45 22
R583 0_4 SPK-R+
ALC269Q-VB6-GR MIC1-R
MIC1-L 21 EXT_MIC_L1
C643 2.2U/6.3V_6
EXT_MIC_L2
R368 1K_4
EXT_MIC_L R1007,R1008,R1009,R1010,R1011,R1012,R1013,R1014
R383 0_4 TP80 ADC_EAPD# 47 SPDIFO2/EAPD

48 SPDIFO MONO-OUT 20
R5005 0_4 18 +3V
Sense B
C674 10P/50V_4 17
MIC2-R
[21] DIGITAL_D1 2 GPIO0/DMIC-DATA MIC2-L 16
1
AGND R1007
12/10 add EMI [21] DIGITAL_CLK DMIC_CLK_R 3 R1010 R1011
GPIO1/DMIC-CLK
1
R654 100/F_4 15
C668 10P/50V_4 LINE2-R
14 Q1005
LINE2-L *220K_4 *0_4 *0_4
ME2303T1
2
HD_APD#_P4 4 ADC_EAPD# 2
PD#
3
AMP_BEEP 12 13 SENSE_A
LDO_CAP
PCBEEP Sense A Q1006
CPVEE
DVSS2
PVSS1
PVSS2
AVSS2
AVSS1
JDREF
PGND
R1008 R1009 R1012 AP2302GN

HP_VOLMUTE 2
3
1K/F_4
3
ALC269Q-VB6-GR *0_4 4.7K_4
10/5 change VB6
7
49
42
43
37
26
34
19
28
9/5 "PD#" circuit modify C1004 Q1007
R1014 R1013
1.delete R650,R372,R373,Q27,Q28,D16,D17,D15
1
ALC269_CPVEE
4.7K_4 1U/10V_4 1K/F_4 2
2.add Q1002,Q1003,Q1004,R1004,R1005,R1006
2 2
C661 0.047U/25V_4
C666 10U/6.3V_8 AP2302GN
R615 20K/F_4
1
+5V AGND
AGND C667 2.2U/10V_6 AGND
12/8 change to 16 AGND
R1004 pin connector

R1005 1K/J_4 +5V (add 2 AGND pin) CN5001
4.7K/F_4 R662 DUAL USB CONN
SENSE_A +5VS5
HD_APD#_P4 1
20K/F_4 11/12 short 8/26 A-->B modify 2
3
3
R376 Q30 [8] USBP1+

Q1002 R1006 47K_4 DMN601K-7 R361 *0_4/S HDA_BEEP1 4
[8] USBP1- 5
[26,29] USB_ENABLE# 6
[29] VOLMUTE# 2 SENSE_MIC 2 7
** SENSE_PHONE
8
3
2N7002E *4.7K/F_4 +3V C1005 SENSE_MIC

Q1003 9
EARP_L 10
1 2 9/8 EMI(near CN18)
1
VOLMUTE# 220P/50V_4 EARP_R 11

2 12
C415
13
5
+5V AGND *0.1U/10V_4 EXT_MIC_L

2N7002E R663 C414 EXT_MIC_R 14
[7] SPKR 1 15
SENSE_A 4 HDA_BEEP2 0.1U/10V_4 AMP_BEEP
3 1
HP_VOLMUTE 16
1 [29] PC_BEEP_EC 2 1
39.2K/F_4 R370 100P/50V_4 C413
3
Q1004 R377 Q33 U10 100K_4

3
47K_4 DMN601K-7 R369 R366 *NC7SZ86 AGND

ACZ_RST#_AUDIO 2 *10K/F_4 *150K/F_4 R367
SENSE_PHONE 2
10/8 change net name
10K/F_4
PROJECT : TWH
2N7002E
10/11 R361 mount, other unmount
1

Custom A
Audio Codec (Realtek_ALC269)
AGND NB5 Date: Tuesday, December 14, 2010 Sheet 23 of 40
A B C D E
5 4 3 2 1
Atheros Lan
24
10/5 AR8151-AL008151005 +3VLANVCC PLACE NEAR LAN IC PIN6
AVDDL C591 1U/6.3V_4
D
** C578
C587
C597
C593
10U/6.3V_8
10U/6.3V_8
1000P/50V_4
1U/6.3V_4
AVDDL
AVDDL
AVDDL
AVDDL
C579
C590
C585
C594
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
+3VS5 +3VLANVCC D
C572 0.1U/10V_4 AVDDL C566 0.1U/10V_4

R559 *0_8
** +3V
13
19
31
34
1
6
U6
11/15 delete R253,R255
VDD33
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG
[8] CLK_PCIE_LANP 33 11 MDI0+ Q2001
REFCLKP TRXP0
2
[8] CLK_PCIE_LANN 32 12 MDI0- 2N7002E
C364 0.1U/10V_4 PCIE_RXP2_LAN_L REFCLKN TRXN0 MDI1+
[8] PCIE_RXP2_LAN 30 TX_P TRXP1 14
[8] PCIE_RXN2_LAN C363 0.1U/10V_4 PCIE_RXN2_LAN_L 29 15 MDI1- 1 3 CKREQ_G#
TX_N TRXN1 [8] PCIE_CLKREQ_LAN#
[8] PCIE_TXP2_LAN 35 17 MDI2+
RX_P TRXP2 MDI2-
[8] PCIE_TXN2_LAN 36 RX_N TRXN2 18
20 MDI3+
TRXP3
R233 *0_4
Atheros MDI3- R2006 *0_4
P L T R S T #
[29] LAN_REST# TRXN3 21
[2,8,14,26,27,29] PLTRST# 2 PERSTn
R2002 *0_4 PCIE_WAKE#_R 3 39 LAN_GLINK100#
[29] LAN_S5_WAKE# WAKEn LED_LINK10/100n
[6,26,27] PCIE_WAKE# R2004 *0_4/S 38 LAN_TX# 10/11 add
LED_ACTn
2 1 CLKREQn/LED2 23
D2002 *RB501V-40
12/13 short +3VLANVCC R542 4.7K_4 CKREQ_G# 4 L15
VDDCT_REG/CKRn LX C562 0.1U/10V_4 LAN_GLINK100# LAN_GLED#
40
10/11 add D2002

R239 2.37K/F_4 RBIAS 10 RBIAS AR8151 LX 4.7uh_C_1A C563
C331
0.1U/10V_4
10U/6.3V_8 LAN_TX# LAN_YLED
C 25 C565 1000P/50V_4 C
SMCLK AVDD_CEN C564 0.1U/10V_4
10/5 add R2004 for LAN wake up 26 SMDATA VDDCT 5 8/26 A-->B modify
8/26 A-->B modify C462 C86
9/28 delete short net TEST_RST 28
AVDDH_REG
XTLO_LAN_C 7 27 1000P/50V_4 1000P/50V_4
DVDD_REG
XTLO TESTMODE
Y2 GND1 41
AVDDH
AVDDH
DVDDL
1 2XTLI_LAN_C 8
GND
GND
GND
GND
GND
GND
GND
GND
GND
XTLI
C325 C324
25MHZ AR8151-AL1A-R 8/26 A-->B modify
37
24
16
22
9
42
43
44
45
46
47
48
49
50
33P/50V_4 33P/50V_4
AVDDH C598 1U/6.3V_4 C463

C337 1U/6.3V_4 C583 0.1U/10V_4 1000P/50V_4
C335 0.1U/10V_4 DVDDL AVDDH C569 0.1U/10V_4
C377 0.1U/10V_4 DVDDL AVDDH C599 0.1U/10V_4 CN11
LAN_YLED R446 330/F_4 12 LED_GRE_P
11 LED_GRE_N
10/11 +/- change
LAN_MX3+ 8
LAN_MX3- RX1-
7 RX1+
LAN_TX# R105 5.1K/F_4 LAN_MX2- 6
B
LAN_MX1- RX0- B
5 TX1-
LAN_MX1+ 4
LAN_MX2+ TX1+
3 RX0+
LAN_MX0+ 2 14
LAN_MX0- TX0- GND1
1 TX0+
C55
T R A N S F O R M E R
GND 13
1000P/50V_4
+3VLANVCC 10 LED_YEL_P
R60 LAN_GLED# 9
330/F_4 LED_YEL_N
PLACE NEAR LAN IC SIDE C545 1U/6.3V_4 AVDD_CEN_T L26 PBY160808T-601Y-N_1A AVDD_CEN
RJ45_CONN
C336 1000P/50V_4 R237 49.9/F_4 MDI0+
R244 49.9/F_4 MDI0- U21 8/31 exchange RJ45 LED color
C328 0.1U/10V_4 MDI0+ 2 23 LAN_MX0+
MDI0- TD1+ MX1+ LAN_MX0-
3 TD1- MX1- 22
C348 1000P/50V_4 R251 49.9/F_4 MDI1+ MDI1+ 5 20 LAN_MX1+
R256 49.9/F_4 MDI1- MDI1- TD2+ MX2+ LAN_MX1-
6 TD2- MX2- 19
C339 0.1U/10V_4 MDI2+ 8 17 LAN_MX2+
MDI2- TD3+ MX3+ LAN_MX2-
9 TD3- MX3- 16
C373 1000P/50V_4 R263 49.9/F_4 MDI2+ MDI3+ 11 14 LAN_MX3+
R285 49.9/F_4 MDI2- MDI3- TD4+ MX4+ LAN_MX3-
12 TD4- MX4- 13
C357 0.1U/10V_4
AVDD_CEN_T 1 24 TERM1 R492 75/F_8 TERM9
C381 1000P/50V_4 R271 49.9/F_4 MDI3+ C548 *1000P/50V_4 AVDD_CEN_T TCT1 MCT1 TERM2 R510 75/F_8
4 TCT2 MCT2 21
R272 49.9/F_4 MDI3- C547 0.1U/10V_4 AVDD_CEN_T 7 18 TERM3 R519 75/F_8 Re
C380 0.1U/10V_4 C546 *1000P/50V_4 AVDD_CEN_T TCT3 MCT3 TERM4 R526 75/F_8 C362
A 10 TCT4 MCT4 15 Rd A
1c
C560 0.1U/10V_4
8/31 change R from 0805 to 0402 C549 *1000P/50V_4 LFE9276A-R 1500P/3KV_1808
0h
C558 0.1U/10V_4
/a
C533 *1000P/50V_4
C550 0.1U/10V_4
PROJECT : TWH
1n

0g
0e
D3A: only UMA sku support 1G,If support 10/100 in UMA SKU, R55,R56 change to 0-ohm Size Document Number Rev
: R0
Custom A
LAN Controller (Atheros_AR8151)
d
5 4 3 2 1
o
R
A B C D E
SP1
SP2
SP3
SP4
XD_RDY
XD_RE#
XD_CE#
XD_CLE
SD_WP
SD_D1
SD_D0
MS_CLK
MS_INS#
25
SP5 XD_ALE SD_D7 MS_D3
SP6 XD_WE# SD_CD#
SP7 XD_WP SD_D6
SP8 XD_D0 SD_CLK MS_D2
SP9 XD_D1 SD_D5 MS_D0
4 4
SP10 XD_D2 SD_CMD
U26 SP12 XD_D4 SD_D3 MS_D1

8 SP1 SP13 XD_D5 SD_D2
SP1 SP2 SP14 XD_D6 MS_BS
+3VCARD 5 CARD_3V3 SP2 9
+3V 4 10 SP3
3V3_IN SP3 SP4
8/26 A-->B modify 17 GPIO0 SP4 11
+3V 12 SP5
SP5 SP6
[8] USBP12- 2 13
[8]
[8]
CLK_48M_CR
USBP12+
R585 *0_4/S RTS5138_CLK_IN 24
3
DM
DP RT5138
SP6
SP7
SP8
14
15
16
SP7
SP8
SP9
Share Pin
C627 *5.6P/50V_4 CLK_IN SP9 SP10
SP10 18
SP11 19
C650 C657 RTS5138_RREF 1 20 SP12
0.1U/10V_4 4.7U/6.3V_6 R614 RREF SP12
1 26.19K/F_4 SP13 21 SP13
C649 *100P/50V_4 22 SP14 CN4
RTS5138_VREG6 SP14 MS_D1
V18 XD_D7 23 1 XD-R/B MS-DATA1 20
C637 1U/10V_4 25 7 2 21 MS_BS
GND XD_CD# XD-RE MS-BS
3 XD-CE 4IN1-GND2 22
4 XD-CLE SD-VCC 23 +3VCARD
RTS5138 5 24 SD_CLK_R 33_4 SD_CLK
+3VCARD +3VCARD XD-ALE SD-CLK SD_D0 R573
6 XD-WE SD-DAT0 25
7 XD-WP XD-D2 26
8 XD-D0 XD-D3 27
9 XD-D1 XD-D4 28
SD_D2 10 29 SD_D1
C611 C641 C608 SD_D3 SD-DAT2 SD-DAT1
3 11 SD-DAT3 XD-D5 30 3
C648 R633 0.1U/10V_4 0.1U/10V_4 *0.1U/10V_4 SD_CMD 12 31
2.2U/10V_6 150K/F_4 SD-CMD XD-D6
13 4IN1-GND1 XD-D7 32
+3VCARD 14 MS-VCC XD-VCC 33
MS_CLK MS_CLK_R 15 34
R572 MS_D3 MS-SCLK XD-CD-SW SD_WP
16 MS-DATA3 SD-WP-SW 35
33_4 MS_INS# 17 36 SD_CD#
MS_D2 MS-INS SD-CD-SW
18 MS-DATA2
MS_D0 19 MS-DATA0
SHIELD1-GND 37
MS_CLK_R SD_CLK_R 38
SHIELD2-GND
SHIELD3-GND 41
SHIELD4-GND 42
C612 C609
CONN_CARDREADER_CM3S-015
*10p/50V_4 *10p/50V_4
+3VCARD
R571 *10K/F_4 XD_WP
System Screw Hold 9/9 ME modify FP

C628 *270P/25V_4 XD_RDY HS1 HS2 HS3 HS4 HS5 HS6 HS7 HL1
*H-C315D110P2 *H-C315D110P2 *H-C236D110P2 *O-TWH-4 *h-tc472bc315d110p2 *H-C315D110P2 *h-tc472bc315d110p2 *H-C394D157P2
2 2
1
H5 H3 H4 H1 H6 H7 H2 H8
*H-TS394BC315D110P2 *H-TS394BC315D110P2 *H-TS394BC315D110P2 *h-tr315x295br394x295d110p2 *O-TWH-2 *H-C110D110N *H-C110D110N *O-TWH-3
CPU Bracket GPU Bracket

HC1 HC2 HC3 HC4 HG1 HG2 HG3
1
1
*H-TC276BC197D150P2 *H-TC276BC197D150P2 *H-TC276BC197D150P2 *H-TC276BC197D150P2 *H-TC276BC197D150P2 *H-TC276BC197D150P2 *H-TC276BC197D150P2
System Pad(Top) H9
*O-TWH-3
H10
*O-TWH-3
1
P1 P2 P3 P4 P5 P6 P7 P8 B2
1
1
MDC NU Screw Hold PCH NU Screw Hold
1
1 12/9 layout change to TOP side 1
NP1 NP2 NS1 NL1

H-C256D122P2 H-C256D122P2 *H-C256D67P2 H-C256D161P2 System Pad(Button)
9/6 delete MDC function P9 P10 P11 P13 P12 P14 B3 PROJECT : TWH
ND1,ND2 Quanta Computer Inc.
1
1
Custom A
A B C D E
5 4 3 2 1
26
D D
C
USB3.0 X 2/USB2.0 COMBO C
USB 2.0
R199 0_4 CN14
USB3.0 CONN
RP4 +5VSUS_USBP0 1
USB30P1-_C 1 VBUS
[8] USBP2- 4 3 2 2 D-
1 2 USB30P1+_C 3
[8] USBP2+ 3 D+
4 4
*WCM2012-90 GND
8/26 A-->B modify 5 5 SSRX-
R208 0_4 6 6 SSRX+
7 7
8 GND
8 SSTX-
9 9 SSTX+
13
12
11
10
USB30P1-_C C536 *Clamp-Diode
13
12
11
10
1 2
B B
USB30P1+_C C534 *Clamp-Diode

1 2
USB 2.0
R248 0_4 CN16
USB3.0 CONN
RP10 +5VSUS_USBP0 1 1 VBUS
4 3 USB30P2-_C 2
[8] USBP4- 2 D-
1 2 USB30P2+_C 3
[8] USBP4+ 3 D+
4 4
+5VS5 C614 *WCM2012-90 GND
8/26 A-->B modify 5 5 SSRX-
U25 *220U/6.3V_6X4.5ESR18 R252 0_4 6
USB_HPE# R3008 *0_4 +5VSUS_USBP0 6 SSRX+
2 VIN1 OUT3 8 7 7 GND
3 VIN2 OUT2 7 8 8
1
1
R3009 0_4 6 C606 C607 C610 9 SSTX-
[23,29] USB_ENABLE# 4 EN OUT1 9
+ + USB30P2-_C C574 *Clamp-Diode SSTX+
1 5
13
12
11
10
GND OC C596 1 2
C605 G547E2P81U 470P/50V_4
2
13
12
11
10
1U/6.3V_4 0.1U/10V_4 100U 16V(+-20%,6.3*5.8)
11/10 modify 470P/50V_4
A A
USB30P2+_C C573 *Clamp-Diode
1 2
11/10 cost down
PROJECT : TWH
[2,6,7,8,9,10,12,13,14,21,22,23,24,25,27,28,29,34,36,37,39] +3V Quanta Computer Inc.
[10,21,23,31,32,33,34,35,36,37,38,39,40] +5VS5
[36] +3VSUS Size Document Number Rev
Custom A
USB 3.0 Controller (TI_TUSB7320)
[33] +1.1V_VL801
5 4 3 2 1
A B C D E
9/4
27
+1.5V_CPU
1.change net name "+MINIEC_5V" to "INT_BT_OFF#"
2.add R1003, net name "INT_BT_OFF#" +3V +3V_WLAN_P
C425 10U/6.3VS_6
Mini Card C427
C429
0.1U/10V_4
0.01U/16V_4 R21 *0_8
C19
C17
10U/6.3VS_6
0.1U/10V_4
+1.5V_CPU +3V_WLAN_P
WLAN/BT(Option) C428
C426
0.1U/10V_4
0.1U/10V_4
CN8
6 +1.5V +3.3V 52 9/3 delete BT function (USB)
EC debug pin 28 +1.5V +3.3V 2 delete net "BLUELED", R18 1 3
4
48 +1.5V +3.3Vaux 24 4
R266 *0_6 INT_BT_OFF# 51 41 R22
+5V Reserved Reserved
R681 *0_4 49 39 R19 10K/F_4 +3V_WLAN_P 4.7K_4 ME2303T1
[29] EC_DEBUG1
2
Reserved Reserved WLAN_LED# R680 *0_4
47 Reserved LED_WLAN# 44 RF_LINK# [29] 12/13 short
INT_BT_OFF# R1003 *0_4 45 46 Q6
Reserved LED_WPAN#
[8] CLK_33M_DEBUG 19 Reserved LED_WWAN# 42 9/6 add "RF_PWR_OFF#" control from PCH
PLTRST# 17 38 USBP10+ [8] 11/11 mount
Reserved USB_D+
9/28 modify[8] PCIE_TXP1 33 PETp0 USB_D- 36 USBP10- [8]
3
[8] PCIE_TXN1 31 32 +3V_WLAN_P [9] RF_PWR_OFF# RF_PWR_OFF# R25
PETn0 SMB_DATA *100K/F_4
[8] PCIE_RXP1 25 PERp0 SMB_CLK 30
[8] PCIE_RXN1 23 22 WLANE_PLTRST# R386 10K/F_4 R17 *0_4/S 2 Q7
PERn0 PERST# D24 2 DTC144EUA
[8] CLK_PCIE_WLANP 13 REFCLK+ W_DISABLE# 20 1 RB501V-40 RF_OFF# [9] [29] RF_PWR_ON
[8] CLK_PCIE_WLANN 11 16 LAD0 LAD0 [7,29] R20 *0_4
R682 *0_4 REQ_WLAN# 7 REFCLK- Reserved LAD1
[8] PCIE_CLKREQ_WLAN# 14 LAD1 [7,29] Avoid leakage issue
1
R27 *0_4 BT_COMBO_EN#15 CLKREQ# Reserved LAD2
[8] BT_COMBO_EN# BT_CHCLK Reserved 12 LAD2 [7,29] 9/6 power changed from +3V to +3V_WLAN_P
3 10 LAD3 LAD3 [7,29] 9/6 R17-stuff, R20-unstuff
MINICAR_PME# BT_DATA Reserved LFRAME# +3V_WLAN_P
1 WAKE# Reserved 8 LFRAME# [7,29]
43 Reserved GND 50 PIN44
37 Reserved GND 40
2
35 GND GND 34
29 GND GND 26
27 18 WLAN_LED# 1 3 RF_LINK#
GND GND Q54 2N7002
21 4
15
GND
GND
GND
GND 9 Mini Card Reset +3V
MLX_67910-5700
+3V_WLAN_P
MIPCIEXP-1775838-1-52P PIN7
R24 PLTRST#
5
3 *0_4 3
2
2 +3V_WLAN_P R196 10K/F_4
WLANE_PLTRST# R23 100/F_4 WLAN_RST_OUT 4
1 PLTRST# PLTRST# [2,8,14,24,26,29] REQ_WLAN# 1 3 PCIE_CLKREQ_WLAN#
Q52 2N7002
U2
3
C18 MC74VHC1G08DFT2G
0.1U/10V_4
+3V_WLAN_P
Support Wake Function(Reserve) PIN5

R265
+3VPCU 10K/F_4
R31 *10K/F_4
LGE mini-pcie power status BT_COMBO_EN#1
WLAN Bluetooth +3V_WLAN_P
2
3
Q53
Radio-ON Radio-ON Power-ON
BT_COMBO_EN# 2
For EMI Suggestion Radio-ON Radio-OFF Power-ON
[6,24,26] PCIE_WAKE# 3 1 MINICAR_PME#
Q8 *DTC144EUA CLK_33M_DEBUG C21 *33P/50V_4 Radio-OFF Radio-ON Power-ON DTC144EUA
1
R26 *0_4
2 Radio-OFF Radio-OFF Power-OFF 2
+3V_WLAN_P
PIN19,51
LED Status (Orange)
LED1 R1001
[29] BATLOW# 4 2 R381 150_6 MDC Connector(Option) 10K/F_4
+3VPCU
[29] MBATLED0# 3 1 R382 39_6
INT_BT_OFF#
SMD 4P WH/YEL(19-123/S2ST1D-C30/2T)
3
Q1001
(White)
INT_BT_COMBO_EN# 2
(White) 9/3 delete MDC function
[8] INT_BT_COMBO_EN#
LED2
SATA_R_LED1 R380 150_6 R538, C570 DTC144EUA
[7] SATA_LED# +3V
1
CN15
C308, R192, R193, C307, C309, C306, C305
(White) "ACZ_SDOUT_MDC"
R379
*0_4 LED3 "ACZ_SYNC_MDC"
RF_LINK# RF_LED# RFON_R_LED1 "ACZ_SDIN1" R1002
+3V
R385 150_6 *0_4
"ACZ_RST#_MDC"
Q29
"BIT_CLK_MDC"
3
DTC144EUA 9/4 Intel COMBO card control circuit

1 1
1.add R1001,R1002,Q1001
+3V_WLAN_P 1 3 2
R378 10K/F_4 2.add net name"INT_BT_COMBO_EN#" -> "INT_BT_OFF#"
Q32
2
ME2303T1
PROJECT : TWH
[29] RF_LINK#
9/3 delete BT function (USB)
delete net "BLUELED", Q31 Size Document Number Rev
Custom A
A B C D E
A B C D E
Power Botton Connector

C93 0.1U/10V_4
CPU FAN
C449 2.2U/6.3V_6
+5V_FAN 1
CN10
Touch Pad Connector
B-stage change footprint to BL121-12R-TAND-12P-L 28
Pin1 : +3VPCU(LIDSWITCH PWR) C448 0.1U/10V_4 2
1 25 mils
8
2 C118 0.1U/10V_4
+3VPCU 1 Pin2 : POWER LED [29] FAN1SIG 3 3 4 4 +5V
[29] PWR_LED# Pin3 : LIDSWITCH +3V C105 0.1U/10V_4
2 R437 4.7K_4 FAN CONN CN3
[21,29] LID_EC# 3 Pin4 : GND +3V
Pin5 : GND R58 4.7K_4
4 4 C452 1000P/50V_4
P/N : DFH03MR026 R59 4.7K_4 4
5 Pin6 : POWERON# P/N : DFH03MR029 12
[29] NBSWON1# 6 Pin7 : NC 11
Pin8 : NC [29] TPCLK TPCLK L8 BLM18BA470SN1 TPCLK-1
10
7
[29] TPDATA TPDATA L7 BLM18BA470SN1 TPDATA-1
CN2 C451 1U/6.3V_4 9
C1008 C1009 C1010 PWR BTN CONN U13 8
+5V_FAN 7
220P/50V_4 220P/50V_4
P/N : DFFC06MR001 +5V 2 VIN VO 3
TP_L 6
220P/50V_4
P/N : DFFC06FR062 THERM_OVER# GND 5
C116 C117 TP_R 5
+5V 1 /FON GND 6 4
R423 10K/F_4 7
GND 10P/50V_4 10P/50V_4 3
[29] VFAN 4 VSET GND 8 2
9/8 EMI(near CN2) 1
G991PV11 8/31 exchange TP_L and TP_R
SW2 SW1 C1006 C1007 TOUCH PAD CONN
TP_R 3 1 TP_L 3 1 P/N : DFFC12FR293
4 2 4 2 220P/50V_4 220P/50V_4
6 5 6 5
TMG-533-S-V-TR 9/8 EMI(near CN3)

TMG-533-S-V-TR
+3V_HDD1 +3V
SATA HDD Connector
R231 *0_8
H5001 +5V
BT Connector
23
24
25
26
3 *h-c197d91p2 3
J3 C299 *10U/6.3V_8
SATA HDD C303 10U/6.3VS_6
+5V: 2 A(4 Pin) C310 4.7U/6.3V_6
C313 0.1U/10V_4
+3V: 2 A(4 Pin)
+3V_HDD1
22
1
1
Gnd : (5 Pin)
C320 *10U/6.3V_8 8/31 delete BT function (USB)
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C323 *0.1U/10V_4
delete CN20, net "BT_OFF#","BLUELED","USB8+","USB8-"
H5002
*h-c197d91p2
+3V_HDD1
SATA_TXP0_D C371 0.01U/16V_4 SATA_TXP0 [7]
+5V SATA_TXN0_D C368 0.01U/16V_4 SATA_TXN0 [7] Keyboard Connector
SATA_RXN0_D C354 0.01U/16V_4
SATA_RXN0 [7]
1
SATA_RXP0_D C347 0.01U/16V_4 +3VPCU

SATA_RXP0 [7]
CN1
26
RP1
12/10 add 8/31 exchange net name RXN and RXP 10 1 MY3 MY1 C65 220P/50V_4 MY2
MY4 MY2 MY2 C85 220P/50V_4 MY15 25
9 2 24
MY5 8 3 MY1 MY4 C73 220P/50V_4 MY14
MY6 MY0 MY0 C64 220P/50V_4 MY13 23
7 4 22
MY7 6 5 MY12
MX4 C68 220P/50V_4 MY11 21
2
10P8R-8.2K MX6 C70 220P/50V_4 MY10 20 2
RP2 MX3 C67 220P/50V_4 MY9 19
MY11 MX2 C66 220P/50V_4 MY8 18
10 1 17
+5V MY12 9 2 MY10 MY7
SATA ODD Connector +5V +5V_ODD MY13
MY14
8
7
3
4
MY9
MY8
MY5
MY6
C74
C75
220P/50V_4
220P/50V_4
MY6
MY5
16
15
+12VALW MY15 MY3 C72 220P/50V_4 MY4 14
6 5 13
R55 0_8 MY7 C76 220P/50V_4 MY3
C52 10P8R-8.2K MX7 12
0.1U/10V_4 MY8 C77 220P/50V_4 MX6 11
9/6 R55 stuff 10
2
8/26 A-->B modify MY9 C78 220P/50V_4 MY2

MY10 C79 220P/50V_4 MX5 9
R65 CN12 MY11 C80 220P/50V_4 MX4 8
7
3
*330K_6 Q14 +5V_ODD C190 0.01U/16V_4 SATA_TXP1_D 2 S1 MX3

[7] SATA_TXP1 TXP 6
*AO3404 C183 0.01U/16V_4 SATA_TXN1_D 3 MY[0..15] MX7 C71 220P/50V_4 MX2
[7] SATA_TXN1 [29] MY[0..15]
1
TXN MX0 C62 220P/50V_4 MY1 5

14 14 4
2 [7] SATA_RXN1 C156 0.01U/16V_4 SATA_RXN1_D 5 MX5 C69 220P/50V_4 MY0
C150 0.01U/16V_4 SATA_RXP1_D RXN MX[0..7] MX1 C63 220P/50V_4 MX1 3
[7] SATA_RXP1 6 RXP 16 16 [29] MX[0..7] 2
1
[9] ODD_PRSNT# 1 2 8 MX0

DP 1
3
R80 1K/F_4 9 MY12 C81 220P/50V_4
27
+5V_ODD +5V
R54 10 S7 MY13 C82 220P/50V_4 6906-25
1
*22_8 [29] EJECT# +5V P1

EJECT# 1 2 ODD_EJECT# 11 MD
MY14 C83 220P/50V_4
1
[29] ODD_PD *0_4 R49 2 R73 *0_4 1 17 MY15 C84 220P/50V_4

2
C50 GND1 17
4 GND2
*0.027U/25V_6 +5V_ODD 7 15
2
Q11 GND3 15
*2N7002 C433 10U/6.3VS_6
12 GND P/N : DFFC24FR030
13
1
GND
3
C434 0.1U/10V_4 P6
1
H5003 H5004 120 mils C435 0.1U/10V_4 SATA ODD
1
*h-c197d91p2 *h-c197d91p2 C440 0.1U/10V_4

2 C438 0.1U/10V_4
Q12
*2N7002 PROJECT : TWH
+3V Quanta Computer Inc.
1
1
1 2 EJECT# [2,4,10,27] +1.5V_CPU

R64 *10K/F_4 [2,6,7,8,9,10,12,13,14,21,22,23,24,25,26,27,29,34,36,37,39] +3V Size Document Number Rev
9/6 "EJECT#" pull high to 3V Custom A
12/10 add
[6,7,10,21,22,23,27,36] +5V
A B C D E
5 4 3 2 1
29
+VCC_RTC +3V_RTC +VCC_RTC Layout Note:
+3VPCU
Place all capacitors close to IT8502N.
1
+3V_ECACC L14 BK1608HS220-T +3VPCU R310 *0_4/S 12 MILS
R305
*0_4
12/13 short C322 C319 C392
D 1U/6.3V_4 1000P/50V_4 0.1U/10V_4 C397 C343 C396 C359 C342 C321 D
1 2
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
+3VPCU +3V +3VPCU
R306 IT8502_AGND IT8502_AGND
*0_4/S +3v_STBY L16 BK1608HS121-T +3VPCU
C393 0.1U/10V_4 Select Pin +3VPCU
2
R309 C378 Rb Ra
470K_4 0.1U/10V_4 R222 10K_4 CB/LG R207 *10K_4 H_PROCHOT#_Q R210 0_4
H_PROCHOT# [2,39]
114
121
127
11
26
50
92
74
3
EC_WRST U7 TWH Select
3
VCC
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
AVCC
VBAT
C395 [7,27] LAD0 10 84 BATLOW TWH Ra
0.1U/10V_4 LAD0 EGCLK/WUI27/GPE3
[7,27] LAD1 9 LAD1 EGCS#/WUI26/GPE2 83 VRON [39]
[7,27] LAD2 8 NC Rb H_PROCHOT#_EC 2
LAD2
[7,27] LAD3 7 LAD3 EGAD/WUI25/GPE1 82 SLP_A# [6]
[2,8,14,24,26,27] PLTRST# 22 Q24
LPCRST#/WUI4/GPD2 2N7002
[8] CLK_33M_KBC 13 LPCCLK KSO16/SMOSI/GPC3 56 EC_PWROK [6]
[7,27] LFRAME# 6 57 SUSACK# [6] R221
1
LFRAME# KSO17/SMISO/GPC5 100K_4
[6] SLP_S5 17 LPCPD#/WUI6/GPE6 LPC L80HLAT/BAO/WUI24/GPE0 19 SUSON [32,33,36]
L80LLAT/WUI7/GPE7 20 LAN_REST# [24]
[9] EC_A20GATE D11 RB501V-40 126 GA20/GPB5 MBATLED0
[7] SERIRQ 5 SERIRQ GPIO SBUSY/GPG1/ID7 107
+3VPCU
[9] SIO_EXT_SMI# D13 RB501V-40 15 99 H_SI R236 0_4 PCH_SPI_SI [7] PWR_LED# [28]
D14 RB501V-40 ECSMI#/GPD4 HMOSIGPH6/ID6 H_SO R232 0_4
[9] SIO_EXT_SCI# 23 ECSCI#/GPD3 HMISO/GPH5/ID5 98 PCH_SPI_SO [7] BATLOW# [27]
3
EC_WRST 14 97 H_CLK R229 0_4 PCH_SPI_CLK [7]
WRST# HSCK/GPH4/ID4
3
[9] EC_RCIN# D12 RB501V-40 4 96 H_SCE# R218 0_4 PCH_SPI_CS0# [7]
KBRST#/GPB6 HSCE#/WUI19/GPH3/ID3 R277
16 PWUREQ#/BBO/GPC7 CTX1/WUI18/GPH2/SMDAT3/ID2 95 MAINON [30,32,33,34,35,36,37,38]
C TP42 94 10K_4 PWR_LED 2 C
CRX1/WUI17/GPH1/SMCLK3/ID1 RF_LINK# [27]
93 CLKRUN# [6] BATLOW 2
CLKRUN#/WUI16/GPH0/ID0 Q26
[30] D/C# 119 NBSWON1# 2N7002E Q21
[6] RSMRST# 123
GPC0
IT8518/BX 2N7002E
1
TMA0/GPB2
1
H_PROCHOT#_EC 86 C372
HDMI_HPD PS2DAT0/TMB1/GPF1 EC_PECI_R R260 43_4 0.1U/10V_4
[22] HDMI_HPD 85 117 EC_PECI [2]
PS2CLK0/TMB0/GPF0 SMCLK2/WUI22/GPF6/PECI
118 SLP_SUS# [6] MBATLED0# [27]
TPDATA SMDAT2/WUI23/GPF7 MBCLK
[28] TPDATA 90
PS2DAT2/WUI21/GPF5 PS/2 SMCLK0/GPB3
110 MBCLK [30]
3
TPCLK MBDATA
[28] TPCLK 89
PS2CLK2/WUI20/GPF4 SMDAT0/GPB4
111 MBDATA [30] For Battery charge/charge and cap board
SM_BUS 115 MBCLK2
SMCLK1/GPC1 MBCLK2 [8,13,17]
12/9 add 116 MBDATA2 For PCH SMB/DDR Thermal IC/VGA
SMDAT1/GPC2 MBDATA2 [8,13,17]
CB/LG CB/LG 80 MBATLED0 2
DAC4/DCD0#/GPJ4
[28] ODD_PD 104
DSR0#/GPG6 Q25
[26] SMI_EN 33
GINT/CTS0#/GPD5 2N7002
[31,32,33,34,35,37,38] HWPG 88
PS2DAT1/RTS0#/GPF3
[21] LID_CONTROL 81 UART 24 LAN_POWER [36]
1
DAC5/RIG0#/GPJ5 PWM0/GPA0 Num LK
[27] RF_PWR_ON 87 25 TP45
PS2CLK1/DTR0#/GPF2 PWM1/GPA1
[7] GPIO33_E 1 2 108 28 AC_PRESENT [6]
RXD/SIN0/GPB0 PWM2/GPA2 SATA5GP
109 29 SATA5GP [9]
D2001 RB501V-40 TXD/SOUT0/GPB1 PWM3/GPA3
10/11 add PWM4/GPA4
30 PWM_VADJ [21]
[27] EC_DEBUG1 PWM5/GPA5
31 SUS_PWR_ACK [6] thermal shutdown circuit
[23,26] USB_ENABLE# 106 32 VOLMUTE# [23]
EC_SCK GPG0 PWM6/SSCK/GPA6 EC_WRST
105 34 PC_BEEP_EC [23]
FSCK PWM7/GPA7 +3VPCU R191
EC_SO 103 FLASH PWM 47 FAN1SIG [28] 10K/F_4 +3V
FMISO TACH0/GPD6
3
EC_SI 102 48 S5_ON [31] MBCLK R247 10K_4 Q23
EC_CE# FMOSI TACH1/TMA1/GPD7 MBDATA
101
FSCE#
R250 10K_4 2 OVT_DETC 2 1 EC_PWROK
[28] EJECT# 100 120 SUSC# [6] LAN_S5_WAKE# R278 *10K_4 D7 RB501V-40
B SSCE0#/GPG2 TMR0/WUI2/GPC4 *MMBT3904-7-F B
[28] MY[0..15] 124 LAN_S5_WAKE# [24] 10/9 remove
1
MY0 TMR1/WUI3/GPC6 SYS_SHDN-1#
36
KSO0/PD0 2 1 VGA_OVT# DGPU_OVT# [17]
MY1 37 D5 *RB501V-40
MY2 KSO1/PD1 +3V
38
KSO2/PD2 9/28 remove R219,R220
MY3 39
MY4 KSO3/PD3 TPCLK R220 *10K_4
40
MY5 KSO4/PD4 TPDATA R219 *10K_4 R184
41
MY6 KSO5/PD5 NBSWON1# MBCLK2 R254 10K_4 EC_CT_UP *4.7K/F_4
42 125 NBSWON1# [28] +1.05V_VTT
MY7 KSO6/PD6 PWRSW/GPE4 MBDATA2 R261 10K_4
43 18 LID_EC# [21,28]
MY8 KSO7/PD7 RI1#/WUI0/GPD0 C304 220P/50V_4
44
KSO8/ACK# WAKE UP RI2#/WUI1/GPD1
21 ACIN [30]
2
MY9 45 KBMX
MY10 KSO9/BUSY
46
KSO10/PE WUI5/GPE5
35 SUSB# [6] PV Change
MY11 51 112 PWR_LED 3 1
KSO11/ERR# RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 PM_THRMTRIP# [2,9]
MY12 52 TP77
MY13 KSO12/SLCT Q22 *MMBT3904-7-F
53
MY14 KSO13 C2004 1U/10V_4
54
KSO14
10/11 add
[28] MX[0..7] MY15 55 66
MX0 KSO15 ADC0/GPI0
58 67 GFX_HWPG [39]
MX1 KSI0/STB# ADC1/GPI1
MX2
59
60
KSI1/AFD#
A/D D/A ADC2/GPI2
68
69
SYS_I
AD_AIR
[30]
[30] For SG/DIS 8/26 A-->B modify SPI FLASH MX25L3205DM2I-12G: AKE39FP0Z00
MX3 KSI2/INIT# ADC3/GPI3
61
KSI3/SLIN# ADC4/WUI28/GPI4
70 TEMP_MBAT [30] W25X32VSSIG: AKE39ZP0N00
MX4 62 71 EC_GPXD1 R224 *0_4 DGPU_PWROK [9,14,37]
MX5 KSI4 ADC5/WUI29/GPI5
63
KSI5 ADC6/WUI30/GPI6
72 TP78 Socket: DG008000031
MX6 64 73 TP79
MX7 KSI6 ADC7/WUI31/GPI7 R223 *100K_4 +3VPCU
65
KSI7 For UMA only Mount for Optimus U20
76 DGPU_PR_EN_E R212 *0_4 DGPU_PWR_EN [9,37,38] EC_CE# 1 8
R299 *0_4 EC_CK32K 128 DAC0/GPJ0 CE# VDD
CLOCK 77 R679 *0_4 EC_SCK R533 47_4 EC_SCK_R
VCORE
[6] PCH_SUSCLK DGPU_HOLD_RST# [9,14] 6

CK32K DAC1/GPJ1 SCK
AVSS
EC_CK32KE 2 78 VFAN [28] For SG/DIS 8/26 A-->B modify EC_SI R532 47_4 EC_SI_R 5
VSS
VSS
VSS
VSS
VSS
VSS
CK32KE DAC2/GPJ2 EC_SO R494 EC_SO_R SI

Y3 79 D8 RB501V-40
DNBSWON# [6]
15_4 2 7R534 10K_4
A DAC3/GPJ3 SO HOLD# C561 A
7/27:Add R399 for EC request
12/13 short 1 4 R195 10K/F_4 +3VS5 +3VPCU R493 10K_4 3 4 0.1U/10V_4
1
27
49
91
113
122
75
12
R300 IT8518E WP# VSS

*0_4/S 2 3 8/26 A-->B modify SPI Flash Socket
*32.768KHZ
C391
*10P/50V_4
C398
*10P/50V_4 IT8502_AGND
C394
0.1U/10V_4 PROJECT : TWH
L13 BK1608HS121-T
D6 RB501V-40 Quanta Computer Inc.
DGPU_HOLD_RST# 1 2 OVT_DETC
Mount for Optimus Custom A
Embedded Controller (ITE_IT8502)
IT8502_AGND NB5 Date: Tuesday, December 14, 2010 Sheet 29 of 40
5 4 3 2 1
5 4 3 2 1
30
+BATCHG PL4
TOP DC_JACK Place this ZVS close to Do Not add test point on BATDIS_G signal
UPB201212T-800Y-N
idea diode CN5
65W/90W PQ34 BP07061-BA015
D PQ35 +VAD PQ33 P1003EVG 1 1 D
CN6 PL6 +VA FDMC4435BZ P0603BDG +PRWSRC 1 8 BATT+ 2 2
DC/B TO M/B UPB201212T-800Y-N 1 2 7 PL3
J1-1 5 2 4 3 3 6 UPB201212T-800Y-N SMD 3
2 1 PC146 PC145 SMC 3
3 4 5 4
4 3 4
1
0.1U/25V_4 0.1U/25V_4 5
6 5 PL8 PC142 BATDIS_G B_TEMP_MBAT 5
6
1
UPB201212T-800Y-N PD13 0.1U/25V_4 PC10 6
7 10
4
P4SMAJ20A 1U/25V_8 PR165 +VIN PR2 7 10
9/10 update 8
8 9
9
PC160 PC159 RC2512-R010 330_4 PR1
2
0.1U/25V_4 0.1U/25V_4 PR17 1 2 330_4 PR3
ACOK_IN BATDIS_G [29] MBDATA 10K/F_4
1
+3VPCU
Check DC_IN pin assignment *100/F_4
[29] MBCLK
+VH28 PD18 PR4
P4SMAJ20A Parallel 1K/F_4
1
PR19 TEMP_MBAT [29]
2
20K/F_4 +VAD 8681_VDDP PR167 PR166
PQ32
PR156 PR155 PR157 PR18 *0_2/S *0_2/S PC7 PC6
Q1
+VA 2 1 1 2 2 1 2 1 100/F_4 68P/50V_4 68P/50V_4 PC2 PC122
2
1K_6 220K_4 220K_4 Place this ZVS close to DB2 Update 0.01U/25V_4 0.01U/25V_4
CSIN
2
CSIP
6 5 PR12 PR14 PR21
Far-Far away +VIN
3
100K/F_4 *100K/F_4 *0_4/S 8681_VDDA
1
3 4 +VAD 2 1 ACOK_IN PC11 PD2 PD1
2
Q2
2 1 UDZ5V6B-7-F UDZ5V6B-7-F
2
PR158 +VAD ACOK# PD8
2 Place this cap
ACIN_1
MMDT2907A
2
1M_4 IDEA_G 1SS355 PR27 PR26 1U/10V_4
close to EC
2
2 1 10/F_4 10/F_4
2
20101013 change PN, and PQ3 PR23
1
2
3
DMN601K-7 PR15 100/F_4 8681_VDDP 20101013 for EMI ISN
footorint will change smaller
1
PR20
3
8681_VDDA
100K/F_4 2 ACIN_PG +VIN_CHG PL5 +VIN
1
PR153 next lot 1M_4 UPB201212T-800Y-N
IACM
1
IACP
1
1M_4 +VIN_CHG
2
C C
PQ1 PC9 PC18
1
2
IMD2 PQ4 1U/10V_4 2 1 PC13
2
MMBT3904-7-F 1U/10V_4 PC156 PC155 PC152 PC151 PC147
15
1
2
6
2.2U/10V_6 PD12 4.7U/25V_8 4.7U/25V_8 1000P/50V_4 0.1U/25V_4 0.1U/25V_4 PC269
4
1
5
PR6 RB501V-40 1500P/50V_4
IACM
IACP
VDDA
VDDP
*0_4/S PR154
1
MBCLK 2 1 SCL 10 2_6 PC4
SCL
ACAVD
BST 12 8681B_2 8681B_1

PR5 4 DB2 Update
PD5 *0_4/S 0.1U/50V_6 PQ37
[29,32,33,34,35,36,37,38] MAINON 2 1 MBDATA 2 1 SDL 11 13 8681HDR AON7410 PR160
SDL HDR PL9 RL1206-R020
DB2 Update
3
2
1
BAS316/DG 10UH/4A
PR8 14 8681LX 8681LR 1 2
PD6 8681_ACAV 9 LX
[36] ACIN_PG 2 1 ACAV
1
8681_ACAV 2 1 100K/F_4
PR7 16 8681LDR PC149 PC148 PC270
PU1 LDR
10U/25V_8
10U/25V_8
1500P/50V_4
BAS316/DG PV_Update 2010/11/15 100K/F_4 PR169 PC158
+VA +VAD_1 2.2_8 PD15 0.1U/25V_4
2 1
OZ8681 4 RB501V-40
2
PD4 PD7 PR9
2 1 +VAD_1 2 1 +VAD_2 DCIN 1 PQ38 PR159
VAC AON7702 PC161 *0_2/S
3
2
1
BAS316/DG BAS316/DG 10_8 2200P/50V_4 PR163
PC3 PR22 *0_2/S
PR16 1U/25V_8 10/F_4
75K/F_4 5 8681ICHP 1 2 8681ICSP1
ICHP
2
COMP 8 PC17
COMP 1U/10V_4 8681ICHM 8681ICHM1
4 1 2
1 1
[29] AD_AIR ICHM
GND
1
IAC
PR25
B PC123 PC19 10/F_4 B
0.1U/10V_4 PR10 0.01U/50V_4
17
2
PR24 0_4 Place this cap
12.4K/F_4
close to IC
2
PR11
2
Place this cap 10/F_4

PV_Update 2010/11/12 PC1 8681IAC 2 1
close to EC SYS_I [29]
0.47U/10V_4
1
1
PC8 PC5
0.01U/50V_4 0.01U/50V_4
2
ACOK_IN
PR13
0_4
2 1
PV_Update 2010/11/15
3
PD3
+3VPCU 2 D/C#_S6A 1 2
EMI Suggestion PQ2
D/C# [29]
ACOK#
PR278 PDTC144EU
*0_4 +VAD BAS316/DG
1
ACIN_PG PR279 +PRWSRC PC15
100K_4 *10U/6.3V_8
1
+VIN
[29] ACIN PR280
*0_4 PR281 PC143 PC150
3
1M_4 22U/25V_1206 22U/25V_1206

2
C3005 C3006 C3007 C3008

A A
0.1U/25V_4 0.1U/25V_4 0.1U/25V_4 0.1U/25V_4 2
3
PR282 PV_Update 2010/11/18 change PN

PQ75 1M_4
DMN601K-7
1
2 ACIN_PG
11/10 add for EMI PQ76

DMN601K-7 PROJECT : TWH
1
[36] +BATCHG
[36] +VAD_1
[36] +VH28 Size Document Number Rev
Custom A
<Doc>
[36] +VA
5 4 3 2 1
5 4 3 2 1
DC/DC +3V_ALW/+5V_ALW/+5V_ALW2 /+15V_ALW

31
D D
Place these CAPs

close to FETs
Place these CAPs +VIN_3VS5 PL11 +VIN

UPB201212T-800Y-N
close to FETs
+VIN PL2 +VIN_5VS5 +5VPCU
UPB201212T-800Y-N PC179 PC178 PC42 PC43 PC174
+VIN PC186 0.1U/25V_4 2200P/50V_4 4.7U/25V_8 4.7U/25V_8 0.1U/25V_4
PC141 4.7U/6.3V_6
0.1U/25V_4 PC144 PC14 PR195
4.7U/25V_8 4.7U/25V_8 10_8
+3VPCU +2VREF
+VIN +5VPCU 1210 cancel 0 ohm

PC64
PC185 PC50
4.7U/6.3V_6
+5V +/- 5% 0.1U/25V_4 1U/6.3V_4
5
6
7
8
PR81
Countinue current:4A PR101 PR82 *0/short_4
+3.3 Volt +/- 5%
8
7
6
5
PC153 PC154 *665K/F_4 *0_4
16
17
Peak current:6A Countinue current:4A
3
C 2200P/50V_4 0.1U/25V_4 PR97 PU4 4 C
*330K/F_4
OCP minimum:7.5A Peak current:6A
VREG3
VREG5
REF
VIN
4 8205EN 13 4 PQ44
EN TONSEL AO4496
5V_UGATE1 21 10 3V_UGATE2 OCP minimum:7.5A
PQ36 PC36 UGATE1 UGATE2 PC65
PR59 PR103
AO4496 5V_BST1 22 9
3
2
1
+5VS5 PL7 BOOT1 BOOT2 PL13 +3VS5
2_6 2_6
2.2UH/8A 0.1U/25V_4 0.1U/25V_4 2.2UH/8A
RT8223M
1
2
3 5V_PHASE1 20 PHASE1 PHASE2 11 3V_PHASE2 +3.3V_ALWP
PR175 1119 change PN for EOD
8
7
6
5
5V_LGATE1 19 12 3V_LGATE2
LGATE1 LGATE2 PR208
1
5
6
7
8
*0_2/S
+ 24 PR201 *0_2/S
ENTRIP1
ENTRIP2
VOUT1
SKIPSEL
PC163 PR168 4 5V_FB1 2 7 2.2_8
FB1 OUT2
1
330U/6.3V_6X5.8 PC157 2.2_8 4
GND
GND
ENC
2
0.1U/10V_4 PGOOD 23 5 3V_FB2 +

PQ40 PGOOD FB2 PC184 PC205
PC166 AO4712 PC207 330U/6.3V_6X5.8
0.1U/10V_4
1
18
25
15
14
2
1500P/50V_4 PR67 PQ50 1500P/50V_4
137K/F_4 AO4712
1
2
3
1119 change PN for EOD
3
2
1
PR73 1210 cancel 0 ohm
15.4K/F_4
Rds(on) 18m ohm
PR92
PR93 6.8K/F_4
*0/short_4
Rds(on) 18m ohm
PR63 +3VPCU
0_4
B PR76 PR84 B
[29,32,33,34,35,37,38] HWPG
10K/F_4 *0_4
PR86
+3VS5 10K/F_4
3
PR62 S5_ON
10K_4
PR179
+3VPCU 2 PR74
*100K_4 0_4
PC47
3
PQ41 0.1U/10V_4
*2N7002K
3
[29] S5_ON 2
PQ8 2
1
*PDTC144EU PR94
137K/F_4
PQ42
*2N7002K
1
A A
PROJECT : TWH
Custom <Doc> A
+5VPCU
5 4 3 2 1
1 2 3 4 5
( VTT/2A )
+0.75V_DDR_VTT +VIN_DDR PL22
UPB201212T-800Y-N
+VIN
32
2
A A
PC131 PC133 PC264 PC262 PC132 PC260 PC261
10U/6.3V_8 10U/6.3V_8 0.1U/25V_4 4.7U/25V_8 4.7U/25V_8 2200P/50V_4 0.1U/25V_4
1
25
PU11
1 24 +1.5VSUS PC263
GND
VTTGND VTT *0.1U/50V_6
+1.5VSUS +/- 5%
5
PR140
2 VTTSNS VLDOIN 23
D
Countinue current:6A
*0_4 PR135 PC129
8207BST 8207BSTR
G
PQ74
Peak current:12A
+1.5VSUS 3 GND VBST 22 1 2 4
S RJK03B9D
PR139 2_6 0.1U/25V_4
OCP minimum 15A
1210 cancel 0 ohm
1
2
3
4 21 8207DRVH
*0/short_4 MODE DRVH PL21 +1.5VSUS
( 3mA ) 1UH/15A
[4,12,13] DDR_VTTREF 5 20 8207LX
VTTREF LL
1
1
PC135 V5FILT 6 19 8207DRVL PC245
COMP DRVL
1
0.033U/10V_4 PR134 0.1U/10V_4
2
2
B + B
D 2.2_8
7 18 G PC247
1
NC PGND 390U/2.5V_6X5.8ESR10
4
2
S PR260
8 17 RILIM = ILIM x RDS(ON) / 10uA PQ73 PC130 *0_2/S
1
2
3
VDDQSNS CS_GND RJK03D3D 2200P/50V_4
PR136
9 16 8207CS
VDDQSET CS +5VS5
1210 cancel 0 ohm 7.5K/F_4 PC265 RDSon=4.7m ohm
10 S3 V5IN 15 2 1
PR274 1U/6.3V_4
8207S5 11 14 V5FILT Place this short pad
[29,33,36] SUSON *0/short_4 S5 V5FILT
close to output CAP
1
PR137
+VIN 8207TON 12 13 DDRPG PC134 10_6
NC PGOOD 1U/6.3V_4
2
PR275 RT8207LGQW *0/short_4
619K/F_4 PR141
HWPG [29,31,33,34,35,37,38]
C 1210 cancel 0 ohm C
1
PR142
10K/F_4
2
1
PR143
10K/F_4
2
PD11 Place this FB parts close to IC

D D
2 1 MAINON [29,30,33,34,35,36,37,38]
RB501V-40 PROJECT : TWH

1
PC136
0.1U/10V_4
1 2 Quanta Computer Inc.
2
PR144 [12,13,36] +0.75V_DDR_VTT

100K/F_4 [2,4,10,12,13,33,38] +1.5VSUS Size Document Number Rev
Custom A
<Doc>
[10,21,23,26,31,33,34,35,36,37,38,39,40]
[21,30,31,33,34,35,36,37,38,40]
+5VS5
+VIN NB5 Date: Tuesday, December 14, 2010 Sheet 32 of 40
1 2 3 4 5
5 4 3 2 1
33
D D
VCCSA (0.9V) +/- 5%

PQ13 Countinue current 3A~6A
RJK03B9D
+1.05V_VTT +VCCSA
3
S
5 2
1
1
G
PC77 PC78 PC85 PC79 PC80
10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 +
4
PC217
390U/2.5V_6X5.8ESR10
2
1119 change PN PR211
1210 cancel 0 ohm +5VS5
22K/F_4
PR213 *0/short_4 PU12 PR210
[29,31,32,34,35,37,38] HWPG 4 PGD DRV 5 1/F_4
1 PR212
[34] 1.05V_VTT_PWRGD EN
G9334 3 0_4 PC208
PR202 ADJ 0.022U/25V_4
100/F_4 +5VS5 6 2 PV_Update 2010/11/15
VCC GND
PC204
*0.22U/10V_4 PC210 PR205
1U/6.3V_4
C VCCUSA_SENSE [4] C
8.06K/F_4 PR209 *0/short_4
PC268
PR206 PR207 1210 cancel 0 ohm
+3VS5 40.2K/F_4 13K/F_4
*100P/50V_4
VCCSA_SEL VCCSA DB2 Update
PR199 PV_Update 2010/11/15
3
0 0.9V 10K/F_4
1 0.8V 2 PV_Update 2010/11/15

PR188 PQ47
3
1K/F_4 DMN601K-7
[4] VCCSA_SEL 2
1
PQ45
1
PC183 MMBT3904-7-F
PR187 0.01U/16V_4
*10K/F_4
USB3.0 POWER
B +1.1V +/- 5% B
+1.5VSUS
+VCCSA PU10 Countinue current:650mA
3 VIN NC 5 Peak current:2A
+VIN PC119 PC118 +1.1V_VL801
PR126 10U/6.3V_8 0.1U/10V_4 G9661
*22_8 6
VOUT
PR130
[29,32,36] SUSON 2 EN
PR64 *10K/F_4
3
*1M_4 +5VS5 4 8 PC115 PC117 PC120

VDD GND 10U/6.3V_8 10U/6.3V_8 0.1U/10V_4
ADJ
PC124 1 9
R1112 0.33U/6.3V_4 PGOOD GND1
2 [29,30,32,34,35,36,37,38] MAINON
10K/F_4 PC116
7
3
PQ7 1U/6.3V_4
*2N7002K 11/12 add
PR58 1.05V_ADJ PR131
9/13 add for VL801 power control
1
1.05V_VTT_PWRGD 2 *1M_4 38.3K/F_4

PQ10 HWPG
*2N7002K PR133 *0/short_4 Vo=(0.8(R1+R2)/R2)
PR132
R2<120Kohm
1
100K/F_4
1210 cancel 0 ohm
A A
PROJECT : TWH
Custom <Doc> A
5 4 3 2 1
5 4 3 2 1
34
D D
10/8 update
+5VS5
+VIN_1.05V_VTT PL10 +VIN
PR28
UPB201212T-800Y-N
10_6
PC20
1U/6.3V_4 PC164
PC170 PC169 PC182 PC181 0.1U/25V_4
PC162 2200P/50V_4 0.1U/25V_4 4.7U/25V_8 4.7U/25V_8
+3V 1U/6.3V_4
RTBST_1 PR51 RTBST +1.05V Volt +/- 5%
RTVDD
2_6 Countinue current:10A
5
PR162 PC26 D
13
Peak current: 12A
9
PD14 100K_4 PR36 PU2 0.1U/25V_4 G
7.5K/F_4 RTDH
2 1 12 4 OCP minimum: 15A
VDD
BST
VDDP
[29,31,32,33,35,37,38] HWPG DH S
C RTILIM 10 C
BAS316/DG *0/short_4 CS PQ43
1
2
3
HWPG_S2A 4 11 RTLX RJK03B9D PL12 +1.05V_VTT
[33] 1.05V_VTT_PWRGD PGOOD PHASE 1UH/15A
PR164 1210 cancel 0 ohm 5 RT8209A 16 RTTON PR38 600 mils
NC TON
PR53 232K/F_4 PR204
RTEN 15 8
EN/DEM DL
PGND
[29,30,32,33,35,36,37,38] MAINON
VOUT
PR85 PC199 PC196
GND
10/F_4 *0_2/S
5
2.2_8 *0.1U/10V_4 0.1U/10V_4
NC
17 PAD FB 3
1
D
RTFB
PC31 G + +
14
VCCP_SENSE_R
*0.33U/6.3V_4 RTDL 4 PC213 PC206
S 390U/2.5V_6X5.8ESR10 *390U/2.5V_6X5.8ESR10
2
PQ46 PC55
1
2
3
PR31 RJK03D3D 1500P/50V_4
PR37
4.02K/F_4 10K/F_4
PC24 PR29
RDSon= 4.7m ohm
*10K/F_4
RTFB1
*100P/50V_4 RILIM = ILIMIT x RSENSE / 20uA
PR57
*0_4
3
PR161
Vo=0.75(R1+R2)/R2 2 H_VTTVID1 [5]
*1K/F_4
PQ39
1
*MMBT3904-7-F
B B
H_VTTVID1=Low, 1V
H_VTTVID1=High, 1.05V
VCCP_SENSE_1 PR52
VCCP_SENSE [4]
0_4
A A
PROJECT : TWH
Custom A
<Doc>
5 4 3 2 1
5 4 3 2 1
35
D D
PR265 +VIN_1.05V PL1 +VIN

10_6 UPB201212T-800Y-N
PR266
+5VS5
360K/F_4
RT8238VCC
RT8238TON
PC257 PC128
1U/6.3V_4 PC127 PC126 PC255 PC125 0.1U/25V_4
2200P/50V_4 0.1U/25V_4 4.7U/25V_8 *4.7U/25V_8 +1.05V +/- 5%
+3VS5
5
C PV_Update 2010/11/15 C
DB2 Update Peak current: 8A
11
5
PR268 PU15
PR273 130K/F_4 3 RT8238DH 4 PQ23 OCP minimum: 10A
VCC
TON
10K_4 RT8238ILIM 10 UGATE PC256 AON7410
CS 8238BST PR264 8238BST-1
1210 cancel 0 ohm BOOST 4
+1.05V
*0/short_4 PR272 RT8228A 2_6 PL20 1210 cancel 0 ohm
3
2
1
[29,31,32,33,34,37,38] HWPG RT8238PG 9 0.1U/25V_4 2.2UH/8A
PGOOD RT8238LX
PHASE 2
[29,30,32,33,34,36,37,38] MAINON RT8238EN 8 EN RT8238DL *0/short_4
LGATE 1
5
MODE
PR271 PR129 PC249
GND
0_4 PC259 13 2.2_8 0.1U/10V_4
FB
PAD
1
*0.1U/10V_4 PR261
+
12
6
4 PQ22 PC248
AON7702 390U/2.5V_6X5.8ESR10
2
PC121
RT8238FB 1500P/50V_4
3
2
1
PC258
*100P/50V_4
*0/short_4 1119 change PN for EOD

+5VS5
PR270 PR269 Rdson=18m ohm
11K/F_4
B 1210 cancel 0 ohm B

PR267
10K/F_4
Vo=0.5(R1+R2)/R2
A A
PROJECT : TWH
Custom A
<Doc>
5 4 3 2 1
5 4 3 2 1
+VA 2
PD9
1 G5934VIN_1 +VAD
+VH28
36
1
*RB501V-40 PR113
PR116 PR117 0_4
PD10
*22_6 22_6
2
+BATCHG 2 1
1
D D
*RB501V-40 PC89 PC86
0.1U/25V_4 1U/35V_6
2
PC88 2 1 PV_Update 2010/11/15
17 G5934VOUT
0.1U/25V_4
20 G5934VIN
19 G5934CN
18 G5934CP
2 1 ACIN_PG [30]
16 DCAP
PC87
1
0.47u/25V_6
PR112
*0_4/S +VAD_1
CP
D_CAP
VOUT
VIN
CN
2
1 15 G5934PG
[29] LAN_POWER ON1 PG
PR114
750K/F_4
1
2 14 G5934VSENSE
[29,30,32,33,34,35,37,38] MAINON ON2 VSENSE
2
+12VALW
PU9 PR115
3 13 100K/F_4
[29,32,33] SUSON ON3 P2806 REG
1
PC90
1U/16V_4
MAINON 4
ON4 PR30 *0_4/S
7 G5934DISC3 2 1 +3VSUS
PR118 DISC3
C C
*0_4/S
+3VS5 2 1 G5934DISC1 5 6 G5934DISC2 2 1
+3VLANVCC DISC1 DISC2 +5V
DRIVER4
DRIVER3
DRIVER1
DRIVER2
PR120
DISC4
*0_4/S +5VS5
GND
8
7
6
5
PC51 PQ12
12
11
10
21
0.1U/10V_4 AO4496
5
6
7
8
4 MAIND3.3V PC12
G5934DISC4
0.1U/10V_4
+1.8V +0.75V_DDR_VTT
PC52 MAIND 4
4.6A 2200P/50V_4
+3V PC16 6A +VIN
1
2
3
2200P/50V_4 PQ5 PR123 PR138

AO4496 +5V *22_8 22_8
3
2
1
1
11/10 add
3
PC68 PC69 PR121 PR119 PQ15
1
0.1U/10V_4 *10U/6.3V_8 *0_4/S 1M_4 *DMN601K-7
2
SUSD PC22 PC21

*10U/6.3V_8 0.1U/10V_4 2 2
2
3
PQ24
DMN601K-7
+3V PR122
1
2 1M_4
+3VS5 PQ14
DMN601K-7 MAIND_G
B B
MAIND [4]
1
PC63 MAIN_ONG [2,4]
1
2
5
6
0.1U/10V_4
PQ6 0.1A 9/28 add

PC29 ME3424D
4
2200P/50V_4 +3VSUS
1
+3VS5
PC23 PC25
*10U/6.3V_8 0.1U/10V_4
2
PQ11
ME3424D PC53
1
2
5
6
0.1U/10V_4
LAN_ON 3 [12,13,32] +0.75V_DDR_VTT

[24] +3VLANVCC
PC45 0.67A [2,4,10,12,13,32,33,38]
[30]
+1.5VSUS
+BATCHG
4
2200P/50V_4 [21,28,38] +12VALW

+3VLANVCC
[10,21,23,26,31,32,33,34,35,37,38,39,40] +5VS5
[2,6,7,8,9,10,14,24,29,31,33,35,38] +3VS5
1
[30] +VAD_1
PC35 PC44 [30] +VH28
A A
*10U/6.3V_8 0.1U/10V_4 [4,7,10,38] +1.8V
2
[21,30,31,32,33,34,35,37,38,40] +VIN
[6,7,10,21,22,23,27,28] +5V
[30] +VA
PROJECT : TWH
Custom A
<Doc>
5 4 3 2 1
5 4 3 2 1
ciucuit default is N12P
type
VGA
PQ17 PQ19 PQ16
PQ18
PR252
37
N12E
peak 53.4A POP(SMT) 1.37K
N12P
NA(no SMT) 806 ohm
D
peak 35.32A D
(CS18062FB29)
Nvideo N12E Nvideo N12P

CNTRL1 CNTRL0 CNTRL1 CNTRL0
N11E-GE N11E-GE
GPIO6 GPIO5 GPIO6 GPIO5
0 0 0.9125V 0 0 1V
0 1 0.8625V 0 1 0.975V
Update 2011/11/12
1 0 0.8125V 1 0 0.825V
PL26
1 1 N/A 1 1 N/A
UPB201212T-800Y-N
+VIN_VGA +VIN
PL27
PR230=180K PR232=49.9K PR226=681K PR230=160K(CS41602FB00) PR232=49.9K UPB201212T-800Y-N
2
PR227=324K PR226=1.43M(CS51432FB10) PC96 PC95 PC231 PC232 PC223 PC219
PR227=182K(CS41822FB18) PC222 PC221 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 0.1U/25V_4 0.1U/25V_4
+VGA_CORE +/- 5%
1
2200P/50V_4 0.1U/25V_4
Countinue current:43.55A
Peak current:65.3A
5
D D OCP minimum 70A
G G 20101118
SI:load line 0.9mV/A=>0.14mV/A 8112HDR2 4 4
VDDA = 4.2V S PQ64 S PQ17
RJK03B9 *RJK03B9 PL18 +VGACORE
1
2
3
1
2
3
PC235 0.36uH/25A_11
PC236 1U/10VC_4 8112LX2 1 2
8122AGND
C 22P/50V_4 C
8122AGND
2
1 2 8112VDDA PR251 PC238
1
2 1
8112BST2
D D PR124 + +
2_6 0.22U/25V_6 G G 2.2_8 PC102 PC100 PC93
8112CSP 8112LDR2 4 4 0.1U/10VC_4 330U_2V_7343 330U_2V_7343
2
S S PR250
8112CSN PQ68 30.1K/F_4 PC237
1
2
3
1
2
3
1
RJK03D3 PQ19 PC101 0.01U/25V_4
20
19
18
16
17
PD17 *RJK03D3 1500P/50V_4
PC228 PC233 RB501V-40 PR242 +VGACORE
LX2
HDR2
BST2
CSP
VDDA
1210 cancel 0 ohm 220P/50V_4 0.01U/25V_4 20101118 PC240 51/F_4

change PN 2 1
2
*0/short_4 PR241 1 15
PR245 CSN LDR2 +5VS5 for EOD 0.018U/25V_4
[14] VSS_GPU_SENSE
51/F_4 8122AGND 8122AGND 20101118
8112RSN_1 1 2 8112RSN 2 14 PC239 PR252
RSN VDDP 1000P/50V_4 806 ohm/F_4
2
PR246 8112CSN
2
*0/short_4 8112RSP_1 1 2 8112RSP 3 PU13 13 PC234 8122AGND
PR249 274/F_4 PR238 RSP GNDP 1U/10VC_4 8112CSP
[14] VGPU_CORE_SENSE OZ8122
1
*0_4 PD16
[29,30,32,33,34,35,36,38] MAINON 1 2 4 12 RB501V-40 +VIN_VGA PR255
ON/SKIP LDR1 PR243 1K/F_4
[9,29,38] DGPU_PWR_EN
1
PR244 220K_6 NTC
PR240 47K/F_4 8112VDDA +VIN_VGA 2 18112VIN 5 11 8112BST12 1 34.8K/F_4
VIN BST1
VDDA = 4.2V 2 1
GNDA
HDR1
VSET
TSET
20101009 for PD19 RB501V-40 PR234 PR239

LX1
PG
1 2 100K/F_4 2_6 PC91 PC92 PC229 PC230 PC97 PC98

EE timing PR230 PC226 2200P/50V_4 0.1U/25V_4 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 PR254
2
5
160K/F_4 1000P/50V_4 30.1K/F_4
6
10
21
+3V PC273 20101118 PC227 D D

0.47U/10V_4 8122AGND 8122VSET 0.22U/25V_6 G G
1
8112PG
8122AGND 8112HDR1 4 4
S PQ63 S PQ16
20101009 for PC225 RJK03B9 *RJK03B9 PL17 +VGACORE
1
2
3
1
2
3
PR236 1000P_4 8112VDDA 20101118 0.36uH/25A_11
EE initial 10K/F_4 PR226 PR232 8112LX1 1 2
3
8122TSET
B B
setting 1.43M/F_4 49.9K/F_4
2
8122AGND
5
1
20101118 PR229 PC103
[17] GFX_CORE_CNTRL0 2 88.7K/F_4 D D PR253 0.1U/10VC_4 +
1
8122AGND G G 2.2_8 PC99
PQ62 8112LDR1 4 4 + 330U_2V_7343
2
2N7002E-G S S PC94
PR227 PQ67 PQ18 330U_2V_7343
1
1
2
3
1
2
3
2
182K/F_4 RJK03D3 *RJK03D3 PC241 PR248
PC224 1500P/50V_4 *0_4
PR231 1000P/50VB_4 PR235 8112RSP_1 1 2
20101009 for EE 20101118 130K/F_4
3
+3V 8112RSN_1 1 2
initial setting 8122AGND *short
PR247
[17] GFX_CORE_CNTRL1 2 8122AGND 8122AGND *0_4
PQ65 PR277
PR237 2N7002E-G 10K/F_4
10K/F_4 +3V_GFX
1
[29,31,32,33,34,35,38] HWPG 1 3 1 2 DGPU_VC_EN [38]

PR276 +3V R3006
PQ20 0_4
*DDTA124EUA-7-F
*4.7K_4
3 2
4.7K_4 R3005
DGPU_PWROK [9,14,29]
3
DGPU_PWR_EN 2 PQ66 Q3003 R3007
*DTC144EUA 100K/F_4
9/3 update net name DGPU_PGOK-1 2
1
R3003 DTC144EUA
1
+1.05V_GFX 4.7K_4 DGPU_POK4 2 Q3001 C3003
A A
MMBT3904-7-F 1000P/50V_4
1
C3001
*1000P/50V_4
3
R3004
+1.5V_GFX 4.7K_4 DGPU_POK2 2
Q3002
1
C3002
*1000P/50V_4
MMBT3904-7-F
PROJECT : TWH
11/10 add for DGPU_PWROK circuit C A
<Doc>
5 4 3 2 1
1 2 3 4 5 6 7 8
VGA Core +1.05V_VTT PC220

0.1U/10V_4
38
5
D
G
4
A S (5A ) A
PQ59
1
2
3
RJK0392DPA +1.05V_GFX
+3V_GFX +1.05V_GFX +12VALW
2010_1009 for EE VGA timing +3VS5
1
+VIN PC216 PC215
PR145 PR125 PR146 0.1U/10V_4 *10U/6.3V_8
2
1
2
5
6
22_8 22_8 1M_4
PC140
3VGFX_OND 3 0.1U/10V_4
3
PR150 PQ26 PQ9
3
1M_4 DMN601K-7 DMN601K-7 PQ25
ME3424D +3V_GFX (2A )
4
2 2 PC138
2 2200P/50V_4
1
2 PR149 PQ27 PC139 PC137
[9,29,37] DGPU_PWR_EN
1
1M_4 DMN601K-7 *10U/6.3V_8 0.1U/10V_4
2
PQ28 DGPU_PR_EN_G
1
DTC144EUA
11/10 add
B B
+12VALW +1.5VSUS PC113

+1.5V_GFX 0.1U/10V_4
2010_1009 for EE VGA timing
5
+VIN PR148
PR147 1M_4 D
22_8 G
1.5VGFX_OND 4
S (10A )
3
PR151 PQ29 PQ21
1
2
3
1M_4 DMN601K-7 RJK0392DPA +1.5V_GFX
PC112
2 2 2200P/50V_4
3
1
PQ30 PC109 PC110
2 PR152 DMN601K-7 *10U/6.3V_8 0.1U/10V_4
[37] DGPU_VC_EN
2
1M_4
PQ31
1
DTC144EUA DGPU_VC_EN_G
C C
+1.8V +/- 5%
+3VS5
PU5 Countinue current:0.8A
3 5
VIN NC Peak current:2A
PC40 PC37 +1.8V
10U/6.3V_8 0.1U/10V_4 G9661
6
VOUT
PR71 9025EN
[29,30,32,33,34,35,36,37] MAINON 2
EN
10K/F_4
+5VS5 4 8 PC67 PC70 PC66
VDD GND
10U/6.3V_8
10U/6.3V_8
0.1U/10V_4
ADJ
PC41 1 9
*0.33U/6.3V_4 PGOOD GND1
PC54
7
1U/6.3V_4
1.8VADJ PR106
127K/F_4
*0/short_4 PR79
9025PGD
[29,31,32,33,34,35,37] HWPG
Vo=(0.8(R1+R2)/R2)
PR104
100K/F_4 R2<120Kohm
D D
1210 cancel 0 ohm
PROJECT : TWH
Custom A
<Doc>
1 2 3 4 5 6 7 8
1.Alert trace routing
between data and clock trace
2.Refer to ground
3.Keep out 20 mils
+1.05V_VTT DB2 Update
9/9 modify B~4350
220K_6 NTC
PUT COLSE
39
PC271
PR184 PR214 to VCORE
PR35 PR33 PR34 0.1U/10V_4 2 1 Phase 1
1.21K/F_4
130/F_4 *75/F_4 54.9/F_4 Inductor
6131SAGND PC171 PC173
PR176
PC165
PR65 PR72
20101014 for load line
SDIO 5600P/25V_4 680P/50V_4 PC176 22P/50V_4
VR_SVID_ALERT# 75K/F_4 165K/F_4
24.9/F_4 PR194
SCLK 100P/50V_4 1 2 CSP1
6131SAGND PC175 150K/F_6
PR173 PR182
1K/F_4 3.01K/F_4 PC39
PR186
PR178 PR181 3300P/50V_4 1 2 CSP2
24.9K/F_4 10/F_4 150K/F_6
1200P/50V_4
PR55
1210 cancel 0 ohm PR61 20K/F_4 20101014 for transient PR193
PC38 1 2 CSP3
100/F_4
*0/short_4 PR54 150K/F_6
[4] VSS_SENSE
CSSUM 470P/50V_4 CSN2 [40]
PC30
1000P/50V_4 PR75 10/F_4 CSN1 PC56
*0/short_4 PR48
VR1_CSREF
[4] VCC_SENSE
PR80 10/F_4 CSN2
PR47
CSCOMP
DIFFOUT
CPUILIM
+VCC_CORE 47n/10V_4
TRBST
6131SAGND
COMP
+3V +3V PR83 10/F_4 CSN3
QC 45W CPU
IMON
100/F_4 PR189 PR95
VSN
CSP2 [40]
FB
*0_4/S
PC46 VID1=1.05V 6.98K/F_4
1000P/50V_4
2-phase POP IccMax=94A
PR172 PR171 +1.05V_VTT CSN3 [40]
10K/F_4 10K/F_4 PU3 R_LL=1.9m ohm
49
47
45
53
44
43
41
40
52
48
51
50
46
42
6131SAGND NCP6131S PR96 PC60
1014 change PN 6131SAGND *0_4 OCP~105A
ILIM
CSSUM
NC2
NC1
FB
CSCOMP
IOUT
EPAD
DIFFOUT
COMP
TRBST
CSREF
VSN
DROOP
GFX_HWPG IMVP_PWRGD +5VS5
PR43 1213 change 47n/10V_4
75/F_4 VSP 1 39 CSN2
TSENSE VSP CSN2 footprint CSPP2
PR100
1018 cancel 0 ohm 2 TSENSE CSP2 38 CSP3 [40]
[2,29] H_PROCHOT# 3 37 CSN3 6.98K/F_4
*0/short_4 PR42 SDIO VRHOT# CSN3 CSPP3
[4] VR_SVID_DATA 4 SDIO CSP3 36
[4] VR_SVID_CLK SCLK 5 35 CSN1 CSN1 [40]
*0/short_4 PR41 SCLK CSN1 CSPP1
[4] VR_SVID_ALERT# 6 ALERT# CSP1 34
IMVP_PWRGD 7 33 DRON PC59
[6] IMVP_PWRGD VR_RDY DRON DRON [40]
[29] GFX_HWPG GFX_HWPG 8 32 VR1_PWM1 [40]
PR40 0_4 VRENABLE VR_RDYA PW M1/ADDR
[29] VRON 9 ENABLE PW M3/VBOOT 31 VR1_PWM3 [40]
PR32 2_6 6131_VCC 10 30 VR1_PWM2 47n/10V_4
+5VS5 VCC PW M2/ISHED VR1_PWM2 [40]
6131SAGND PR177 10K/F_4 11 29 PR192 73.2K/F_4 6131SAGND
+VIN_VCC_CORE ROSC IMAX PR99
TSENSE TSENSEA 12 28 PWMA VR1_PWMA [40] CSP1 [40]
VRMP PW MA/IMAXA
CSCOMPA
DIFFOUTA
TSENSEA 13 27 PR102 *0_4 PV2 12/7
+5VS5 6.98K/F_4
DROOPA
CSSUMA
TSENSEA VBOOTA
TRBSTA
PR39
COMPA
IOUTA
CSNA
VSNA
CSPA
VSPA
1K/F_4 PR91 PR191 PR190
ILIMA
FBA
PC27 PC167 PR90 *100K/F_4 10K/F_4 10K/F_4
0.01U/50V_4
PR174 PR89 20.5K/F_4
1U/6.3V_4
*14K/F_4 10K/F_4
14
15
16
17
18
19
20
21
22
23
24
25
26
6131SAGND 6131SAGND 6131SAGND
IMONA
0_4 DROOPA
DB2 Update 6131SAGND
PR216 6131SAGND 6131SAGND 9/28 try 100K for boot +5VS5
1
1
100K_4 NTC
6131SAGND PC58 2-phase POP

PC168 PR170 PC172 PR180 PR215 6131SAGND
PR44
0.1U/10V_4
0.1U/10V_4
8.25K/F_4
8.25K/F_4
100K_4 NTC
DROOPA *0_4 1000P/50V_4 CSNA PR98

PC57 *0_4
2
CSPPA
CSNA [40]
PR70
PR78
*0_4 CSSUMA 47n/10V_4
6131SAGND
PR88
6131SAGND 6131SAGND CSCOMPA PC48 1200P/50V_4 PR87 CSPA CSPA [40] VR1_PWM2
PR69 69.8K/F_4 6.98K/F_4
PUT COLSE PUT COLSE
6131SAGND
TO VCORE TO V_GT 14K/F_4 COMPA PC49 270P/25V_4 2010 1012 for FAE suggestion change 0603size
HOT SPOT HOT SPOT
DIFFOUTA
PC32 PR68 PR77
PR56 10/F_4 75K/F_4 165K/F_4
2phase 35W /3phase 45W option
circuit default is 45W CPU
68P/50V_4
PR45
PR60 1K/F_4 2 1
100/F_4 1018 cancel 0 ohm PR80 PR186
PC33 PR258 B~4350
*0/short_4 PR46 FBA 220K_6 NTC PR96 PR95 PR109 PC56 PR61
[4] VSS_AXG_SENSE
component PC73 PR111
PC28 100P/50V_4 PR98
*0/short_4 PR50 1000P/50V_4 PC34
PC76 PU8 PQ57
[4] VCC_AXG_SENSE PR66 PUT COLSE
PQ58 PL16
TO V_GT
PR49 3.01K/F_4
3300P/50V_4 Inductor
PR217 PR198
+VCC_GFX PC197
100/F_4
2phase 12.1K
POP NA(NO SMT) Change to 0ohm (CS31212FB28)
35WCPU
(CS00002JB38) OCP 65A
PV2 12/7 IMON IMONA
component PR192 PR185 3Phase
45WCPU NA POP(SMT) POP 20K
PR183 PC177 41.2K 24.3K OCP 105A
PR185 PC180 24K/F_4 0.1U/10V_4 2phase
22.6K/F_4 0.1U/10V_4 CS34122FB19 CS32432FB19
35WCPU
6131SAGND 6131SAGND
6131SAGND 6131SAGND
3Phase
73.2K
22.6K PROJECT : TWH
45WCPU CS37322BB00 CS32262FB15 Quanta Computer Inc.
Custom A
<Doc>
DB2 Update
PL24
UPB201212T-800Y-N
40
+VIN_VCC_CORE PL23 +VIN
UPB201212T-800Y-N
1
PC74
0.22U/25V_6 PC211 PC203 PC202 PC201 PC200 PC209 PC267 +
PR107
VREG_BSTRC1 2200P/50V_4 *4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 *4.7U/25V_8 0.1U/25V_4 0.1U/25V_4 PC266
2_6 470U/25V_EC_10H
2
5
5
D D
10/8 update PU6 G G
1
4
S
4
S Reserve for Acoustic
VREG_BST1 8 VREG_SW1_HG PQ54 PQ53 PL14
BST
NCP5911 HG RJK03B9D *RJK03B9D 0.36uH
1
2
3
1
2
3
2 7 VREG_SW1_OUT
[39] VR1_PWM1 PWM SW
PR105
5
DRON 3
49.9/F_4
EN GND 6
D D PR224
+VCC_CORE (Quad Core 45W)
4 VREG_SW1_LG 2.2_8 PR219
+5VS5 VCC LG
5
4
G
4
G
*0_2/S
PAD S PQ60 S
PC71 9 RJK03D2D PQ61
CSN1 [39] Peak current:94A
1
2
3
1
2
3
2.2U/6.3V_6 *RJK03D3D
PC218
CSP1 [39] Load Line : -1.9mV/A
1500P/50V_4 PR220
*0_2/S Parallel routing
+VCC_CORE (Dual Core 35W)
PV_Update 2010/11/17 +VIN_VCC_CORE Countinue current:43A
Peak current: 53A
PC72 Load Line : -1.9mV/A
PR108
VREG_BSTRC3 PC62 PC61 PC188 PC189 PC191 PC192
5
2200P/50V_4
4.7U/25V_8
4.7U/25V_8
0.1U/25V_4
*4.7U/25V_8
*4.7U/25V_8
2_6
0.22U/25V_6 D D
G G DB2 Update 2010_1009 for SMT change footprint
10/8 update PU7 4 4
S S
VREG_BST3 1 8 VREG_SW3_HG PQ55 PQ49 +VCC_CORE
1
2
3
1
2
3
BST HG
NCP5911 RJK03B9D *RJK03B9D PL15
2 7 VREG_SW3_OUT
PR110 0.36uH
1
DRON 3
GND 6
5
[39] DRON EN
49.9/F_4 PR196 PC104 + + + +
4 5 VREG_SW3_LG D D 2.2_8 PR223 0.1U/10V_4 PC81 PC82 PC83 PC84
+5VS5 VCC LG
G G *0_2/S 330u_2.5V_7343 *330u_2.5V_7343 330u_2.5V_7343 *330u_2.5V_7343
2
PAD
4 4 CSN3 [39]
PC75 9 S PQ56 S
2.2U/6.3V_6 RJK03D2D PQ48
1
2
3
1
2
3
CSP3 [39]
*RJK03D3D PC195
1500P/50V_4 PR218
*0_2/S Parallel routing
35W CPU NA PV_Update 2010/11/17
+VIN_VCC_CORE
PC73
PR109
VREG_BSTRC2 PC212 PC214 PC198 PC190 PC194 PC193
2200P/50V_4
4.7U/25V_8
4.7U/25V_8
0.1U/25V_4
*4.7U/25V_8
*4.7U/25V_8
2_6
5
5
0.22U/25V_6
D D
10/15 update PU8 G G
4 4
VREG_BST2 1 8 VREG_SW2_HG S PQ58 S PQ52 DB2 Update
BST
NCP5911 HG RJK03B9D *RJK03B9D PL16
1
2
3
1
2
3
2 7 VREG_SW2_OUT
PR111 0.36uH
5
DRON 3
GND 6
1
EN
49.9/F_4 D D
4 5 VREG_SW2_LG G G PR198 + +
+5VS5 VCC LG
4 4 2.2_8 PC242 PC243
PAD S PQ57 S PQ51 PR222 330u_2.5V_7343 330u_2.5V_7343
2
PC76 9 RJK03D2D *RJK03D3D *0_2/S PR217
1
2
3
1
2
3
2.2U/6.3V_6
CSN2 [39]
0_4
PC197
CSP2 [39]
1500P/50V_4
PR221
PV_Update 2010/11/17 *0_2/S Parallel routing 9/9 modify
PL28
UPB201212T-800Y-N
PV_Update 2010/11/12 +VIN

PL25
UPB201212T-800Y-N
+VCC_GFX
1
Discrete Only NA PC251 PC250 PC114 PC111 PC252 PC246 PC187 Countinue current:14A
2200P/50V_4 0.1U/25V_4
Peak current: 26A
4.7U/25V_8
4.7U/25V_8
4.7U/25V_8
0.1U/25V_4
*4.7U/25V_8
2
PC253 PV_Update 2010/11/13
PR262
Load Line : -3.9mV/A
5
2_6
0.22U/25V_6 Del PQ72 D
G
10/8 update PU14 4
S PQ72 DEL PC106, PC108 (Update 20101112)
1 8 VREG_SWA_HG RJK03B9D +VCC_GFX
1
2
3
BST
NCP5911 HG PL19
2 7 VREG_SWA
[39] VR1_PWMA PWM SW
PR263 0.36uH
5
1
DRON 3
GND 6
1
EN +
49.9/F_4 D D PR256 PC107
4 5 VREG_SWA_LG G G 2.2_8 0.1U/10V_4 PC105 + + +
+5VS5 VCC LG
4 4 PR257 *330U_2.5V_7343 PC272 PC274 PC275
2
PAD S PQ69 S PQ70 *0_2/S 390U/2.5V_6X5.8ESR10 390U/2.5V_6X5.8ESR10 390U/2.5V_6X5.8ESR10
2
PC254 9 RJK03D2D *RJK03D3D
1
2
3
1
2
3
CSNA [39]
2.2U/6.3V_6
PC244
CSPA [39]
1500P/50V_4
PR259 PV_Update 2010/11/12
*0_2/S Parallel routing 9/9 add
PROJECT : TWH
C A
<Doc>

A560 A580 Quanta TWH DATWHMB18D0

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A560 A580 Quanta TWH DATWHMB18D0

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5 4 3 2 1

TWH (15.6") Intel Huron River Platform Block Diagram 01

LAYER 1 : TOP LAYER 1 : TOP

Maxima 4GBs Power Source

USB2.0 Port x 3 Camera Bluetooth Realtek RTS5138 NCP6131/NCP5911/RT8209/G9334

LPC Interface PCIE Gen 1 x 1 Lane Power :

Sandy Bridge Processor (DMI,PEG,FDI)

3/26 DB for H/W modify.

PCI EXPRESS* - GRAPHICS

FDI1_TX#[0] PEG_RX[7] PEG_RX8 PRDY# XDP_PREQ#

JTAG & BPM

PEG_TX[7] C_PEG_TX8 R43 1K_4 CPU_DRAMRST#

FDI_FSYNC can gang all these 4

Sandy Bridge Processor (DDR3) 03

DDR SYSTEM MEMORY B

Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61

9/4 all of these 22uF/6.3V capacitors are

PEG AND DDR

DDR3 -1.5V RAILS

VCC67 VIDALERT# H_CPU_SVIDCLK

R31 C517 0.1U/10V_4

AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13

Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61

CFG[6:5] (PCIE Port Bifurcation Straps)

CFG4 CFG4 R156 *1K_4

Digital Display Interface

System Power Management

CougarPoint_Rev_0p7 [7,10,21,22,23,27,28,36] +5V

PM_RI# R610 10K_4

C399 *0.1U/10V_4 ** 5/12: modify +3VPCU

RSMRST# R547 10K_4 R201 150/F_4 PCH_CRT_G R511 *2N7002 R496

RTCX1 FW H0 / LAD0 C38

PCH_JTAG_TDI_R K5 Y10 SATA_COMP R302 37.4/F_4 R242 33_4 ACZ_BCLK

[23] ACZ_SYNC_AUDIO R520 33_4 1 3 ACZ_SYNC

P3 R640 10K_4 R522 33_4 ACZ_RST#

Pin Name Strap description Sampled Configuration Circuit

Flash Descriptor Security 0 = Override 8/26 A-->B modify U22

0 = Default (weak pull-down 20K) Size Document Number Rev

PCI_PIRQD# PIRQC# USBP8N CLKOUT_PCIE2P CLKIN_DMI_N CLK_BUF_PCIE_3GPLL

REQ2# / GPIO52 USBP10N CLKIN_GND1_N CLK_BUF_BCLK_P

CLK_PCIE_REQ3# R612 10K_4 3/26 DB change Part reference.

+3VS5 R587 2.2K_4 CLK_PCH_SRC0P +3VS5

0_4 CLK_BUF_DREFSSCLK# R315 10K_4 [26] CLK_PCIE_USB3N RP8 2 1 CLK_PCH_PEGBN

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

BD49 VSS_NCTF_10 VSS_NCTF_28 D49

10/11 no need pull high

1=Dis. x R356 *10K_4 BOARD_ID1 R357 *10K_4

0=YES GFX Present +3V

Cougar Point-M (POWER) wave noise 3 Vin Vout 1

Clock and Miscellaneous

1U/6.3V_4 65mA (10mils) 0.1U/10V_4

+1.05V R588 *0_4/S +VTT_VCCPCPU V21 8mA (10mils) 1U/6.3V_4

V_PROC_IO=1mA BJ8 L27 +1.05V_VCCA_B_DPL C586 1U/6.3V_4

IBEX PEAK-M (GND)

CougarPoint_Rev_0p7 PROJECT : TWH

[3] M_A_A[15:0] M_A_A0

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

Place these Caps near So-Dimm0. VREF DQ0 M1 Solution

C177 1U/6.3V_4 C286 1U/6.3V_4 R115

A C146 *10U/6.3V_6 +SMDDR_VREF_DQ0 A

8/31 C513 FP changed from

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

1=Dis. x R356 10K_4 BOARD_ID1 R357 10K_4

1U/6.3V_4 215K/F/04 TXLOUT0- 7