Dell 5560 Daojwamb8c1 Rev C

5 4 3 2 1
fix
vina JWA 15.6" Intel Chief River Platform Block Diagram 01
PCB 8L STACK UP
Channel A
PCI-E Gen2 VRAM DDR3 x 4 LAYER 1 : TOP
DDR3 On Board x 8 Lane Nvidia N13P-GV2 (64bit)
D DDR3 1333/1600 MT/s Intel Ivy Bridge 1GB/2GB LAYER 2 : SGND D
Maxima 1GB/2GB
Power : 27.5 Watt PAGE 18 LAYER 3 : IN1
PAGE 11~12 Processor : Daul Core
Package : FCBGA595 LAYER 4 : IN2
Channel B Power : 35/17 Watt
m
Size : 23 x 23 mm LAYER 5 : SVCC
DDR3 SO-DIMM2 Package : BGA1023
DDR3 1333/1600 MT/s LAYER 6 : IN3
Maxima 4GB Size : 31 x 24 mm LVDS Conn
LAYER 7 : GND
RVS PAGE 13
PAGE 6~10 PAGE 14~17 PAGE 26 LAYER 8 : BOT
o
Power Source
BCLK 100MHz
27MHz VGA Conn
PAGE 17 BQ24707
System Charger Power (+BATCHG)
FDI x 8
DMI x 4
.c
32.768KHz PAGE 27
SATA - 1st HDD
PAGE 53
Package : SATA0 6GB/s
LVDS Interface TPS51125ARGER
Power : PAGE 34 HDMI Conn System Power (+3VS5/+5VS5)
mSATA - 2nd HDD SATA1 6GB/s CRT PAGE 28
PAGE 46
x
C
Package : Intel Panther Point C
Power : PAGE 35 Platform LayController Hub USB3.0 Port x 1 TPS51216RUK

HDMI Interface DP PortB System Memory Power (+1.5VSUS/
Power : 4.1 Watt Support USB Charger +0.75V_DDR_VTT/DDR_VTTREF)
fi
ODD SATA2 3GB/s IC : TPS2540ARTER
Package : FCBGA989 HM77 USB3.0 Interface USB 3.0 Port 2(USB 2.0 Port 1) PAGE 47
Package : PAGE 31
Size : 25 x 25 mm RT8241DZQW / RT8068AZQW
Power : PAGE 34 Processor Power (+VCCSA/+1.8V)
25MHz
USB2.0 Interface
a
PAGE 19~25 PAGE 50
Port12 Port9
RT8240BGQW
Azalia
Camera Touch Screen PCH Power (+1.05V)
Power : Power :
in
Package : Package :
PAGE 49
SPI Interface PAGE 28 PAGE 43
LPC Interface PCIE Gen 1 x 1 Lane NCP3218MNR
DGPU Power (+VGACORE/+3V_GFX/
+1.5V_GFX/+1.05V_GFX)
Port3 Port5 Port4 Port1
PAGE 54
IT8518E/HX Combo Jack Realtek RTS5229-GR Atheros
B
System BIOS 8M Embedded Controller

iPHONE type
PAGE 36
ALC290Q-GR
Power :
h Card Reader
Power :
AR8161-BL3A-R
LAN Controller
Power :
Halt Mini Card
WLAN / BT Combo
NCP6132
Processor Power (+VCC_CORE/
+VCC_GFX)
PAGE 51/52
B
.c
SPI ROM Power : Package : QFN48 Package : LQPF48
PAGE 39 Package : OFN48
Package : LQFP128 Size : 7 x 7 mm Size : 7 x 7 mm DC JACK & Battery CONN
Size : 6 x 6 mm
Keyboard Size : 16 x 16 mm
PAGE 40
PAGE 45
PAGE 36 PAGE 33 PAGE 30 PAGE 35
Touch Pad
w
PAGE 40
I2S Interface
Audience Subwoofer 25MHz
Thermal IC SMBUS DMIC1
Fan1 eS305BQ TPA2011D1
PAGE 36
PWM Power : DB
w
PAGE 37
PAGE 42 PAGE 38 Package : LQPF48 USB3.0 Port x 2
DMIC2
Size : 7 x 7 mm USB 3.0 Port 1/3
LED PAGE 36 (USB 2.0 Port 0/2)
PAGE 36
PAGE 29 PAGE 32
w
A A
HALL Sensor Power Button 12.288MHz

PAGE 40 PAGE 41
MB Label P/N: HCR0A011010
Quanta Computer Inc.
PROJECT : JWA
Size Document Number Rev
3A
Block Diagram
5 4
http://vinafix.vn 3 2
Date: Tuesday, February 26, 2013
1
Sheet 1 of 54
1 2 3 4 5 6 7 8
fix +3.3V_RUN
202
ina
200
A0
JDIM1A SCREW PAD
v
H18 H10 H2 H3 H15 H1 H5 H9
*H-CT276C205D98P2 *O-JWA-5 *O-JWA-1 *H-C276D98P2 *H-C276D98P2 *O-JWA-2 *H-C276D98P2 *H-C205D98P2
2.2K 2.2K
H14 SMBCLK
1
C9 SMBDATA 12
H6 H13 H7 H4 H17 H14 H11
A *H-C122D122N *H-C315D118P2 *H-C295D150PT *H-C295D150PT *H-O98X138D98X138N *H-O122X201D122X201N *H-C248D248N A
+3.3V_SUS
PCH
1
2.2K 2.2K
m
C8 SML0CLK
G12 SML0DATA
+3.3V_SUS
o
2.2K 2.2K
E14 SMB_CLK_ME1 H8 intel-cpu-bkt-ulv
*intel-cpu-bkt-ulv
.c
H12 H16 H20 H19
M16 SMB_DATA_ME1 *spad-c197 *spad-c197 *MBGC1002010_NC MBGC1002010
4
1 3
+3.3V_SUS
+3.3V_SUS
+3.3V_ALW
1
N-MOS
N-MOS
2
B
CPU BLEKET B
2.2K 2.2K
mSATA WLAN
x
116 SMBDAT1
115 SMBCLK1
fi
+3.3V_ALW
100
3
4 Battery 16h
2.2K 2.2K
SIO Function IC SMBus Address
a
100
110 SMBCLK0 9
JDIM1A A0h
DDR3
ITE8518E 111 SMBDAT0 8 Charger 12
+3.3V_RUN
EMC1422 1001100xb (98h)
Thermal IC
in
G781-1P8 1001101xb (9Ah)
Charge IC BQ24707ARGRR 0b0001001x (0x12h)
Battery Battery 16h
2.2K 2.2K Audio DSP eS305QB 3Eh
94 SMBCLK3 8 GPU N13P-GV2 9Eh
C C
95 SMBDAT3 7 THERMAL(EMC1422) 98
7
h
THERMAL (G781-1P8) 9A
.c
42
43 Audio DSP 3E
eS305QB
N-MOS
N-MOS
+3V_GFX
4.7K 4.7K
D9
w
D8 GPU 9E
D D
w

PROJECT : JWA
3A
SMB/SCREW PAD
Date: Friday, March 01, 2013 Sheet 2 of 54
1 2 3 4 5 6 7 8
http://vinafix.vn
1 2 3 4 5 6 7 8
fix
vina
USB Master Port Assignment SATA Master Port Assignment PCIE Master Port Assignment
A A
USB0 External port#1 (USB3.0) SATA0 HDD PCIE 1 WLAN
m
External port#2 (USB3.0 SATA1 mSATA PCIE 2 NC
USB1 /Power share/debug port)
SATA2 NC PCIE 3 Card reader
o
USB2 External port#3 (USB3.0)
SATA3 ODD PCIE 4 NC
USB3 NC
.c
SATA4 NC PCIE 5 LAN
USB4 MiniCard 1 (WLAN/BT)
SATA5 NC PCIE 6 NC
USB5 NC
PCIE 7 NC
x
B B
USB6 NC
PCIE 8 NC
USB7 NC
fi
USB8 NC
a
USB9 Touch panel
USB10 NC
in
USB11 NC
USB12 Camera
C USB13 NC
h C
.c
w
w
w
D D

PROJECT : JWA
3A
PORT ASSIGNMENT
1 2 3 http://vinafix.vn
4 5 6
7
Sheet 3
8
of 54
5 4 3 2 1
f ix
ina
Adapter 90W
VER : 3A
v
Charger
BQ24707ARGRR PWR_SRC
D D
Battery 3S1P
m
+3.3V_EN2 ALW_ON
SIO_SLP_S4# SIO_SLP_S3# 1.5V_SUS_PWRGD VCCSA_EN +3.3V_RUN IMVP_VR_ON
TI (PU2)
o
TI(PU3) RichTek(PU6) RichTek(PU5) ON(PU8)
TPS51125ARGER NCP6132A
TPS51216RUKR LDO RT8241DGQW RT8240BGQW
.c
+1.5V_SUS
+3.3V_ALW +5V_ALW +15V_ALW
TDC: 3.84A TDC: 7.82A
+1.5V_SUS +0.75V_DDR_VTT +VCCSA_CORE +1.05V_PCH
TDC: 13.6A TDC: 1A TDC: 4.2A TDC: 13.5A
C C
PQ2 PQ40 PQ42
x
SUS_ON SUS_ON RUN_ON RUN_ON DGPU_PWR_ON# SIO_SLP_S3# DGFX_VR_PWRGD
fi
+VCC_CORE +VCC_iGFX_CORE
TDC: 32A TDC: 21.5A
Load Switch(PQ6) Load Switch(PQ4) Load Switch(PQ9) Load Switch(PQ8) Load Switch(PQ39) Load Switch(Q19) Load Switch(PQ39)
AO6402A AO6402A AO6402A AO6402A MDV1522URH AON7410 MDV1522URH
a
For dGPU only For dGPU only
+3.3V_SUS +5V_SUS +5V_RUN +1.5V_RUN +1.5V_GFX +1.5V_CPU +1.05V_GFX
in
TDC: 0.33A TDC: 0.1A TDC: 1.88A TDC: 0.81A TDC: 5.4A TDC: 5A TDC: 2.76A
For dGPU
B B
+3V_GFX
DGPU_PWR_EN 1.05V_PCH_PWRGD
Load Switch(PQ3)
AO6402A
RUN_ON
Load Switch(PQ5)
AO6402A
RichTek(PU7)
RT8068AZQW
h ON(PU1)
NCP3218MNR2G
.c
For dGPU only
For dGPU only
+VCC_DGFX_CORE
+3.3V_RUN +3V_GFX +1.8V_RUN TDC: 40A
TDC: 1.81A TDC: 0.97A TDC: 0.86A
w
w
A A
w

PROJECT : JWA
3A
Power Block Diagram
Date: Tuesday, February 26, 2013 Sheet 4 of 54
5 4 3 2 1
http://vinafix.vn
1 2 3 4 5 6 7 8
ix
af
Battery Mode +PWR_SRC 1 +PWR_SRC +VCHGR
2
vin
3 +5V_ALW2 +3.3V_ALW
POWER_SW_IN0#
5
+5V_ALW 8
3V/5V
+5V_ALW +5V_SUS 11 PWR SW VR CHARGER Battery
+15V_ALW 9
SUS
EN2
EN1
+3.3V_ALW SW +3.3V_SUS 12
SYS_PWR_SW#
A A
4 3.3V_ALW_ON
G
SUS_ON 10
m
7
+PWR_SRC
6 ALW_ON
20 13 RSMRST#
o
+1.5V_SUS
DDR/0.75V DPWROK
ME_SUS_PWR_ACK 14
SUSWARN#
+DDR_VTTREF 22 EC AC_PRESENT
15 ACPRESENT
35
.c
SIO_PWRBTN#
HWPG 16 PWRBTN#
+0.75V_DDR_VTT 23 SIO_SLP_S5# 17
SLP_S5#
SIO_SLP_S4#
18 SLP_S3#
SIO_SLP_S3#
1.5V_SUS_PWRGD 24 PCH
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
PG 19
IMVP_VR_ON
APWROK
x
S4
S3
EC_PWROK
B PM_DRAM_PWRGD B
VCCSA_PWRGD 38 DRAMPWROK
SUS_ON
RUN_ON
PCH_CLK
RC Delay SIO_SLP_S3# 10 39
19 34 SYS_PWROK
PROCPWRGD
fi
SIO_SLP_S4# SYS_PWROK
PLTRST#
DGPU_PWR_EN
18 25 37 36 48
19 18 17 DGPU_PWROK
+1.5V_SUS +1.5V_CPU 21 Buffer
SLP_S3 53 54
a
SWITCH SYS_PWROK
DGPU_HOLD_RST#
H_PWRGOOD
31 49
PLTRST#
+5V_ALW +1.8V_RUN +3.3V_ALW +3V_GFX
G
1.8V GPU PWR 44 IMVP_PWRGD
in
SIO_SLP_S3# 19 VR SWITCH 45
+1.5V_SUS +1.5V_GFX
VCCSA_EN 37 EC_PWROK
PG
EN
+PWR_SRC 52 55 41 46
32
38 PM_DRAM_PWRGD 40
+GFX_PWR_SRC
G
C RUN PWR +PWR_SRC
h U2
SM_SDRAMPWROK C
RESET#
UNCOREPWRGOOD
SWITCH 48 37 EC_PWROK
+5V_ALW +5V_RUN 26 33 DGPU_PWR_EN SVID
+VCCSA_CORE
.c
VCCSA 42
+3.3V_ALW +3.3V_RUN 27 +PWR_SRC
VR 34
VCCSA_PWRGD 50
+1.5V_SUS +1.5V_RUN 28 PG +VCC_DGFX_CORE
EN
GPU CPU
VR 51
w
VCCSA_EN
G
DGFX_VR_PWRGD
EN PG
RUN_ON +PWR_SRC
25
46
43 +3.3V_GFX
w
+VCC_CORE PLTRST# 56
+PWR_SRC
IMVP GPU_RST#
VR 47
+VCC_GFX_CORE 53 DGPU_HOLD_RST#
GPU
+1.05V_PCH 29 +1.05V_PCH +1.05V_GFX
1.05V GPU PWR
w
D 55 D
VR 44 SWITCH
1.05V_PCH_PWRGD IMVP_PWRGD
PG PG
EN
EN
30
G

+3.3V_RUN SVID IMVP_VR_ON 36 DGFX_VR_PWRGD
PROJECT : JWA
PCH 42 CPU GPU Size Document Number Rev
3A
POWER SEQUENCE
1 2 3 http://vinafix.vn 4 5 6
7
Sheet 5
8
of 54
5 4 3 2 1
f ix
ina
DP & PEG Compensation
v Ivy Bridge Processor (RESERVED, CFG) +1.05V_PCH
D PEG_ICOMPO 12mil eDP_COMP R2671 2 24.9/F_4

D
PEG_ICOMPI, PEG_RCOMPO 4mil,

U18A eDP_COMPIO and ICOMPO signals should
G3 PEG_COMP be shorted near balls and
PEG_ICOMPI G1
m
DMI_TXN0 M2 PEG_ICOMPO G4
routed within 500 mils
[19] DMI_TXN0 DMI_RX#[0] PEG_RCOMPO
[19] DMI_TXN1 P6
DMI_TXN1 DMI_RX#[1]
[19] DMI_TXN2 P1
DMI_TXN2 DMI_RX#[2]
[19] DMI_TXN3 P10 H22 PEG_RXN0 [14]
DMI_TXN3 DMI_RX#[3] PEG_RX#[0] PEG_RXN0
J21 PEG_RXN1 [14]
PEG_RX#[1] PEG_RXN1 +1.05V_PCH
[19] DMI_TXP0 N3 B22 PEG_RXN2 [14]
DMI_TXP0 DMI_RX[0] PEG_RX#[2] PEG_RXN2
[19] DMI_TXP1 P7 D21 PEG_RXN3 [14]
DMI
P3 A19
o
[19] DMI_TXP2 PEG_RXN4 [14]
[19] DMI_TXP3 P11 D17 PEG_RXN5 [14]
B14 PEG_RXN6 [14]
PEG_RX#[6] PEG_RXN6
[19] DMI_RXN0 K1 D13 PEG_RXN7 [14]
DMI_RXN0 DMI_TX#[0] PEG_RX#[7] PEG_RXN7
[19] DMI_RXN1 M8 A11
DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
[19] DMI_RXN2 N4 B10 PEG_COMP R2591 2 24.9/F_4
DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
.c
[19] DMI_RXN3 R2 G8
DMI_RXN3 DMI_TX#[3] PEG_RX#[10] A8 PEG_ICOMPI and RCOMPO signals should
DMI_RXP0 K3 PEG_RX#[11] B6
[19] DMI_RXP0 DMI_TX[0] PEG_RX#[12] be routed within 500 mils
[19] DMI_RXP1 M7 H8
DMI_RXP1 DMI_TX[1] PEG_RX#[13]
[19] DMI_RXP2 P4 E5
DMI_RXP2 DMI_TX[2] PEG_RX#[14] PEG_ICOMPO signals should
[19] DMI_RXP3 T3 K7
DMI_RXP3 DMI_TX[3] PEG_RX#[15] be routed within 500 mils
K22 PEG_RXP0 [14]
PEG_RX[0] PEG_RXP0
K19 PEG_RXP1 [14]
PEG_RX[1] PEG_RXP1
C21 PEG_RXP2
x
PEG_RX[2] PEG_RXP2 [14]
C
[19] FDI_TXN0 U7 D19 PEG_RXP3 [14]
C
FDI_TXN0 FDI0_TX#[0] PEG_RX[3] PEG_RXP3
[19] FDI_TXN1 W11 C19 PEG_RXP4 [14]
[19] FDI_TXN2 W1 D16 PEG_RXP5 [14]
[19] FDI_TXN3 AA6 C13 PEG_RXP6 [14]
FDI_TXN4 W6 D12 PEG_RXP7
PCI EXPRESS -- GRAPHICS

[19] FDI_TXN4 FDI1_TX#[0] PEG_RX[7] PEG_RXP7 [14]
fi
[19] FDI_TXN5 V4 C11
FDI_TXN5 FDI1_TX#[1] PEG_RX[8]
[19] FDI_TXN6 Y2 C9
[19] FDI_TXN7 AC9 F8
Intel(R) FDI
C8
PEG_RX[11] C5
FDI_TXP0 U6 PEG_RX[12] H6
[19] FDI_TXP0 FDI0_TX[0] PEG_RX[13]
[19] FDI_TXP1 W10 F6
FDI_TXP1 FDI0_TX[1] PEG_RX[14]
FDI_TXP2 W3 K6
a
[19] FDI_TXP2 FDI0_TX[2] PEG_RX[15]
[19] FDI_TXP3 AA7
FDI_TXP3 FDI0_TX[3]
[19] FDI_TXP4 W7 G22 PEG_TXN0_C C128 2 1 0.1U/16V_4 PEG_TXN0 [14]
FDI_TXP4 FDI1_TX[0] PEG_TX#[0] PEG_TXN0
[19] FDI_TXP5 T4 C23 PEG_TXN1_C C125 2 1 0.1U/16V_4 PEG_TXN1 [14]
[19] FDI_TXP6 AA3 D23 PEG_TXN2_C C465 2 1 0.1U/16V_4 PEG_TXN2 [14]
[19] FDI_TXP7 AC8 F21 PEG_TXN3_C C130 2 1 0.1U/16V_4 PEG_TXN3 [14]
in
H19 PEG_TXN4_C C132 2 1 0.1U/16V_4 PEG_TXN4 [14]
PEG_TX#[4] PEG_TXN4
[19] FDI_FSYNC0 AA11 C17 PEG_TXN5_C C116 2 1 0.1U/16V_4 PEG_TXN5 [14]
FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] PEG_TXN5
[19] FDI_FSYNC1 AC12 K15 PEG_TXN6_C C123 2 1 0.1U/16V_4 PEG_TXN6 [14]
FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] PEG_TXN6
F17 PEG_TXN7_C C121 2 1 0.1U/16V_4 PEG_TXN7 [14]
PEG_TX#[7] PEG_TXN7
[19] FDI_INT U11 F14
FDI_INT FDI_INT PEG_TX#[8] A15
FDI_LSYNC0 AA10 PEG_TX#[9] J14
[19] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
[19] FDI_LSYNC1 AG8 H13
FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
eDP_ICOMPO 12mil M10
PEG_TX#[12] F10
B
eDP_COMPIO 4mil
eDP_COMP
AF3
AD2
AG11
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
h
D9
J4
F22
A23
D24
PEG_TXP0_C
PEG_TXP1_C
PEG_TXP2_C
C127
C126
C464
2
2
2
1
1
1
0.1U/16V_4
0.1U/16V_4
0.1U/16V_4
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP0
PEG_TXP1
[14]
[14]
B
.c
PEG_TX[2] PEG_TXP2 [14]
E21 PEG_TXP3_C C129 2 1 0.1U/16V_4 PEG_TXP3 [14]
PEG_TX[3] PEG_TXP3
AG4 G19 PEG_TXP4_C C131 2 1 0.1U/16V_4 PEG_TXP4 [14]
eDP_AUX# PEG_TX[4] PEG_TXP4
AF4 B18 PEG_TXP5_C C115 2 1 0.1U/16V_4 PEG_TXP5 [14]
eDP_AUX PEG_TX[5] PEG_TXP5
K17 PEG_TXP6_C C124 2 1 0.1U/16V_4 PEG_TXP6 [14]
PEG_TX[6] PEG_TXP6
eDP
G17 PEG_TXP7_C C122 2 1 0.1U/16V_4 PEG_TXP7 [14]

PEG_TX[7] PEG_TXP7
AC3 E14
AC4 eDP_TX#[0] PEG_TX[8] C15
AE11 eDP_TX#[1] PEG_TX[9] K13
AE7 eDP_TX#[2] PEG_TX[10] G13
w
eDP_TX#[3] PEG_TX[11] K10

AC1 PEG_TX[12] G10
AA4 eDP_TX[0] PEG_TX[13] D8
AE10 eDP_TX[1] PEG_TX[14] K4
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]
w
IC,IVB_2CBGA,0P7
w
A A
CPU QPN
i7-3540M AJ0QD5J8T00 Quanta B 35W
i5-3230M AJSR0WXQT01 WIN BS 35W
i3-3120M AJSR0TYRT01 WIN BS 35W Quanta Computer Inc.
PROJECT : JWA
3A
Ivy Bridge 1/5
5 4 http://vinafix.vn 3 2
Date: Tuesday, February 26, 2013 Sheet
1
6 of 54
5 4 3 2 1
fix Ivy Bridge Processor (CLK,MISC,JTAG)

vina U18B
J3 CLK_CPU_BCLKP
BCLK CLK_CPU_BCLKP [23]
SNB_IVB# N.A at SNB EDS #27637 0.7v1 H2 CLK_CPU_BCLKN
BCLK# CLK_CPU_BCLKN [23]
MISC
CLOCKS
[22] H_SNB_IVB# F49 R265 1 2 1K_4
H_SNB_IVB# PROC_SELECT# AG3 CLK_DP_P_R
DPLL_REF_CLK AG1 CLK_DP_N_R
H_CPUDET# C57 DPLL_REF_CLK# R266 1 2 1K_4
D TP10 +1.05V_PCH D
PROC_DETECT#
CATERR# C49
m
TP13 CATERR#
THERMAL
[38] PECI_EC R46 1 2 43_4 PECI_EC_R A48 AT30 CPU_DRAMRST#
PECI_EC PECI SM_DRAMRST#
DDR3
MISC
BF44 SM_RCOMP_0 R271 1 2 140/F_4
IMVP7_PROCHOT# R2471 2 56_4 C45 SM_RCOMP[0] BE43 SM_RCOMP_1 R270 1 2 25.5/F_4
o
[38,51,53] H_PROCHOT#
IMVP7_PROCHOT# PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP_2 R269 1 2 200/F_4
SM_RCOMP[2]
PM_THRMTRIP# D45
SM_RCOMP_0, SM_RCOMP_1 20mil / SM_RCOMP_2 15mil.
Over 130 degree C will [24] PM_THRMTRIP# THERMTRIP#
drive low
.c
N53
PRDY# N55
PREQ#
L56 XDP_TCLK TP60
TCK L55 XDP_TMS TP58 +1.05V_PCH
TMS
PWR MANAGEMENT
J58 XDP_TRST# TP59
TRST#
JTAG & BPM

[19] H_PM_SYNC C48 M60 XDP_TDI TP62
H_PM_SYNC PM_SYNC TDI L59 XDP_TDO TP61
x
C TDO +3.3V_RUN C
IMVP7_PROCHOT# R246 2 1 62_4
[24] H_PW RGOOD B46
H_PW RGOOD UNCOREPWRGOOD K58 XDP_DBRST# 1 2
10K_4 2 1 R52 DBR# R256 1K_4
fi
SM_DRAMPW ROK BE45 G58
SM_DRAMPWROK BPM#[0] E55
BPM#[1] E59
BPM#[2] G55
BPM#[3] G59
PLTRST# 2 1 CPU_PLTRST#_R D44 BPM#[4] H60
[22,30,33,35,38] PLTRST# RESET# BPM#[5]
R250 1.5K/F_4 J59
a
BPM#[6] J61
BPM#[7]
1
R251
750/F_4
in
2
IC,IVB_2CBGA,0P7
Intel spec VinH min =VCCIO X 0.7 Boot S3 S3 RSM
B
+1.5V_CPU
DRAM_PWRGD
h 100 ns after +1.5V_CPU
Follow #DG1.5 471984 P130
DRAMRST# Routing Illustration
+1.5V_SUS
B
.c
SYS_PWROK reaches 80%
2
SM_DRAMPWROK
R86 Q13
Follow #DG1.5 471984 P119 2N7002W
1K_4
1
[11,12,13] DDR3_DRAMRST# DDR3_DRAMRST# 2 1 DDR3_DRAMRST#_R 3 1 CPU_DRAMRST#
w
R87 1K_4
Follow #DG1.5 471984 P128
1
DDR Power Gating Topology DDR_HVREF_RST_PCH
[23] DDR_HVREF_RST_PCH R76
1
4.99K/F_4
w
+3.3V_SUS C199
2
+3.3V_SUS 1 2 0.047U/10V_4
2
R84 1K_4
+1.5V_CPU
1
C193
2
R83 *0.1U/16V_4_NC
2
w
A
*200_4_NC A
R81
2
U7 200_4
[19] PM_DRAM_PW RGD PM_DRAM_PW RGD 2
1
4 SM_DRAMPW ROK_R 1 2 SM_DRAMPW ROK

[19,38] EC_PW ROK 1 R80 130_4
EC_PW ROK
*74AHC1G09GW _NC Quanta Computer Inc.
3
PROJECT : JWA
3 Size Document Number Rev
2 1 3A
Ivy Bridge 2/5
http://vinafix.vn
R82 *0_4_SHORT_NC
5 4 3 2 1
5 4 3 2 1
f ix
vina Ivy Bridge Processor (DDR3)
U18D
U18C [13] M_B_DQ[63:0]
D D
[11,12] M_B_DQ0 AL4
M_A_DQ[63:0] M_A_DQ0 AG6 M_B_DQ1 AL1 SB_DQ[0] BA34
SA_DQ[0] SB_DQ[1] SB_CK[0] M_B_CLKP0 [13]
M_A_DQ1 AJ6 AU36 [11,12] M_B_DQ2 AN3 AY34 [13]
SA_DQ[1] SA_CK[0] M_A_CLKP0 SB_DQ[2] SB_CK#[0] M_B_CLKN0
M_A_DQ2 AP11 AV36 [11,12] M_B_DQ3 AR4 AR22 [13]
SA_DQ[2] SA_CK#[0] M_A_CLKN0 SB_DQ[3] SB_CKE[0] M_B_CKE0
M_A_DQ3 AL6 AY26 M_B_DQ4 AK4
m
SA_DQ[3] SA_CKE[0] M_A_CKE0 [11,12] SB_DQ[4]
M_A_DQ4 AJ10 M_B_DQ5 AK3
M_A_DQ5 AJ8 SA_DQ[4] M_B_DQ6 AN4 SB_DQ[5]
M_A_DQ6 AL8 SA_DQ[5] M_B_DQ7 AR1 SB_DQ[6]
M_A_DQ7 AL7 SA_DQ[6] M_B_DQ8 AU4 SB_DQ[7]
M_A_DQ8 AR11 SA_DQ[7] M_B_DQ9 AT2 SB_DQ[8] BA36
SA_DQ[8] SB_DQ[9] SB_CK[1] M_B_CLKP1 [13]
M_A_DQ9 AP6 AT40 M_B_DQ10 AV4 BB36 [13]
SA_DQ[9] SA_CK[1] SB_DQ[10] SB_CK#[1] M_B_CLKN1
M_A_DQ10 AU6 AU40 M_B_DQ11 BA4 BF27 [13]
SA_DQ[10] SA_CK#[1] SB_DQ[11] SB_CKE[1] M_B_CKE1
AV9 BB26 AU3
o
M_A_DQ11 M_B_DQ12
M_A_DQ12 AR6 SA_DQ[11] SA_CKE[1] M_B_DQ13 AR3 SB_DQ[12]
M_A_DQ13 AP8 SA_DQ[12] M_B_DQ14 AY2 SB_DQ[13]
M_A_DQ14 AT13 SA_DQ[13] M_B_DQ15 BA3 SB_DQ[14]
M_A_DQ15 AU13 SA_DQ[14] M_B_DQ16 BE9 SB_DQ[15]
M_A_DQ16 BC7 SA_DQ[15] M_B_DQ17 BD9 SB_DQ[16] BE41
SA_DQ[16] SB_DQ[17] SB_CS#[0] M_B_CS#0 [13]
.c
M_A_DQ17 BB7 BB40 [11,12] M_B_DQ18 BD13 BE47 [13]
SA_DQ[17] SA_CS#[0] M_A_CS#0 SB_DQ[18] SB_CS#[1] M_B_CS#1
M_A_DQ18 BA13 BC41 M_B_DQ19 BF12
M_A_DQ19 BB11 SA_DQ[18] SA_CS#[1] M_B_DQ20 BF8 SB_DQ[19]
M_A_DQ20 BA7 SA_DQ[19] M_B_DQ21 BD10 SB_DQ[20]
M_A_DQ21 BA9 SA_DQ[20] M_B_DQ22 BD14 SB_DQ[21]
M_A_DQ22 BB9 SA_DQ[21] M_B_DQ23 BE13 SB_DQ[22]
M_A_DQ23 AY13 SA_DQ[22] M_B_DQ24 BF16 SB_DQ[23] AT43
SA_DQ[23] SB_DQ[24] SB_ODT[0] M_B_ODT0 [13]
M_A_DQ24 AV14 AY40 [11,12] M_B_DQ25 BE17 BG47 [13]
SA_DQ[24] SA_ODT[0] M_A_ODT0 SB_DQ[25] SB_ODT[1] M_B_ODT1
M_A_DQ25 AR14 BA41 M_B_DQ26 BE18
M_A_DQ26 AY17 SA_DQ[25] SA_ODT[1] M_B_DQ27 BE21 SB_DQ[26]
x
C M_A_DQ27 AR19 SA_DQ[26] M_B_DQ28 BE14 SB_DQ[27] C
M_A_DQ28 BA14 SA_DQ[27] M_B_DQ29 BG14 SB_DQ[28]
M_A_DQ29 AU14 SA_DQ[28] M_B_DQ30 BG18 SB_DQ[29]
SA_DQ[29] SB_DQ[30] M_B_DQSN[7:0] [13]
M_A_DQ30 BB14 M_B_DQ31 BF19 AL3 M_B_DQSN0
M_A_DQ31 BB17 SA_DQ[30] AL11 M_B_DQ32 BD50 SB_DQ[31] SB_DQS#[0] AV3 M_B_DQSN1
SA_DQ[31] SA_DQS#[0] M_A_DQSN0 [11] SB_DQ[32] SB_DQS#[1]
fi
M_A_DQ32 BA45 AR8 [11] M_B_DQ33 BF48 BG11 M_B_DQSN2
M_A_DQ33 AR43 SA_DQ[32] SA_DQS#[1] AV11 M_A_DQSN1 M_B_DQ34 BD53 SB_DQ[33] SB_DQS#[2] BD17 M_B_DQSN3
M_A_DQ34 AW48 AT17 [11] M_B_DQ35 BF52 BG51 M_B_DQSN4
M_A_DQ35 BC48 SA_DQ[34] SA_DQS#[3] AV45 M_A_DQSN3 M_B_DQ36 BD49 SB_DQ[35] SB_DQS#[4] BA59 M_B_DQSN5
DDR SYSTEM MEMORY B

M_A_DQ36 BC45 AY51 [12] M_B_DQ37 BE49 AT60 M_B_DQSN6
SA_DQ[36] SA_DQS#[5] M_A_DQSN5 SB_DQ[37] SB_DQS#[6]
DDR SYSTEM MEMORY A
M_A_DQ37 AR45 AT55 [12] M_B_DQ38 BD54 AK59 M_B_DQSN7

M_A_DQ38 AT48 SA_DQ[37] SA_DQS#[6] AK55 M_A_DQSN6 M_B_DQ39 BE53 SB_DQ[38] SB_DQS#[7]
SA_DQ[38] SA_DQS#[7] M_A_DQSN7 [12] SB_DQ[39]
M_A_DQ39 AY48 M_B_DQ40 BF56
a
M_A_DQ40 BA49 SA_DQ[39] M_B_DQ41 BE57 SB_DQ[40]
M_A_DQ41 AV49 SA_DQ[40] M_B_DQ42 BC59 SB_DQ[41]
M_A_DQ42 BB51 SA_DQ[41] M_B_DQ43 AY60 SB_DQ[42]
M_A_DQ43 AY53 SA_DQ[42] M_B_DQ44 BE54 SB_DQ[43]
M_A_DQ44 BB49 SA_DQ[43] M_B_DQ45 BG54 SB_DQ[44]
SA_DQ[44] SB_DQ[45] M_B_DQSP[7:0] [13]
in
M_A_DQ45 AU49 AJ11 [11] M_B_DQ46 BA58 AM2 M_B_DQSP0
M_A_DQ46 BA53 SA_DQ[45] SA_DQS[0] AR10 M_A_DQSP0 M_B_DQ47 AW59 SB_DQ[46] SB_DQS[0] AV1 M_B_DQSP1
SA_DQ[46] SA_DQS[1] M_A_DQSP1 [11] SB_DQ[47] SB_DQS[1]
M_A_DQ47 BB55 AY11 [11] M_B_DQ48 AW58 BE11 M_B_DQSP2
M_A_DQ48 BA55 SA_DQ[47] SA_DQS[2] AU17 M_A_DQSP2 M_B_DQ49 AU58 SB_DQ[48] SB_DQS[2] BD18 M_B_DQSP3
M_A_DQ49 AV56 AW45 [12] M_B_DQ50 AN61 BE51 M_B_DQSP4
M_A_DQ50 AP50 SA_DQ[49] SA_DQS[4] AV51 M_A_DQSP4 M_B_DQ51 AN59 SB_DQ[50] SB_DQS[4] BA61 M_B_DQSP5
M_A_DQ51 AP53 AT56 [12] M_B_DQ52 AU59 AR59 M_B_DQSP6
M_A_DQ52 AV54 SA_DQ[51] SA_DQS[6] AK54 M_A_DQSP6 M_B_DQ53 AU61 SB_DQ[52] SB_DQS[6] AK61 M_B_DQSP7
M_A_DQ53 AT54 M_B_DQ54 AN58
M_A_DQ54 AP56 SA_DQ[53] M_B_DQ55 AR58 SB_DQ[54]
B
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
AP52
AN57
AN53
AG56
AG53
AN55
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
h M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
AK58
AL58
AG58
AG59
AM60
AL59
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60] BF32 M_B_A0
M_B_A[15:0] [13]
B
.c
SA_DQ[60] M_A_A[15:0] [11,12] SB_DQ[61] SB_MA[0]
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ62 AF61 BE33 M_B_A1
M_A_DQ62 AG55 SA_DQ[61] SA_MA[0] BB34 M_A_A1 M_B_DQ63 AH60 SB_DQ[62] SB_MA[1] BD33 M_B_A2
M_A_DQ63 AK56 SA_DQ[62] SA_MA[1] BE35 M_A_A2 SB_DQ[63] SB_MA[2] AU30 M_B_A3
SA_DQ[63] SA_MA[2] BD35 M_A_A3 SB_MA[3] BD30 M_B_A4
SA_MA[3] AT34 M_A_A4 SB_MA[4] AV30 M_B_A5
SA_MA[4] AU34 M_A_A5 SB_MA[5] BG30 M_B_A6
SA_MA[5] BB32 M_A_A6 BG39 SB_MA[6] BD29 M_B_A7
SA_MA[6] [13] M_B_BS#0 SB_BS[0] SB_MA[7]
[11,12] BD37 AT32 M_A_A7 [13] BD42 BE30 M_B_A8
M_A_BS#0 SA_BS[0] SA_MA[7] M_B_BS#1 SB_BS[1] SB_MA[8]
[11,12] BF36 AY32 M_A_A8 [13] AT22 BE28 M_B_A9
w
M_A_BS#1 SA_BS[1] SA_MA[8] M_B_BS#2 SB_BS[2] SB_MA[9]

[11,12] BA28 AV32 M_A_A9 BD43 M_B_A10
M_A_BS#2 SA_BS[2] SA_MA[9] SB_MA[10]
BE37 M_A_A10 AT28 M_B_A11
SA_MA[10] BA30 M_A_A11 SB_MA[11] AV28 M_B_A12
SA_MA[11] BC30 M_A_A12 AV43 SB_MA[12] BD46 M_B_A13
SA_MA[12] [13] M_B_CAS# SB_CAS# SB_MA[13]
[11,12] BE39 AW41 M_A_A13 [13] BF40 AT26 M_B_A14
M_A_CAS# SA_CAS# SA_MA[13] M_B_RAS# SB_RAS# SB_MA[14]
[11,12] BD39 AY28 M_A_A14 [13] BD45 AU22 M_B_A15
M_A_RAS# SA_RAS# SA_MA[14] M_B_W E# SB_WE# SB_MA[15]
[11,12] AT41 AU26 M_A_A15
w
M_A_W E# SA_WE# SA_MA[15]
IC,IVB_2CBGA,0P7
IC,IVB_2CBGA,0P7
w
A A

PROJECT : JWA
3A
Ivy Bridge 3/5
1
8 of 54
5 4 3 2 1
f ix
Ivy Bridge Processor Ivy Bridge Processor (GRAPHIC POWER)
ina
1.05V_PCH CPU VGT
SNB: 21.5A POWER
v
SNB: 8.5A U18G
CPU Core Power IVY: 33A
SNB: 53A U18F POWER +1.05V_PCH
IVY: 8.5A
10F x12
10uF x 12
IVY: 53A AY43 +VDDR_REF_CPU
SM_VREF +VDDR_REF_CPU
10uF x 24 AA46
VREF
+VCC_GFX_CORE VAXG[1]
+VCC_CORE AB47
AF46 AB50 VAXG[2] BE7
VCCIO[1] AG48 AB51 VAXG[3] SA_DIMM_VREFDQ BG7
VCCIO[3] AG50 AB52 VAXG[4] SB_DIMM_VREFDQ
C153 C463 C108 C99 A26 VCCIO[4] AG51 AB53 VAXG[5]
A29 VCC[1] VCCIO[5] AJ17 AB55 VAXG[6]
VCC[2] VCCIO[6] VAXG[7]
1
1
10U/6.3V_8 *10U/6.3V_8_NC A31 AJ21 AB56
D
A34 VCC[3] VCCIO[7] AJ25 AB58 VAXG[8] D
10U/6.3V_6 10U/6.3V_8 A35 VCC[4] VCCIO[8] AJ43 AB59 VAXG[9]

2
2
A38 VCC[5] VCCIO[9] AJ47 C178 C167 C144 C166 C165 C164 AC61 VAXG[10]
A39 VCC[6] VCCIO[10] AK50 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 C182 C168 C155 C161 AD47 VAXG[11]
1
A42 AK51 AD48
1
C26 AL14 10U/6.3V_8 10U/6.3V_8 AD50
C27 VCC[9] VCCIO[13] AL15 AD51 VAXG[14] AJ28 CPU MCH
- 1.5V RAILS
2
2
C151 C112 C95 C451 C32 VCC[10] VCCIO[14] AL16 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 AD52 VAXG[15] VDDQ[1] AJ33
2
C34 VCC[11] VCCIO[15] AL20 10U/6.3V_6 10U/6.3V_6 AD53 VAXG[16] VDDQ[2] AJ36 SNB: 5A
m
VCC[12] VCCIO[16] VAXG[17] VDDQ[3]
1
1
10U/6.3V_8 *10U/6.3V_8_NC C37 AL22 AD55 AJ40
C39 VCC[13] VCCIO[17] AL26 AD56 VAXG[18] VDDQ[4] AL30 IVY: 5A
10U/6.3V_6 *10U/6.3V_8_NC C42 VCC[14] VCCIO[18] AL45 C181 C171 C183 C184 AD58 VAXG[19] VDDQ[5] AL34 10uF x 6
2
2
D27 VCC[15] VCCIO[19] AL48 AD59 VAXG[20] VDDQ[6] AL38
1
D32 AM16 10U/6.3V_8 10U/6.3V_8 AE46 AL42
D34 VCC[17] VCCIO[21] AM17 C173 C177 N45 VAXG[22] VDDQ[8] AM33 C179 C176 C196 C192
VCC[18] VCCIO[22] VAXG[23] VDDQ[9] +1.5V_CPU
D37 AM21 *10U/6.3V_8_NC P47 AM36
2
1
D39 AM43 10U/6.3V_6 10U/6.3V_6 P48 AM40
PEG IO AND DDR IO

D42 VCC[20] VCCIO[24] AM47 P50 VAXG[25] VDDQ[11] AN30
C466 C119 C117 C461 E26 VCC[21] VCCIO[25] AN20 P51 VAXG[26] VDDQ[12] AN34 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
2
E28 VCC[22] VCCIO[26] AN42 *10U/6.3V_8_NC C154 C156 C145 C162 P52 VAXG[27] VDDQ[13] AN38
o
1
10U/6.3V_8 10U/6.3V_8 E32 AN45 P53 AR26
DDR3
1
E34 AN48 10U/6.3V_8 P55 AR28
GRAPHICS
10U/6.3V_8 E37 VCC[25] VCCIO[29] P56 VAXG[30] VDDQ[16] AR30 C175 C174
2
*10U/6.3V_8_NC E38 VCC[26] P61 VAXG[31] VDDQ[17] AR32
2
VCC[27] VAXG[32] VDDQ[18]
1
CORE SUPPLY
F25 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 T48 AR34
F26 VCC[28] T58 VAXG[33] VDDQ[19] AR36
F28 VCC[29] T59 VAXG[34] VDDQ[20] AR40 10U/6.3V_6 10U/6.3V_6
2
F32 VCC[30] T61 VAXG[35] VDDQ[21] AV41
.c
C94 C114 C457 C450 F34 VCC[31] U46 VAXG[36] VDDQ[22] AW26
F37 VCC[32] AA14 V47 VAXG[37] VDDQ[23] BA40
1
10U/6.3V_8 *10U/6.3V_8_NC F38 AA15 V48 BB28

F42 VCC[34] VCCIO[31] AB17 V50 VAXG[39] VDDQ[25] BG33
10U/6.3V_8 *10U/6.3V_8_NC G42 VCC[35] VCCIO[32] AB20 V51 VAXG[40] VDDQ[26]
2
H25 VCC[36] VCCIO[33] AC13 V52 VAXG[41]

H26 VCC[37] VCCIO[34] AD16 V53 VAXG[42]
C H32 VCC[40] VCCIO[37] AE14 V58 VAXG[45] C
H34 VCC[41] VCCIO[38] AE15 V59 VAXG[46]
C152 C138 C149 C139 H35 VCC[42] VCCIO[39] AF16 W50 VAXG[47]
H37 VCC[43] VCCIO[40] AF18 W51 VAXG[48]
x
1
10U/6.3V_6 10U/6.3V_6 H38 AF20 W52

H40 VCC[45] VCCIO[42] AG15 W53 VAXG[50]
10U/6.3V_6 10U/6.3V_6 J25 VCC[46] VCCIO[43] AG16 W55 VAXG[51]
2
J26 VCC[47] VCCIO[44] AG17 W56 VAXG[52]

J28 VCC[48] VCCIO[45] AG20 W61 VAXG[53]
J29 VCC[49] VCCIO[46] AG21 Y48 VAXG[54]
J32 VCC[50] VCCIO[47] AJ14 Y61 VAXG[55]
J34 VCC[51] VCCIO[48] AJ15 VAXG[56] Only BGA
fi
C150 C148 C146 C147 J35 VCC[52] VCCIO[49]
J37 VCC[53]
VCC[54]
1
10U/6.3V_6 10U/6.3V_6 J38 2 1

VCC[55] +VCC_GFX_CORE
J40 100_4 R63
VCC[56]
QUIET RAILS
10U/6.3V_6 10U/6.3V_6 J42 AM28
SENSE
LINES
+1.5V_CPU
2
K26 VCC[57] W16 VCC_AXG_SENSE F45 VCCDQ[1] AN26

VCC[58] VCCIO50 [51] VCC_AXG_SENSE VAXG_SENSE VCCDQ[2]
K27 W17 VSS_AXG_SENSE G45 C185 1 2 1U/6.3V_4
VCC[59] VCCIO51 [51] VSS_AXG_SENSE VSSAXG_SENSE
K29
K32 VCC[60] 2 1
K34 VCC[61] 100_4 R62
a
K35 VCC[62]
K37 VCC[63]
1.8V RAIL
K39 VCC[64]
K42 VCC[66] BC22 C483 C482 C481 BB3
VCC[67] VCCIO_SEL +1.8V_RUN VCCPLL[1]
L25 BC1
L28 VCC[68] BC4 VCCPLL[2]
VCC[69] CPU VCCPL VCCPLL[3]
1
L33
L36 VCC[70]
VCC[71] SNB: 1.2A
in
L40 10U/6.3V_6 1U/6.3V_4 1U/6.3V_4
IVY: 1.2A
2
N26 VCC[72] BC43
N30 VCC[73] AM25 VDDQ_SENSE BA43
QUIET
RAILS
VCC[74] VCCPQE[1] +1.05V_PCH 10uF x 1 VSS_SENSE_VDDQ
SENSE LINES
N34 AN22 1uF x 2
N38 VCC[75] VCCPQE[2] 1U/6.3V_4 L17
VCC[76] C169 1 2 L21 VCCSA[1]
N16 VCCSA[2]
N20 VCCSA[3]
B +VCCSA_CORE VCCSA[4] B
N22 1 2
SA RAIL
VCCSA[5] +VCCSA_CORE
1
C143 C141 C157 P17 R61 100_4
CPU SA P20 VCCSA[6] U10 VCCSA_SENSE
[50]
A44 H_CPU_SVIDALRT# R16 VCCSA[7] VCCSA_SENSE VCCSA_SENSE
SNB: 6A 10U/6.3V_6 10U/6.3V_6 1U/6.3V_4
2
VIDALERT# B43 VR_SVID_CLK R18 VCCSA[8]
VIDSCLK IVY: 6A VCCSA[9]
SVID
VIDSOUT
C44 VR_SVID_DATA
h 10uF x 3
R21
U15 VCCSA[10]
VCCSA VID
V16 VCCSA[11]
V17 VCCSA[12] D48 VCCSA_VID0
VCCSA[13] VCCSA_VID[0] VCCSA_VID0 [50]
lines
V18 D49 VCCSA_VID1
VCCSA[14] VCCSA_VID[1] VCCSA_VID1 [50]
V21
W20 VCCSA[15] VCCSA_VID0 1 2
VCCSA[16] R48 1K_4
1 2 VCCSA_VID1 1 2
.c
+VCC_CORE +1.05V_PCH
R50 100/F_4 R2551 2*1K_4_NC
F43 VCCSENSE R47 1K_4
VCC_SENSE VCCSENSE [51]
SENSE LINES
G43 VSSSENSE IC,IVB_2CBGA,0P7

VSS_SENSE VSSSENSE [51]
1 2
R51 100/F_4
1 2
+1.05V_PCH
R68 10_4
VCCIO_SENSE
AN16 VCCIO_SENSE
VCCIO_SENSE [49]
S3 Power reduce
AN17 VSSIO_SENSE
VSS_SENSE_VCCIO 1 2 VSSIO_SENSE [49] +1.5V_SUS +1.5V_CPU
+5V_ALW +15V_ALW
R69 10_4 5A
Take care Q3 Vgs(MAX)=2.5
1
Q16
w
R85 AON7410
IC,IVB_2CBGA,0P7 +1.5V_CPU +VDDR_REF_CPU 10K_4 R89 8 3
100K_4 7 2
6 1
2
PS_S3CNTRL 5
PS_S3CNTRL [13]
2
R78
4
1K/F_4
PS_S3CNTRL_S
w
6
A A
1
SIO_SLP_S3# 5 Q15A 2 Q15B
[19,38,47] SIO_SLP_S3#
2
DMN66D0LDW-7 DMN66D0LDW-7 C201
1
R77 0.1U/16V_4
Place PU resistor close to CPU
2
1K/F_4 C194
Place PU resistor close to CPU *4700P/25V_4_NC
Layout note: need routing
2
+1.05V_PCH +1.05V_PCH
together and ALERT need 1
SVID CLK SVID DATA SVID ALERT
between CLK and DATA
1
1
w
R249 R252 Quanta Computer Inc.

130_4 75/F_4
VR_SVID_CLK
VR_SVID_CLK [51] PROJECT :JWA
2
VR_SVID_DATA H_CPU_SVIDALRT# 1 2 VR_SVID_ALERT#

VR_SVID_DATA [51] VR_SVID_ALERT#[51]
R248 43_4 3A
Ivy Bridge 4/5
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix U18H
Ivy Bridge Processor (GND) Ivy Bridge Processor (RESERVED, CFG)
vina A13
VSS[1] VSS[91]
AM38
U18I U18E
A17 AM4
A21 VSS[2] VSS[92] AM42 BG17 M4 B50 N59
A25 VSS[3] VSS[93] AM45 BG21 VSS[181] VSS[250] M58 C51 CFG[0] BCLK_ITP N58
A28 VSS[4] VSS[94] AM48 BG24 VSS[182] VSS[251] M6 CFG2 B54 CFG[1] BCLK_ITP#
A33 VSS[5] VSS[95] AM58 BG28 VSS[183] VSS[252] N1 D53 CFG[2]
VSS[6] VSS[96] VSS[184] VSS[253] TP12 CFG[3]
A37 AN1 BG37 N17 CFG4 A51 N42
A40 VSS[7] VSS[97] AN21 BG41 VSS[185] VSS[254] N21 CFG5 C53 CFG[4] RSVD30 L42
A45 VSS[8] VSS[98] AN25 BG45 VSS[186] VSS[255] N25 CFG6 C55 CFG[5] RSVD31 L45
D D
A49 VSS[9] VSS[99] AN28 BG49 VSS[187] VSS[256] N28 H49 CFG[6] RSVD32 L47
VSS[10] VSS[100] VSS[188] VSS[257] TP11 CFG[7] RSVD33
A53 AN33 BG53 N33 A55
A9 VSS[11] VSS[101] AN36 BG9 VSS[189] VSS[258] N36 H51 CFG[8]
AA1 VSS[12] VSS[102] AN40 C29 VSS[190] VSS[259] N40 K49 CFG[9] M13
AA13 VSS[13] VSS[103] AN43 C35 VSS[191] VSS[260] N43 K53 CFG[10] RSVD34 M14
m
AA50 VSS[14] VSS[104] AN47 C40 VSS[192] VSS[261] N47 F53 CFG[11] RSVD35 U14
AA51 VSS[15] VSS[105] AN50 D10 VSS[193] VSS[262] N48 G53 CFG[12] RSVD36 W14
AA52 VSS[16] VSS[106] AN54 D14 VSS[194] VSS[263] N51 L51 CFG[13] RSVD37 P13
AA53 VSS[17] VSS[107] AP10 D18 VSS[195] VSS[264] N52 F51 CFG[14] RSVD38
AA55 VSS[18] VSS[108] AP51 D22 VSS[196] VSS[265] N56 D52 CFG[15]
AA56 VSS[19] VSS[109] AP55 D26 VSS[197] VSS[266] N61 L53 CFG[16] AT49
AA8 VSS[20] VSS[110] AP7 D29 VSS[198] VSS[267] P14 CFG[17] RSVD39 K24
AB16 VSS[21] VSS[111] AR13 D35 VSS[199] VSS[268] P16 RSVD40
o
VSS[22] VSS[112] VSS[200] VSS[269]
RESERVED
AB18 AR17 D4 P18 H43
VSS[23] VSS[113] VSS[201] VSS[270] TP18 VCC_VAL_SENSE
AB21 AR21 D40 P21 K43 AH2
VSS[24] VSS[114] VSS[202] VSS[271] TP17 VSS_VAL_SENSE RSVD41
AB48 AR41 D43 P58 AG13
AB61
AC10
VSS[25]
VSS[26]
VSS[27]
VSS[115]
VSS[116]
VSS[117]
AR48
AR61
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
TP16
H45
VAXG_VAL_SENSE
RSVD42
RSVD43
RSVD44
AM14
AM15
.c
AC14 AR7 D54 R17 K45
VSS[28] VSS[118] VSS[206] VSS[275] TP15 VSSAXG_VAL_SENSE
AC46 AT14 D58 R20
AC6 VSS[29] VSS[119] AT19 D6 VSS[207] VSS[276] R4 N50
AD17 VSS[30] VSS[120] AT36 E25 VSS[208] VSS[277] R46 F48 RSVD45
AD20 VSS[31] VSS[121] AT4 E29 VSS[209] VSS[278] T1 G48 VCC_DIE_SENSE
AD4 VSS[32] VSS[122] AT45 E3 VSS[210] VSS[279] T47 RSVD47
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
E35
E40
VSS[211]
VSS[212]
VSS[213]
VSS[280]
VSS[281]
VSS[282]
T50
T51
H48
K48 RSVD6
RSVD7
AE8 AU1 F13 T52 A4
AF1 VSS[36] VSS[126] AU11 F15 VSS[214] VSS[283] T53 DC_TEST_A4 C4
x
C AF17 VSS[37] VSS[127] AU28 F19 VSS[215] VSS[284] T55 BA19 DC_TEST_C4 D3 C
AF21 VSS[38] VSS[128] AU32 F29 VSS[216] VSS[285] T56 AV19 RSVD8 DC_TEST_D3 D1
AF47 VSS[39] VSS[129] AU51 F35 VSS[217] VSS[286] U13 AT21 RSVD9 DC_TEST_D1 A58
AF48 VSS[40] VSS[130] AU7 F40 VSS[218] VSS[287] U8 BB21 RSVD10 DC_TEST_A58 A59
AF50 VSS[41] VSS[131] AV17 F55 VSS[219] VSS[288] V20 BB19 RSVD11 DC_TEST_A59 C59
VSS[42] VSS[132] VSS[220] VSS[289] RSVD12 DC_TEST_C59
fi
AF51 AV21 G51 V61 AY21 A61
AF52 VSS[43] VSS[133] AV22 G6 VSS[221] VSS[290] W13 BA22 RSVD13 DC_TEST_A61 C61
AF53 VSS[44] VSS[134] AV34 G61 VSS[222] VSS[291] W15 AY22 RSVD14 DC_TEST_C61 D61
AF55 VSS[45] VSS[135] AV40 H10 VSS[223] VSS[292] W18 AU19 RSVD15 DC_TEST_D61 BD61
AF56 VSS[46] VSS[136] AV48 H14 VSS[224] VSS[293] W21 AU21 RSVD16 DC_TEST_BD61 BE61
AF58 VSS[47] VSS[137] AV55 H17 VSS[225] VSS[294] W46 BD21 RSVD17 DC_TEST_BE61 BE59
AF59 VSS[48] VSS[138] AW13 H21 VSS[226] VSS[295] W8 BD22 RSVD18 DC_TEST_BE59 BG61
AG10 VSS[49] VSS[139] AW43 H4 VSS[227] VSS[296] Y4 BD25 RSVD19 DC_TEST_BG61 BG59
a
AG14 VSS[50] VSS[140] AW61 H53 VSS[228] VSS[297] Y47 BD26 RSVD20 DC_TEST_BG59 BG58
AG18 VSS[51] VSS[141] AW7 H58 VSS[229] VSS[298] Y58 BG22 RSVD21 DC_TEST_BG58 BG4
AG47 VSS[52] VSS[142] AY14 J1 VSS[230] VSS[299] Y59 BE22 RSVD22 DC_TEST_BG4 BG3
AG52 VSS[53] VSS[143] AY19 J49 VSS[231] VSS[300] BG26 RSVD23 DC_TEST_BG3 BE3
AG61 VSS[54] VSS[144] AY30 J55 VSS[232] BE26 RSVD24 DC_TEST_BE3 BG1
VSS[55] VSS[145] VSS[233] RSVD25 DC_TEST_BG1
in
AG7 AY36 K11 BF23 BE1
AH4 VSS[56] VSS[146] AY4 K21 VSS[234] BE24 RSVD26 DC_TEST_BE1 BD1
AH58 VSS[57] VSS[147] AY41 K51 VSS[235] RSVD27 DC_TEST_BD1
AJ13 VSS[58] VSS[148] AY45 K8 VSS[236] A5
AJ16 VSS[59] VSS[149] AY49 L16 VSS[237] VSS_NCTF_1 A57
AJ20 VSS[60] VSS[150] AY55 L20 VSS[238] VSS_NCTF_2 BC61
AJ22 VSS[61] VSS[151] AY58 L22 VSS[239] VSS_NCTF_3 BD3 IC,IVB_2CBGA,0P7
AJ26 VSS[62] VSS[152] AY9 L26 VSS[240] VSS_NCTF_4 BD59
AJ30 VSS[63] VSS[153] BA1 L30 VSS[241] VSS_NCTF_5 BE4
NCTF
AJ34 VSS[64] VSS[154] BA11 L34 VSS[242] VSS_NCTF_6 BE58

B
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
BA17
BA21
BA26
BA32
BA48
BA51
L38
L43
L48
L61
M11
M15
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
h
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
BG5
BG57
C3
C58
D59
E1
B
.c
AK52 VSS[71] VSS[161] BB53 VSS[249] VSS_NCTF_13 E61
AL10 VSS[72] VSS[162] BC13 VSS_NCTF_14
AL13 VSS[73] VSS[163] BC5
AL17 VSS[74] VSS[164] BC57
AL21 VSS[75] VSS[165] BD12
AL25 VSS[76] VSS[166] BD16
AL28 VSS[77] VSS[167] BD19 IC,IVB_2CBGA,0P7
AL33 VSS[78] VSS[168] BD23
AL36 VSS[79] VSS[169] BD27 CFG[6:5] (PCIE Port Bifurcation Straps)
w
AL40 VSS[80] VSS[170] BD32

AL43 VSS[81] VSS[171] BD36
VSS[82] VSS[172]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AL47 BD40 CFG5 2 1 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
AL61 VSS[83] VSS[173] BD44 CFG6 R2542 1*1K_4_NC
AM13 VSS[84] VSS[174] BD48 R45 *1K_4_NC
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
AM20 VSS[85] VSS[175] BD52 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AM22 VSS[86] VSS[176] BD56
w
AM26 VSS[87] VSS[177] BD8

AM30 VSS[88] VSS[178] BE5
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180]
The CFG signals have a default value of '1' if not terminated on the board.
Processor Strapping CFG2 2 1
R253 *1K_4_NC
1 0
w
A A
IC,IVB_2CBGA,0P7 CFG2 CFG4 2 1
R49 *1K_4_NC
(PEG Static Lane Reversal) Normal Operation Lane Reversed
CFG4
Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP
(DP Presence Strap) Quanta Computer Inc.
PROJECT : JWA
3A
Ivy Bridge 5/5
1
10 of 54
1 2 3 4 5 6 7 8
f ix
DDR3 TERMINATION FOR MEMORY DOWN
ina
M_A_DQ[15:0] [8] M_A_DQ[31:16] [8]
v
Please these resistor D0 D1
closely DIMMA,all +0.75V_DDR_VTT U9 U8
trace length<750 mil. [8,12] M_A_A[15:0]
M_A_A0 N3 E3 M_A_DQ6 M_A_A0 N3 E3 M_A_DQ23
16
M_A_A1 P7 A0 DQL0 F7 M_A_DQ1 M_A_A1 P7 A0 DQL0 F7 M_A_DQ21
M_A_A1 36X4 2 1 RN4 M_A_A3 N2 A2 DQL2 F8 M_A_DQ5 M_A_A3 N2 A2 DQL2 F8 M_A_DQ16
M_A_A2 4 3 M_A_A4 P8 A3 DQL3 H3 M_A_DQ7 M_A_A4 P8 A3 DQL3 H3 M_A_DQ19
M_A_A5 6 5 M_A_A5 P2 A4 DQL4 H8 M_A_DQ0 M_A_A5 P2 A4 DQL4 H8 M_A_DQ17
M_A_BS#1 8 7 M_A_A6 R8 A5 DQL5 G2 M_A_DQ3 M_A_A6 R8 A5 DQL5 G2 M_A_DQ22
M_A_A7 R2 A6 DQL6 H7 M_A_DQ4 M_A_A7 R2 A6 DQL6 H7 M_A_DQ20
A A
M_A_A13 36X4 2 1 RN5 M_A_A8 T8 A7 DQL7 D7 M_A_DQ12 M_A_A8 T8 A7 DQL7 D7 M_A_DQ30
M_A_A11 4 3 M_A_A9 R3 A8 DQU0 C3 M_A_DQ10 M_A_A9 R3 A8 DQU0 C3 M_A_DQ25
M_A_A9 6 5 M_A_A10 L7 A9 DQU1 C8 M_A_DQ9 M_A_A10 L7 A9 DQU1 C8 M_A_DQ29
M_A_A4 8 7 M_A_A11 R7 A10/AP DQU2 C2 M_A_DQ11 M_A_A11 R7 A10/AP DQU2 C2 M_A_DQ27
M_A_A12 N7 A11 DQU3 A7 M_A_DQ13 M_A_A12 N7 A11 DQU3 A7 M_A_DQ24
m
M_A_A3 36X4 2 1 RN3 A12/BC DQU4 A2 M_A_DQ14 A12/BC DQU4 A2 M_A_DQ26
M_A_A12 4 3 M_A_A13 T3 DQU5 B8 M_A_DQ8 M_A_A13 T3 DQU5 B8 M_A_DQ28
M_A_A0 6 5 M_A_A14 T7 A13 DQU6 A3 M_A_DQ15 M_A_A14 T7 A13 DQU6 A3 M_A_DQ31
M_A_BS#2 8 7 M_A_A15 M7 A14 DQU7 M_A_A15 M7 A14 DQU7
A15 A15
M_A_A8 36X4 2 1 RN6
M_A_A6 4 3 [8,12] M2 C7 [8] M_A_BS#0 M2 C7 [8]
M_A_BS#0 BA0 DQSU M_A_DQSP1 BA0 DQSU M_A_DQSP3
6 5 N8 F3 N8 F3
o
M_A_A7 [8,12] [8] M_A_BS#1 [8]
M_A_BS#1 BA1 DQSL M_A_DQSP0 BA1 DQSL M_A_DQSP2
M_A_A14 8 7 [8,12] M3 B7 [8] M_A_BS#2 M3 B7 [8]
M_A_BS#2 BA2 DQSU# M_A_DQSN1 BA2 DQSU# M_A_DQSN3
[8,12] L2 G3 [8] M_A_CS#0 L2 G3 [8]
M_A_CS#0 CS# DQSL# M_A_DQSN0 CS# DQSL# M_A_DQSN2
M_A_CS#0 36X4 2 1 [8,12] J7 M_A_CLKP0 J7
M_A_CLKP0 CK CK
M_A_ODT0 4 3 RN2 [8,12] K7 D3 M_A_CLKN0 K7 D3
M_A_CLKN0 CK# DMU CK# DMU
M_A_A10 6 5 [8,12] K9 E7 M_A_CKE0 K9 E7
M_A_CKE0 CKE DML CKE DML
.c
M_A_BS#0 8 7 [8,12] K3 M_A_CAS# K3
M_A_CAS# CAS# CAS#
[8,12] J3 M_A_RAS# J3
M_A_RAS# RAS# RAS#
M_A_W E# 36X4 2 1 RN1 [8,12] L3 M_A_W E# L3
M_A_W E# WE# WE#
M_A_CAS# 4 3
M_A_RAS# 6 5 [8,12] K1 M_A_ODT0 K1
M_A_ODT0 ODT ODT
M_A_CKE0 8 7
M_A_A15 R133 36/F_4
x
B B
+1.5V_SUS B2 A9 +1.5V_SUS B2 A9
M_A_CLKP0 D9 VDD#B2 VSS#A9 B3 D9 VDD#B2 VSS#A9 B3
G7 VDD#D9 VSS#B3 E1 G7 VDD#D9 VSS#B3 E1
K2 VDD#G7 VSS#E1 G8 K2 VDD#G7 VSS#E1 G8
VDD#K2 VSS#G8 VDD#K2 VSS#G8
fi
R110 K8 J2 K8 J2
N1 VDD#K8 VSS#J2 J8 N1 VDD#K8 VSS#J2 J8
30.1/F_4 N9 VDD#N1 VSS#J8 M1 N9 VDD#N1 VSS#J8 M1
R1 VDD#N9 VSS#M1 M9 R1 VDD#N9 VSS#M1 M9
C297 R9 VDD#R1 VSS#M9 P1 R9 VDD#R1 VSS#M9 P1
1.8P/50V_4 VDD#R9 VSS#P1 P9 VDD#R9 VSS#P1 P9
A1 VSS#P9 T1 A1 VSS#P9 T1
C235 A8 VDDQ#A1 VSS#T1 T9 A8 VDDQ#A1 VSS#T1 T9
a
R114 0.1U/10V_4 C1 VDDQ#A8 VSS#T9 C1 VDDQ#A8 VSS#T9
C9 VDDQ#C1 B1 C9 VDDQ#C1 B1
30.1/F_4 D2 VDDQ#C9 VSSQ#B1 B9 D2 VDDQ#C9 VSSQ#B1 B9
E9 VDDQ#D2 VSSQ#B9 D1 E9 VDDQ#D2 VSSQ#B9 D1
M_A_CLKN0 F1 VDDQ#E9 VSSQ#D1 D8 F1 VDDQ#E9 VSSQ#D1 D8
VDDQ#F1 VSSQ#D8 VDDQ#F1 VSSQ#D8
in
H2 E2 H2 E2
H9 VDDQ#H2 VSSQ#E2 E8 H9 VDDQ#H2 VSSQ#E2 E8
VDDQ#H9 VSSQ#E8 F9 VDDQ#H9 VSSQ#E8 F9
VSSQ#F9 G1 VSSQ#F9 G1
VSSQ#G1 G9 VSSQ#G1 G9
+0.75V_DDR_VTT +0.75V_DDR_VTT +0.75V_DDR_VTT H1 VSSQ#G9 H1 VSSQ#G9
+M_VREF_DQ_MD VREFDQ +M_VREF_DQ_MD VREFDQ
+M_VREF_CA_MD M8 +M_VREF_CA_MD M8
VREFCA VREFCA
J1 T2 J1 T2 DDR3_DRAMRST#
NC#J1 RESET# DDR3_DRAMRST#[7,12,13] NC#J1 RESET#
C288 C257 L1 C298 C258 L1
C
C212 C239 C322 C268 C282 C307
0.1U/10V_4
0.1U/10V_4
J9
L9
NC#L1
NC#J9
NC#L9 96-BALL
h ZQ
L8 DDR_ZQ1 0.1U/10V_4
0.1U/10V_4
J9
L9
NC#L1
NC#J9
NC#L9 96-BALL
ZQ
L8 DDR_ZQ2
C
2
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 SDRAM DDR3 SDRAM DDR3
R127 R139
H5TC4G63AFR-11C H5TC4G63AFR-11C
.c
240/F_4 240/F_4
bga96-samsung-k4b4g1646b-hck0 bga96-samsung-k4b4g1646b-hck0
1
+1.5V_SUS
+1.5V_SUS +M_VREF_DQ_MD +1.5V_SUS +M_VREF_CA_MD

w
C306 C226 C227 C244 C270 C264 C219 C233

R146 R141 1U/10V_6 1U/10V_6 1U/10V_6 1U/10V_6 1U/10V_6 1U/10V_6 1U/10V_6 1U/10V_6
1K/F_4 1K/F_4
+1.5V_SUS
w
R129
1
1
R131
1K/F_4 C251 C265 C223 C230 C243 C245 C314 C232
1K/F_4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
2
2
w
D D

PROJECT : JWA
Hynix: Vendor PN is H5TC4G63AFR-11C. Quanta buy QPN is AKD5PGWTW05. Size Document Number Rev
3A
DDR3 (A) On Board_A,1Rank
7
Sheet 11
8
of 54
5 4 3 2 1
fix
vina 17
D D
M_A_DQ[63:48] [8]
M_A_DQ[47:32] [8]
D3
m
D2 U10
[8,11] U11 M_A_A0 N3 E3 M_A_DQ57
M_A_A[15:0] A0 DQL0
M_A_A0 N3 E3 M_A_DQ44 M_A_A1 P7 F7 M_A_DQ59
M_A_A2 P3 A1 DQL1 F2 M_A_DQ40 M_A_A3 N2 A2 DQL2 F8 M_A_DQ63
M_A_A3 N2 A2 DQL2 F8 M_A_DQ45 M_A_A4 P8 A3 DQL3 H3 M_A_DQ60
P8 A3 DQL3 H3 P2 A4 DQL4 H8
o
M_A_A4 M_A_DQ41 M_A_A5 M_A_DQ62
M_A_A5 P2 A4 DQL4 H8 M_A_DQ47 M_A_A6 R8 A5 DQL5 G2 M_A_DQ56
M_A_A6 R8 A5 DQL5 G2 M_A_DQ42 M_A_A7 R2 A6 DQL6 H7 M_A_DQ58
M_A_A7 R2 A6 DQL6 H7 M_A_DQ43 M_A_A8 T8 A7 DQL7 D7 M_A_DQ52
M_A_A8 T8 A7 DQL7 D7 M_A_DQ36 M_A_A9 R3 A8 DQU0 C3 M_A_DQ54
M_A_A9 R3 A8 DQU0 C3 M_A_DQ34 M_A_A10 L7 A9 DQU1 C8 M_A_DQ48
A9 DQU1 A10/AP DQU2
.c
M_A_A10 L7 C8 M_A_DQ37 M_A_A11 R7 C2 M_A_DQ50
M_A_A11 R7 A10/AP DQU2 C2 M_A_DQ38 M_A_A12 N7 A11 DQU3 A7 M_A_DQ53
M_A_A12 N7 A11 DQU3 A7 M_A_DQ33 A12/BC DQU4 A2 M_A_DQ55
A12/BC DQU4 A2 M_A_DQ39 M_A_A13 T3 DQU5 B8 M_A_DQ49
M_A_A13 T3 DQU5 B8 M_A_DQ32 M_A_A14 T7 A13 DQU6 A3 M_A_DQ51
M_A_A14 T7 A13 DQU6 A3 M_A_DQ35 M_A_A15 M7 A14 DQU7
M_A_A15 M7 A14 DQU7 A15
A15
M_A_BS#0 M2 C7 [8]
M2 C7 M_A_BS#1 N8 BA0 DQSU F3 M_A_DQSP6
x
[8,11] M_A_BS#0 BA0 DQSU M_A_DQSP4 [8] BA1 DQSL M_A_DQSP7 [8]
C
[8,11] N8 F3 [8] M_A_BS#2 M3 B7 [8]
C
M_A_BS#1 BA1 DQSL M_A_DQSP5 BA2 DQSU# M_A_DQSN6
[8,11] M3 B7 [8] M_A_CS#0 L2 G3 [8]
M_A_BS#2 BA2 DQSU# M_A_DQSN4 CS# DQSL# M_A_DQSN7
[8,11] L2 G3 [8] M_A_CLKP0 J7
M_A_CS#0 CS# DQSL# M_A_DQSN5 CK
[8,11] J7 M_A_CLKN0 K7 D3
M_A_CLKP0 CK CK# DMU
[8,11] K7 D3 M_A_CKE0 K9 E7
M_A_CLKN0 CK# DMU CKE DML
fi
[8,11] K9 E7 M_A_CAS# K3
M_A_CKE0 CKE DML CAS#
[8,11] K3 M_A_RAS# J3
M_A_CAS# CAS# RAS#
[8,11] J3 M_A_W E# L3
M_A_RAS# RAS# WE#
[8,11] L3
M_A_W E# WE# M_A_ODT0 K1
K1 ODT
[8,11] M_A_ODT0 ODT
a
+1.5V_SUS B2 A9
B2 A9 D9 VDD#B2 VSS#A9 B3
+1.5V_SUS VDD#B2 VSS#A9 VDD#D9 VSS#B3
in
D9 B3 G7 E1
G7 VDD#D9 VSS#B3 E1 K2 VDD#G7 VSS#E1 G8
K2 VDD#G7 VSS#E1 G8 K8 VDD#K2 VSS#G8 J2
K8 VDD#K2 VSS#G8 J2 N1 VDD#K8 VSS#J2 J8
N1 VDD#K8 VSS#J2 J8 N9 VDD#N1 VSS#J8 M1
N9 VDD#N1 VSS#J8 M1 R1 VDD#N9 VSS#M1 M9
R1 VDD#N9 VSS#M1 M9 R9 VDD#R1 VSS#M9 P1
R9 VDD#R1 VSS#M9 P1 VDD#R9 VSS#P1 P9
VDD#R9 VSS#P1 P9 A1 VSS#P9 T1
A1 VSS#P9 T1 A8 VDDQ#A1 VSS#T1 T9
B
A8
C1
C9
D2
E9
F1
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
T9
B1
B9
D1
D8
h C1
C9
D2
E9
F1
H2
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
B1
B9
D1
D8
E2
B
.c
H2 VDDQ#F1 VSSQ#D8 E2 H9 VDDQ#H2 VSSQ#E2 E8
H9 VDDQ#H2 VSSQ#E2 E8 VDDQ#H9 VSSQ#E8 F9
VDDQ#H9 VSSQ#E8 F9 VSSQ#F9 G1
VSSQ#F9 G1 VSSQ#G1 G9
VSSQ#G1 G9 H1 VSSQ#G9
VSSQ#G9 +M_VREF_DQ_MD VREFDQ
+M_VREF_DQ_MD H1 +M_VREF_CA_MD M8
M8 VREFDQ VREFCA
+M_VREF_CA_MD VREFCA J1 T2 DDR3_DRAMRST#
J1 T2 C273 C252 L1 NC#J1 RESET#
w
NC#J1 RESET# DDR3_DRAMRST#[7,11,13] NC#L1

C295 C253 L1 0.1U/10V_4 J9 L8 DDR_ZQ4
0.1U/10V_4 J9 NC#L1 L8 DDR_ZQ3 0.1U/10V_4 L9 NC#J9 ZQ
0.1U/10V_4 L9 NC#J9 ZQ NC#L9 96-BALL
NC#L9 96-BALL
2
SDRAM DDR3
2
SDRAM DDR3 R140

R130 H5TC4G63AFR-11C 240/F_4
H5TC4G63AFR-11C 240/F_4 bga96-samsung-k4b4g1646b-hck0
w
bga96-samsung-k4b4g1646b-hck0
1
1
w
A A

PROJECT : JWA
3A
DDR3 (A) On Board_B,1Rank
1
12 of 54
1 2 3 4 5 6 7 8
fix
vina [8] M_B_A[15..0]
M_B_A0 98
JDIM1A
A0 DQ0
5 M_B_DQ1
M_B_DQ[63..0] [8] +1.5V_SUS
M_B_A1 97 7 M_B_DQ0
M_B_A2 96 A1 DQ1 15 M_B_DQ3 JDIM1B
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
95
92
91
90
86
A2
A3
A4
A5
A6
DQ2
DQ3
DQ4
DQ5
DQ6
17
4
6
16
18
M_B_DQ2
M_B_DQ5
M_B_DQ4
M_B_DQ6
M_B_DQ7
H=4mm,RVS 75
76
81
82
87
VDD1
VDD2
VDD3
VDD4
VSS16
VSS17
VSS18
VSS19
44
48
49
54
55
M_B_A8 89 A7 DQ7 21 M_B_DQ9 88 VDD5 VSS20 60
A A
M_B_A11 84 A10/AP DQ10 35 M_B_DQ10 99 VDD8 VSS23 66
M_B_A13 119 A12/BC# DQ12 24 M_B_DQ12 105 VDD10 VSS25 72
m
M_B_A14 80 A13 DQ13 34 M_B_DQ11 +3.3V_RUN 106 VDD11 VSS26 127
A14 DQ14 VDD12 VSS27
PC2100 DDR3 SDRAM SO-DIMM

M_B_A15 78 36 M_B_DQ15 111 128
A15 DQ15 39 M_B_DQ20 112 VDD13 VSS28 133
DQ16 VDD14 VSS29
PC2100 DDR3 SDRAM SO-DIMM

[8] M_B_BS#0 109 41 M_B_DQ17 117 134
M_B_BS#0 BA0 DQ17 VDD15 VSS30
[8] M_B_BS#1 108 51 M_B_DQ19 118 138
[8] M_B_BS#2 79 53 M_B_DQ23 123 139
1
[8] M_B_CS#0 114 40 M_B_DQ21 124 144
M_B_CS#0 S0# DQ20 VDD18 VSS33
121 42 145
o
[8] M_B_CS#1 M_B_DQ16 C221
M_B_CS#1 S1# DQ21 VSS34
[8] M_B_CLKP0 101 50 M_B_DQ18 0.1U/16V_4 199 150
M_B_CLKP0
2
M_B_CLKN0 103 CK0 DQ22 52 M_B_DQ22 VDDSPD VSS35 151
[8] M_B_CLKN0 CK0# DQ23 VSS36
[8] M_B_CLKP1 102 57 M_B_DQ29 77 155
M_B_CLKP1 CK1 DQ24 NC1 VSS37
[8] M_B_CLKN1 104 59 M_B_DQ25 122 156
M_B_CLKN1 CK1# DQ25 NC2 VSS38
[8] M_B_CKE0 73 67 M_B_DQ27 125 161
M_B_CKE0 CKE0 DQ26 NCTEST VSS39
.c
[8] M_B_CKE1 74 69 M_B_DQ26 162
M_B_CKE1 CKE1 DQ27 VSS40
[8] M_B_CAS# 115 56 M_B_DQ28 +3.3V_RUN R101 1 2 *10K_4_NC 198 167
M_B_CAS# CAS# DQ28 EVENT# VSS41
[8] M_B_RAS# 110 58 M_B_DQ24 [7,11,12] DDR3_DRAMRST# 30 168
M_B_RAS# RAS# DQ29 DDR3_DRAMRST# RESET# VSS42
[8] M_B_W E# 113 68 M_B_DQ31 172
M_B_W E# WE# DQ30 VSS43
R112 1 2 10K_4 DIMM1_SA0 197 70 M_B_DQ30 173
R111 1 2 10K_4 DIMM1_SA1 201 SA0 DQ31 129 M_B_DQ36 1 VSS44 178
SA1 DQ32 +SMDDR_VREF_DQ1 VREF_DQ VSS45
+3.3V_RUN [23,40] SMBCLK 202 131 M_B_DQ37 126 179
SMBCLK SCL DQ33 +SMDDR_VREF_DIMM1 VREF_CA VSS46
[23,40] SMBDATA 200 141 M_B_DQ35 184
SMBDATA SDA DQ34 143 M_B_DQ34 VSS47 185
M_B_ODT0 116 DQ35 130 M_B_DQ33 2 VSS48 189
x
[8] M_B_ODT0 ODT0 DQ36 VSS1 VSS49
B
[8] M_B_ODT1 120 132 M_B_DQ32 3 190 B
M_B_ODT1 ODT1 DQ37 VSS2 VSS50
140 M_B_DQ39 8 195
11 DQ38 142 M_B_DQ38 9 VSS3 VSS51 196
(204P)
SO-DIMMB SPD Address is 0XA4 28 DM0 DQ39 147 M_B_DQ40 13 VSS4 VSS52
46 DM1 DQ40 149 M_B_DQ44 14 VSS5
SO-DIMMB TS Address is 0X34 DM2 DQ41 VSS6
fi
63 157 M_B_DQ42 19
(204P)
136 DM3 DQ42 159 M_B_DQ43 20 VSS7
153 DM4 DQ43 146 M_B_DQ45 S3 Power reduce 25 VSS8
170 DM5 DQ44 148 M_B_DQ41 26 VSS9 203
DM6 DQ45 VSS10 VTT1 +0.75V_DDR_VTT
187 158 M_B_DQ46 31 204
DM7 DQ46 160 M_B_DQ47 +0.75V_DDR_VTT 32 VSS11 VTT2
[8] M_B_DQSP[7..0] DQ47 VSS12
M_B_DQSP0 12 163 M_B_DQ49 37
M_B_DQSP1 29 DQS0 DQ48 165 M_B_DQ48 38 VSS13
a
M_B_DQSP2 47 DQS1 DQ49 175 M_B_DQ54 43 VSS14
GND
GND
M_B_DQSP3 64 DQS2 DQ50 177 M_B_DQ55 VSS15
DQS3 DQ51
2
M_B_DQSP4 137 164 M_B_DQ52 R98
M_B_DQSP5 154 DQS4 DQ52 166 M_B_DQ53 22_4 DDR3-DIMM1
205
206
M_B_DQSP6 171 DQS5 DQ53 174 M_B_DQ50
DQS6 DQ54
in
[8] M_B_DQSP7 188 176 M_B_DQ51
M_B_DQSN[7..0] M_B_DQSN0 10 DQS7 DQ55 181 M_B_DQ61
1
M_B_DQSN1 27 DQS#0 DQ56 183 M_B_DQ56
M_B_DQSN4 135 DQS#3 DQ59 180 M_B_DQ57 Q18
DQS#4 DQ60
3
M_B_DQSN5 152 182 M_B_DQ60
M_B_DQSN6 169 DQS#5 DQ61 192 M_B_DQ58 2 PS_S3CNTRL
DQS#6 DQ62 PS_S3CNTRL [9]
M_B_DQSN7 186 194 M_B_DQ59
DQS#7 DQ63
h
1
2N7002W
C DDR3-DIMM1 C
Place these Caps near So-Dimm1.

.c
+1.5V_SUS +0.75V_DDR_VTT
1
C209 C317 C222 C204 C206 C208 C228 C224 C234 C220 C215 EC33 EC29
M1 VREF
0.1U/16V_4 0.1U/16V_4 10U/6.3V_6 10U/6.3V_6 1U/6.3V_4 *1U/6.3V_4_NC
2
0.1U/16V_4 0.1U/16V_4 10U/6.3V_6 *10U/6.3V_6_NC 10U/6.3V_8 1U/6.3V_4 *1U/6.3V_4_NC

w
+1.5V_SUS
2 +SMDDR_VREF_DQ1 +1.5V_SUS +SMDDR_VREF_DIMM1
2
R108 R97
1K/F_4 1K/F_4
w
1
C207 C217
2
2
C225 C231
1
1
R109 R99
1K/F_4 1K/F_4
w
1U/10V_6 1U/10V_6
2
2
D D
1
1
0.1U/16V_4 0.1U/16V_4

PROJECT : JWA
3A
DDR3 DIMM-1
7
Sheet 13
8
of 54
5 4 3 2 1
fix
vina
U16A
+1.05V_GFX
1/14 PCI_EXPRESS
Near GPU
C401 22U/6.3VS_6
C31 22U/6.3VS_6 PEX_WAKE AB6 NVDD = 32.22 ~ 26.66 A +VCC_DGFX_CORE
D D
C402 4.7U/6.3V_6
C26 4.7U/6.3V_6 AA22 PEX_IOVDD Under GPU U16E
C404 4.7U/6.3V_6 AB23 PEX_IOVDD PEX_RST AC7 GPU_RST# 11/14 NVVDD
AC24 PEX_IOVDD C37 0.1U/10V_4 K10 VDD
AD25 AC6 PEX_CLKREQ# C65 0.1U/10V_4 K12
C28 1U/6.3V_4 AE26
PEX_IOVDD
PEX_IOVDD
PEX_CLKREQ
C54 0.1U/10V_4 K14
VDD
VDD U16C VDD33 = 56mA
C4 1U/6.3V_4 AE27 PEX_IOVDD PEX_REFCLK AE8 C42 0.1U/10V_4 K16 VDD 14/14 XVDD/VDD33
CLK_PCIE_VGAP [23]
m
PEX_REFCLK AD8 C61 0.1U/10V_4 K18 VDD
CLK_PCIE_VGAN[23] L11 AD10 G10
Under GPU C51 4.7U/6.3V_6 VDD NC VDD33 +3V_GFX
PEX_TX0 AC9 C_PEG_RX0 C423 1 2 0.1U/16V_4 [6] C62 4.7U/6.3V_6 L13 VDD AD7 NC VDD33 G12
PEG_RXP0
AB9 C_PEG_RX#0 C405 1 2 0.1U/16V_4 C38 4.7U/6.3V_6 L15 B19 G8
PEX_IOVDD + PEX_IOVDDQ = 1.042A PEX_TX0 PEG_RXN0 [6]
C43 4.7U/6.3V_6 L17
VDD
VDD
NC VDD33
VDD33 G9
PEX_RX0 AG6 [6] C63 4.7U/6.3V_6 M10 VDD
PEG_TXP0
+1.05V_GFX AA10 PEX_IOVDDQ PEX_RX0 AG7 [6] C40 4.7U/6.3V_6 M12 VDD F11 3V3AUX_NC Near GPU
PEG_TXN0
C12 22U/6.3VS_6 AA12 PEX_IOVDDQ C56 4.7U/6.3V_6 M14 VDD C35 4.7U/6.3V_6
C11 22U/6.3VS_6 AA13 PEX_IOVDDQ PEX_TX1 AB10 C_PEG_RX1 C409 1 2 0.1U/16V_4 [6] C44 4.7U/6.3V_6 M16 VDD V5 FERMI_RSVD1_NC C427 1 2 2.2U/10V_6
PEG_RXP1
C10 4.7U/6.3V_6 AA16 PEX_IOVDDQ PEX_TX1 AC10 C_PEG_RX#1 C408 1 2 0.1U/16V_4 [6] C58 4.7U/6.3V_6 M18 VDD V6 FERMI_RSVD2_NC
PEG_RXN1
C13 4.7U/6.3V_6 AA18 C50 4.7U/6.3V_6 N11
o
PEX_IOVDDQ VDD
C403 4.7U/6.3V_6 AA19 PEX_IOVDDQ PEX_RX1 AF7 [6]
N13 VDD C70 0.1U/10V_4
PEG_TXP1
AA20 PEX_IOVDDQ PEX_RX1 AE7 [6] N15 VDD C72 0.1U/10V_4
PEG_TXN1
Near GPU AA21 PEX_IOVDDQ N17 VDD C32 0.1U/10V_4
AB22 PEX_IOVDDQ PEX_TX2 AD11 C_PEG_RX2 C421 1 2 0.1U/16V_4 [6] P10 VDD CONFIGURABLE C69 0.1U/10V_4
PEG_RXP2
AC23 PEX_IOVDDQ PEX_TX2 AC11 C_PEG_RX#2 C420 1 2 0.1U/16V_4 [6] P12 VDD POWER CHANNELS
AD24 PEG_RXN2 P14
PEX_IOVDDQ VDD * nc on substrate Under GPU
Under GPU AE25 PEX_IOVDDQ PEX_RX2 AE9 [6] P16 VDD
PEG_TXP2
.c
C27 1U/6.3V_4 AF26 PEX_IOVDDQ PEX_RX2 AF9 [6] P18 VDD G1 XPWR_G1
PEG_TXN2
C30 1U/6.3V_4 AF27 PEX_IOVDDQ R11 VDD G2 XPWR_G2
PEX_TX3 AC12 C_PEG_RX3 C418 1 2 0.1U/16V_4 [6] R13 VDD G3 XPWR_G3
PEG_RXP3
PEX_TX3 AB12 C_PEG_RX#3 C419 1 2 0.1U/16V_4 [6] C48 10U/6.3V_6 R15 VDD G4 XPWR_G4
PEG_RXN3
C431 10U/6.3V_8 R17 VDD G5 XPWR_G5
PEX_RX3 AG9 [6] C434 4.7U/6.3V_6 T10 VDD G6 XPWR_G6
PEG_TXP3
PEX_RX3 AG10 [6] C46 4.7U/6.3V_6 T12 VDD G7 XPWR_G7
PEG_TXN3
C47 4.7U/6.3V_6 T14 VDD
PEX_TX4 AB13 C_PEG_RX4 C7 1 2 0.1U/16V_4 [6] C433 4.7U/6.3V_6 T16 VDD
AC13 C_PEG_RX#4 C6 1 2 0.1U/16V_4 PEG_RXP4 T18 V1
PEX_TX4 [6] C45 4.7U/6.3V_6 VDD XPWR_V1
PEG_RXN4
U11 V2
C
PEX_PLL_HVDD + PEX_RX4 AF10 [6] Near GPU U13
VDD
VDD
XPWR_V2
C
PEG_TXP4
PEX_SVDD_3V3 = 143mA AE10 U15
x
PEX_RX4 PEG_TXN4 [6] VDD
U17 VDD
PEX_TX5 AD14 C_PEG_RX5 C24 1 2 0.1U/16V_4 [6] V10 VDD
PEG_RXP5
+3V_GFX AA8 PEX_PLL_HVDD PEX_TX5 AC14 C_PEG_RX#5 C23 1 2 0.1U/16V_4 [6] V12 VDD W1 XPWR_W1
PEG_RXN5
AA9 PEX_PLL_HVDD V14 VDD W2 XPWR_W2
C39 0.1U/10V_4 PEX_RX5 AE12 [6]
V16 VDD W3 XPWR_W3
PEG_TXP5
C33 4.7U/6.3V_6 PEX_RX5 AF12 [6]
V18 VDD W4 XPWR_W4
AB8 PEG_TXN5
C34 4.7U/6.3V_6 PEX_SVDD_3V3
fi
Near GPU PEX_TX6 AC15 C_PEG_RX6 C8 1 2 0.1U/16V_4 [6]
PEG_RXP6
PEX_TX6 AB15 C_PEG_RX#6 C9 1 2 0.1U/16V_4 [6]
bga595-nvidia-n13p-gv2-s-a2 bga595-nvidia-n13p-gv2-s-a2 COMMON
PEG_RXN6 COMMON
PEX_RX6 AG12 [6]

AG13 PEG_TXP6
PEX_RX6 PEG_TXN6 [6]
PEX_TX7 AB16 C_PEG_RX7 C22 1 2 0.1U/16V_4 [6]

PEG_RXP7
PEX_TX7 AC16 C_PEG_RX#7 C21 1 2 0.1U/16V_4 [6]
PEG_RXN7
AF13
a
PEX_RX7 PEG_TXP7 [6]
PEX_RX7 AE13 [6]
PEG_TXN7
AD17
VDD33
PEX_TX8
NC
PEX_TX8 AC17 +3.3V_GFX
NC
AE15
t>=0
2 1
NC PEX_RX8
AF15
IFP(AB)_IOVDD
NC PEX_RX8
+VCC_DGFX_CORE +1.8V_GFX
in
R219 100_4
F2 AC18
[54] VDD_SENSE VDD_SENSE NC
NC
PEX_TX9
PEX_TX9 AB18 Power up NVVDD t>0
[54] GND_SENSE
F1 GND_SENSE NC PEX_RX9 AG15 sequence +VCC_DGFX_CORE
NC PEX_RX9 AG16 t>0
2 1
R220 100_4 PEX_TX10 AB19
3 FBVDDQ
NC
PEX_TX10 AC19 +1.5V_GFX
NC
[22] DGPU_HOLD_RST#
2 1 GPU_RST#
NC PEX_RX10 AF16 R216 *0_4_SHORT_NC PEX_VDD t>0
2
PEX_RX10 AE16
B NC
R218 +1.05V_GFX B
NC
NC
PEX_TX11
PEX_TX11
AD20
AC20
h 100K_4
IFP(CDEF)_IOVDD
+1.05V_GFX
t>=0
1
PEX_RX11 AE18
NC
NC PEX_RX11 AF18
NC PEX_TX12 AC21
.c
NC PEX_TX12 AB21
*200/F_4_NC R203 PEX_TSTCLK AF22 PEX_TSTCLK_OUT NC PEX_RX12 AG18 0718 Change R1241 PN to CS41002JB20(1%->5%)
PEX_TSTCLK# AE22 PEX_TSTCLK_OUT NC PEX_RX12 AG19
PEX_PLLVDD = 130mA (120,200MA) AD23
+1.05V_GFX L2 1 2 BLM18AG121SN1D
NC
NC
PEX_TX13
PEX_TX13 AE23 Power down
Near GPU PEX_PLLVDD AA14 PEX_PLLVDD NC PEX_RX13 AF19 sequence
4.7U/6.3V_6 C14 AA15 PEX_PLLVDD NC PEX_RX13 AE19
1U/6.3V_4 C5
PEX_TX14 AF24
NC
0.1U/10V_4 C29 AE24
w
NC PEX_TX14
Under GPU
NC PEX_RX14 AE21
NC PEX_RX14 AF21
10K/F_4 R208 TESTMODE AD9 TESTMODE
NC PEX_TX15 AG24
NC PEX_TX15 AG25
NC PEX_RX15 AG21
PEX_RX15 AG22
NC
w
GF117 GF119
2.49K/F_4 R204 PEX_TERMP AF25 PEX_TERMP
bga595-nvidia-n13p-gv2-s-a2 COMMON
A A
w
3 PU in PCH
PEX_CLKREQ# 2 1
PEG_A_CLKRQ# [23]
R217 *0_4_SHORT_NC

PROJECT : JWA
3A
N13P-GV2 (PCIE I/F) /NVDD
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix
vina
U16B
2/14 FBA VMA_DQ[63:0]
VMA_DQ[63:0] [18]
R22 10K/F_4 PS_FB_CLAMP F3 NC GF119 FBA_D0 E18 VMA_DQ0
D D
FBA_D1 F18 VMA_DQ1
FB_CLAMP GF117 FBA_D2 E16 VMA_DQ2
F17 VMA_DQ3
FBA_D3
FBA_D4 D20 VMA_DQ4 FBVDDQ + FBVDD = 3.116A U16F
FBA_D5 D21 VMA_DQ5 13/14 GND
FBA_D6 F20 VMA_DQ6 +1.5V_GFX U16D A2 GND GND M13
FBA_D7 E21 VMA_DQ7 12/14 FBVDDQ AB17 GND GND M15
m
FBA_D8 E15 VMA_DQ8 AB20 GND GND M17
FBA_D9 D15 VMA_DQ9 C52 0.1U/10V_4 B26 FBVDDQ AB24 GND GND N10
FBA_ODT_L FBA_CMD2 R41 10K/F_4 FBA_D10 F15 VMA_DQ10 C73 0.1U/10V_4 C25 FBVDDQ AC2 GND GND N12
FBA_D11 F13 VMA_DQ11 C93 0.1U/10V_4 E23 FBVDDQ AC22 GND GND N14
FBA_ODT_H FBA_CMD18 R205 10K/F_4 FBA_D12 C13 VMA_DQ12 C59 0.1U/10V_4 E26 FBVDDQ AC26 GND GND N16
FBA_D13 B13 VMA_DQ13 C459 1 2 2.2U/10V_6 F14 FBVDDQ AC5 GND GND N18
FBA_RST# FBA_CMD5 R16 10K/F_4 FBA_D14 E13 VMA_DQ14 C41 1 2 2.2U/10V_6 F21 FBVDDQ AC8 GND GND P11
FBA_D15 D13 VMA_DQ15 C110 4.7U/6.3V_6 G13 FBVDDQ AD12 GND GND P13
FBA_CKE_L FBA_CMD3 R241 10K/F_4 FBA_D16 B15 VMA_DQ16 C460 10U/6.3V_6 G14 FBVDDQ AD13 GND GND P15
FBA_D17 C16 VMA_DQ17 C111 10U/6.3V_6 G15 FBVDDQ A26 GND GND P17
FBA_CMD19 R4 10K/F_4 A13 VMA_DQ18 G16 AD15 P2
o
FBA_CKE_H FBA_D18 FBVDDQ GND GND
FBA_D19 A15 VMA_DQ19 G18 FBVDDQ AD16 GND GND P23
FBA_D20 B18 VMA_DQ20 G19 FBVDDQ AD18 GND GND P26
FBA_D21 A18 VMA_DQ21 G20 FBVDDQ AD19 GND GND P5
FBA_D22 A19 VMA_DQ22 G21 FBVDDQ AD21 GND GND R10
FBA_D23 C19 VMA_DQ23 H24 FBVDDQ AD22 GND GND R12
FBA_D24 B24 VMA_DQ24 H26 FBVDDQ AE11 GND GND R14
FBA_D25 C23 VMA_DQ25 J21 FBVDDQ AE14 GND GND R16
.c
FBA_D26 A25 VMA_DQ26 K21 FBVDDQ AE17 GND GND R18
FBA_D27 A24 VMA_DQ27 L22 FBVDDQ AE20 GND GND T11
FBA_D28 A21 VMA_DQ28 L24 FBVDDQ AB11 GND GND T13
FBA_D29 B21 VMA_DQ29 L26 FBVDDQ AF1 GND GND T15
FBA_D30 C20 VMA_DQ30 M21 FBVDDQ AF11 GND GND T17
FBA_D31 C21 VMA_DQ31 N21 FBVDDQ AF14 GND GND U10
FBA_D32 R22 VMA_DQ32 R21 FBVDDQ AF17 GND GND U12
[18] C27 FBA_CMD0 FBA_D33 R24 VMA_DQ33 T21 FBVDDQ AF20 GND GND U14
FBA_CMD0 C26 T22 VMA_DQ34 V21 AF23 U16
TP53 FBA_CMD1 FBA_CMD1 FBA_D34 FBVDDQ GND GND
[18]
E24 FBA_CMD2 FBA_D35 R23 VMA_DQ35 W21 FBVDDQ AF5 GND GND U18
FBA_CMD2
[18] F24 FBA_CMD3 FBA_D36 N25 VMA_DQ36 AF8 GND GND U2
FBA_CMD3
[18] D27 FBA_CMD4 FBA_D37 N26 VMA_DQ37 AG2 GND GND U23
FBA_CMD4
D26 N23 VMA_DQ38 AG26 U26
x
C FBA_CMD5 FBA_D38 GND GND C
[18] FBA_CMD5
[18]
F25 FBA_CMD6 FBA_D39 N24 VMA_DQ39 AB14 GND GND U5
FBA_CMD6
[18] F26 FBA_CMD7 FBA_D40 V23 VMA_DQ40 B1 GND GND V11
FBA_CMD7
[18] F23 FBA_CMD8 FBA_D41 V22 VMA_DQ41 B11 GND GND V13
FBA_CMD8
[18] G22 FBA_CMD9 FBA_D42 T23 VMA_DQ42 B14 GND GND V15
FBA_CMD9
[18]
G23 FBA_CMD10 FBA_D43 U22 VMA_DQ43 B17 GND GND V17
FBA_CMD10
[18]
G24 FBA_CMD11 FBA_D44 Y24 VMA_DQ44 B20 GND GND Y2
FBA_CMD11 F27 AA24 VMA_DQ45 B23 Y23
FBA_CMD12 FBA_D45 GND GND
fi
[18] FBA_CMD12
[18]
G25 FBA_CMD13 FBA_D46 Y22 VMA_DQ46 B27 GND GND Y26
FBA_CMD13
[18] G27 FBA_CMD14 FBA_D47 AA23 VMA_DQ47 B5 GND GND Y5
FBA_CMD14
[18]
G26 FBA_CMD15 FBA_D48 AD27 VMA_DQ48 B8 GND
FBA_CMD15
[18]
M24 FBA_CMD16 FBA_D49 AB25 VMA_DQ49 E11 GND
FBA_CMD16 M23 AD26 VMA_DQ50 E14
TP1 FBA_CMD17 FBA_CMD17 FBA_D50 GND
[18]
K24 FBA_CMD18 FBA_D51 AC25 VMA_DQ51 E17 GND
FBA_CMD18
[18]
K23 FBA_CMD19 FBA_D52 AA27 VMA_DQ52 E2 GND
FBA_CMD19
[18]
M27 FBA_CMD20 FBA_D53 AA26 VMA_DQ53 E20 GND
FBA_CMD20 M26 W26 VMA_DQ54 E22
[18] FBA_CMD21 FBA_CMD21 FBA_D54 GND
M25 Y25 VMA_DQ55 E25
a
[18] FBA_CMD22 FBA_CMD22 FBA_D55 GND
[18]
K26 FBA_CMD23 FBA_D56 R26 VMA_DQ56 E5 GND
FBA_CMD23
[18] K22 FBA_CMD24 FBA_D57 T25 VMA_DQ57 E8 GND
FBA_CMD24
[18] J23 FBA_CMD25 FBA_D58 N27 VMA_DQ58 H2 GND
FBA_CMD25
[18] J25 FBA_CMD26 FBA_D59 R27 VMA_DQ59 H23 GND
FBA_CMD26
[18] J24 FBA_CMD27 FBA_D60 V26 VMA_DQ60 H25 GND
FBA_CMD27
[18]
K27 FBA_CMD28 FBA_D61 V27 VMA_DQ61 FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ R39 40.2/F_4 +1.5V_GFX
H5 GND
FBA_CMD28
[18]
K25 FBA_CMD29 FBA_D62 W27 VMA_DQ62 K11 GND
FBA_CMD29
in
[18] J27 FBA_CMD30 FBA_D63 W25 VMA_DQ63 K13 GND
FBA_CMD30
TP52 FBA_CMD31 J26 FBA_CMD31 FB_CAL_PU_GND C24 FB_CAL_PU_GND R32 42.2/F_4 K15 GND
K17 GND
FBA_DQM0 D19 VMA_DM0 [18] L10 GND
D14 VMA_DM1 VMA_DM[7:0] B25 FB_CAL_TERM_GND R36 51.1/F_4 L12
FBA_DQM1 FB_CALTERM_GND GND
FBA_DQM2 C17 VMA_DM2 L14 GND
FBA_DQM3 C22 VMA_DM3 L16 GND
FBA_DQM4 P24 VMA_DM4 bga595-nvidia-n13p-gv2-s-a2 L18 GND
FBA_DQM5 W24 VMA_DM5 COMMON L2 GND
FBA_DQM6 AA25 VMA_DM6 L23 GND
+1.5V_GFX R15 *60.4/F_4_NC FBA_DEBUG F22 FBA_DEBUG0 FBA_DQM7 U25 VMA_DM7 L25 GND
R14 *60.4/F_4_NC FBA_DEBUG1 J22 FBA_DEBUG1 L5 GND GND AA7
M11 AB7
B
[18]
[18]
[18]
[18]
VMA_CLKP0
VMA_CLKN0
VMA_CLKP1
VMA_CLKN1
D24
D25
N22
M22
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
h
E19 VMA_WDQS0
C15 VMA_WDQS1
B16 VMA_WDQS2
B22 VMA_WDQS3
R25 VMA_WDQS4
W23 VMA_WDQS5
AB26 VMA_WDQS6
VMA_WDQS[7:0] [18]
GND
bga595-nvidia-n13p-gv2-s-a2
GND
COMMON
B
.c
FBA_DQS_WP7 T26 VMA_WDQS7
D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0 [18]

C18 C14 VMA_RDQS1 VMA_RDQS[7:0]
FBA_WCK01 FBA_DQS_RN1
D17 FBA_WCK23 FBA_DQS_RN2 A16 VMA_RDQS2
D16 FBA_WCK23 FBA_DQS_RN3 A22 VMA_RDQS3
T24 FBA_WCK45 FBA_DQS_RN4 P25 VMA_RDQS4
U24 FBA_WCK45 FBA_DQS_RN5 W22 VMA_RDQS5
V24 FBA_WCK67 FBA_DQS_RN6 AB27 VMA_RDQS6
V25 FBA_WCK67 FBA_DQS_RN7 T27 VMA_RDQS7
FB_PLLAVDD = 55mA
w
(120,200MA)
+1.05V_GFX L1 1 2 BLM18AG121SN1D +FB_PLLAVDD F16 FB_PLLAVDD
C1 22U/6.3VS_6 P22 FB_PLLAVDD

C68 0.1U/10V_4
C2 0.1U/10V_4 H22 FB_DLLAVDD GF119
C3 0.1U/10V_4
FB_PLLAVDD GF117
w
FB_DLLAVDD = 15mA
FB_VREF_PROBE D23
A bga595-nvidia-n13p-gv2-s-a2 COMMON A
w

PROJECT : JWA
3A
N13P-GV2 (MEMORY/GND)
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
fix
ina
U16G U16J
4/14 IFPAB
7/14 IFPEF
v
GF117 GF119 GF119
AC4 GF117
NC IFPA_TXC DVI-DL DVI-SL/HDMI DP
IFPA_TXC AC3
NC
GF119 GF117 IFPE_AUX J3
GF119 GF117 NC I2CY_SDA I2CY_SDA
AA6 IFPAB_RSET NC I2CY_SCL I2CY_SCL IFPE_AUX J2
NC
IFPA_TXD0 Y3 J7 IFPEF_PLLVDD
NC NC
IFPA_TXD0 Y4
NC
IFPE_L3 J1
NC TXC TXC
V7 IFPAB_PLLVDD IFPE_L3 K1
NC NC TXC TXC
IFPA_TXD1 AA2 K7 IFPEF_PLLVDD
NC NC
D
W7 IFPAB_PLLVDD IFPA_TXD1 AA3 IFPE_L2 K3 D
NC NC NC TXD0 TXD0
IFPE_L2 K2 U16K
NC TXD0 TXD0
3/14 DACA
IFPA_TXD2 AA1 K6 IFPEF_RSET IFPE_L1 M3
NC NC NC TXD1 TXD1 GF119
IFPA_TXD2 AB1 IFPE_L1 M2 GF117 GF119
NC NC TXD1 TXD1 GF117
W5 DACA_VDD I2CA_SCL B7
NC NC
IFPE_L0 M1 I2CA_SDA A7
NC TXD2 TXD2 NC
IFPA_TXD3 AA5 IFPE_L0 N1 AE2 DACA_VREF
NC NC TXD2 TXD2 TSEN_VREF
AA4
m
NC IFPA_TXD3
AF2 DACA_RSET NC NC DACA_HSYNC AE3
IFPE NC DACA_VSYNC AE4
NC IFPB_TXC AB4
IFPB_TXC AB5
NC
NC HPD_E HPD_E GPIO18 C2 DACA_RED AG3
GF119 GF117 NC
W6 IFPA_IOVDD IFPB_TXD4 AB2 DACA_GREEN AF4
NC NC NC
IFPB_TXD4 AB3
NC GF119 GF117
Y6 AF3
o
IFPB_IOVDD NC NC DACA_BLUE
H6 IFPE_IOVDD NC
IFPB_TXD5 AD2 GF119
NC
IFPB_TXD5 AD3 J6 IFPF_IOVDD GF117
NC NC DVI-DL DVI-SL/HDMI DP
H4 bga595-nvidia-n13p-gv2-s-a2 COMMON
NC I2CZ_SDA IFPF_AUX
IFPB_TXD6 AD1 NC I2CZ_SCL IFPF_AUX H3
NC
AE1
.c
NC IFPB_TXD6
NC TXC IFPF_L3 J5
IFPB_TXD7 AD5 NC TXC IFPF_L3 J4
NC
IFPB_TXD7 AD4
NC
IFPF_L2 K5
NC TXD3 TXD0
NC IFPF_L2 K4
TXD3 TXD0
C C
NC TXD4 TXD1 IFPF_L1 L4
IFPF NC TXD4 TXD1 IFPF_L1 L3
NC GPIO14 B3
IFPAB IFPF_L0 M5
x
NC TXD5 TXD2
IFPF_L0 M4
NC TXD5 TXD2
U16H
5/14 IFPC
IFPC NC HPD_F GPIO19 F7
fi
GF119 GF117
T6 IFPC_RSET NC GF117 GF119
DVI/HDMI DP
M7 N5 bga595-nvidia-n13p-gv2-s-a2 COMMON
IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX
N7 IFPC_PLLVDD NC NC I2CW_SCL IFPC_AUX N4
a
NC TXC IFPC_L3 N3 PLLVDD = 38mA
NC IFPC_L3 N2 (120,200MA) C445 10P/50V_4
TXC
+1.05V_GFX L18 1 2 BLM18AG121SN1D +NV_PLLVDD
4
3
IFPC_L2 R3 C64 0.1U/10V_4
NC TXD0
IFPC_L2 R2 C432 22U/6.3VS_6 XTALIN Y2
NC TXD0
XTALOUT 27MHZ +-10PPM
TXD1 IFPC_L1 R1
NC
in
NC TXD1 IFPC_L1 T1
1
2
SP_PLLVDD = 17mA U16M C444 10P/50V_4
IFPC_L0 T3 9/14 XTAL_PLL
NC TXD2
NC TXD2 IFPC_L0 T2 +1.05V_GFX L17 HCB1608KF-181T15 SP_PLLVDD
B C55 0.1U/10V_4 L6 PLLVDD B
C49 0.1U/10V_4 M6 SP_PLLVDD
C430 4.7U/6.3V_6
P6 IFPC_IOVDD NC GPIO15 C3 C429 22U/6.3VS_6 N6 VID_PLLVDD
NC GF119
bga595-nvidia-n13p-gv2-s-a2 COMMON NC GF117

VID_PLLVDD = 41mA
U6
U16I
6/14 IFPD
GF119
IFPD_RSET
GF117
NC
GF117 GF119
R235
h 10K/F_4
XTALIN
XTAL_SSIN A10
C11
XTALSSIN
XTALIN
XTALOUTBUFF
XTALOUT
C10 BXTALOUT
B10 XTALOUT
R237 10K/F_4
.c
DVI/HDMI DP bga595-nvidia-n13p-gv2-s-a2 COMMON
T7 IFPD_PLLVDD NC NC I2CX_SDA IFPD_AUX P4

NC I2CX_SCL IFPD_AUX P3
R7 IFPD_PLLVDD NC
IFPD_L3 R5
NC TXC
NC TXC IFPD_L3 R4
IFPD_L2 T5
NC TXD0
TXD0 IFPD_L2 T4
NC
w
TXD1 IFPD_L1 U4
NC
IFPD NC TXD1 IFPD_L1 U3
IFPD_L0 V4
NC TXD2
IFPD_L0 V3
NC TXD2
A A
w
R6 IFPD_IOVDD GF119 NC GPIO17 D4
NC GF117

bga595-nvidia-n13p-gv2-s-a2 COMMON PROJECT : JWA
w

3A
N13P-GV2 (DISPLAY)
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
f ix
+3V_GFX +3V_GFX
ina
U16L Default: HYNIX
10/14 MISC2
v R226
10K/F_4
R228
10K/F_4
R230
10K/F_4
E10
F10
VMON_IN0
VMON_IN1 ROM_CS D12 ROM_CS TP4
R222
10K/F_4
R223
10K/F_4
R26 R25
*10K/F_4_NC *10K/F_4_NC
DGPU_VID5 ROM_SI B12 ROM_SI

DGPU_VID4 ROM_SO A12 ROM_SO ROM_SI STRAP0
DGPU_VID3 STRAP0 D1 STRAP0 ROM_SCLK C12 ROM_SCLK ROM_SO STRAP1
DGPU_VID2 STRAP1 D2 STRAP1 ROM_SCLK STRAP2
DGPU_VID1 STRAP2 E4 STRAP2 STRAP3
D DGPU_VID0 STRAP3 E3 STRAP3 STRAP4 D
STRAP4 D3 STRAP4
GF119 GF117
R227 R229 R37 R221 R224 R225 R23 R29
R232 R231 R33 C1 STRAP5_NC 10K/F_4 10K/F_4 10K/F_4 *10K/F_4_NC 10K/F_4 10K/F_4 10K/F_4
NC
10K/F_4 10K/F_4 10K/F_4 BUFRST D11
*10K/F_4_NC
F6 D10
m
MULTISTRAP_REF0_GND PGOOD
GF119 GF117
F4
N13P-GV2 NVDD HW BOOT Voltage = 0.875V MULTISTRAP_REF1_GND NC
E9
VID = 110010 F5 MULTISTRAP_REF2_GND NC
CEC
Binary Strap Mode Mapping
Output VID0 VID1 VID2 VID3 VID4 VID5
Strap Pin name Strap Mapping Resistance Polarity
o
N13P-GV2 0.875V 0 1 0 0 1 1
ROM_SCLK SMB_ALT_ADDR 10Kohm Pull-down to GND
Pull-UP to 3V3 if VBIOS ROM Exists
U16N ROM_SI SUB_VENDOR 10Kohm
Pull-down to GND if no VBIO ROM
.c
8/14 MISC1
I2CS_SCL D9 I2CS_SCL
I2CS_SDA D8 I2CS_SDA ROM_SO VGA_DEVICE 10Kohm Pull-down to GND ( no dispaly )
I2CC_SCL A9 EXT_EDIDCLK R234 2.2K_4 +3V_GFX STRAP0 RAMCFG[0] 10Kohm USER defined
I2CC_SDA B9 EXT_EDIDDATA R236 2.2K_4
STRAP1 RAMCFG1] 10Kohm USER defined
C C
VGA_THERMDN [42] E12 THERMDN GF117 GF119 STRAP2 RAMCFG[2] 10Kohm USER defined
VGA_THERMDN C9
NC I2CB_SCL
VGA_THERMDP [42] F12 THERMDP NC I2CB_SDA C8 STRAP3 RAMCFG[3] 10Kohm USER defined
VGA_THERMDP
x
STRAP4 PCIE_MAX_SPEED 10Kohm Pull-down to GND
TP49 JTAG_TCK AE5 JTAG_TCK
TP51 JTAG_TMS AD6 JTAG_TMS
TP50 JTAG_TDI AE6 JTAG_TDI ROM_SI
TP47 JTAG_TDO AF6 JTAG_TDO VRAM Configuration Table
TP48 JTAG_TRST# AG4 JTAG_TRST GPIO0 C6 [54]
DGPU_VID4
fi
GPIO1 B2 [54] RAMCFG
DGPU_VID3
GPIO2 D6 DGPU_DPST_PWM TP2 [3:0] DESCRIPTION Vendor Vendor P/N QCI P/N
GPIO3 C7 DPRSLPVR_R1 TP55
GPIO4 F9 DGPU_LVDS_BLON TP8 0000 Reserved
GPIO5 A3 [54] 2Gb 1100 IC SDRAM(96P)H5TQ2G63DFR-11C(FBGA) HYNIX H5TQ2G63DFR-11C AKD5MGWTW16
DGPU_VID1
GPIO6 A4 [54] 2Gb 1011 IC SDRAM(96P)K4W2G1646E-BC11(FBGA) SAMSUNG K4W2G1646E-BC11 AKD5MGGT520
DGPU_VID2
GPIO7 B6 3DVISION TP56 4Gb 0011 IC SDRAM(96P)H5TQ4G63MFR-11C(FBGA) HYNIX H5TQ4G63MFR-11C AKD5PGWTW04
GPIO8 A6 VGA_OVT# TP54 4Gb 0001 IC SDRAM(96P)K4W4G1646B-HC11(FBGA) SAMSUNG K4W4G1646B-HC11 AKD5MGWT516
GPIO9 F8 VGA_ALERT 4Gb 0101 IC SDRAM(96P) MT41K256M16HA-107G:E(FBGA) Micron MT41K256M16HA-107G AKD5PGSTL00
a
GPIO10 C5 MEM_VREF_CTL TP57
GPIO11 E7 [54]
DGPU_VID0
GPIO12 D7 VGA_PWR_LEVEL#
GPIO13 B4 [54]
DGPU_VID5
GF117 GF119 GPIO ASSIGNMENTS
in
GPIO16 D5
NC
E6
NC GPIO20
GPIO21 C4 GPIO I/O PIN USAGE
NC
B 0 OUT GPU_VID4 GPU CORE_VDD VID4 B
bga595-nvidia-n13p-gv2-s-a2 COMMON 1 OUT GPU_VID3 GPU CORE_VDD VID3

+3V_GFX 2 OUT LCD_BL_PWM LCD BACKLIGHT PWM
3 OUT LCD_VCC PANEL POWER ENABLE
+3V_GFX R40
I2CS_SCL
4.7K_4
4
Q28
5
3
+3V_GFX
SMBCLK3 [36,38,42]
VGA_PWR_LEVEL# R30
VGA_OVT#
VGA_ALERT
R233
R28
10K/F_4
10K/F_4
10K/F_4 h
JTAG_TRST# R215 10K/F_4
4
5
6
OUT LCD_BLEN
OUT
OUT
GPU_VID1
GPU_VID2
PANEL BACKLIGHT ENABLE
GPU CORE_VDD VID1
GPU CORE_VDD VID2
.c
2 7 OUT 3D VISION 3D VISION LEFT/RIGHT VISION
I2CS_SDA 1 6 8 I/O OVERT ACTIVE LOW THERMAL OVER TEMP
SMBDAT3 [36,38,42]
R238 4.7K_4 9 I/O ALERT ACTIVE LOW THERMAL ALERT
+3V_GFX
DMN66D0LDW-7 10 OUT MEM VREF MEMMORY VREF CONTROL
11 OUT GPU_VID0 GPU CORE_VDD VID0
12 IN PWR_LEVEL Power Detect ,HIGH=AC, LOW=DC
w
Q32
5VGA_PWR_LEVEL_PWR 13 OUT GPU_VID5 GPU CORE_VDD VID5
VGA_PWR_LEVEL_PWR [54]
4 3 VGA_PWR_LEVEL#
14 IN HPD_AB HOT PLUG DETECT FOR IFPAB
A
15 IN HPD_C HOT PLUG DETECT FOR IFPC A
2VGA_PWR_LEVEL_EC
VGA_PWR_LEVEL_EC [38] 16 OUT MEM VDD MEMMORY VDD CONTROL
w
1 6
17 IN HPD_D HOT PLUG DETECT FOR IFPD
18 IN HPD_E HOT PLUG DETECT FOR IFPE
DMN66D0LDW-7
19 IN HPD_F HOT PLUG DETECT FOR IFPF Quanta Computer Inc.
20/21 RESERVE PROJECT : JWA
w

3A
N13P-GV2 (GPIO/STRAPS)
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix
ina
900MHz VRAM size:
Samsung 64Mx16, P/N = AKD5EGGT500
v
Samsung 128Mx16, P/N = AKD5MGWT516
Hynix 64Mx16, P/N = AKD5LZWTW02
Hynix 128Mx16, P/N = AKD5PGWTW04
[15]
D [15]
[15]
[15]
VMA_DQ[63..0]
VMA_DM[7..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0]
CHANNEL A: 256MB/512MB DDR3 D
VRAM2 VRAM4 VRAM1 VRAM3
VREFC_VMA1 M8 E3 VMA_DQ13 VREFC_VMA1 M8 E3 VMA_DQ25 VREFC_VMA3 M8 E3 VMA_DQ40 VREFC_VMA3 M8 E3 VMA_DQ62

VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ9 VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ28 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ45 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ59
VREFDQ DQL1 F2 VMA_DQ14 VREFDQ DQL1 F2 VMA_DQ27 VREFDQ DQL1 F2 VMA_DQ42 VREFDQ DQL1 F2 VMA_DQ60
DQL2 DQL2 DQL2 DQL2
m
[15]
N3 F8 VMA_DQ8 FBA_CMD9 N3 F8 VMA_DQ29 FBA_CMD9 N3 F8 VMA_DQ46 FBA_CMD9 N3 F8 VMA_DQ56
FBA_CMD9 P7 A0 DQL3 H3 VMA_DQ12 FBA_CMD11 P7 A0 DQL3 H3 VMA_DQ26 FBA_CMD11 P7 A0 DQL3 H3 VMA_DQ43 FBA_CMD11 P7 A0 DQL3 H3 VMA_DQ61
[15] FBA_CMD11 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
P3 H8 VMA_DQ10 FBA_CMD8 P3 H8 VMA_DQ31 FBA_CMD8 P3 H8 VMA_DQ47 FBA_CMD8 P3 H8 VMA_DQ58
[15]
N2 G2 VMA_DQ15 FBA_CMD25 N2 G2 VMA_DQ24 FBA_CMD25 N2 G2 VMA_DQ41 FBA_CMD25 N2 G2 VMA_DQ63
FBA_CMD25 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7
VMA_DQ11 FBA_CMD10 VMA_DQ30 FBA_CMD10 VMA_DQ44 FBA_CMD10 VMA_DQ57
P2 FBA_CMD24 P2 FBA_CMD24 P2 FBA_CMD24 P2
[15] FBA_CMD24 A5 A5 A5 A5
R8 FBA_CMD22 R8 FBA_CMD22 R8 FBA_CMD22 R8
[15] FBA_CMD22 A6 A6 A6 A6
R2 D7 VMA_DQ5 FBA_CMD7 R2 D7 VMA_DQ16 FBA_CMD7 R2 D7 VMA_DQ34 FBA_CMD7 R2 D7 VMA_DQ54
[15] FBA_CMD7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
[15]
T8 C3 VMA_DQ1 FBA_CMD21 T8 C3 VMA_DQ23 FBA_CMD21 T8 C3 VMA_DQ36 FBA_CMD21 T8 C3 VMA_DQ48
FBA_CMD21 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8
L7 C2 VMA_DQ2 FBA_CMD29 L7 C2 VMA_DQ21 FBA_CMD29 L7 C2 VMA_DQ38 FBA_CMD29 L7 C2 VMA_DQ51
[15]
o
FBA_CMD29 R7 A10/AP DQU3 A7 VMA_DQ4 FBA_CMD23 R7 A10/AP DQU3 A7 VMA_DQ18 FBA_CMD23 R7 A10/AP DQU3 A7 VMA_DQ33 FBA_CMD23 R7 A10/AP DQU3 A7 VMA_DQ53
N7 A2 VMA_DQ3 FBA_CMD28 N7 A2 VMA_DQ22 FBA_CMD28 N7 A2 VMA_DQ37 FBA_CMD28 N7 A2 VMA_DQ50
[15] FBA_CMD28 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
[15]
T3 B8 VMA_DQ7 FBA_CMD20 T3 B8 VMA_DQ19 FBA_CMD20 T3 B8 VMA_DQ35 FBA_CMD20 T3 B8 VMA_DQ52
FBA_CMD20 T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3
M7 FBA_CMD14 M7 FBA_CMD14 M7 FBA_CMD14 M7
[15] FBA_CMD14 A15 A15 A15 A15
M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2

[15]
.c
FBA_CMD12 N8 BA0 VDD#B2 D9 +1.5V_GFX N8 BA0 VDD#B2 D9 N8 BA0 VDD#B2 D9 +1.5V_GFX N8 BA0 VDD#B2 D9
FBA_CMD27 FBA_CMD27 FBA_CMD27
[15] FBA_CMD27 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7
[15] FBA_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 VMA_CLKP0 J7 VDD#N1 N9 J7 VDD#N1 N9 VMA_CLKP1 J7 VDD#N1 N9
[15] VMA_CLKP0 CK VDD#N9 CK VDD#N9 [15] VMA_CLKP1 CK VDD#N9 CK VDD#N9
K7 R1 VMA_CLKN0 K7 R1 K7 R1 VMA_CLKN1 K7 R1
[15] VMA_CLKN0 CK VDD#R1 CK VDD#R1 [15] VMA_CLKN1 CK VDD#R1 CK VDD#R1 +1.5V_GFX
K9 R9 FBA_CMD3 K9 R9 K9 R9 FBA_CMD19 K9 R9
[15] FBA_CMD3 CKE VDD#R9 CKE VDD#R9 +1.5V_GFX[15] FBA_CMD19 CKE VDD#R9 CKE VDD#R9
K1 A1 FBA_CMD2 K1 A1 K1 A1 FBA_CMD18 K1 A1
[15] FBA_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 [15] FBA_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
[15]
L2 A8 FBA_CMD0 L2 A8 [15]
L2 A8 FBA_CMD16 L2 A8
FBA_CMD0 J3 CS VDDQ#A8 C1 FBA_CMD30 J3 CS VDDQ#A8 C1 FBA_CMD16 FBA_CMD30 J3 CS VDDQ#A8 C1 FBA_CMD30 J3 CS VDDQ#A8 C1
x
[15] FBA_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
C K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 C
[15] FBA_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
[15]
L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2
FBA_CMD13 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_WDQS1 F3 VDDQ#F1 H2 VMA_WDQS3 F3 VDDQ#F1 H2 VMA_WDQS5 F3 VDDQ#F1 H2 VMA_WDQS7 F3 VDDQ#F1 H2
VMA_RDQS1 G3 DQSL VDDQ#H2 H9 VMA_RDQS3 G3 DQSL VDDQ#H2 H9 VMA_RDQS5 G3 DQSL VDDQ#H2 H9 VMA_RDQS7 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9
fi
VMA_DM1 E7 A9 VMA_DM3 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9
VMA_DM0 D3 DML VSS#A9 B3 VMA_DM2 D3 DML VSS#A9 B3 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_WDQS0 C7 VSS#G8 J2 VMA_WDQS2 C7 VSS#G8 J2 VMA_WDQS4 C7 VSS#G8 J2 VMA_WDQS6 C7 VSS#G8 J2
VMA_RDQS0 B7 DQSU VSS#J2 J8 VMA_RDQS2 B7 DQSU VSS#J2 J8 VMA_RDQS4 B7 DQSU VSS#J2 J8 VMA_RDQS6 B7 DQSU VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9
a
[15] FBA_CMD5 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R18 VSSQ#B9 D1 R242 VSSQ#B9 D1 R1 VSSQ#B9 D1 R12 VSSQ#B9 D1
Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1
243/F_4 D8 243/F_4 D8 243/F_4 D8 243/F_4 D8
in
Ohms +-1% VSSQ#D8 Ohms +-1% VSSQ#D8 Ohms +-1% VSSQ#D8 Ohms +-1% VSSQ#D8
E2 E2 E2 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
H5TQ4G63MFR-11C H5TQ4G63MFR-11C H5TQ4G63MFR-11C H5TQ4G63MFR-11C
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

B
VMA_CLKP0
R38
80.6/F_4
R24
1.33K/F_4 h
R239
1.33K/F_4
VMA_CLKP1
R2
1.33K/F_4
R207
1.33K/F_4
B
.c
VREFC_VMA1 VREFD_VMA1 R6 VREFC_VMA3 VREFD_VMA3
VMA_CLKN0 80.6/F_4
1
1
R243 R240 VMA_CLKN1 R3 R206
1.33K/F_4 C455 1.33K/F_4 C453 1.33K/F_4 C17 1.33K/F_4 C417
0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4
2
2
+1.5V_GFX
+1.5V_GFX
w
C109 10U/6.3V_6 C458 10U/6.3V_6 +1.5V_GFX
+1.5V_GFX C412 1U/6.3V_4 C407 10U/6.3V_6 C15 10U/6.3V_6

C102 1U/6.3V_4
+1.5V_GFX C406 10U/6.3V_6 C456 1U/6.3V_4 C19 0.1U/10V_4 C16 10U/6.3V_6
C415 1U/6.3V_4 C101 0.1U/10V_4
C107 1U/6.3V_4 C399 1U/6.3V_4 C454 1U/6.3V_4 C105 0.1U/10V_4
C413 1U/6.3V_4 C410 1U/6.3V_4 C100 1U/6.3V_4 C104 0.1U/10V_4
C18 1U/6.3V_4 C416 1U/6.3V_4 C103 1U/6.3V_4 C106 0.1U/10V_4 C411 0.1U/10V_4
C436 1U/6.3V_4 C20 1U/6.3V_4 C36 1U/6.3V_4 C57 0.1U/10V_4 C414 0.1U/10V_4
w
w
A A

PROJECT : JWA
http://vinafix.vn
3A
N13P-GV2 DDR3 VRAM
5 4 3 2 1
5 4 3 2 1
ix
af
Cougar Point/Panther Point (DMI,FDI,PM)
vin
PCH Pull-high/low(CLG)
U21C
+3.3V_SUS
[6] DMI_RXN0 BC24 BJ14 FDI_TXN0 [6]
DMI_RXN0 DMI0RXN FDI_RXN0 FDI_TXN0
[6] DMI_RXN1 BE20 AY14 FDI_TXN1 [6] RP23 10KX4
[6] DMI_RXN2 BG18 BE14 FDI_TXN2 [6] PM_RI# 1 2
[6] DMI_RXN3 BG20 BH13 FDI_TXN3 [6] [23] PCIE_CLK_REQ5# 3 4
DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 PCIE_CLK_REQ5#
BC12 FDI_TXN4 [6] ME_SUS_PW R_ACK 5 6
FDI_RXN4 FDI_TXN4
[6] DMI_RXP0 BE24 BJ12 FDI_TXN5 [6] AC_PRESENT 7 8
DMI_RXP0 DMI0RXP FDI_RXN5 FDI_TXN5
D [6] DMI_RXP1 BC20 BG10 FDI_TXN6 [6] D
[6] DMI_RXP2 BJ18 BG9 FDI_TXN7 [6]
[6] DMI_RXP3 BJ20
DMI_RXP3 DMI3RXP BG14 FDI_TXP0 [6]
FDI_RXP0 FDI_TXP0
[6] DMI_TXN0 AW24 BB14 FDI_TXP1 [6] PM_BATLOW # R161 1 2 10K_4
DMI_TXN0 DMI0TXN FDI_RXP1 FDI_TXP1
DMI_TXN1 AW20 BF14 FDI_TXP2
m
[6] DMI_TXN1 DMI1TXN FDI_RXP2 FDI_TXP2 [6]
[6] DMI_TXN2 BB18 BG13 FDI_TXP3 [6]
[6] DMI_TXN3 AV18 BE12 FDI_TXP4 [6]
DMI
FDI
BG12 FDI_TXP5 [6] +3.3V_RUN
FDI_RXP5 FDI_TXP5
[6] DMI_TXP0 AY24 BJ10 FDI_TXP6 [6]
DMI_TXP0 DMI0TXP FDI_RXP6 FDI_TXP6
[6] DMI_TXP1 AY20 BH9 FDI_TXP7 [6] RP26 10KX2
DMI_TXP1 DMI1TXP FDI_RXP7 FDI_TXP7
[6] DMI_TXP2 AY18 CLKRUN# 1 2
DMI_TXP2 DMI2TXP
[6] DMI_TXP3 AU18 SYS_RESET# 3 4
DMI_TXP3 DMI3TXP AW16
o
FDI_INT [6]
FDI_INT FDI_INT
DMI_ZCOMP, DMI_IRCOMP 4mil BJ24 AV12 FDI_FSYNC0 [6]

DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0
+1.05V_PCH R145 1 2 49.9/F_4 DMI_COMP BG25 BC10 FDI_FSYNC1 [6]

DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1
RSMRST# R321 1 2 10K_4
.c
R292 2 1 750/F_4 DMI2RBIAS BH21 AV14 FDI_LSYNC0 [6] SYS_PW ROK R320 1 2 100K_4
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0
BB10 FDI_LSYNC1 [6]
FDI_LSYNC1 FDI_LSYNC1
A18 DSW VRMEN

*100P/50V_4_NC 2 1 C346 SYS_PW ROK DSWVRMEN
RSMRST# C502 1 2 *100P/50V_4_NC
System Power Management

*100P/50V_4_NC 2 1 C290 EC_PW ROK ME_SUS_PW R_ACK C12 E22 RSMRST#
x
C SUSACK# DPWROK C
SYS_RESET# K3 B9 PCIE_W AKE# [23]

SYS_RESET# WAKE# PCIE_W AKE#
fi
SYS_PW ROK P12 +3V N3 CLKRUN# [38]
SYS_PWROK CLKRUN# / GPIO32 CLKRUN#
[7,38] EC_PW ROK L22 +3V_S5 G8

EC_PW ROK PWROK SUS_STAT# / GPIO61
+RTC_CELL
[38,44] HW PG L10 +3V_S5 N14 SUSCLK
HW PG APWROK SUSCLK / GPIO62 TP38
2
TP37
[7] PM_DRAM_PW RGD B13 +3V_S5 D10 SIO_SLP_S5# [38] R293
PM_DRAM_PW RGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5#
330K_4
[38] RSMRST# C21 H4 SIO_SLP_S4# [38,47]

RSMRST# SIO_SLP_S4#
1
RSMRST# SLP_S4#
in
DSW VRMEN
1
[38] ME_SUS_PW R_ACK ME_SUS_PW R_ACK K16 +3V_S5 F4 SIO_SLP_S3# [9,38,47]
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3#
R290
*330K_4_NC
[38] SIO_PW RBTN# E20 DSW G10 W/O support iAMT
SIO_PW RBTN# PWRBTN# SLP_A#
2
[38] AC_PRESENT H20 DSW G16
AC_PRESENT ACPRESENT / GPIO31 SLP_SUS#
W/O support Deep Sx
B PM_BATLOW #
PM_RI#
E10
A10
BATLOW# / GPIO72 +3V_S5
RI# +3V_S5
h PMSYNCH
SLP_LAN# / GPIO29
AP14
K14 SIO_SLP_LAN#
H_PM_SYNC
TP35
H_PM_SYNC [7]
On Die DSW VR Enable
High = Enable (Default)
Low = Disable
B
.c
BD82HM77-SLJ8C-MM#915664
w
w
3
EC_PW ROK SYS_PW ROK 2 1 [38,42,51]
IMVP_PW RGD
R182 *0_4_SHORT_NC
w
1
A A
R147
100K_4
2

PROJECT : JWA
3A
Panther Point 1/7
1
19 of 54
5 4 3 2 1
fix
vina Cougar Point/Panther Point (LVDS,DDI) Cougar Point/Panther Point (GND)
U21I U21H
H5
AY4 H46 VSS[0]
U21D AY42 VSS[159] VSS[259] K18 AA17 AK38
AY46 VSS[160] VSS[260] K26 AA2 VSS[1] VSS[80] AK4
PANEL_BKEN J47 AP43 AY8 VSS[161] VSS[261] K39 AA3 VSS[2] VSS[81] AK42
[38] PANEL_BKEN L_BKLTEN SDVO_TVCLKINN VSS[162] VSS[262] VSS[3] VSS[82]
[26] ENVDD M45 AP45 B11 K46 AA33 AK46
ENVDD L_VDD_EN SDVO_TVCLKINP VSS[163] VSS[263] VSS[4] VSS[83]
D B15 K7 AA34 AK8 D
LCD_PW M P45 AM42 B19 VSS[164] VSS[264] L18 AB11 VSS[5] VSS[84] AL16
[26] LCD_PW M L_BKLTCTL SDVO_STALLN VSS[165] VSS[265] VSS[6] VSS[85]
AM40 B23 L2 AB14 AL17
LCD_DDCCLK T40 SDVO_STALLP B27 VSS[166] VSS[266] L20 AB39 VSS[7] VSS[86] AL19
[26] LCD_DDCCLK L_DDC_CLK VSS[167] VSS[267] VSS[8] VSS[87]
[26] LCD_DDCDAT K47 AP39 B31 L26 AB4 AL2
LCD_DDCDAT L_DDC_DATA SDVO_INTN AP40 B35 VSS[168] VSS[268] L28 AB43 VSS[9] VSS[88] AL21
m
DIS_L_CTRL_CLK T45 SDVO_INTP B39 VSS[169] VSS[269] L36 AB5 VSS[10] VSS[89] AL23
DIS_L_CTRL_DATA P39 L_CTRL_CLK B7 VSS[170] VSS[270] L48 AB7 VSS[11] VSS[90] AL26
L_CTRL_DATA F45 VSS[171] VSS[271] M12 AC19 VSS[12] VSS[91] AL27
R121 2 1 2.37K/F_4 LVDS_IBG AF37 P38 HDMI_SCL BB12 VSS[172] VSS[272] P16 AC2 VSS[13] VSS[92] AL31
LVD_IBG SDVO_CTRLCLK HDMI_SCL [28] VSS[173] VSS[273] VSS[14] VSS[93]
LVDS_VBG AF36 M39 HDMI_SDA [28] BB16 M18 AC21 AL33
TP29 LVD_VBG SDVO_CTRLDATA HDMI_SDA VSS[174] VSS[274] VSS[15] VSS[94]
BB20 M22 AC24 AL34
AE48 BB22 VSS[175] VSS[275] M24 AC33 VSS[16] VSS[95] AL48
LVD_VREFH VSS[176] VSS[276] VSS[17] VSS[96]
INT. HDMI
AE47 AT49 BB24 M30 AC34 AM11
o
LVD_VREFL DDPB_AUXN AT47 BB28 VSS[177] VSS[277] M32 AC48 VSS[18] VSS[97] AM14
DDPB_AUXP AT40 INT_HDMI_HPD BB30 VSS[178] VSS[278] M34 AD10 VSS[19] VSS[98] AM36
DDPB_HPD INT_HDMI_HPD [28] VSS[179] VSS[279] VSS[20] VSS[99]
[26] INT_TXLCLKOUTN INT_TXLCLKOUTN AK39 BB38 M38 AD11 AM39
LVDSA_CLK# VSS[180] VSS[280] VSS[21] VSS[100]
LVDS
[26] INT_TXLCLKOUTP INT_TXLCLKOUTP AK40 AV42 INT_HDMI_TXN2 [28] BB4 M4 AD12 AM43
LVDSA_CLK DDPB_0N INT_HDMI_TXN2 VSS[181] VSS[281] VSS[22] VSS[101]
AV40 INT_HDMI_TXP2 [28] BB46 M42 AD13 AM45
DDPB_0P INT_HDMI_TXP2 VSS[182] VSS[282] VSS[23] VSS[102]
.c
[26] INT_TXLOUTN0 AN48 AV45 INT_HDMI_TXN1 [28] BC14 M46 AD19 AM46
INT_TXLOUTN0 LVDSA_DATA#0 DDPB_1N INT_HDMI_TXN1 VSS[183] VSS[283] VSS[24] VSS[103]
[26] INT_TXLOUTN1 AM47 AV46 INT_HDMI_TXP1 [28] BC18 M8 AD24 AM7
INT_TXLOUTN1 LVDSA_DATA#1 DDPB_1P INT_HDMI_TXP1 VSS[184] VSS[284] VSS[25] VSS[104]
Digital Display Interface

[26] INT_TXLOUTN2 AK47 AU48 INT_HDMI_TXN0 [28] BC2 N18 AD26 AN2
INT_TXLOUTN2 LVDSA_DATA#2 DDPB_2N INT_HDMI_TXN0 VSS[185] VSS[285] VSS[26] VSS[105]
AJ48 AU47 INT_HDMI_TXP0 [28] BC22 P30 AD27 AN29
LVDSA_DATA#3 DDPB_2P INT_HDMI_TXP0 VSS[186] VSS[286] VSS[27] VSS[106]
AV47 INT_HDMI_TXCN [28] BC26 N47 AD33 AN3
DDPB_3N INT_HDMI_TXCN VSS[187] VSS[287] VSS[28] VSS[107]
[26] INT_TXLOUTP0 AN47 AV49 INT_HDMI_TXCP [28] BC32 P11 AD34 AN31
INT_TXLOUTP0 LVDSA_DATA0 DDPB_3P INT_HDMI_TXCP VSS[188] VSS[288] VSS[29] VSS[108]
[26] INT_TXLOUTP1 AM49 BC34 P18 AD36 AP12
INT_TXLOUTP1 LVDSA_DATA1 VSS[189] VSS[289] VSS[30] VSS[109]
[26] INT_TXLOUTP2 AK49 BC36 T33 AD37 AP19
INT_TXLOUTP2 LVDSA_DATA2 VSS[190] VSS[290] VSS[31] VSS[110]
AJ47 P46 BC40 P40 AD38 AP28
LVDSA_DATA3 DDPC_CTRLCLK P42 BC42 VSS[191] VSS[291] P43 AD39 VSS[32] VSS[111] AP30
x
C DDPC_CTRLDATA BC48 VSS[192] VSS[292] P47 AD4 VSS[33] VSS[112] AP32 C
INT_TXUCLKOUTN AF40 BD46 VSS[193] VSS[293] P7 AD40 VSS[34] VSS[113] AP38
[26] INT_TXUCLKOUTN LVDSB_CLK# VSS[194] VSS[294] VSS[35] VSS[114]
[26] INT_TXUCLKOUTP INT_TXUCLKOUTP AF39 AP47 BD5 R2 AD42 AP4
LVDSB_CLK DDPC_AUXN AP49 BE22 VSS[195] VSS[295] R48 AD43 VSS[36] VSS[115] AP42
INT_TXUOUTN0 AH45 DDPC_AUXP AT38 BE26 VSS[196] VSS[296] T12 AD45 VSS[37] VSS[116] AP46
[26] INT_TXUOUTN0 LVDSB_DATA#0 DDPC_HPD VSS[197] VSS[297] VSS[38] VSS[117]
fi
[26] INT_TXUOUTN1 AH47 BE40 T31 AD46 AP8
INT_TXUOUTN1 LVDSB_DATA#1 VSS[198] VSS[298] VSS[39] VSS[118]
[26] INT_TXUOUTN2 AF49 AY47 BF10 T37 AD8 AR2
INT_TXUOUTN2 LVDSB_DATA#2 DDPC_0N VSS[199] VSS[299] VSS[40] VSS[119]
AF45 AY49 BF12 T4 AE2 AR48
LVDSB_DATA#3 DDPC_0P AY43 BF16 VSS[200] VSS[300] W34 AE3 VSS[41] VSS[120] AT11
INT_TXUOUTP0 AH43 DDPC_1N AY45 BF20 VSS[201] VSS[301] T46 AF10 VSS[42] VSS[121] AT13
[26] INT_TXUOUTP0 LVDSB_DATA0 DDPC_1P VSS[202] VSS[302] VSS[43] VSS[122]
[26] INT_TXUOUTP1 AH49 BA47 BF22 T47 AF12 AT18
INT_TXUOUTP1 LVDSB_DATA1 DDPC_2N VSS[203] VSS[303] VSS[44] VSS[123]
[26] INT_TXUOUTP2 AF47 BA48 BF24 T8 AD14 AT22
INT_TXUOUTP2 LVDSB_DATA2 DDPC_2P VSS[204] VSS[304] VSS[45] VSS[124]
AF43 BB47 BF26 V11 AD16 AT26
a
LVDSB_DATA3 DDPC_3N BB49 BF28 VSS[205] VSS[305] V17 AF16 VSS[46] VSS[125] AT28
DDPC_3P BD3 VSS[206] VSS[306] V26 AF19 VSS[47] VSS[126] AT30
BF30 VSS[207] VSS[307] V27 AF24 VSS[48] VSS[127] AT32
INT_CRT_BLU N48 M43 BF38 VSS[208] VSS[308] V29 AF26 VSS[49] VSS[128] AT34
[27] INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK VSS[209] VSS[309] VSS[50] VSS[129]
[27] INT_CRT_GRE P49 M36 BF40 V31 AF27 AT39
INT_CRT_GRE CRT_GREEN DDPD_CTRLDATA VSS[210] VSS[310] VSS[51] VSS[130]
in
[27] INT_CRT_RED T49 BF8 V36 AF29 AT42
INT_CRT_RED CRT_RED VSS[211] VSS[311] VSS[52] VSS[131]
BG17 V39 AF31 AT46
AT45 BG21 VSS[212] VSS[312] V43 AF38 VSS[53] VSS[132] AT7
DDPD_AUXN VSS[213] VSS[313] VSS[54] VSS[133]
CRT
[27] INT_DDCCLK T39 AT43 BG33 V7 AF4 AU24

INT_DDCCLK INT_DDCDAT M40 CRT_DDC_CLK DDPD_AUXP BH41 BG44 VSS[214] VSS[314] W17 AF42 VSS[55] VSS[134] AU30
[27] INT_DDCDAT CRT_DDC_DATA DDPD_HPD VSS[215] VSS[315] VSS[56] VSS[135]
BG8 W19 AF46 AV16
BB43 BH11 VSS[216] VSS[316] W2 AF5 VSS[57] VSS[136] AV20
INT_CRT_HSYNC M47 DDPD_0N BB45 BH15 VSS[217] VSS[317] W27 AF7 VSS[58] VSS[137] AV24
[27] INT_CRT_HSYNC CRT_HSYNC DDPD_0P VSS[218] VSS[318] VSS[59] VSS[138]
[27] INT_CRT_VSYNC M49 BF44 BH17 W48 AF8 AV30
INT_CRT_VSYNC CRT_VSYNC DDPD_1N VSS[219] VSS[319] VSS[60] VSS[139]
BE44 BH19 Y12 AG19 AV38
B DAC_IREF T43
T42 DAC_IREF
CRT_IRTN
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
BF42
BE42
BJ42
h H10
BH27
BH31
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
Y38
Y4
Y42
AG2
AG31
AG48
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
AV4
AV43
AV8
B
1
BG42 BH33 Y46 AH11 AW14

DDPD_3P BH35 VSS[224] VSS[324] Y8 AH3 VSS[65] VSS[144] AW18
R116 BD82HM77-SLJ8C-MM#915664 BH39 VSS[225] VSS[325] BG29 AH36 VSS[66] VSS[145] AW2
.c
1K/F_4 BH43 VSS[226] VSS[328] N24 AH39 VSS[67] VSS[146] AW22
BH7 VSS[227] VSS[329] AJ3 AH40 VSS[68] VSS[147] AW26
2
D3 VSS[228] VSS[330] AD47 AH42 VSS[69] VSS[148] AW28

D12 VSS[229] VSS[331] B43 AH46 VSS[70] VSS[149] AW32
D16 VSS[230] VSS[333] BE10 AH7 VSS[71] VSS[150] AW34
D18 VSS[231] VSS[334] BG41 AJ19 VSS[72] VSS[151] AW36
D22 VSS[232] VSS[335] G14 AJ21 VSS[73] VSS[152] AW40
D24 VSS[233] VSS[337] H16 AJ24 VSS[74] VSS[153] AW48
D26 VSS[234] VSS[338] T36 AJ33 VSS[75] VSS[154] AV11
R & C place close to PCH
w
D30 VSS[235] VSS[340] BG22 AJ34 VSS[76] VSS[155] AY12

R273 1 2 150/F_4 INT_CRT_BLU D32 VSS[236] VSS[342] BG24 AK12 VSS[77] VSS[156] AY22
D34 VSS[237] VSS[343] C22 AK3 VSS[78] VSS[157] AY28
R275 1 2 150/F_4 INT_CRT_GRE D38 VSS[238] VSS[344] AP13 VSS[79] VSS[158]
D42 VSS[239] VSS[345] M14 BD82HM77-SLJ8C-MM#915664
R274 1 2 150/F_4 INT_CRT_RED D8 VSS[240] VSS[346] AP3
+3.3V_RUN E18 VSS[241] VSS[347] AP1
w
E26 VSS[242] VSS[348] BE16

G18 VSS[243] VSS[349] BC16
LCD_DDCDAT RP5 1 2 2.2KX2 G20 VSS[244] VSS[350] BG28
HDMI_SDA 3 4 G26 VSS[245] VSS[351] BJ28
DIS_L_CTRL_CLK RP6 1 2 2.2KX2 G28 VSS[246] VSS[352]
LCD_DDCCLK 3 4 G36 VSS[247]
DIS_L_CTRL_DATA RP7 1 2 2.2KX2 G48 VSS[248]
w
HDMI_SCL 3 4 H12 VSS[249]

A VSS[250] A
H18
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34
F3
VSS[256]
VSS[257]
VSS[258]
PROJECT : JWA
BD82HM77-SLJ8C-MM#915664 2A
Panther Point 2/7
1
20 of 54
5 4 3 2 1
fix Cougar Point/Panther Point (HDA,JTAG,SATA)
v ina 18P/50V_4 2 1 C501 KB_DET#

RP16
1
10KX2
2
+3.3V_RUN
IRQ_SERIRQ 3 4
1
Y4 U21A
32.768KHZ R288
10M_4 RTC_X1 A20 C38 LPC_LAD0 [35,38]
RTCX1 FWH0 / LAD0 A38 LPC_LAD1 LPC_LAD0
[35,38]
2
FWH1 / LAD1 LPC_LAD1
LPC
18P/50V_4 2 1 C498 RTC_X2 C20 B37 LPC_LAD2 [35,38]
RTCX2 FWH2 / LAD2 C37 LPC_LAD3 LPC_LAD2
D [35,38] D
RTC_RST# D20 FWH3 / LAD3 LPC_LAD3
RTCRST# D36 LPC_LFRAME#
FWH4 / LFRAME# LPC_LFRAME# [35,38]
SRTC_RST# G22
SRTCRST# E36 LPC_LDRQ0#
LDRQ0# TP28
1 2 1M_4 K22
RTC
R149 SM_INTRUDER# K36 LCD_CE
m
+RTC_CELL INTRUDER# LDRQ1# / GPIO23 TP25
PCH_INTVRMEN C17 +3V V5 IRQ_SERIRQ [38]
INTVRMEN SERIRQ IRQ_SERIRQ
EC31 2 1 *22P/50V_4_NC
AM3 SATA_RXN0 [34]

SATA0RXN SATA_RXN0
[36] ACZ_BITCLK R119 1 2 33_4 ACZ_BITCLK_R N34 AM1 SATA_RXP0 [34]
ACZ_BITCLK HDA_BCLK SATA0RXP SATA_RXP0
AP7 SATA_TXN0 SATA HDD/SSD
SATA 6G
SATA0TXN SATA_TXN0 [34]
R117 1 2 33_4 L34 AP5
o
ACZ_SYNC_R1 ACZ_SYNC_R SATA_TXP0 [34]
HDA_SYNC SATA0TXP SATA_TXP0
[36] ACZ_SPKR ACZ_SPKR T10 AM10 SATA_RXN1 [35]

ACZ_SPKR SPKR SATA1RXN SATA_RXN1
AM8 SATA_RXP1 [35]
SATA1RXP SATA_RXP1
[36] ACZ_RST# R118 1 2 33_4 ACZ_RST#_R K34 AP11 SATA_TXN1 [35] mSATA
ACZ_RST# HDA_RST# SATA1TXN SATA_TXN1
AP10 SATA_TXP1 [35]
SATA1TXP SATA_TXP1
.c
[36] ACZ_SDIN0 E34 AD7
ACZ_SDIN0 HDA_SDIN0 SATA2RXN AD5
G34 SATA2RXP AH5
TP27 HDA_SDIN1 SATA2TXN AH4
C34 SATA2TXP
HDA_SDIN2 AB8 SATA_RXN3 +RTC_CELL
IHDA
SATA3RXN SATA_RXN3 [34]
[38] PCH_MELOCK R125 1 2 1K_4 A34 AB10 SATA_RXP3 [34]
PCH_MELOCK HDA_SDIN3 SATA3RXP SATA_RXP3
AF3 SATA_TXN3 [34] SATA ODD
SATA3TXN SATA_TXN3
AF1 SATA_TXP3 RTC_RST# R150 1 2 20K/F_4
x
SATA3TXP SATA_TXP3 [34]
C
[36] ACZ_SDOUT R284 1 2 33_4 ACZ_SDOUT_R A36 C
ACZ_SDOUT HDA_SDO Y7 SRTC_RST# R142 1 2 20K/F_4
SATA
SATA4RXN Y5
W W AN_RADIO_DIS# C36 SATA4RXP AD3
TP31 HDA_DOCK_EN# / GPIO33 +3V SATA4TXN AD1
SATA4TXP
1
fi
N32 +3V_S5 C304 C283
HDA_DOCK_RST# / GPIO13 Y3
Q19 SATA5RXN Y1 1U/6.3V_4 1U/6.3V_4
2
2N7002W SATA5RXP AB3
PCH_JTAG_TCK J3 SATA5TXN AB1
TP79 JTAG_TCK SATA5TXP
[36] 1 3 ACZ_SYNC_R1
ACZ_SYNC
PCH_JTAG_TMS H7 Y11
TP76 JTAG_TMS SATAICOMPO
JTAG
a
1
PCH_JTAG_TDI K5 Y10 SATA_COMP R162 1 2 37.4/F_4 +1.05V_PCH

TP44
2
R120 JTAG_TDI SATAICOMPI

R128
1M_4 PCH_JTAG_TDO H1
TP77 JTAG_TDO
+5V_RUN AB12
SATA3RCOMPO
2
in
AB13 SATA3_COMPR159 1 2 49.9/F_4
10K/F_4 SATA3COMPI
[39] PCH_SPI_CLK T3 AH1 SATA3_RBIASR308 1 2 750/F_4

PCH_SPI_CLK SPI_CLK SATA3RBIAS
[39] PCH_SPI_CS0# Y14
PCH_SPI_CS0# SPI_CS0#
T1
TP78 SPI_CS1#
SPI
P3 PCH_SATA_LED#
SATALED# PCH_SATA_LED# [29]
B [39]
[39]
PCH_SPI_SI
PCH_SPI_SO
EC34
PCH_SPI_SI
PCH_SPI_SO
*10P/50V_4_NC
V4
U3
h
SPI_MOSI
SPI_MISO
+3V
+3V
SATA0GP / GPIO21
SATA1GP / GPIO19
V14
P1
KB_DET# TP45
B
.c
2 1 PCH_SPI_CLK
2 1 ACZ_BITCLK
EC30 *10P/50V_4_NC
PCH Strap Table

w
Pin Name Strap description Sampled Configuration note

0 = Default (weak pull-down 20K)
SPKR No reboot mode setting PWROK 1 = Setting to No-Reboot mode
w
0 = Default (weak pull-down 20K)

HDA_SDO Flash Descriptor Security PWROK 1 = Override
w
A A
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +RTC_CELL R294 1 2 330K_4 PCH_INTVRMEN
0 = Support by 1.8V (weak PD) +3.3V_SUS R115 1 2 1K_4 ACZ_SYNC_R Quanta Computer Inc.
HDA_SYNC On-Die PLL VR Volatge Select RSMRST 1 = Support by 1.5V
PROJECT : JWA
3A
Panther Point 3/7
1
21 of 54
5 4 3 2 1
f ix
ina
U21E
AY7
Cougar Point-M/Panther Point (PCI,USB,NVRAM) RSVD1
v
AV7
BG26 RSVD2 AU3
BJ26 TP1 RSVD3 BG4
+3.3V_RUN BH25 TP2 RSVD4
+3.3V_SUS BJ16 TP3 AT10
RP9 BG16 TP4 RSVD5 BC8
RP8 10 1 USB_OC6# AH38 TP5 RSVD6
USB_OC4# 9 2 USB_OC0# AH37 TP6 AU2
5 6 PCIE_MCARD2_DET# USB_OC1# 8 3 SIO_EXT_W AKE# AK43 TP7 RSVD7 AT4
PCI_PIRQA# 4 7 HDD_FALL_INT1 USB_OC2# 7 4 USB_OC5# AK45 TP8 RSVD8 AT3
PCI_PIRQB# 3 8 SATA_ODD_MD# USB_OC3# 6 5 C18 TP9 RSVD9 AT1
D D
PCI_PIRQC# 2 9 TS_RST# N30 TP10 RSVD10 AY3
PCI_PIRQD# 1 10 10KX8 H3 TP11 RSVD11 AT5
AH12 TP12 RSVD12 AV3
+3.3V_RUN AM4 TP13 RSVD13 AV1
8.2KX8 AM5 TP14 RSVD14 BB1
m
DGPU_HOLD_RST# 10K_4 2 1 R106 Y13 TP15 RSVD15 BA3
LCD_DBC 10K_4 2 1 R102 K24 TP16 RSVD16 BB5
DGPU_PW R_EN 10K_4 2 1 R105 L24 TP17 RSVD17 BB3
INT_H 10K_4 2 1 R104 AB46 TP18 RSVD18 BB7
AB45 TP19 RSVD19 BE8
TP20 RSVD20
RSVD
BD4
RSVD21 BF6
RSVD22
o
B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
BG46 TP23 AT8
TP24 RSVD25
USB3.0
.c
AY5
RSVD26 BA2
USB3.0_RX1- BE28 RSVD27
[32] USB3.0_RX1- TP25 USB30_RX1N
[31] USB3.0_RX2- BC30 USB30_RX2N AT12
USB3.0_RX2- TP26 RSVD28
[32] USB3.0_RX3- BE32 USB30_RX3N BF3
USB3.0_RX3- TP27 RSVD29
BJ32 USB30_RX4N
SJ6 USB3.0_RX1+ BC28 TP28
[32] USB3.0_RX1+ TP29 USB30_RX1P
SJ0402 [31] USB3.0_RX2+ BE30 USB30_RX2P
USB3.0_RX2+ TP30
PCI_PLTRST# 2 1 [7,30,33,35,38] [32] USB3.0_RX3+ BF32 USB30_RX3P
2 1 PLTRST# USB3.0_RX3+ TP31
BG32 C24 USBP0N
x
TP32 USB30_RX4P USBP0N USBP0N [32]
C
[32] USB3.0_TX1- AV26 USB30_TX1N A24 USBP0P [32] USB2.0/USB3.0 COMBO C
USB3.0_TX1- TP33 USBP0P USBP0P
[31] USB3.0_TX2- BB26 USB30_TX2N C25 USBP1N [31]
USB3.0_TX2- TP34 USBP1N USBP1N
[32] USB3.0_TX3- AU28 USB30_TX3N B25 USBP1P [31] USB2.0/USB3.0 COMBO
USB3.0_TX3- TP35 USBP1P USBP1P
AY30 USB30_TX4N C26 USBP2N [32]
USB3.0_TX1+ AU26 TP36 USBP2N A26 USBP2P USBP2N
[32] USB3.0_TX1+ TP37 USB30_TX1P USBP2P USBP2P [32] USB2.0/USB3.0 COMBO
fi
[31] USB3.0_TX2+ AY26 USB30_TX2P K28
USB3.0_TX2+ TP38 USBP3N
[32] USB3.0_TX3+ AV28 H28
USB3.0_TX3+ TP39 USB30_TX3P USBP3P
AW30 E28 USBP4N [35]
TP40 USB30_TX4P USBP4N USBP4N
D28 USBP4P [35] (WLAN/BT)
USBP4P C28 USBP4P
USBP5N A28
USBP5P C29
USBP6N B29
a
PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
Pin Name Strap description Sampled Configuration PIRQB# USBP7P
PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
PIRQD# USBP8P G30 USBP9N
Should not be pull-down USBP9N USBP9N [43]
in
GNT2# / GPIO53 ESI strap (Server only) PWROK DGPU_HOLD_RST# C46 +5V E30 USBP9P AUO-eTP
(weak pull-up 20K) [14] DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USBP9P [43]
USB
[26] LCD_DBC C44 +5V C30
LCD_DBC REQ2# / GPIO52 USBP10N
DGPU_PW R_EN E40 +5V A30
[54] DGPU_PW R_EN REQ3# / GPIO54 USBP10P L32
1
0 = "top-block swap" mode D47 USBP11N K32
GNT3# / GPIO55 Top-Block Swap Override PWROK 1 = Default (weak pull-up 20K) GNT1# / GPIO51 +3V USBP11P
PCIE_MCARD2_DET# E42 +3V G32 USBP12N [43]
TP21 PCI_GNT3# F46 GNT2# / GPIO53 USBP12N E32 USBP12P USBP12N
GNT3# / GPIO55 +3V USBP12P USBP12P [43] Camera
C32 USBP13N [43]
USBP13N A32 USBP13P USBP13N
USBP13P USBP13P [43] Touch screen
HDD_FALL_INT1 G42 +3V
B
GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK Bit 0
1
Bit 1
1
Boot Location
SPI
h [34]
[43]
[43]
SATA_ODD_MD#
TS_RST#
INT_H
TP39
SATA_ODD_MD#
TS_RST#
INT_H
PCI_PME#
G40
C42
D44
K10
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
+3V
+3V
+3V
USBRBIAS#
USBRBIAS
C33
B33
USB_BIAS R123 1 2 22.6/F_4
1 B
.c
* PME#
GPIO19 Boot BIOS Selection 0 [bit-0] PWROK PCI_PLTRST# C6 +3V_S5 A14 USB_OC0#
0 0
4 PLTRST#
+3V_S5
OC0# / GPIO59 K20 USB_OC1#
USB_OC0# [31]
LPC OC1# / GPIO40 B17
USB_OC1# [32]
*22_4_NC +3V_S5 USB_OC2#
CLK_33M_LPC R277 1 2 CLK_33M_LPC_R H49 OC2# / GPIO41 C16 USB_OC3#
[35] CLK_33M_LPC CLKOUT_PCI0 +3V_S5 OC3# / GPIO42
Default weak pull-up on GNT0/1# 22_4 H43 +3V_S5 L16 USB_OC4#
CLK_33M_KBC R276 1 2 CLK_33M_KBC_R J48 CLKOUT_PCI1 OC4# / GPIO43 A16 USB_OC5#
[Need external pull-down for LPC [38] CLK_33M_KBC CLKOUT_PCI2 +3V_S5 OC5# / GPIO9
22_4 K42 +3V_S5 D14 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10
BIOS] [23] CLK_PCI_FB R122 1 2 CLK_PCI_FB_R H40 +3V_S5 C14 SIO_EXT_W AKE# [38]
w
CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 SIO_EXT_W AKE#
w
DF_TVS DMI and FDI Tx/Rx

Termination Voltage PWROK weak pull-down 20kohm
EC60 *10P/50V_4_NC
2 1 CLK_33M_KBC
w
A
R178 2 1 2.2K_4 +1.8V_RUN A
2 1 DF_TVS [24]
DF_TVS
R177 1K_4 EC61 *10P/50V_4_NC
H_SNB_IVB# [7] 2 1 CLK_33M_LPC
H_SNB_IVB#
EC32 *10P/50V_4_NC
2 1 CLK_PCI_FB
PROJECT : JWA
3A
Panther Point 4/7
1
22 of 54
5 4 3 2 1
f ix Cougar Point-M/Panther Point (PCI-E,SMBUS,CLK) SMBus/Pull-up(CLG)
ina
U21B
v
+3.3V_RUN
[35] PCIE_RXN1 BG34
PCIE_RXN1 PERN1
WLAN [35] PCIE_RXP1 BJ34 +3V_S5 E12 PCH_SMB_ALERT# R169 *0_4_NC [40]
PCIE_RXP1 PERP1 SMBALERT# / GPIO11 SMB_INT#
[35] PCIE_TXN1 C495 2 1 0.1U/16V_4 PCIE_TXN1_CAV32
PCIE_TXN1 PETN1
1
3
[35] PCIE_TXP1 C494 2 1 0.1U/16V_4 PCIE_TXP1_CAU32 H14 SMBCLK
PCIE_TXP1 PETP1 SMBCLK RP14
BE34 C9 SMBDATA
BF34 PERN2 SMBDATA 2.2KX2
BB32 PERP2
AY32 PETN2
2
4
PETP2
SMBUS
D +3V_S5 A12 DDR_HVREF_RST_PCH SMBCLK D
SML0ALERT# / GPIO60 DDR_HVREF_RST_PCH [7] SMBCLK [13,40]
[33] BG36
PCIE_RXN3_CR PERN3
[33] BJ36 C8 SML0CLK
PCIE_RXP3_CR PERP3 SML0CLK
Card Reader
[33] C493 2 1 0.1U/16V_4 PCIE_TXN3_CR_C AV34
PCIE_TXN3_CR PETN3
[33] C492 2 1 0.1U/16V_4 PCIE_TXP3_CR_C AU34 G12 SML0DATA
PCIE_TXP3_CR PETP3 SML0DATA
m
BF36
BE36 PERN4 SMBDATA
PERP4 SMBDATA [13,40]
AY34 +3V_S5 C13 PCH_GPIO74
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74
PETP4 E14 SMB_CLK_ME1
+3V_S5 SML1CLK / GPIO58
BG37
PCI-E*
[30] PCIE_RXN5
PCIE_RXN5 PERN5
LAN [30] PCIE_RXP5 BH37 +3V_S5 M16 SMB_DATA_ME1 Q23A
PCIE_RXP5 PERP5 SML1DATA / GPIO75
C489 2 1 0.1U/16V_4 PCIE_TXN5_CAY36
o
[30] PCIE_TXN5
PCIE_TXN5 PETN5
[30] PCIE_TXP5 C491 2 1 0.1U/16V_4 PCIE_TXP5_CBB36 SMB_CLK_ME1 4 3 SMBCLK1 [38]
PCIE_TXP5 PETP5 SMBCLK1
DMN66D0LDW -7
BJ38
BG38 PERN6
5
AU36 PERP6 M7
Controller
PETN6 CL_CLK1 +3.3V_SUS
.c
AV36
PETP6
2
Link
BG40 T11
BJ40 PERN7 CL_DATA1 DMN66D0LDW -7
AY40 PERP7 SMB_DATA_ME1 1 6 SMBDAT1
PETN7 SMBDAT1 [38]
BB40 P10 Q23B
PETP7 CL_RST1#
BE38
BC38 PERN8
AW38 PERP8 +3.3V_SUS
x
C AY38 PETN8 C
PETP8
+3V_S5 M10 PEG_A_CLKRQ# PCH_GPIO74 RP11 1 2 10KX2
PEG_A_CLKRQ# / GPIO47 PEG_A_CLKRQ# [14]
[35] CLK_PCIE_W LANN CLK_PCIE_W LANN Y40 PCH_SMB_ALERT# 3 4
CLK_PCIE_W LANP Y39 CLKOUT_PCIE0N
WLAN [35] CLK_PCIE_W LANP CLKOUT_PCIE0P
fi
AB37 CLK_PCIE_VGAN
CLKOUT_PEG_A_N CLK_PCIE_VGAN [14]
PCIE_CLK_REQ0# J2 +3V_S5 AB38 CLK_PCIE_VGAP
CLOCKS
[35] PCIE_CLK_REQ0# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGAP [14]
AB49 AV22 CLK_CPU_BCLKN SML0CLK RP13 3 4 2.2KX2

CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_BCLKN [7]
AB47 AU22 CLK_CPU_BCLKP SML0DATA 1 2
CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_BCLKP [7]
SMB_CLK_ME1 RP10 3 4 2.2KX2
PCIE_CLK_REQ1# M1 +3V SMB_DATA_ME1 1 2
a
PCIECLKRQ1# / GPIO18 AM12
CLKOUT_DP_N AM13 +3.3V_SUS
CLK_PCIE_CRN AA48 CLKOUT_DP_P RP24 10KX4
[33] CLK_PCIE_CRN CLKOUT_PCIE2N
Card Reader [33] CLK_PCIE_CRP CLK_PCIE_CRP AA47 PCIE_CLK_REQ0# 1 2
CLKOUT_PCIE2P BF18 CLK_DMI PCIE_CLK_REQ4# 3 4
CLKIN_DMI_N
in
[33] PCIE_CLK_REQ2# PCIE_CLK_REQ2# V10 +3V BE18 R155 1 2 10K_4 PCIE_CLK_REQ3# 5 6
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P PCIE_W AKE# 7 8
[19] PCIE_W AKE#
PCIE_CLK_REQ6# 3 4 10KX2
Y37 BJ30 PCIE_CLK_REQ7# 1 2
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 R134 1 2 10K_4 RP12
CLKOUT_PCIE3P CLKIN_GND1_P PEG_B_CLKRQ# 1 2
PCIE_CLK_REQ3# A8 +3V_S5 10K_4 R166
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREFCLK
CLKIN_DOT_96N E24 R132 1 2 10K_4 +3.3V_RUN
CLK_PCIE_LANN Y43 CLKIN_DOT_96P
B
LAN
[30] CLK_PCIE_LANN
[30] CLK_PCIE_LANP
[30] PCIE_CLK_REQ4#
CLK_PCIE_LANP
PCIE_CLK_REQ4#
Y45
L12
V45
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26 +3V_S5 h CLKIN_SATA_N

CLKIN_SATA_P
AK7 CLK_BUF_DREFSSCLK
AK5
K45 CLK_PCH_14M
R309 1 2 10K_4
PCIE_CLK_REQ2#
PCIE_CLK_REQ1#
1
3
RP25
2
4
10KX2
+3.3V_SUS
B
.c
V46 CLKOUT_PCIE5N REFCLK14IN PEG_A_CLKRQ# 10K_4 1 2 R173
CLKOUT_PCIE5P
[19] PCIE_CLK_REQ5# PCIE_CLK_REQ5# L14 +3V_S5 H45 CLK_PCI_FB [22] C488 1 2 27P/50V_4
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB
2
AB42 V47 XTAL25_IN Y3 CLK_REQ/Strap Pin(CLG)
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT R282
CLKOUT_PEG_B_P XTAL25_OUT 25MHz
1M_4
1
PEG_B_CLKRQ# E6 +3V_S5
w
2
PEG_B_CLKRQ# / GPIO56 C487 1 2 27P/50V_4
Y47 XCLK_RCOMP
V40 XCLK_RCOMP R113 90.9/F_4 Stuff for Integrated CLK Gen Mode
V42 CLKOUT_PCIE6N 1 2
CLKOUT_PCIE6P +1.05V_PCH
PCIE_CLK_REQ6# T13 +3V_S5
PCIECLKRQ6# / GPIO45 CLK_PCH_14M R103 1 2 10K_4
w
V38 +3V K43 CLK_48M_CARD_R TP24

CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
V37
CLKOUT_PCIE7P F47 CLK_VGA_27M_R TP22
+3V CLKOUTFLEX1 / GPIO65
PCIE_CLK_REQ7# K12 +3V_S5
PCIECLKRQ7# / GPIO46 H47 CLK_FLEX2 TP70
+3V CLKOUTFLEX2 / GPIO66
XDP CLK_PCIE_XDPN AK14
AK13 CLKOUT_ITPXDP_N K49
CLK_PCIE_XDPP +3V AP_24M [36]
w
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67

A A
Configurable as a GPIO or as a programmable output clock
which can be configured as one of the following:
CLKOUTFLEX0 /GPIO64 ‧33 /27 /48/ 14.318 MHz / DC Output logic ‘0’
CLKOUTFLEX1 /GPIO65 unsupported clock output value (Default) / 27/ 14.318 MHz output to SIO/EC /48/24 MHz
CLKOUTFLEX2 /GPIO66 ‧ 33/25/27/48/24/14.318 MHz / DC Output logic ‘0’ PROJECT : JWA
CLKOUTFLEX3 /GPIO67 ‧ 27/14.318 output to SIO/48/24 MHz (Default) Panther Point 5/7 3A
1
23 of 54
5 4 3 2 1
fix Point/Panther Point (GPIO,VSS_NCTF,RSVD)

Cougar
vina
U21F
BMBUSY# T7 +3V +3V C40 MEM_BOARD_ID2

BMBUSY# / GPIO0 TACH4 / GPIO68
[38] SIO_EXT_SMI# A42 +3V +3V B41 PCH_GPIO69

SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69
[35] PCIE_MCARD1_DET# PCIE_MCARD1_DET# H36 +3V +3V C41 PCH_GPIO70
TACH2 / GPIO6 TACH6 / GPIO70
D D
[38] SIO_EXT_SCI# E38 +3V +3V A40 PCH_GPIO71
SIO_EXT_SCI# TACH3 / GPIO7 TACH7 / GPIO71
TP36 BD2 C10 +3V_S5
GPIO8
LAN_PHY_PW R_CTRL C4 +3V_S5
m
LAN_PHY_PWR_CTRL / GPIO12
HOST_ALERT#1 G2 P4 SIO_A20GATE
GPIO15 +3V_S5 A20GATE SIO_A20GATE [38]
AU16
SATA_MCARD3_DET# U2 PECI
[35] SATA_MCARD3_DET# SATA4GP / GPIO16 +3V P5 SIO_RCIN#
RCIN# SIO_RCIN# [38]
GPIO
D40 AY11
o
TP26 DGPU_PW ROK +3V H_PW RGOOD
TACH0 / GPIO17 PROCPWRGD H_PW RGOOD [7]
CPU/MISC
DGPU_VREN T5 +3V AY10 PCH_THRMTRIP# 1 2 PM_THRMTRIP#
SCLOCK / GPIO22 THRMTRIP# PM_THRMTRIP#[7]
TP41 CAP_LED E8 T14 R165 390_4
GPIO24 / MEM_LED +3V_S5 INIT3_3V#
.c
MEM_BOARD_ID0 E16 DSW AY1 DF_TVS [22]
GPIO27 DF_TVS DF_TVS
PLL_ODVR_EN P8 +3V_S5
GPIO28 AH8
MEM_BOARD_ID1 K1 TS_VSS1
STP_PCI# / GPIO34 +3V
AK11
USB_MCARD1_DET# K4 TS_VSS2
[35] USB_MCARD1_DET# GPIO35 +3V AH10
CAMERA_CBL_DET# V8 TS_VSS3
SATA2GP / GPIO36 +3V +3.3V_RUN
AK10
x
C TP43 TP_LED2 M5 TS_VSS4 C
SATA3GP / GPIO37 +3V
[35] W LAN_RADIO_DIS# W LAN_RADIO_DIS# N2 +3V P37 RP17 10KX4
SLOAD / GPIO38 NC_1 1 2 SIO_A20GATE
[35] BT_RADIO_DIS# M3 +3V 3 4 SIO_RCIN#
BT_RADIO_DIS# SDATAOUT0 / GPIO39
fi
5 6 SIO_EXT_SMI#
FFS_INT2 V13 +3V BG2 7 8 SIO_EXT_SCI#
SDATAOUT1 / GPIO48 VSS_NCTF_15
Default: On Board DDR3 MODC_EN V3 +3V BG48
[34] MODC_EN SATA5GP / GPIO49 VSS_NCTF_16
R285 10K/F_4 MEM_BOARD_ID2 R283 *10K/F_4_NC SV_DET D6 BH3 R180 1 2 10K_4 USB_MCARD1_DET#
+3.3V_RUN GPIO57 +3V_S5 VSS_NCTF_17
R312 *10K/F_4_NCMEM_BOARD_ID1 R311 10K/F_4 BH47 R316 1 2 10K_4 BT_RADIO_DIS#
a
VSS_NCTF_18 R126 1 2 10K_4 PCIE_MCARD1_DET#
R143 *10K/F_4_NCMEM_BOARD_ID0 R144 10K/F_4 +3.3V_SUS A4 BJ4 R183 1 2 10K_4 FFS_INT2
VSS_NCTF_1 VSS_NCTF_19 R317 1 2 10K_4 SATA_MCARD3_DET#
A44 BJ44 RP22 10KX4
VSS_NCTF_2 VSS_NCTF_20 1 2 PCH_GPIO69
in
A45 BJ45 3 4 PCH_GPIO70
VSS_NCTF_3 VSS_NCTF_21 5 6 PCH_GPIO71
NCTF
A46 BJ46 7 8
VSS_NCTF_4 VSS_NCTF_22
A5 BJ5
System Memory BOARD ID SETTING A6
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_23
VSS_NCTF_24
BJ6
+3.3V_SUS
B3 C2
GPIO68 GPIO35 GPIO27 VSS_NCTF_7 VSS_NCTF_25 R304 1 2 10K_4 LAN_PHY_PW R_CTRL
B
HYNIX DDR3-1600 2GB

SAMSUNG DDR3-1600 2GB
MEM_BOARD_ID2
0
0
MEM_BOARD_ID1
0
0
MEM_BOARD_ID0
0
1
h B47
BD1
BD49
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
C48
D1
D49
R171 1 2 *10K_4_NC CAP_LED
B
.c
BE1 E1 R170 2 1 *10K_4_NC DGPU_VREN
On Board DDR3 N.C 0 1 1 VSS_NCTF_11 VSS_NCTF_29
BE49 E49
RESERVE 0 1 0 VSS_NCTF_12 VSS_NCTF_30
BF1 F1
BF49 F49
RESERVE 1 1 1
w
RESERVE 1 1 0
Pin Name Strap description Sampled Configuration
+3.3V_SUS
w
GPIO28 On-die PLL Voltage Regulator RSMRST# 0 = Disable HOST_ALERT#1 R305 1 2 1K_4
1 = Enable (Default) +3.3V_SUS
R168 1 2 *1K_4_NC PLL_ODVR_EN Intel ME Crypto Transport Layer R172 1 2 10K_4 SV_DET
Security (TLS) cipher suite
w
A
Low = Disable (Default) A
BMBUSY#:(Intel feedback) High = Enable

SGPIO +3.3V_RUN
Follow CRB checklist, 1K is
CAMERA_CBL_DET# R164 1 2 10K_4
for intel BIOS validation purpose.
MFG-TEST Quanta Computer Inc.
Low = Tx, Rx terminated to BMBUSY#: +3.3V_RUN
DMI TERMINATION same voltage (DC Coupling Mode) BMBUSY# R176 1 2 10K_4
VOLTAGE OVERRIDE (DEFAULT)
If not used, require a weak pull-up
W LAN_RADIO_DIS# R314 1 2 10K_4 PROJECT : JWA
(8.2- KΩ to 10 kΩ) to Vcc3_3. R310 1 2 *0_4_NC Size Document Number Rev
CRB(V1.0)P28: it has 1K PU and 3A
Panther Point 6/7
http://vinafix.vn
100 ohm on this net for validation purpose.
5 4 3 2 1
5 4 3 2 1
f ix
ina Cougar Point/Panther Point (POWER) Cougar Point/Panther Point (POWER)
v
Tie to 3.3V_SUS, when +3.3V_SUS= 10mA(10mil) U21J POWER +1.05V_VCCUSBCORE +1.05V_PCH
don't support Deep SX TP71 AD49 N26

+3.3V_SUS VCCACLK VCCIO[29]
CP_v1.0 p88
P26 C269 1 2 1U/6.3V_4
C262 2 1 0.1U/16V_4 T16 VCCIO[30]
VccADAC =63mA(10mils) VCCDSW3_3
+3.3V_RUN P28
+3.3V_RUN VCCIO[31]
D R100 D
0_6 PCH_VCCDSW V12 T27
1 2 TP40 DCPSUSBYP VCCIO[32]
+VCCA_DAC_1_2
1
T29
+1.05V_PCH
1.7 A (70mils) U21G POWER C213 1 2 10U/6.3V_6 C216 C218 T38
VCC3_3[5]
VCCIO[33] +3.3V_SUS
C211 1 2 0.1U/16V_4 10U/6.3V_6 1U/6.3V_4 +3V_SUS_CLKF33 =30mA(10mils) +3.3V_SUS= 50mA(10mil)
2
C214 1 2 0.01U/25V_4 T23
VCCSUS3_3[7]
m
AA23 U48 BH23
AC23 VCCCORE[1] VCCADAC TP73 VCCAPLLDMI2 T24 C281 1 2 0.1U/16V_4
10U/6.3V_8 2 1 C277 AD21 VCCCORE[2] AL29 VCCSUS3_3[8]
CRT
VCCCORE[3] +1.05V_PCH VCCIO[14]
AD23 U47 +1.05V_VCCIO =40mA(10mils) V23
VCCCORE[4] VSSADAC VCCSUS3_3[9]
USB
1U/6.3V_4 2 1 C291 AF21
VCC CORE
1U/6.3V_4 2 1 C301 AF23 VCCCORE[5] AL24 V24
VCCCORE[6] +3.3V_RUN TP32 DCPSUS[3] VCCSUS3_3[10]
1U/6.3V_4 2 1 C324 AG21 +VCCALVDS C300 1 2 0.1U/16V_4
AG23 VCCCORE[7] P24
VCCCORE[8]
VccALVDS=1mA (10mils) VCCSUS3_3[6]
AG24 AK36 +3.3V_SUS= 100mA(10mil)
AG26 VCCCORE[9] VCCALVDS AA19
o
AG27 VCCCORE[10] AK37 VCCASW[1] T26
VCCCORE[11] VSSALVDS +1.8V_RUN VCCIO[34] +1.05V_PCH
AG29 AA21
AJ23 VCCCORE[12] VCCASW[2]
VCCCORE[13]
+5V_PCH_VCC5REFSUS=1mA(10mil)
LVDS
AJ26 AM37 AA24 M26 +5V_PCH_VCC5REFSUS 1 2 +5V_SUS
AJ27 VCCCORE[14] VCCTX_LVDS[1] VCCASW[3] V5REF_SUS R124 10_4
VCCCORE[15]
+1.8V_RUN=40mA (10mils)
AJ29 AM38 AA26 1 2 +3.3V_SUS
VCCCORE[16] VCCTX_LVDS[2] VCCASW[4]
Clock and Miscellaneous

AJ31 AN23 TP33 D14 SDM10K45-7-F
VCCCORE[17] DCPSUS[4]
.c
AP36 C242 1 2 10U/6.3V_8 AA27 1 2
+1.05V_PCH VCCTX_LVDS[3] C248 1 2 0.01U/25V_4 VCCASW[5] AN24 +3.3V_SUS C279 0.1U/16V_4
AP37 C254 1 2 0.01U/25V_4 +1.05V_PCH AA29 VCCSUS3_3[1]
+1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[4] VCCASW[6]
AN19
VCCIO[28] AA31
VccASW =0.903A VCCASW[7]
V5REF= 1mA(10mil)
(40mils)
TP74 BJ22 +3V_VCC_GIO +3.3V_RUN C163 2 1 10U/6.3V_8 AC26 P34 +5V_PCH_VCC5REF 1 2
VCCAPLLEXP VCCASW[8] V5REF +5V_RUN
Vcc3_3 = 0.228A (15mils) C261 2 1 10U/6.3V_8 R96 10_4
V33 AC27 1 2 +3.3V_RUN
VCC3_3[6] VCCASW[9]
HVCMOS
AN16 C246 2 1 1U/6.3V_4 N20 D13 SDM10K45-7-F

VCCIO[15] VCCSUS3_3[2]
PCI/GPIO/LPC
C271 2 1 1U/6.3V_4 AC29 C247 1 2 1U/6.3V_4
AN17 C255 1 2 0.1U/16V_4 C266 2 1 1U/6.3V_4 VCCASW[10] N22 +3.3V_SUS =
x
C VCCIO[16] V34 AC31 VCCSUS3_3[3] C
VCC3_3[7] VCCASW[11]
40mA (10mils)
P20 +3.3V_SUS
AN21 AD29 VCCSUS3_3[4]
VCCIO[17] VCCASW[12] P22 C311 1 2 1U/6.3V_4
+1.05V_PCH AN26 AD31 VCCSUS3_3[5]
VccIO =3.711 A(160mils) +1.5V_RUN
VCCIO[18] +1.05V_PCH VCCASW[13]
fi
AN27 AT16 W21 AA16 +3.3V_SUS =50mA(10mils) +3.3V_RUN
VCCIO[19] VCCVRM[3] VCCASW[14] VCC3_3[1]
AP21 W23 W16 C368 1 2 0.1U/16V_4
VCCIO[20] VCCASW[15] VCC3_3[8]
1U/6.3V_4 2 1 C259 AP23 AT20 C312 1 2 1U/6.3V_4 W24 T34 +3.3V_RUN
1U/6.3V_4 2 1 C320 VCCIO[21] VCCDMI[1] VCCASW[16] VCC3_3[4]
VccDMI =47mA (10mils)
DMI
1U/6.3V_4 2 1 C263 AP24 W26 C256 1 2 0.1U/16V_4

VCCIO[22] VCCASW[17]
VCCIO
1U/6.3V_4 2 1 C284
AP26 AB36 +1.05V_PCH W29
VCCIO[23] VCCCLKDMI VCCASW[18]
a
AT24 W31 AJ2 +3.3V_RUN
VCCIO[24] VCCASW[19] VCC3_3[2]
C250 1 2 1U/6.3V_4 W33 C508 1 2 0.1U/16V_4
AN33 VCCASW[20] AF13
+3.3V_RUN VCCIO[25] VCCIO[5]
+VCC_DMI_CCI= 70mA (10mils)
+3V_VCC_EXP AN34 AG16 C315 1 2 0.1U/16V_4 +VCCRTCEXT N16
VCCIO[26] VCCDFTERM[1] DCPRTC AH13 +1.05V_VCCIO= 400mA(20mils)
in
+1.8V_RUN VCCIO[12] +1.05V_PCH
C274 2 1 0.1U/16V_4 BH29 AG17 +1.5V_RUN
Y49 AH14 C321 1 2 1U/6.3V_4
VCC3_3[3] VCCDFTERM[2] VCCVRM[4] VCCIO[13]
DFT / SPI
+VCCP_NAND
VCCPNAND = 2 mA(10mils)
AJ16 +1.05V_PCH AF14
VCCDFTERM[3] +1.05V_PCH BD47 VCCIO[6]
80mA(10mils) VCCADPLLA
SATA
+1.5V_RUN
AP16 C309 1 2 0.1U/16V_4 AK1 TP46
VCCVRM[2] AJ17 +1.05V_PCH BF47 VCCAPLLSATA
VCCDFTERM[4]
80mA(10mils) VCCADPLLB
C313 2 1 1U/6.3V_4 +VCCDIFFCLK= 40mA(10mils)
BG6 AF11
TP42 VccAFDIPLL VCCVRM[1] +1.5V_RUN
+3V_VCCME_SPI AF17
VCCIO[7]
B
+1.05V_PCH
+1.05V_VCCIO=40mA(10mils)
AP17
VCCIO[27] V1
VCCSPI = 10mA(10mils)
+3.3V_RUN
h C249 2 1 1U/6.3V_4
VCCDIFFCLKN= 55mA(10mils)
AF33
AF34
AG34
VCCDIFFCLKN[1]
VCCDIFFCLKN[2] VCCIO[2]
AC16
+1.05V_PCH
B
FDI
VCCSPI VCCDIFFCLKN[3] AC17

AU20 C366 1 21U/6.3V_4 VCCIO[3]
+1.05V_PCH VCCDMI[2]
1
AG33 AD17
VCCSSC VCCIO[4] C294
VCCSSC= 95mA(10mils)
.c
VccDMI =0.047 A(10mils) BD82HM77-SLJ8C-MM#915664 C260 2 1 1U/6.3V_4 1U/6.3V_4
2
2 1 +VCCSST V16
C331 0.1U/16V_4 DCPSST
T17 T21 +1.05V_PCH

TP34 DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC
+VTT_VCCPCPU 1mA(10mils) V21
VCCASW[23]
CPU
+1.05V_PCH
BJ8
C337 2 1 4.7U/6.3V_6 V_PROC_IO T19
C338 2 1 0.1U/16V_4 VCCASW[21]
w
C267 2 1 *0.1U/16V_4_NC VCCSUSHDA= 10mA(10mils)

A22 P32
RTC
+RTC_CELL VCCRTC VCCSUSHDA +3.3V_SUS
HDA
C287 2 1 1U/6.3V_4
VCCRTC<1mA(10mils) C285 2 1 0.1U/16V_4
C286 2 1 *0.1U/16V_4_NC BD82HM77-SLJ8C-MM#915664 C293 1 2 0.1U/16V_4
w
+1.05V_PCH
1
C240
C237
10U/6.3V_8 1U/6.3V_4
w
A Closed VCCADPLLA A
1
C236
C238
10U/6.3V_8 1U/6.3V_4
2
Closed VCCADPLLB Quanta Computer Inc.

PROJECT : JWA
3A
Panther Point 7/7
5 4
http://vinafix.vn 3 2
1
Sheet 25 of 54
5 4 3 2 1
f ix Follow PDC LVDS pin define & LVDS connector P/N.
v ina
D 7 D
J1
1 USBP9N_L EL13 1 2 *DLP11SN900HL2L_NC USBP9N [43]
1 2 USBP9P_L 4 3 USBP9P USBP9N
2 USBP9P [43]
m
44 3 R326 2 1 *0_4_NC
44 3 4 8 5
4 +3.3V_RUN
43 5
42 43 5 6 +LCDVCC
41 42 6 7 LCD_TST
41 7 LCD_TST [38]
8 LCD_DDCCLK [20]
8 LCD_DDCCLK
1
9 LCD_DDCDAT [20] C424
9 10 INT_TXUCLKOUTN LCD_DDCDAT
10 INT_TXUCLKOUTN[20]
o
11 INT_TXUCLKOUTP [20] 0.1U/16V_4
INT_TXUCLKOUTP
2
11 12
12 13 INT_TXUOUTN2
13 INT_TXUOUTN2 [20]
14 INT_TXUOUTP2
14 INT_TXUOUTP2 [20]
+3.3V_RUN +LCDVCC 15
15 16 INT_TXUOUTN1
16 INT_TXUOUTN1 [20] EL13 R326 R280
.c
17 INT_TXUOUTP1
U15 17 INT_TXUOUTP1 [20]
18
4 1 18 19 INT_TXUOUTN0
IN OUT 19 INT_TXUOUTN0 [20]
5 20 INT_TXUOUTP0 AUO eTP
2
3
IN
GND
EN
20
21
22
21
22 INT_TXLCLKOUTN
INT_TXUOUTP0 [20]
INT_TXLCLKOUTN[20]
O O O
23 INT_TXLCLKOUTP
23 INT_TXLCLKOUTP[20]
1
1
C422 24 NON
C 0.1U/16V_4
G5243A C426
0.1U/16V_4
24
25
25
26
INT_TXLOUTN2
INT_TXLOUTP2
INT_TXLOUTN2 [20]
[20]
AUO eTP X X X C
x
INT_TXLOUTP2
2
2
26 27
27 28 INT_TXLOUTN0
28 INT_TXLOUTN0 [20]
29 INT_TXLOUTP0 [20]
29 INT_TXLOUTP0
30
30 31 INT_TXLOUTN1
31 INT_TXLOUTN1 [20]
32 INT_TXLOUTP1
fi
32 INT_TXLOUTP1 [20]
33 NV_PWM
D17 33 34 LCD_BAK
34 35 LCD_DBC_R R211 2 1 0_4 LCD_DBC
35 LCD_DBC [22]
[20] ENVDD 1 36 R280 2 1 *0_4_NC
ENVDD R213 36 +3.3V_RUN
37
3 EN_LCDVCC 1 2 37 38 8 5
38 39 +GFX_PWR_SRC
39
a
[38] LCDVCC_TST_EN 2 40
LCDVCC_TST_EN 10K_4 40
BAT54C T/R CONNECTOR SMD HEADER,4P,1R,MR(P1.25)
EMC Reserve
in
INT_TXLCLKOUTN EC46 1 2 3.3P INT_TXLCLKOUTP
INT_TXLOUTN2 EC42 1 2 3.3P INT_TXLOUTP2
+PWR_SRC
INT_TXUCLKOUTN EC44 1 2 3.3P INT_TXUCLKOUTP

B 40mil INT_TXUOUTN2 EC40 1 2 3.3P INT_TXUOUTP2 B
40mil
h 1
1
Q26
AO3409
3 INT_TXUOUTN1
INT_TXUOUTN0
EC45
EC41
1
1
2
2
3.3P
3.3P
INT_TXUOUTP1
INT_TXUOUTP0
2
1
C425
Backlight Enable
1
R212 0.1U/25V_6 C400
.c
100K_4
2
2 0.1U/25V_6
2
[38] LCD_BAK
LCD_BAK
1
2
Close to J1
R210 R214
10K_4 100K_4
w
2
1
LCD_BAK EC39 1 2 *100P/50V_4_NC
Brightness Control D16 RUN_ON 2

3
Q27
[38,48] RUN_ON
2N7002W
[20] LCD_PWM 1
LCD_PWM
1
w
3 NV_PWM
1
[38] PWM_VADJ 2
PWM_VADJ
R209
BAT54C T/R 10K_4
A A
w 2

PROJECT : JWA
2A
LVDS CONN
Date: Tuesday, March 05, 2013 Sheet 26 of 54
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
fix
v ina +5V_RUN
2
D18
SDM10K45-7-F
D D
1
Layout Note:
Setting R,G,B treac CRTF1
impedance to 50 ohm. EL3 1206L110THYR
m
BLM18BB750SN1D
[20] INT_CRT_RED 1 2 RED
INT_CRT_RED
+5V_CRT_REF
EL2
BLM18BB750SN1D
INT_CRT_GRE 1 2 GREEN
16
[20] INT_CRT_GRE
JVGA1
o
EL1
BLM18BB750SN1D 6
[20] INT_CRT_BLU 1 2 BLUE 1 11
INT_CRT_BLU
7
1
2 12
1
R64 R65 R66 EC21 EC23 EC26 EC22 EC24 EC25 8
.c
150/F_4 150/F_4 150/F_4 10P/50V_4 3 13
22P/50V_4 22P/50V_4 10P/50V_4 9
2
22P/50V_4 10P/50V_4 4 14
2
10
5 15
17
10296-00021
18
x
C +5V_CRT_REF C
+3.3V_RUN
fi
1
1
R261 R263 R262 R260
2.2K_4 2.2K_4 2.2K_4 2.2K_4
Q30
BSS138-7-F
2
INT_DDCDAT 1 3 G_DAT_DDC_C
a
[20] INT_DDCDAT
2
+3.3V_RUN
in
[20] INT_DDCCLK 1 3 G_CLK_DDC_C
INT_DDCCLK
+5V_RUN Q29
BSS138-7-F
h
5
B U4 B
[20] INT_CRT_HSYNC INT_CRT_HSYNC 2 4 HSYNC_R 1 2 HSYNC

ER2 33_4
.c
74AHCT1G125GW Place near
C140 74AHCT125 <
0.1U/16V_4
2 1
200 mil
5
U3
[20] INT_CRT_VSYNC INT_CRT_VSYNC 2 4 VSYNC_R 1 2 VSYNC

w
ER1 33_4
74AHCT1G125GW
w
w
A A

PROJECT : JWA
3A
VGA BOARD
Date: W ednesday, March 27, 2013 Sheet
1
27 of 54
1 2 3 4 5 6 7 8
f ix
ina
Reserve for EMI and close to HDMI CONN
v
EXC24CG900U EL6
HDMI_TX2-_R 4 3 HDMI_TX2-_C HDMI_TX0+_R 2 1 HDMI_TX0+_C
HDMI_TX2+_R 1 2 HDMI_TX2+_C HDMI_TX0-_R 3 4 HDMI_TX0-_C
EL7 EXC24CG900U
A A
m
EL5 EL4
HDMI_TX1+_R 1 2 HDMI_TX1+_C HDMI_CLK+_R 1 2 HDMI_CLK+_C
HDMI_TX1-_R 4 3 HDMI_TX1-_C HDMI_CLK-_R 4 3 HDMI_CLK-_C
EXC24CG900U EXC24CG900U
o
HDMI
.c
INT_HDMI_TXP2 C371 1 2 0.1U/16V_4 HDMI_TX2+_R
[20] INT_HDMI_TXP2
INT_HDMI_TXN2 C369 1 2 0.1U/16V_4 HDMI_TX2-_R
HDMI_HPD spec VinH_min=2.0V
[20] INT_HDMI_TXN2
[20] INT_HDMI_TXP1
[20] INT_HDMI_TXN1
INT_HDMI_TXP1
INT_HDMI_TXN1
C348 1
C344 1
2 0.1U/16V_4
2 0.1U/16V_4
HDMI_TX1+_R
HDMI_TX1-_R +3.3V_RUN HDMI HPD
INT_HDMI_TXP0 C353 1 2 0.1U/16V_4 HDMI_TX0+_R
x
[20] INT_HDMI_TXP0
B
[20] INT_HDMI_TXN0 INT_HDMI_TXN0 C362 1 2 0.1U/16V_4 HDMI_TX0-_R B
[20] INT_HDMI_TXCP INT_HDMI_TXCP C339 1 2 0.1U/16V_4 HDMI_CLK+_R
3
[20] INT_HDMI_TXCN INT_HDMI_TXCN C335 1 2 0.1U/16V_4 HDMI_CLK-_R
Q31 2 1 2 HDMI_HPD
fi
MMST3904-7-F 150K_4 R154
[20] HDMI_SCL
1
HDMI_SCL HDMI_SDA INT_HDMI_HPD
[20] HDMI_SDA
[20] INT_HDMI_HPD INT_HDMI_HPD
2
R286
5.1K/F_4
a
1
R315 2 1 680_4 HDMI_TX2+_R
R313 2 1 680_4 HDMI_TX2-_R
IB=(5V-0.7V)/(150K+(70+1)5.1K)=8.4uA
in
R302 2 1 680_4 HDMI_TX1+_R
R301 2 1 680_4 HDMI_TX1-_R
IE=(1+70)X8.4uA=596.4uA
+HDMI_LS
R306 2 1 680_4 HDMI_TX0+_R

R307 2 1 680_4 HDMI_TX0-_R
VE=596.4uA X 5.1K=3.04V
R298 2 1 680_4 HDMI_CLK+_R
B=70
R297 2 1 680_4 HDMI_CLK-_R +5V_HDMIF1
h
3
2
C 2 C
+3.3V_RUN
Q20 D20 D19
2N7002W SDM10K45-7-F SDM10K45-7-F
1
1
.c 1
R136
1M_4 CN6
+5V_HDMIF1_D
22
2
+5V_HDMIF1_D35 SHELL3 20
HDMI_TX2+_C
HDMI_TX2-_C
1
2
3
D2+
SHELL1
D2 Shield
HDMI Conn.
HDMI_TX1+_C 4 D2-
5 D1+
w
D1 Shield
1
3
HDMI_TX1-_C 6
HDMI_TX0+_C 7 D1-
RP15 8 D0+
Q25 FDV301N 2.2KX2 HDMI_TX0-_C 9 D0 Shield
HDMI_CLK+_C 10 D0-
HDMI_SCL 1 3 11 CK+
2
4
HDMI_CLK-_C 12 CK Shield
w
13 CK-
14 CE Remote
2
HDMI_CLK 15 NC
+3.3V_RUN DDC CLK
HDMI_DAT 16
DDC DATA
2
17
HDMIF1 1206L110THYR +5V_HDMIF1 18 GND
+5V_RUN +5V
HDMI_SDA 1 3 HDMI_HPD 19
w
HP DET 21
D SHELL2 D
23
Q24 FDV301N SHELL4
HDMI CONN_4 pin GND

PROJECT : JWA
3A
HDMI CONN
7
Sheet 28
8
of 54
5 4 3 2 1
fix
vina
+5V_SUS
System status LED
1
R7
D 330_4 D
Power Button LED
2
+5V_RUN
D2
m
1
LED_W hite
R8
330_4
2
BREATH_PWRLED
2
o
D4
LED_W hite
.c
3
BREATH_LED 2 Q1
2
[38] BREATH_LED
2N7002W
x
C C
fi
+5V_ALW
Battrey charger LED HDD access LED

1
R5
a
330_4 +5V_RUN
+3.3V_RUN
2
2
R9
in
D3 330_4
LED_W hite
1
D1
3
1
2 Q3
2 R10 R11
LED_W hite
[38] BAT1_LED
2N7002W 10K_4 100K_4
h
1
3
B B
5 DMN66D0LDW -7 2
Q2A
4
6
Q2B
.c
[21] PCH_SATA_LED# PCH_SATA_LED# 2
DMN66D0LDW -7
1
w
w
w
A A

PROJECT : JWA
3A
LED
1
29 of 54
5 4 3 2 1
f ix
These Caps close to LAN Chip VDD33 pins Close to Pin6
ina
+3.3V_ALW
v
+1.1V_AVDD
+3.3V_LAN wider>30mil
C443 1U/6.3V/X5R_4
C449 10U/6.3V/X5R_8 C446 0.1U/16V_4
C470 1U/6.3V/X5R_4
C441 0.1U/16V_4
C442 1000P/50V/X7R_4
Close to Pin9
D +2.7V_AVDD D
C447 1U/6.3V/X5R_4
U1 C448 0.1U/16V_4
+1.1V_DVDD wider>20mil
C85 1 2 0.1U/16V_4 PCIE_RXN5_C 29 24 PPS TP7
m
[23] PCIE_RXN5 TX_N DVDDL
[23] C84 1 2 0.1U/16V_4 PCIE_RXP5_C 30 37 +1.1V_DVDD
PCIE_RXP5 TX_P DVDDL_REG
[23] 36 Close to Pin37
PCIE_TXN5 RX_N
[23] 35 40 LX
PCIE_TXP5 RX_P LX
[23]
[23]
CLK_PCIE_LANN
CLK_PCIE_LANP
32
33 REFCLKN
REFCLKP Atheros VDD33
1
9
+3.3V_ALW
+2.7V_AVDD
+2.7V_AVDD wider>20mil
+1.1V_DVDD
C81 1U/6.3V/X5R_4
AVDDH_REG 16
o
+3.3V_ALW C92 0.1U/16V_4 C78 0.1U/16V_4
AR8161 AVDDH
AVDDH
22 C90 0.1U/16V_4 C89 *1U/6.3V/X5R_4_NC
TP5
TP6
LAN_SMBDAT
LAN_SMBCLK
26
25 SMDATA
SMCLK
AR8162 AVDDL_REG
6 +1.1V_AVDD +1.1V_AVDD wider>20mil
13 C97 0.1U/16V_4 AVDDVCO L4 1 2 +1.1V_AVDD
AVDDL
.c
[7,22,33,35,38] PLTRST# 2 19 C98 0.1U/16V_4 HCB1608KF-181T15_6
PERSTn AVDDL 31 C80 0.1U/16V_4 C79 *1U/6.3V/X5R_4_NC
3 AVDDL 34 AVDDVCO C82 0.1U/16V_4 1 2
[38] PCIE_EC_W AKE# WAKEn AVDDL C71 *4.7U/6.3V_6_NC
R31 2.37K/F_4 10 4 PCIE_CLK_REQ4#
RBIAS VDDCT_REG/CLKREQn PCIE_CLK_REQ4#[23]
5 +VDDCT R27 2 1 30K/F_4 +3.3V_RUN
27 VDDCT/ISOLATn
28 TESTMODE
TEST_RST 21 NB_LOM_TRDN3
TRXN[3] 20 NB_LOM_TRDP3
x
C LAN_XTALI 8 TRXP[3] 18 NB_LOM_TRDN2 C
XTLI TRXN[2] 17 NB_LOM_TRDP2
LAN_XTALO 7 TRXP[2] 15 NB_LOM_TRDN1
XTLO TRXN[1] 14 NB_LOM_TRDP1
TRXP[1] 12 NB_LOM_TRDN0
TRXN[0]
fi
41 11 NB_LOM_TRDP0
GND_PAD TRXP[0]
38 LED_ACT
LAN_XTALI LED0 39
LED1 23
CLKREQn/LED2
Y1
LED1
a
1
1 2 LAN_XTALO AR8161-BL3A-R (Pin39) Regulator select
R19
C91 C87 *4.7K_4_NC LDO Low

33P/50V/NPO_4 33P/50V/NPO_4
2
25MHz
in
R20 2 1 *4.7K_4_NC LED_ACT SWR* High SWR mode
L5
4.7uH/700mA_8 L3
Core voltage select
RJ-45 Connector
B
LX 2 1
0.1U/16V_4
C67
+1.1V_DVDD
C66
10U/6.3V/X5R_6
1 2
HCB1608KF-181T15_6
+1.1V_AVDD
LED_ACT
h High core
voltage
Low core
voltage
R244
R245
R257
R258
75/F_4
75/F_4
75/F_4
75/F_4
TXCT0
TXCT1
TXCT2
TXCT3
CN2
B
.c
EC50
1 0 4.7P/3KV/NPO_18
RJ45-TX3- 8
RJ45-TX3+ 7 RX1-
RJ45-TX1- 6 RX1+
RJ45-TX2- 5 RX0- 9
4 TX1- GND2
Place ESD diodes as RJ45-TX2+
TX1+
close as TRANSFORMER RJ45-TX1+ 3 10
w
RJ45-TX0- 2 RX0+ GND1

L19 RJ45-TX0+ 1 TX0- 11
ESD2 +3.3V_ALW 24 TXCT0 TX0+ GND3
NB_LOM_TRDP0 1 6 NB_LOM_TRDP1 C120 1 MCT0 12
2 1 6 5 TCT0 23 RJ45-TX3+ GND4
NB_LOM_TRDN0 3 2 5 4 NB_LOM_TRDN1 0.1U/16V_4 NB_LOM_TRDP3 2 TX0+
3 4 TD0+ 22 RJ45-TX3-
w
*SRV05-4.TCT_NC NB_LOM_TRDN3 3 TX0-

C467 TD0- 21 TXCT1
*0.1U/16V_4_NC C134 4 MCT1 EC18 *6.8P/50V/NPO_4_NC NB_LOM_TRDP0 RJ45_CONN
TCT1 20 RJ45-TX2+ EC17 *6.8P/50V/NPO_4_NC NB_LOM_TRDN0 DFTJ08FR322
0.1U/16V_4 NB_LOM_TRDP2 5 TX1+ EC16 *6.8P/50V/NPO_4_NC NB_LOM_TRDP1 rj45-jm361c-hp34aa03-9h-8p
TD1+ 19 RJ45-TX2- EC15 *6.8P/50V/NPO_4_NC NB_LOM_TRDN1
NB_LOM_TRDN2 6 TX1- EC14 *6.8P/50V/NPO_4_NC NB_LOM_TRDP2
w
TD1- 18 TXCT2 EC13 *6.8P/50V/NPO_4_NC NB_LOM_TRDN2

A MCT2 A
ESD1 +3.3V_ALW C137 7 EC12 *6.8P/50V/NPO_4_NC NB_LOM_TRDP3
NB_LOM_TRDP2 1 6 NB_LOM_TRDP3 TCT2 17 RJ45-TX1+ EC10 *6.8P/50V/NPO_4_NC NB_LOM_TRDN3
2 1 6 5 0.1U/16V_4 NB_LOM_TRDP1 8 TX2+
NB_LOM_TRDN2 3 2 5 4 NB_LOM_TRDN3 TD2+ 16 RJ45-TX1-
3 4 NB_LOM_TRDN1 9 TX2-
*SRV05-4.TCT_NC TD2- 15 TXCT3
C462
*0.1U/16V_4_NC
C113 10
TCT3
MCT3
14 RJ45-TX0+
0.1U/16V_4 NB_LOM_TRDP0 11 TX3+
TD3+ 13 RJ45-TX0- PROJECT : JWA
NB_LOM_TRDN0 12 TX3- Size Document Number Rev
TD3- 3A
LAN (AR8161A / AR8162)colay
http://vinafix.vn
DTA_LFE9276C-R
5 4 3 2 1
A B C D E
fixCONN with Power share (USB3.0 port 2)

USB
a
v i n
+USB_BACK_PW R
4 USBP0_BUS_SW_CB0 Mode Operating at C511 1 2 10U/6.3V_8 4
C509 1 2 *10U/6.3V_8_NC
Low DCP, Auto-detect S3/S4/S5, 1.5 A C379 1 2 0.1U/10V/X7R_4
m
High CDP, BC Spec 1.1 S0, 1.5 A
R109 mA +5V_ALW USB3.0 PORT2 with power share

+USB_BACK_PW R
R195
close to conn CN9
OC 100k ohm 480
o
22.1K/F_4
limitation C380 *4.7U/6.3V/X5R_6_NC
100 mil 1
USB_OC0# [22] VBUS
22.1k ohm 2171 Applied Now
1
C384 USBP1N_L 2
C381 2 1 0.1U/10V/X7R_4 C512 0.1U/16V_4 C385 USBP1P_L 3 D- USB2.0
17
16
15
14
13
U14 +USB_BACK_PW R *10U/6.3V_8_NC 150P/50V_4 D+
2
.c
4
PwPd
ILIM0
ILIM1
GND
FAULT
GND
[22] USB3.0_RX2- 5
USB3.0_RX2- SSRX-
1 12 [22] USB3.0_RX2+ 6
IN OUT USB3.0_RX2+ SSRX+
[22] USBP1N 2 11 USBP1N_R
USBP1N DM_OUT DM_IN
[22] USBP1P 3 10 USBP1P_R [22] USB3.0_TX2- C514 2 1 0.1U/16V_4 USB3.0_TX2-_C 8 USB 3.0
USBP1P DP_OUT DP_IN USB3.0_TX2- SSTX-
R188 2 1 10K_4 4 9 [22] USB3.0_TX2+ C513 2 1 0.1U/16V_4 USB3.0_TX2+_C 9 10
ILIM_SEL N/C USB3.0_TX2+ SSTX+ GND 11
+5V_ALW 7 GND 12
CTL1
CTL2
CTL3
GND GND 13
EN
GND
x
1
3 TPS2540ARTER USB3.0 9P FR 3
5
6
7
8
R181
[38] 100K_4
USB_BACK_EN
fi
[38] USBP0_BUS_SW _CB0 EL8
USBP1N_R 1 2 USBP1N_L
USBP1P_R 4 3 USBP1P_L
DLP11SN900HL2L
a
EU1 ESD7004MUTAG
USB3.0_TX2+_C 1 10 USB3.0_TX2+_C
1- NC
USB3.0_TX2-_C 2 9 USB3.0_TX2-_C
1+ NC
in
3 8
GND GND
USB3.0_RX2+ 4 7 USB3.0_RX2+
2- NC
USB3.0_RX2- 5 6 USB3.0_RX2-
2+ NC
h USBP1N_L
USBP1P_L
1
2
3
ESD3
1
2
3
*TVL ST23 04 AD0_NC
6
5
4
6
5
4
+5V_ALW
2
.c
w
w
w
1 1

PROJECT : JWA
http://vinafix.vn
3A
USB 3.0 port / USB power share
A B C D E
A B C D E
USBfixCONN*2 (USB3.0 port 0 & 3) BTB CN

i n a
v
+5V_ALW
4 4
1
C241 C490
CN4
2
*10U/6.3V_8_NC 1
m
2 1
0.1U/16V_4 3 2
4 3
5 4
6 5
7 6
8 7
9 8
[22] USB_OC1# 9
o
[38] 10
USB_RIGHT_EN# 10
11
12 11
[22] USBP0N 12
[22] 13
USBP0P 14 13
15 14
[22] USBP2N 15
.c
[22] 16
USBP2P 17 16
18 17
19 18
20 19
21 20
22 21
23 22
[22] USB3.0_RX1- 23
24
USB3.0 PORT1 [22] USB3.0_RX1+
25 24
[22] USB3.0_TX1- 25
x
26
3
USB3.0 PORT1 [22] USB3.0_TX1+
27 26 3
[22] USB3.0_RX3- 27
28
USB3.0 PORT3 [22] USB3.0_RX3+
29 28 31
[22] USB3.0_TX3- 29 31
30 32
USB3.0 PORT3 [22] USB3.0_TX3+ 30 32
fi
7300L30-000000-G4_20120203
a
in
2
h 2
.c
w
w
w
1 1

PROJECT : JWA
http://vinafix.vn
3A
USB 3.0 port*2
A B C D E
5 4 3 2 1
a fix
Cardreader (RTS5229) Support Micro SD/ MMC
v i n
SD / MMC
D CARD READER D
Place close to JCARD1

Connector +CARD_3V3 SD_D2 1
m
SD_D3 2 DAT2
SD_CMD 3 DAT3
SD_CD# 4 CMD
5 C/D
6 VSS1
+CARD_3V3 VDD
SD_CLK 7
CLK
1
8
9 VSS2
o
C485 C486 SD_D0
10U/6.3V_6 SD_D1 10 DAT0
0.1U/16V_4
2
SD_W P 11 DAT1
12 W/P
13 GND
14 GND
GND
.c
15
GND
PSDBTS-09GLBS1NN4H0
DFHS11FR106
sdcard-psdbts-09glbs1nn4h0-11p
+CARD_3V3
+3.3V_RUN
x
C C471 C
DV33_18
1U/6.3V_4
1
C479 C476
fi
10U/6.3V_6 0.1U/16V_4
2
25
10
15
U19
9
CARD_3V3
DV33_18
GND
3V3_IN
[23] 1
PCIE_TXP3_CR HSIP
2
a
[23] PCIE_TXN3_CR HSIN
EMI solution
20 SD_W P
3 SP7 18 SD_D2
15
[23] CLK_PCIE_CRP REFCLKP SP6
[23] 4 17 SD_D3
CLK_PCIE_CRN REFCLKN SP5 16 SD_CMD
RTS5229 SP4
in
[23] C473 2 1 0.1U/16V_4 PCIE_RXP3_CR_R 5 14 SP3_R ER6 22_4 SD_CLK EC59 22P/50V_4
PCIE_RXP3_CR HSOP SP3
[23] C472 2 1 0.1U/16V_4 PCIE_RXN3_CR_R 6 13 SD_D0
PCIE_RXN3_CR HSON SP2 11 DV12_S
DV12_S
1
23
MS_INS#
[7,22,30,35,38] PLTRST# PERST#
SD_CD#
[23] 24 C475 C478
PCIE_CLK_REQ2# CLKREQ#
RREF 0.1U/16V_4 4.7U/6.3V_6
GPIO
AV12
2
SP1
RTS5229-GR
h
7
19
21
22
12
B Close to chip pin B
RREF
AV12
1
.c
SD_CD#
C477 C474
4.7U/6.3V_6 0.1U/16V_4 6.2k/F_4
2
R268 SD_D1
R264 10K_4 +3.3V_RUN

w
w
w
A A

PROJECT : JWA
3A
Card Reader (RTS5229)
1
33 of 54
1 2 3 4 5 6 7 8
a fix
vin
HDD ODD
CON1
24 20
23 GND12 GND1 19 SATA_TXP0_C C340 2 1 0.01U/25V_4 SATA_TXP0 CN7
GND11 RXP SATA_TXP0 [21]
22 18 SATA_TXN0_C C345 2 1 0.01U/25V_4 SATA_TXN0 [21] 14
GND10 RXN SATA_TXN0 GND14
A 21 17 DG: Place TX cap close to connector A
GND9 GND2 16 SATA_RXN0_C C351 2 1 0.01U/25V_4 SATA_RXN0 1
TXN SATA_RXN0 [21] GND
15 SATA_RXP0_C C360 2 1 0.01U/25V_4 SATA_RXP0 [21] 2 SATA_TXP3_C C375 1 2 0.01U/25V_4 SATA_TXP3 [21]
TXP SATA_RXP0 A+ SATA_TXP3
14 3 SATA_TXN3_C C373 1 2 0.01U/25V_4 SATA_TXN3 [21]
GND3 A- SATA_TXN3
4
GND 5 SATA_RXN3_C C365 1 2 0.01U/25V_4 SATA_RXN3
m
B- SATA_RXN3 [21]
13 6 SATA_RXP3_C C359 1 2 0.01U/25V_4 SATA_RXP3 [21]
3.3V_0 B+ SATA_RXP3
12 7
3.3V_1 11 GND
3.3V_2 10
GND4 9 8 SATA_ODD_PRSNT#
GND5 8 DP 9
TP75 Internal PD, for Hot Plug function
GND6 7 5V 10
5V_0 +5V_RUN 5V +5V_MOD
6 11
o
SATA_ODD_MD#
5V_1 MD SATA_ODD_MD# [22]
5 12
5V_2 4 GND 13
GND7 3 FFS_INT2_R TP80 GND
RSVD 2 15
GND8 1 GND15
NC
.c
C18582-11309-L
7300J20-000000-G4-R
gs12201-1011-9f-20p-l-smt
+5V_MOD Place caps close to connector.
x
B B
1
550mA C332 C325
+5V_RUN C319
Place caps close to connector. 10U/6.3V_8 0.1U/16V_4
2
1U/6.3V_4
fi
1
C378 C374
C484 C370
10U/6.3V_8 10U/6.3V_8 1U/6.3V_4 0.1U/16V_4
2
a
Support Zero power ODD
in
+5V_MOD
+5V_ALW
Q22 FDC655BN
6
C
h +3.3V_ALW 5
2
1
4
C
3
1
.c
+3.3V_RUN R148
100K_4 R151 100K_4
+15V_ALW 2 1 MOD_EN_5V
2
1
3
R135
5 DMN66D0LDW -7
10K_4
Q21A
w
4
6
DMN66D0LDW -7
1
[24] MODC_EN 2
MODC_EN Q21B C302
0.1U/25V_6
2
w
w
D D

PROJECT : JWA
3A
SATA HDD/ODD
4 5 6
7
Sheet 34
8
of 54
5 4 3 2 1
f ix
ina
+3.3V_AUX MiniCard WLAN connector
v PCIE_CLK_REQ0#_R
WLAN_RADIO_DIS#_R
R57
R35
1
1
2 *10K_4_NC
2 *10K_4_NC
+3.3V_AUX
+3.3V_AUX
2
D R54 1 2 *10K_4_NC D
R58 +3.3V_AUX +3.3V_AUX +3.3V_ALW +3.3V_RUN +3.3V_AUX
*10K_4_NC
J2 PCIE_CLK_REQ0#
PCIE_CLK_REQ0# [23]
3
R179 0_8
1
PCIE_EC_WAKE#_1 R278 1 2 *0_4_NC 1 2 For Debug Only, Remove at QT PCIE_CLK_REQ0#_R 5
[38] PCIE_EC_WAKE#_1 WAKE# 3.3V_1
3 4 Q10A
RESERVED_1 GND0 4
6
5 6 *DMN66D0LDW-7_NC Q8 *FDC655BN_NC
4
PCIE_CLK_REQ0#_R 7 RESERVED_2 1.5V_1 8 LPC_LFRAME#_R R59 1 2 *0_4_NC LPC_LFRAME# 2 Q10B 6
m
CLKREQ# UIM_PWR LPC_LFRAME# [21,38]
9 10 LPC_LAD3_R R55 1 2 *0_4_NC LPC_LAD3 5 4
GND1 UIM_DATA LPC_LAD3 [21,38]
CLK_PCIE_WLANN 11 12 LPC_LAD2_R R60 1 2 *0_4_NC LPC_LAD2 *DMN66D0LDW-7_NC 2
[23] CLK_PCIE_WLANN [21,38]
1
CLK_PCIE_WLANP 13 REFCLK- UIM_CLK 14 LPC_LAD1_R R53 1 2 *0_4_NC LPC_LAD1 LPC_LAD2 1
[23] CLK_PCIE_WLANP REFCLK+ UIM_RESET LPC_LAD1 [21,38]
15 16 LPC_LAD0_R R44 1 2 *0_4_NC LPC_LAD0
GND2 UIM_VPP LPC_LAD0 [21,38]
For Debug Only, Remove at QT
3
4 2 1
PLTRST# R43 1 2 *0_4_NC PLTRST#_R 17 18 0_4 R56 R17 *100K_4_NC
CLK_33M_LPC
R42 1 2 *0_4_NC CLK_LPC_DEBUG_R 19 UIM_C8 GND3 20 WLAN_RADIO_DIS#_R 2 1
[22] CLK_33M_LPC UIM_C4 W_DISABLE# +15V_ALW
21 22 PLTRST#
GND4 PERST# PLTRST# [7,22,30,33,38]
PCIE_RXN1 23 24
o
[23] PCIE_RXN1 PERn0 3.3VAUX1 +3.3V_AUX
3
PCIE_RXP1 25 26 Q4
[23] PCIE_RXP1 PERp0 GND5
27 28 AUX_EN# 2
GND6 1.5V_2 [38] AUX_EN#
29 30
GND7 SMB_CLK
1
PCIE_TXN1 31 32 *2N7002W_NC
[23]
1
PCIE_TXN1 PCIE_TXP1 33 PETn0 SMB_DATA 34
[23] C74
PCIE_TXP1 35 PETp0 GND8 36
[22] +3.3V_RUN *0.1U/25V_6_NC
2
PCIE_MCARD1_DET# 37 GND9 USB_D- 38 USBP4N
[24] PCIE_MCARD1_DET# RESERVED_3 USB_D+ USBP4P [22]
39 40 USB_MCARD1_DET#
USB_MCARD1_DET# [24]
.c
RESERVED_4 GND10
2
41 42 Q9
43 RESERVED_5 LED_WWAN# 44
45 RESERVED_6 LED_WLAN# 46 WLAN_RADIO_DIS#_R 3 1 WLAN_RADIO_DIS#
47 RESERVED_7 LED_WPAN# 48 WLAN_RADIO_DIS# [24]
49 RESERVED_8 1.5V_3 50
BT_RADIO_DIS# 51 RESERVED_9 GND11 52 *2N7002W_NC
[24] BT_RADIO_DIS# RESERVED_10 3.3V_2
2 1
Mini PCI Express/H=4 0_4 R34
C C
x
+3.3V_AUX Place caps close to connector.
R57 R58 R56 R54 R34R179 R17 R35 Q10 Q8 Q4 Q9 C74 R278
1
1
C83 C96 C86 C136 C88
0.1U/16V_4 0.1U/16V_4 10U/6.3V_8
fi
0.01U/25V_4 0.01U/25V_4
2
2
AOAC
O O X O X X O O O O O O O O
No
AOAC X X O X O O X X X X X X X X
a
in
mSATA Connector
+3.3V_RUN +3.3V_RUN
J4
B 1 2 B
3 WAKE# 3.3V_1 4
RESERVED_1 GND0
5
7
9
11
13
15
RESERVED_2
CLKREQ#
GND1
REFCLK-
REFCLK+
GND2
1.5V_1
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
6
8
10
12
14
16 h J4 C363 C354 C347 C343 C382 C310 C275 H20
.c
17 18
19 UIM_C8 GND3 20
21 UIM_C4 W_DISABLE# 22
MSATA
[21]
[21]
SATA_RXP1
SATA_RXN1
SATA_RXP1 C363 2
SATA_RXN1 C354 2
1 *0.01U/25V_4_NCSATA_RXP1_C
1 *0.01U/25V_4_NCSATA_RXN1_C
23
25
27
GND4
PERn0
PERp0
PERST#
3.3VAUX1
GND5
24
26
28
+3.3V_RUN O O O O O O O O O
29 GND6 1.5V_2 30
Non
[21]
[21]
SATA_TXN1
SATA_TXP1
SATA_TXN1 C347 2
SATA_TXP1 C343 2
1 *0.01U/25V_4_NCSATA_TXN1_C
1 *0.01U/25V_4_NCSATA_TXP1_C
31
33
GND7
PETn0
PETp0
SMB_CLK
SMB_DATA
GND8
32
34 MSATA X X X X X X X X X
35 36
37 GND9 USB_D- 38
39 RESERVED_3 USB_D+ 40
41 RESERVED_4 GND10 42
w
43 RESERVED_5 LED_WWAN# 44
45 RESERVED_6 LED_WLAN# 46
47 RESERVED_7 LED_WPAN# 48
49 RESERVED_8 1.5V_3 50
SATA_MCARD3_DET# 51 RESERVED_9 GND11 52
[24] SATA_MCARD3_DET# RESERVED_10 3.3V_2
*Mini PCI Express/H=4_NC

w
A A
w
+3.3V_RUN
Place caps close to connector.
1
C382 C310 C275 Quanta Computer Inc.

*0.01U/25V_4_NC *0.1U/16V_4_NC *10U/6.3V_8_NC
2
PROJECT : JWA
3A
MiniCard / mSATA
5 4 3 2 1
http://vinafix.vn
1 2 3 4 5 6 7 8
f ix +5V_RUN +5V_RUN
Int. Speaker
ina
ANALOG DIGITAL
L9 HCB1608KF-181T15 PVDD1 L20 HCB1608KF-181T15 PVDD2
v
88266-04001-06
C507 C272 C303 C305 C186 C468 +5V_AVDD L8 HCB1608KF-181T15 AUD_R+ L10 TI160808U600 AUD_R+_R 4
+5V_RUN 4
0.1U/10V_4 10U/6.3V_6 10U/6.3V_6 0.1U/10V_4 10U/6.3V_6 0.1U/10V_4 C503 C500 AUD_R- L11 TI160808U600 AUD_R-_R 3
10U/6.3V_6 0.1U/10V_4 AUD_L- L12 TI160808U600 AUD_L-_R 2 3
C280 AUD_L+_R C358 680P/50V_4 AUD_L+ L13 TI160808U600 AUD_L+_R 1 2
Close to Codec 1
Close to Codec 10U/6.3V_6 AUD_L-_R C357 680P/50V_4
AUD_R-_R C356 680P/50V_4 JSPK1
AUD_R+_R C355 680P/50V_4
A A
AGND
Close to Codec Close to Codec Moat
+3.3V_SUS
C328 1 2 2.2U/10V_6
PVDD2 PVDD1
C299 10U/6.3V_6
+5V_AVDD
40mils
Audio Combo Jack
0.1U/10V_4 C308 0.1U/10V_4 AGND
C330
+3.3V_RUN +5V_AVDD
C327 1 2 2.2U/10V_6 C296 10U/6.3V_6
0.1U/10V_4 C292 0.1U/10V_4 AGND
m
C329 Close to Codec
45
39
38
27
Close to Codec
3
U22
Close to Codec
DVDD
DVDD-IO
PVDD2
PVDD1
AVDD2
AVDD1
36 CBP
C506 *10P/50V_4_NC CBP
[21] 5 35 CBNC2761 2 2.2U/10V_6

ACZ_SDOUT SDATA-OUT CBN
EC64 *10P/50V_4_NC
o
[21] 6 32 EARP_R2 R138 75/F_4 EARP_R
ACZ_BITCLK BCLK HP-OUT-R 31 EARP_L2 R137 75/F_4 EARP_L
R299 22_4 ACZ_SDIN0_R 8 HP-OUT-L
[21] ACZ_SDIN0 SDATA-IN
C505 *10P/50V_4_NC 30 Close to Codec
MIC1_VREFO
Digital
[21] 10 23 VREFOUT_AL R291 2.2K_4 EXT_MIC_R R287 22K/F_4 AGND
ACZ_SYNC SYNC LINE1-VREFO
[21] 11
ACZ_RST# RESET#
.c
Analog
15 C289 0.1U/10V_4
B
I2S_MCLK 25 VREF C2781 2 2.2U/10V_6 B
VREF AGND
I2S_BCLK R157 33_4 I2S_BCLK_R 16
C323 *10P/50V_4_NC I2S_SCLK 29 EXT_MIC_R1 C497 4.7U/6.3V_6 EXT_MIC_2 R289 1K/F_4 EXT_MIC_R C392 100P/50V_4 JCOMBO1
LINE1-R AGND
7
28 EXT_MIC_L1 C496 4.7U/6.3V_6 3
AP_I2S_DIN 17 LINE1-L EARP_L L16 FCM1608KF-301T02 EARP_L1 1
I2S_LRCK_FS 18 I2S_DOUT
I2S_LRCK
Audio Jack type:
AP_I2S_DOUT 24
I2S_DIN
ALC290Q-GR MIC1-R
20
19 SENSE_COMBO 5
Normal Open
MIC1-L
AUD_L+ 40 C391 100P/50V_4 Combo Jack(IPHONE)
x
SPK-L+ AGND
AUD_L- 41 6
SPK-L- 37 EARP_R L15 FCM1608KF-301T02 EARP_R1 2
MONO-OUT SUB_OUT [37]
AUD_R- 43 EXT_MIC_R L14 FBM-11-160808-601A10T EXT_MIC_1 4
AUD_R+ 44 SPK-R-
14 SPK-R+ C390 *100P/50V_4_NC 2SJ3061-021111F
AGND
COMBOJACK 46
GPIO2/DMIC-DATA34
fi
[38] ADSP_PORTA_CLK R167 *0_4_NC 48 COMBOJACK R202 22K_4
GPIO4/I2S_Float_CTRL
GPIO3/SPDIFO AGND
GPIO_A R200 0_4 4 14 Close to Codec C386 10U/6.3V_6
PORTD_FS R199 0_4 2

GPIO1/DMIC-DATA12 Sense B
13 SENSE_A R296 39.2K/F_4 SENSE_COMBO Audio Processor AGND
COMBO_JACK
GPIO0/DMIC-CLK Sense A
R191 *0_NC_Short +VDD_305 EARP_L1 EXT_MIC_1
LDO-CAP
+3.3V_RUN
NB_MUTE# 47
3
CPVEE
[37,38] NB_MUTE# JDREF
PVSS1
AVSS2
AVSS1
EAPD
PGND
AMP_BEEP 12 C376 1U/6.3V_4

PCBEEP
a
R107 10K_4 C3771 20.01U/25V_4
2 1 R192 *0_4_NC ADSP_SIN0_R
1
+3.3V_RUN [38] ADSP_SIN0
ALC290Q-GR [38] R194 *0_4_NC ADSP_SOUT0_R SMBDAT3_DSP R185 *0_4_SHORT_NC
ADSP_SOUT0 SMBDAT3 [17,38,42]
7
42
49
1
33
26
34
22
21
+3.3V_RUN R193 10K_4 SMBCLK3_DSP R186 *0_4_SHORT_NC C393 C389

SMBCLK3 [17,38,42]
2
R201 *100K/F_4_NC [23] *Clamp-Diode_NC *Clamp-Diode_NC
C AP_24M C
R303 *0_4_NC
+3.3V_RUN 14 GPIO_A VDD_DPD
in
C504 C318 10U/6.3V_6
R300 4.7K_4 10U/6.3V_6 R295 20K/F_4
C4991 2 2.2U/10V_6 EARP_R1 SENSE_COMBO
U13
49
48
47
46
45
44
43
42
41
40
39
38
37
AGND
Moat
UART_SOUT
PORTA_CLK
GPIO_A
I2C_DATA
I2C_CLK
VDD_P
GND
UART_SIN
CLK_IN
VDD_DPD
NC
NC
VDD_IO
R175 47K_4 AGND
3
1
AMP_BEEP C341 1U/10V_4 HDA_BEEP2 1 2 C352 1U/6.3V_4 EMI
ACZ_SPKR [21] 40mils +3.3V_RUN C387 C388
2
C350 100P/50V_4 ER5 *0_4_SHORT_NC *Clamp-Diode_NC *Clamp-Diode_NC
R174 4.7K_4 C364 1U/6.3V_4 1 36
BEEP [38] I2S Float Contral SJ5 SJ0805 2 PORTA_FS NC 35
H I2S Float
I2S Enable (internal PD)

h1
1 2
2 R196
R197
100K/F_4
100K/F_4
VDD_DAL
PORTD_FS
3
4
5
6
7
8
9
PORTA_DI
PORTA_DO
VDD_IO
PORTD_DO
VDD_DAL
PORTD_CLK
PORTD_FS
eS305BQ
NC
NC
NC
NC
NC
NC
NC
34
33
32
31
30
29
28
.c
L AGND AP_I2S_DOUT 10 PORTD_DI
PORTC_DO
NC
NC
27
I2S_BCLK 11 26 C349
I2S_LRCK_FS 12 PORTC_CLK NC 25 VDD_DAL 1U/6.3V_4
PORTC_FS VDD_DAL 1 2 0.01U/25V_4
PORTB_CLK
R198 C383
PORTB_DO
PORTB_FS
PORTC_DI
PORTB_DI
VDD_DPD
*0_4_NC
VDD_IO
VDD_IO
RESET
D D
TEST
GND
GND
[43] R318 0_4 DIGITAL_D1
DIGITAL_D1_R
10
w
From Touch screen eS305BQ
13
14
15
16
17
18
19
20
21
22
23
24
[43] R163 1 2 75/F_4 DIGITAL_CLK
DIGITAL_CLK_R
3 Quanta Computer Inc.
+3.3V_RUN +3.3V_RUN
AP_I2S_DIN VDD_DPD
DIGITAL_CLK PLTRST#_R2 R187 *0_4_SHORT_NC
DIGITAL_D1
DSP_RST# [38] PROJECT : JWA
C361 1U/6.3V_4 Size Document Number Rev
w
R190 100K/F_4 C367 1 20.01U/25V_4 3A

Closed pin22
CODEC (CX20672)
1 2 3 4 5 6 7 8
w
http://vinafix.vn
5 4 3 2 1
fix
a
Subwoofer Amp
v i n
Follow JW9 3
R158 *0_6_SHORT_NC
D D
+3.3V_RUN
+PSUB
11
SUB_GND
R319 *0_4_NC
R153
10K_4
m
*SDM10K45-7-F_NC 1 2 D21
B1
B2
[36,38] NB_MUTE#
U12
VDD
PVDD
+5V_RUN +PSUB
SDM10K45-7-F 1 2 D22 C2
[38] SUB_MUTE#_D EN 3
TI 30mil
[36] SUB_OUT R152 C1 A3 SUBWOOFER- CN5 R156 *0_8_SHORT_NC
SUB_OUT
C316 100K/F_4 IN- TPA2011D1 VO- SUBWOOFER-_M 2
2
o
0.015U/16V_4 SUBWOOFER+_M 1
R160 A1 C3 SUBWOOFER+ 1
IN+ VO+
PGND
100K/F_4 ACS_85205-0200L C334 C333
GND
1U/10V_6 0.1U/10V_4
C336
A2
B3
0.015U/16V_4
.c
TPA2011D1 SUB_GND SUB_GND
SUB_GND
C C
SUB_GND
EMI
R325 *0_8_NC R328 *0_8_NC
13
x
SUBWOOFER-_M
Q34 FDC655BN Q35 FDC655BN SUBWOOFER+_M
SUBWOOFER- 6 SUBWOOFER+ 6
13 5 4 SUBWOOFER-_M 5 4 SUBWOOFER+_M
fi
2 2
1
1 1
EC67 EC68
0.01U/25V_4 0.01U/25V_4
2
+3.3V_RUN
a
1
R327 200K_4
R322 2 1 WOOFER_EN
+15V_ALW
100K_4
B B
Q36
2
in
5
4 3
1
2 SUB_MUTE#_D
C516
1 6 0.1U/25V_6
2
SUB_GND
DMN66D0LDW-7
SUB_GND h
.c
A A
R319 D21 D22 R153
w
NB_MUTE control SUB.

X X X O Quanta Computer Inc.
SUB can be PROJECT : JWA
controlled separately. O X O X Size Document Number Rev
w
3A
Subwoofer
5 4 3 2 1
w
http://vinafix.vn
5 4 3 2 1
f ix
ina
IMVP7_PROCHOT#
IMVP7_PROCHOT# [7,51,53]
v
CLK_33M_KBC +RTC_CELL +3.3V_ALW _AVCC
1
BAT1_LED [29]
BAT1_LED
1
+3.3V_ALW ALW _ON C197

ALW _ON [41,46]
ER4 RP3 2.2KX2 EC_PW ROK [7,19] 47P/50V_4
EC_PW ROK
2
3
*10_4_NC SMBDAT0 1 2 SIO_SLP_S4# 2N7002W
+3.3V_ALW SIO_SLP_S4# [19,47]
SMBCLK0 3 4 VGA_PW R_LEVEL_EC H_PROCHOT#_EC 2
0.1U/16V_4 VGA_PW R_LEVEL_EC [17]
1
EC_SPI_SI [39] Q14
EC_SPI_SI
1 2
SMBDAT1 RP2 1 2 2.2KX2 C195 +3.3V_RUN EC_SPI_SO

EC_SPI_SO [39]
1
SMBCLK1 3 4 EC_SPI_CLK [39]
EC_SPI_CLK
2
EC28 EC_SPI_CS0#
D EC_SPI_CS0# [39] +3.3V_ALW D
PCIE_EC_W AKE#
*2.2P/50V_4_NC R88 1 2 10K_4 CLKRUN# [19]
2
CLKRUN#
114
121
127
2
11
26
50
92
74
84
83
82
19
20
99
98
97
96
93
3
U20
LPC_LAD0 10 110 SMBCLK0 R79
m
EGCLK/WUI27/GPE3
EGCS#/WUI26/GPE2
EGAD/WUI25/GPE1
L80HLAT/BAO/WUI24/GPE0
L80LLAT/WUI7/GPE7
HMOSI/GPH6/ID6
HMISO/GPH5/ID5
HSCK/GPH4/ID4
HSCE#/WUI19/GPH3/ID3
CLKRUN#/WUI16/GPH0/ID0
VCC
AVCC
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VBAT
[21,35] LPC_LAD0 LAD0/GPM0 SMCLK0/GPB3 SMBCLK0 [45,53]
[21,35] LPC_LAD1 9 111 SMBDAT0 [45,53] Charge ,BAT 100K_4
SM BUS
LPC_LAD1 LPC_LAD2 8 LAD1/GPM1 SMDAT0/GPB4 115 SMBCLK1 SMBDAT0
[21,35] [23]
1
LPC_LAD2 LPC_LAD3 7 LAD2/GPM2 SMCLK1/GPC1 116 SMBDAT1 SMBCLK1
[21,35] LPC_LAD3 PLTRST# 22 LAD3/GPM3 SMDAT1/GPC2 117 PECI_EC SMBDAT1 [23] PCH 1 2 W RST#
[7,22,30,33,35] PLTRST# LPCRST#/WUI4/GPD2 PECI/SMCLK2/WUI22/GPF6 PECI_EC [7] [42,44] THERM_STP#
[22] CLK_33M_KBC 13 118 ADAPT_TRIP_SET D8 *SDMK0340L-7-F_NC
CLK_33M_KBC LPCCLK/GPM4 SMDAT2/WUI23/GPF7 ADAPT_TRIP_SET [53]
[21,35] LPC_LFRAME# 6
LPC_LFRAME# LFRAME#/GPM5 85 PCH_MELOCK [21] C198
PS2CLK0/TMB0/GPF0 PCH_MELOCK +3.3V_RTC_LDO
17 86
o
[26] LCD_TST H_PROCHOT#_EC 1U/6.3V_4
LCD_TST LPCPD#/WUI6/GPE6 PS2DAT0/TMB1/GPF1 89 CLK_TP_SIO [40]
PS2CLK2/WUI20/GPF4 CLK_TP_SIO
PS/2
[24] SIO_A20GATE D6 2 1
SDM10K45-7-F 126 90 DAT_TP_SIO [40]
SIO_A20GATE GA20/GPB5 PS2DAT2/WUI21/GPF5 DAT_TP_SIO
1
[21] IRQ_SERIRQ 5
IRQ_SERIRQ SERIRQ/GPM6
[24] SIO_EXT_SMI# D9 2 1
SDM10K45-7-F 15
SIO_EXT_SMI# ECSMI#/GPD4
[24] SIO_EXT_SCI# D11 2 1
SDM10K45-7-F 23 LPC PR115
SIO_EXT_SCI# ECSCI#/GPD3
.c
W RST# 14 GPIO 100K_4
WRST#
6
[24] SIO_RCIN# D7 2 1
SDM10K45-7-F 4
SIO_RCIN#
2
IMVP_VR_ON 16 KBRST#/GPB6 2 PQ14B
[51] IMVP_VR_ON PWUREQ#/BBO/GPC7 DMN66D0LDW -7
3
24 BREATH_LED [29]
BREATH_LED
1
PWM0/GPA0 25 5 PQ14A
PWM1/GPA1 AUX_EN# [35]
28 FAN1_PW M [42] DMN66D0LDW -7
PWM2/GPA2 FAN1_PW M
[19,42,51] IMVP_PW RGD IMVP_PW RGD 119 IT8518(HX) 29 PW M_VADJ [26]
PW M_VADJ
4
RUN_ON 123 CRX0/GPC0 PWM3/GPA3 30
C [26,48] RUN_ON CTX0/TMA0/GPB2 CIR PWM4/GPA4 DSP_RST# [36] C
31 KB_BACKLITE_EN TP69
x
PWM5/GPA5
PWM
[19] RSMRST# RSMRST# 80
NB_MUTE# 104 DAC4/DCD0#/GPJ4 47 FAN1_TACH +3.3V_RUN
[36,37]NB_MUTE# DSR0#/GPG6 TACH0A/GPD6 FAN1_TACH [42]
[26] LCDVCC_TST_EN LCDVCC_TST_EN 33 48 AC_OFF [45] RP4 2.2KX2
GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7 AC_OFF
fi
[53] 88 SMBDAT3 1 2
BATSHIP PS2DAT1/RTS0#/GPF3
[19] SIO_PW RBTN# D10 2 1
SDM10K45-7-F 81 120 LID_SW # [40] SMBCLK3 3 4
SIO_PW RBTN# DAC5/RIG0#/GPJ5 TMRI0/WUI2/GPC4 LID_SW #
TP68 PS_ID 87 124 SIO_SLP_S3# [9,19,47]
PS2CLK1/DTR0#/GPF2 TMRI1/WUI3/GPC6 SIO_SLP_S3#
[36] ADSP_SIN0 ADSP_SIN0 109 IMVP_PW RGD R72 1 2 10K_4
ADSP_SOUT0 108 TXD/SOUT0/GPB1 R90 1 2 *100K_4_NC
[36] ADSP_SOUT0 RXD/SIN0/GPB0 +3.3V_ALW
SUS_ON R73 1 2 100K_4
[45] PBAT_PRES# 71 125 SYS_PW R_SW #
PBAT_PRES# ADC5/DCD1#/WUI29/GPI5 PWRSW/GPE4 SYS_PW R_SW #[41]
IINP 72 UART port 18 IMVP_PW RGD C189 1 2 *100P/50V_4_NC
a
[53] IINP ADC6/DSR1#/WUI30/GPI6 RI1#/WUI0/GPD0
[19] SIO_SLP_S5# 73 21 D12 2 1 ACAV_IN [41,53] PECI_EC C187 1 2 *100P/50V_4_NC
SIO_SLP_S5# ADC7/CTS1#/WUI31/GPI7 RI2#/WUI1/GPD1 ACAV_IN
LCD_BAK [26] 35 WAKE UP SDM10K45-7-F LID_SW # C188 1 2 *100P/50V_4_NC
LCD_BAK BEEP 34 RTS1#/WUI5/GPE5
[36] BEEP PWM7/RIG1#/GPA7
HW PG [19,44] 107 112 AC_PRESENT
HW PG DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 AC_PRESENT [19]
[17,36,42] SMBDAT3 95 Board ID Straps
SMBDAT3 CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2 +3.3V_ALW
in
SMBCLK3 94
Thermal [17,36,42] SMBCLK3
ER3 33_4 CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1
[39]EC_FLASH_SPI_CLK EC_FLASH_SPI_CLK 1 2EC_FLASH_SPI_CLK_R 105
EC_FLASH_SPI_CS# 101 FSCK
[39]EC_FLASH_SPI_CS# FSCE#
1
[39]EC_FLASH_SPI_DIN EC_FLASH_SPI_DIN 102 EXTERNAL SERIAL FLASH
EC_FLASH_SPI_DO 103 FMOSI 66 BD0
[39] EC_FLASH_SPI_DO FMISO ADC0/GPI0 67 BD1 R95 R93
TP72 56 ADC1/GPI1 68 ME_SUS_PW R_ACK 12K/F_4 45.3K/F_4
B KSO16/SMOSI/GPC3 ADC2/GPI2 ME_SUS_PW R_ACK [19] B
USB_BACK_EN [31] 57 69 T_CPU
USB_BACK_EN T_CPU [42] 9
2
SUB_MUTE#_D 32 KSO17/SMISO/GPC5 ADC3/GPI3 70 PANEL_BKEN BD0
[37]
[48]
SUB_MUTE#_D
SUS_ON
SUS_ON 100
PWM6/SSCK/GPA6
SSCE0#/GPG2
h A/D D/A
ADC4/WUI28/GPI4 PANEL_BKEN [20]
BD1
100K/F_4: CS41002FB28
45.3K/F_4: CS34532FB18
1
[36] ADSP_PORTA_CLK 106 SPI ENABLE 24.3K/F_4: CS32432FB19
SSCE1#/GPG0 76 USBP0_BUS_SW _CB0
GPJ0 USBP0_BUS_SW _CB0 [31] 12K/F_4 : CS31202FB15
KSO0 36 77 SIO_EXT_W AKE# [22] R94 R92 6.49K/F_4: CS26492FB23
KSO0/PD0 GPJ1 SIO_EXT_W AKE#
KSO1 37 78 PCIE_EC_W AKE# 20K/F_4 20K/F_4 1.65K/F_4: CS21652FB29
.c
KSO1/PD1 DAC2/TACH0B/GPJ2 PCIE_EC_W AKE# [30]
KSO2 38 79 [35]
PCIE_EC_W AKE#_1
2
KSO3 39 KSO2/PD2 DAC3/TACH1B/GPJ3
KSO4 40 KSO3/PD3
KSO4/PD4 KBMX
KSO5 41
KSO6 42 KSO5/PD5
[40] KSO[0..15] KSO6/PD6
KSO7 43 BD1
KSO8 44 KSO7/PD7 000 0.5V PU 100K Ivy SV UMA
[40] KSI[0..7] KSO8/ACK#
KSO9 45 001 1.0V PU 45.3K Ivy SV Optimus 2G
KSO10 46 KSO9/BUSY 010 1.5V PU 24.3K Ivy ULV UMA
w
EC_FLASH_SPI_CLK KSO11 51 KSO10/PE 2 BAT2_LED TP67 100 2.0V PU 12K Ivy ULV Optimus 2G
KSI3/SLIN#
KSO11/ERR# CK32KE
KSI1/AFD#
KSI0/STB#
KSI2/INIT#
KSO12 52 CLOCK 128 USB_RIGHT_EN# 101 2.5V PU 6.49K Ivy SV Optimus 1G

KSO12/SLCT CK32K USB_RIGHT_EN# [32]
KSO13 53 110 3.0V PU 1.65K Ivy ULV Optimus 1G
VCORE
KSO13
1
AVSS
KSO14 54 R75 1 2 10K_4

KSI4
KSI5
KSI6
KSI7
VSS
VSS
VSS
VSS
VSS
VSS
EC27 KSO15 55 KSO14

18P/50V_4 KSO15 For Crystal-Free BD0
2
000 0.5V PU 100K SSI (X00)

w 58
59
60
61
62
63
64
65
27
49
91
113
122
75
12
001 1.0V PU 45.3K PT (X01)

+3.3V_ALW +3.3V_ALW 010 1.5V PU 24.3K ST (X02)
L6 100 2.0V PU 12K QT (A00)
ITE8502IX_JX
Place these caps close to ITE8518.

A FCM1608KF-121T02 101 2.5V PU 6.49K (A01) A
2 1 +3.3V_ALW _AVCC 110 3.0V PU 1.65K (A02)
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
1
1
C160 C203 C205
w
0.1U/16V_4 C191
1
C202 0.1U/16V_4
2
2
L7 2 1 0.1U/16V_4 1U/6.3V_4 0.1U/16V_4 0.1U/16V_4
C200
2
FCM1608KF-121T02
PROJECT : JWA
9 Size Document Number Rev
3A
SIO (ITE8518E)
Date: W ednesday, March 06, 2013 Sheet 38 of 54
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
a fix
vin FLASH / RTC
D D
m
For EC 64Mbit (8M Byte) +3.3V_ALW
o
4
2
RP1
10KX2
RTC
.c
3
1
U5
[38]EC_FLASH_SPI_CS# EC_FLASH_SPI_CS# 1 8
EC_FLASH_SPI_CLK 6 CE# VDD
[38]EC_FLASH_SPI_CLK SCK
[38]EC_FLASH_SPI_DIN EC_FLASH_SPI_DIN 5 +RTC_CELL +3.3V_RTC_LDO
SI
1
[38]EC_FLASH_SPI_DO EC_FLASH_SPI_DO 2 7
SO HOLD# C142
3 4 0.1U/16V_4
x
2
C WP# VSS C
W 25Q64FVSSIG
RTCD1
2
fi
3 RTCBT1
RTCR1 1K_4
1 +RTC_2 1 2 +RTC_1
1
BAT54C T/R 2
For PCH 64Mbit (8M Byte)
1
BAT_CONN
a
+3.3V_RUN C394
1U/6.3V_4
2
2
4
in
RP19
*10KX2_NC
1
3
Double, 25'C, Vf=0.4V, If=25mA RTC-BATTERY

one, 25'C, Vf=0.35V, If=15.8mA
U23
PCH_SPI_CS0# 1 8
B
[21]
[21]
[21]
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_CLK
PCH_SPI_SI
6
5
CE#
SCK
SI
VDD
h B
1
[21] PCH_SPI_SO 2 7
PCH_SPI_SO SO HOLD# C510
3 4 *0.1U/16V_4_NC
2
WP# VSS
.c
*W 25Q64FVSSIG_NC
2
4
6
8
RP21
0X4
1
3
5
7
[38] EC_SPI_CS0#
[38]
w
EC_SPI_SI
[38] EC_SPI_SO
[38] EC_SPI_CLK
w
w
A A

PROJECT : JWA
3A
FLASH / RTC
1
39 of 54
1 2 3 4 5 6 7 8
fix
vina
KB CONN
TP CONNECTOR
A JKB1 A
KSI0 1
+3.3V_RUN KSI1 2 1
4.7KX2 2
KSO0 3
1 2 CLK_TP_SIO KSO1 4 3
3 4 DAT_TP_SIO +3.3V_RUN KSI2 5 4
m
KSI3 6 5
C372 2 1 0.1U/16V_4 KSI4 7 6
RP18 7
C342 2 1 0.1U/16V_4 KSI5 8
CN8 KSO2 9 8
ACS_88513-080N KSI6 10 9
3 [38] KSO[0..15]
KSI7 11 10
CLK_TP_SIO R184 *0_6_SHORT_NC CLK_TP_SIO_L 1 KSO3 12 11
[38] CLK_TP_SIO 2 12
13
o
[38] DAT_TP_SIO R189 *0_6_SHORT_NC DAT_TP_SIO_L [38] KSO4
DAT_TP_SIO 3 KSI[0..7] 13
KSO5 14
4 KSO6 15 14
[13,23] SMBDATA 5 15
[13,23] KSO7 16
SMBCLK 6 KSO8 17 16
[23] SMB_INT# 7 17
KSO9 18
8 18
.c
KSO10 19
KSO11 20 19
KSO12 21 20
KSO13 22 21
KSO14 23 22
KSO15 24 23
KSO2 25 24
26 25 29
27 26 29 30
28 27 30
x
B 28 B
50690-0284N-001
fi
a
ECP3 100PX4 ECP5 100PX4
8 7 KSO4 8 7 KSI2
6 5 KSO5 6 5 KSI3
4 3 KSO6 4 3 KSI4
in
2 1 KSO7 2 1 KSI5
ECP1 100PX4 ECP2 100PX4

8 7 KSO12 8 7 KSO8
6 5 KSO13 6 5 KSO9
4 3 KSO14 4 3 KSO10
C
h 2 1
ECP4 100PX4
KSO15 2 1
ECP6 100PX4
KSO11
C
.c
8 7 KSO2 8 7 KSI0
6 5 KSI6 6 5 KSI1
4 3 KSI7 4 3 KSO0
2 1 KSO3 2 1 KSO1
Layout Note: 100P CAPS CLOSE TO JKB1

w
HALL Sensor
w
+3.3V_ALW
w
1 2
D D
C118 0.1U/16V_4
U2
1
VDD
2
VSS
3 LID_SW #
OUT LID_SW # [38]
APX9132H AI-TRG PROJECT : JWA
3A
TP / KB/HALL
4 5 6
7
Sheet 40
8
of 54
5 4 3 2 1
fix
vina
3V ALW ON POWER LOGIC
D +3.3V_ALW D
+5V_ALW2
m
R13
2
100K_4
R21
100K_4
2
1
R67
o
100K_4
SYS_PWR_SW# [38]
SYS_PWR_SW#
1
1
C60
.c
0.1U/16V_4
2
3.3V_ALW_ON
D5 3.3V_ALW_ON [44]
2
POWER_ SW_IN0# 3
3
1 POWER_SW# 5 DMN66D0LDW-7
Q7A
C C
x 4
BAT54C T/R
1
C75
*0.1U/16V_4_NC
fi 6
ALW_ON 2 DMN66D0LDW-7
[38,46] ALW_ON Q7B
1
3
[38,53] ACAV_IN ACAV_IN 2
a
Q6
1
2N7002W
in
B B
h
.c
PWR button SW1
w
POWER_ SW_IN0# 1 3
2 4
C53 SKQGCAE010
*100P/50V/0402_NC
w
A A
w

PROJECT : JWA
3A
PWR SW/LED
5 4 3 2 1
http://vinafix.vn
5 4 3 2 1
f ix
ina
AOAC
FAN CONN
v
+5V_RUN
+3.3V_ALW 50271-0040N-001
4 6
3 4 6 5
[38] FAN1_TACH 2 3 5
FAN1_TACH 2
1
[38] 1
C480 FAN1_PW M 1
RT1 C158
*10K/NTC_6_NC 2.2U/6.3V_6 0.1U/16V_4 J3
2
D D
2
[38] T_CPU
T_CPU
R272 2 1 4.7K_4
m
+5V_RUN
1 R91
*1.5K/F_4_NC
2
G781-1P8
o
SMBus address is 1001101xb (9Ah) (x is R/W bit).
EMC1422 SMBus address is 1001_100xb (98h) (x is R/W bit).
+3.3V_RUN
SYS_SHD#
.c
C1 should
place close to 4.7K 6.8K 10K 15K 22K 33K
C210 *0.1U/16V_4_NC
IC 1 2 ALERT#
U17
[17] VGA_THERMDP 1 8 SMBCLK3 [17,36,38,42] 4.7K 77'C 83'C 89'C 95'C 101'C 107'C
VGA_THERMDP VDD SCLK SMBCLK3
2 7 SMBDAT3 [17,36,38,42]
D+ SDATA SMBDAT3
1
C452
C1
x
C *2200P/50V_4_nC 3 6 6.8K 78'C 84'C 90'C 96'C 102'C 108'C C
D- ALERT#
2
[17] VGA_THERMDN 4 5
VGA_THERMDN THERM# GND
*G781-1P8_NC 10K 79'C 85'C 91'C 97'C 103'C 109'C
fi
15K 80'C 86'C 92'C 98'C 104'C 110'C
22K 81'C 87'C 93'C 99'C 105'C 111'C
a
THERMAL IC
33K 82'C 88'C 94'C 100'C 106'C 112'C
in
1.Place C586 close to EMC1422-U1
2.Place C585 to be close to Q38
Total capacitance between D+/D- is 2200pF(max)
if use 2200pF for C586, then C585 should be dummy
Place under CPU 10/20mils

B REM_DIODE1_P
+3.3V_RUN
U6 h B
3
C190 1 8 SMBCLK3 [17,36,38,42]

C172 VDD SCL SMBCLK3
2 2200P/50V_4
.c
*100P/50V_4_NC 2 7 SMBDAT3 [17,36,38,42]
SMBDAT3
2
MMST3904-7-F DP SDA
1
Q11 REM_DIODE1_N 3 6 THERM_ALERT#

DN ALERT#
4 5
SYS_SHDN# GND
EMC1422-1-ACZL-TR
w
1
C170
0.1U/16V_4 SYS_SHDN#
2
Q12
2N7002W CHECK OTP WITH Thermal.
w
1 3 THERM_STP#
A THERM_STP# [38,44] OTP 85 degree C A
R1
2
+3.3V_RUN R71 1 2 10K/F_4 THERM_ALERT#

[19,38,51] IMVP_PW RGD IMVP_PW RGD
R70 1 2 10K/F_4 SYS_SHDN#
R2
EMC1422 17 NTC7718W
PROJECT : JWA
OTP 85 degree : R1 = 10K, R2 = 6.8K OTP 85 degree : R361 = 18.7K, R362 = 2K Size Document Number Rev
3A
OTP 90 degree : R1 = 6.8K, R2 = 10K OTP 91 degree : R361 = 10.5K, R362 = 7.5K FAN & THERMAL
5 4 http://vinafix.vn OTP 90 degree : R1 = 10K, R2 = 10K
3 2
1
42 of 54
5 4 3 2 1
fix
vina
D D
Touch Screen
m
+5V_RUN +3.3V_RUN
o
1
1
C515 C229
*0.1U/16V_4_NC 0.1U/16V_4
.c
CN3
1
1 2
2 3
3 4
4 5
5 6
6 7 TS_RST#_R1 R323 2 1 *0_4_NC
x
7 TS_RST# [22]
C 8 USBP13N_L USBP13N_L EL12 1 2*DLP11SN900HL2L_NC [43]
C
8 9 USBP13P_L USBP13P_L 4 3 USBP13N
9 10 INT_H_R1 R324 2 1 *0_4_NC
INT_H [22]
USBP13P [43] TOUCH SCREEN
10 11 USBP12N_L
11 12 USBP12P_L USBP12N_L EL11 1 2DLP11SN900HL2L
12 USBP12N [22]
fi
13 USBP12P_L 4 3
13 14 DMIC_CLK_TS R281 0_4 USBP12P [22] CCD
14 15 DMIC_DATA_TS R279 0_4
1
15 16
21 16 17 DIGITAL_D1_R
21 17 DIGITAL_D1_R [36]
22 18
23 22 18 19 DIGITAL_CLK_R
DIGITAL_CLK_R [36]
DMIC and CCD To DSP
24 23 19 20
a
24 20
7300J20-000000-G4-R
in
DIGITAL_D1_R
DIGITAL_CLK_R
EC66 EC65
180P/50V_4 180P/50V_4
h B
.c
w
w
w
A A

PROJECT : JWA
3A
Touch Screen
Date: Tuesday, March 05, 2013 Sheet
1
43 of 54
1 2 3 4 5 6 7 8
fix
vina
+3.3V_RUN
A A
1
R74
10K_4
m
2
SR3 SR2
*SR_0402 *SR_0402
[47]1.5V_SUS_PW RGD 1.5V_SUS_PW RGD 1 2 [38,42] THERM_STP# THERM_STP# 1 2
1 2 1 2
o
SR4
*SR_0402 [41] 3.3V_ALW _ON 1 2 +3.3V_EN2 [46]
3.3V_ALW _ON 1 2 +3.3V_EN2
[50]VCCSA_PW RGD VCCSA_PW RGD 1 2 HW PG [19,38]
1 2 HW PG
SR1
*SR_0402
.c
x
B B
fi
+PW R_SRC +PW R_SRC
+PW R_SRC +1.05V_PCH +1.05V_PCH
1
1
1
C437 C76
a
C438 1U/25V_6 0.1U/25V_6 C133 C135
2
1U/25V_6 1U/6.3V_4 0.1U/16V_4
2
2
in
+VCHGR +VCHGR
1
C396 C397 +PW R_SRC +PW R_SRC

1U/25V_6 0.1U/25V_6 +PW R_SRC +PW R_SRC
2
1
h
1
C77 C435
C 0.1U/25V_6 C428 C440 C
2 1U/25V_6
2
+VCHGR +VCHGR 1U/25V_6 0.1U/25V_6
2
1
.c
C398 C395
1U/25V_6 0.1U/25V_6
2
+5V_RUN +5V_RUN +5V_RUN
+VCC_GFX_CORE +VCC_GFX_CORE
w
1
1
C25 C326 C469
C180 C159
1U/6.3V_4 0.1U/16V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
2
2
+PW R_SRC
w
1
C439
1U/25V_6
2
D D

PROJECT : JWA
1A
System Reset Circuit
http://vinafix.vn
1 2 3 4 5 6 7 8
A B C D E
fix
ina
+VCHGR
CN10
BP07061-BA015
v +VCHGR
B_TEMP_MBAT
1
2 1
3
2
PC130 PC129 4 3
0.1U/25V_4 0.1U/25V_4 SMC 5 4
SMD 6 5
7 6 10
8 7 10 9
8 9
1 PR147 1
PR149 PR148 200K/J_4
Parallel routing 330/F_4 330/F_4 +3.3V_ALW
[38,53] PR146
SMBDAT0 1K/F_4
m
[38,53] SMBCLK0
PBAT_PRES# [38,45]
+3.3V_ALW PC128 PC127

0.01U/25V_4 0.01U/25V_4
ESD4
3 4
o
2 3 4 5
1 2 5 6
1 6 Place this cap
close to EC
TVL ST23 04 AD0
.c
+DC_IN_SS
x
2 CN1 EL10 PQ27 2
POWER_JACK HCB2012KF800T50 AON7403
1 +DCIN_JACK 1 2 +DC_IN 1 8
2 2 7
3 3 6
1
fi
5
4
1
1
1
PC134 PC135 PR154 PR155
4
1
EC49 EC48 EC1 PC136 PR161 0.01U/25V_4 0.1U/25V_6 *6.8K/F_4_NC *6.8K/F_4_NC
2
2200P/50V_4 1000P/50V_4 0.1U/25V_6 EC5 PR169 0.47U/25V_8 240K_4
2
2
2 0.1U/25V_6 *2.4K_12_NC
2
2
PQ29
a
*IMD2AT108_NC
2
6
PR153
in
PQ4B PR162 2 PQ2B *0_4_NC
[53] AC_OK
6
*DMN66D0LDW-7_NC 47K_4 *DMN66D0LDW-7_NC
2
1
1
3 HW1 PR17
h 3
1
*1K_4_NC
[38] 2 1 2 1 +3.3V_ALW
AC_OFF
PC4
2
PR14 *10K_4_NC *1U/25V_6_NC
.c
PQ4A
*DMN66D0LDW-7_NC PR3
3
3
*1K_4_NC
[38,45] PBAT_PRES# 5 PBAT_PRES# 1 2 5 PQ2A
PBAT_PRES#
*DMN66D0LDW-7_NC
4
4
HW2 HW3
1
PC7
w
*0.01U/25V_4_NC
2
w
w
4 4

PROJECT : JWA
1A
DC IN / BATT
A B
http://vinafix.vn C D
E
45 of 54
5 4 3 2 1
f ix
vina
+3.3V_RTC_LDO
PC89
1U/6.3V_4
2 1
D D
PR99 PR110
30K/F_4 13K/F_4
TPS51125A_FB1 1 2 TPS51125A_VFB1 TPS51125A_VFB2 1 2 TPS51125A_FB2
1
PR101
m
TPS51125A_VREF
20K/F_4 20K/F_4
6 PR97 PR185 PR109 6
182K/F_4 121K/F_4
2
1 2 5V_EN 3.3V_EN 1 2
+PWR_SRC +3.3V_RTC_LDO +PWR_SRC
2/18
1
1
10U/25V_8
PC152
0.1U/25V_6
EC55
2200P/50V_4
EC56
PC92
2/18
1
2200P/50V_4
EC58
0.1U/25V_6
EC57
10U/25V_8
PC165
1 2
o
2
2
1U/6.3V_4
34
25
2
1
6
+3.3V_ALW
ENTRIP1
VFB1
TONSEL
VFB2
ENTRIP2
GPAD
GPAD
VREF
33 26
GPAD GPAD
3.3 Volt +/- 5%
+5V_ALW Fsw : 375K
5 Volt +/- 5% Current : 2.35A
.c
TPS51125A_VO1 24 7 TPS51125A_VO2
VO1 VO2
Fsw : 300K PQ34
PC79 PR92 23
PGOOD VREG3
8 PR112 PC93 OCP : 5A
0.1U/25V_6 0.1U/25V_6
Current : 8.802A 2.2_6 2.2_6
8
7
6
5
5
6
7
8
AON7410 2 1 1 2 5V_BST 22 PU5 9 3.3V_BST 1 2 2 1
VBST1 VBST2
OCP : 15.1A
4 5V_DH 21 TPS51125ARGER 10 3.3V_DH 4 PQ38
DRVH1 DRVH2 RQ3E070BNFU7TB
PL8 20 11 PL9
6 2.2UH20%12A(TMPB0603M-2R2MN-Z01) LL1 LL2 2.2UH20%12A(TMPB0603M-2R2MN-Z01)
6
3
2
1
1
2
3
+5V_ALW 2 1 5V_LX 19 12 3.3V_LX 1 2 +3.3V_ALW
DRVL1 DRVL2
1
1
PQ35 32 27
x
2/18
SKIPSEL
8 GPAD GPAD
7
6
5
5
6
7
8
C PC81 AON7752 PC170 C
VREG5
1
1
GPAD
GPAD
150U/6.3V_7343
150U/6.3V_7343
31 28
VCLK
*2200P/50V_4_NC 2200P/50V_4
2/18
GND
1 2
1 2
EN0
GPAD GPAD
1
1
VIN
PC155
0.1U/25V_6
PC153
0.1U/25V_6
SJ15 SJ16 + 4 5V_DL 3.3V_DL 4 PQ36 + SJ19 SJ20
1
1
PC160
PC161
SJ0201 SJ0201 RQ3E070BNFU7TB SJ0201 SJ0201
2
2
TP19 5V_DH
2
30
18
17
16
15
14
13
29
2
PR93 SJ3 3.3V_DH TP66 PR189
2
3
2
1
1
2
3
2
*2.2_8_NC 5V_DL 1 2 2.2_8
fi
TP64 1 2
TPS51125A_VO1
TPS51125A_VO2
3.3V_DL
TPS51125A_FB1
TPS51125A_FB2
TP65
2
2
SJ0402
AGND_DC/DC
VCLK +3.3V_RTC_LDO
+5V_ALW2
close to close to
a
output Cap +5V_ALW output Cap
PC85
PC86 10U/6.3V_8
2
0.1U/25V_6 BAT54S-7-F
2 1 1 PC84
0.1U/25V_6
PD2 3 2 1
+3.3V_RTC_LDO
in
2 1 2
Enable
1
PC76
0.1U/25V_6 +PWR_SRC
1
PR108
PC80 10K_4
2
1
BAT54S-7-F 0.1U/25V_6
2
1 PC88 3.3V_EN
0.1U/25V_6
2
PD1 3
6
2
+15V_ALW
PQ13A 5 PQ13B 2 [44]
B +3.3V_EN2 B
DMN66D0LDW-7 DMN66D0LDW-7
1
1
PC73
0.1U/25V_6 PC95
2
*100P/50V_4_NC
2
.c
+3.3V_RTC_LDO
2
PR187
10K_4
w
1
5V_EN
TPS51125A TONSEL Connection and Switching Frequency
6
PQ40A 5 PQ40B 2
ALW_ON [38,41]
Ton REG5 REG3 VREF GND DMN66D0LDW-7 DMN66D0LDW-7
w
1
PC90
*100P/50V_4_NC
2
Channel1 Fs 365 kHz 300 kHz 245 kHz 200 kHz
Channel2 Fs
w
460 kHz 375 kHz 305 kHz 250 kHz

A A

PROJECT : JWA
http://vinafix.vn
1A
3.3V_ALW / 5V_ALW (TPS51125ARGER)
5 4 3 2 1
5 4 3 2 1
fix
vina [44]
Need confirm with EE or not have pull high resister for PG.
1.5V_SUS_PWRGD +1.5V_SUS(UMA)
1.5 Volt +/- 5%
Fsw : 400K
2
D D
+PWR_SRC
6 PR122 200K_4 53.6K/F_4 Current : 7A
SJ0402 2/18 PR118 PR119 6 OCP : 12.1A
1 2 1.5V_S5
[19,38] SIO_SLP_S4#
1.5V_MODE 1
1
R1
1.5V_RIP
PR121
10K_4 2/18
1 2 1.5V_S3
[9,19,38] SIO_SLP_S3# +1.5V_SUS(Dis)
1
PC173
0.047U/10V_4
EC62 EC63
0.1U/25V_6
PC113
10U/25V_8
PC112
10U/25V_8
1.5 Volt +/- 5%
2200P/50V_4
Fsw : 400K
2
2 1
m
Current : 9.209A
17
16
20
19
18
24 PQ17 OCP : 15.9A
MODE
TRIP
PGOOD
S3
S5
PwPd
5
6
7
8
25 AON7430L
23 PwPd
PwPd 26 4
22 PwPd PC110 +1.5V_SUS
PwPd PR124
0_6 0.1U/25V_6
4 15 1.5V_BST 1 2 2 1
1
2
3
VTTGND VBST
o
C C
1 14 1.5V_DH PL11
VTTSNS DRVH 0.68UH 20% 16A(TMPB0603M-R68MN-Z01)
3 TPS51216RUKR 13 1.5V_LX 1 2
6
+0.75V_DDR_VTT VTT SW
PU7
+DDR_VTTREF
5 11 1.5V_DL
VTTREF DRVL
1
2/18
1
1
PC103 +1.5V_VLDOIN 2 12 PC111
VLDOIN V5IN +5V_ALW
.c
PC102 0.22U/10V_6 PQ18 1000P/50V_4
1 2
1
5
6
7
8
1
10U/6.3V_8 AON7754
2
1
VDDQSNS
PC108 + SJ21 SJ4
1
1U/6.3V_4 4 PC107 PC174 PC109 SJ0201 SJ0603
2
REFIN
PGND
2
VREF
PwPd
PR126 0.1U/16V_4 390U/2.5V_63*58 *10U/6.3V_8_NC
GND
2
1.5V_DH TP23 2.2_8
2
close to
1
2
3
2
1.5V_DL TP30 output Cap
10
21
+1.5V_VLDOIN
VOUT = (R3/(R2 +R3))*1.8
TPS51216_REFIN
x
1
TPS51216_VREF
PR117
20K/F_4 1.5V_FB
B B
For Dis For UMA R2
2
Outputs Management by S3, S5 control
fi
PQ17: AON7430L PQ17: AON7410 1
1
1
PN: BAM74300000 PN: BAM74100001 PR120 State S3 S5 VDDQ VTTREF VTT
PC105 110K/F_4 PC106
PQ18: AON7754 PQ18: AON7702A 0.1U/16V_4 0.01U/25V_4
2
S0 HI HI On On On
2
PN: BAM77540000 PN: BAM77020001

PR119: 53.6K PR119: 38.3K S3 LO HI On On Off (Hi-Z)
a
R3
PN: CS35362FB17 PN: CS33832FB08
S4/S5 LO LO Off (discharge) Off (discharge) Off (discharge)
PC112: Pop 10uF PC112: De-pop 10uF
in
A A

PROJECT : JWA
5 4
h 3 2
Date:
1.5_SUS/0.75_DDR_VTT (TPS51216RUKR)
Tuesday, February 26, 2013
1
Sheet 47 of 54
1A
.c
w
w
w
http://vinafix.vn
1 2 3 4 5
f ix
ina
+5V_ALW2 +15V_ALW +5V_ALW +5V_RUN
+5V_RUN
v
PQ11
6
AO6402A Current : 3.87A +5V_ALW2 +15V_ALW +3.3V_ALW +3.3V_SUS
+3.3V_SUS
1
5 4 PQ37
PR2 PR1
2
1 6
AO6402A Current : 285mA
1
100K_4 100K_4 5 4
PC72 2
3
RUN_ON_ENABLE 1 2 0.1U/16V_4 PR88 PR91 1
1
50uA 100K_4 100K_4
1
A PR87 PC162 A
3
RUN_ON# 5 PQ1A 10K_4 PC77 SUS_ON_ENABLE 1 2 0.1U/16V_4
2
DMN66D0LDW-7 4700P/25V_4 50uA
2
6
1
PR182
4
[26,38]
2 PQ1B SUS_ON# 5 PQ12A 100K_4 PC159
RUN_ON
DMN66D0LDW-7 DMN66D0LDW-7 0.047U/25V_4
2
6
1
4
[38] 2 PQ12B
SUS_ON
DMN66D0LDW-7
m
+3.3V_ALW +3.3V_RUN
PQ39 +3.3V_RUN +5V_ALW
6
AO6402A Current : 1.2A PQ9
+5V_SUS
5 4 AO6402A +5V_SUS
2
1
6
5 4
Current : 30.5mA
1
2
PC169 1
3
1 2 0.1U/16V_4
o
2
1
3
1
PR186 PC74
150K_4 PC167 1 2 0.1U/16V_4
2
0.047U/25V_4
1
PR90
10K_4 PC78
4700P/25V_4
.c
B B
+1.5V_SUS +1.5V_RUN
PQ15 +1.5V_RUN
6
AO6402A Current : 467mA
5 4
2
1
x
PC101
3
1 2 0.1U/16V_4
2
PR116
200K_4 1
PC100
0.047U/25V_4
2
fi
a
C C
in
h
.c
D D
w

PROJECT : JWA
w

1A
Load Switch
1 2 3 4 5
w
http://vinafix.vn
1 2 3 4 5
fix
vina
A A
+3.3V_RUN
m
6 +1.05V_PCH
1
PR96 +PW R_SRC
1
10_4
2 1.05V_VCC
PR95 1.05 Volt DC +/- 2%
10K_4
+5V_SUS
Fsw : 400K
o
2/18 TDC : 11.606A
2
1
PC83 OCP : 20A
1
4.7U/6.3V_6
2
EC20 EC19 PC71 PC154
.c
2200P/50V_4 0.1U/25V_6 10U/25V_8 10U/25V_8
2
11
5
PQ8
5
6
7
8
PR98 AON7430L
G0
VCC
Need confirm with EE 80.6K/F_4
or not have pull high 1 2 1.05V_CS 10 3 1.05V_DH 4
CS UGATE PC75
resister for PG. PR94
0_6 0.1U/25V_6
[50] 9 4 1.05V_BST 1 2 2 1
1.05V_PCH_PW RGD
1
2
3
PGOOD BOOT PL6
6
x
B PU4 1UH 20% 12A(TMPB0603M-1R0MN-Z01) B
+3.3V_RUN 1 2 1.05V_EN 8 RT8240BZQW 2 1.05V_LX 1 2 +1.05V_PCH

PR103 100K_4 EN PHASE
13 1 1.05V_DL PQ10 2/18

PAD LGATE
RGND
5
6
7
8
fi
VOUT
AON7754
GND
1
1
1
4 PC157
1
PC87 *1000P/50V_4_NC +
12
1
0.047U/10V_4 1.05V_DH TP20 PC151 PC156
2
PR100 0.1U/16V_4 330U/2V_7343
1
2
3
2
1
1.05V_DL TP63 *10_4_NC
a
PR181
2
*2.2_8_NC
2
in
6 2/18
VCCIO_SENSE1 1 2
VCCIO_SENSE [9]
PR105 SJ0402
PR106 SJ0402
VSSIO_SENSE1 1 2 [9]
VSSIO_SENSE
h 2/18
1
C C
PR102
6
*10_4_NC
.c
2
w
w
w
D D

PROJECT : JWA
1A
+1.05V_PCH / VTT (RT8240BZQW)
5
49 of 54
5 4 3 2 1
f ix
vina
PR64
6
10_4
+5V_SUS 1 2 VCSA_VCC +PW R_SRC
1
D D
1
PC54
4.7U/6.3V_6 EC52 EC53 PC55 2/18
+VCCSA_CORE
2
2200P/50V_4 0.1U/25V_4 4.7U/25V_8
2
PQ7 0.9 Volt +/- 5%
5
6
7
8
RQ3E070BNFU7TB
12
13
m
Fsw : 300K
5
Need confirm VCCSA_DH 4
TDC : 4.2A
VCC
GND
PAD
with EE or not PR49
have pull high
1
162K/F_4
2 11 3
OCP : 7A
resister for PG. VCCSA_CS PR62 PC46
1
2
3
CS UGATE 0.1U/25V_6
0_6
4 VCCSA_BST 1 2 2 1 PL5
9 PU2 BOOST
o
1UH 20% 12A(TMPB0603M-1R0MN-Z01)
[44] VCCSA_PW RGD PGOOD
RT8241DZQW 2 VCCSA_LX 1 2
6
PHASE +VCCSA_CORE
PR59 SJ0402
1
VCCSA_EN 1 2 VCCSA_EN1 6 1 PQ6
EN LGATE
5
6
7
8
1
RQ3E070BNFU7TB PC49
2/18
1
*1000P/50V_4_NC +
1 2
.c
VCCSA_DL 4 PC144 PC147
G0
G1
FB
1
0.1U/25V_4 220U/2.5V_7343
2
1
PC53
10
*0.047U/10V_4_NC PR54 PR50
2
1
2
3
VCCSA_DH TP14 *2.2_8_NC *100_4_NC
2
VCCSA_DL TP9
2
[9] VCCSA_VID0 PR51
SJ0402
x
C
[9] VCCSA_FB 1 2 C
VCCSA_VID1 VCCSA_SENSE [9]
6 2/18
fi
VCCSA_VID1 VCCSA_VID0 VCCSA_CORE
a
Low Low 0.9V
High Low 0.8V
in
Low High 0.725V
High High 0.675V
+5V_ALW
+3.3V_RUN
B
6
h B
2
PR107
2/18
.c
10K_4
PL10
1UH 20% 12A(TMPB0603M-1R0MN-Z01)
6
2/18
1
VCCSA_EN 4 1 1 2 +1.8V_RUN
PGOOD LX1
9 2
PVIN LX2
1
+1.8V_RUN
1
10 3 PC94
PVIN LX3
PU6 7
*22P/50V_4_NC PR113
20K/F_4
R1 1.8 Volt +/- 5%
TDC : 0.869A
w
2
RT8068AZQW NC
1
8 6
SVIN FB PC168 PC164 PC163
OCP : 3.5A
11 5 1 2 +3.3V_RUN 0.1U/25V_4 10U/6.3V_6 10U/6.3V_6
2
GND EN
1
PR104 10K_4
R2
1
PC98 PC97 PC96 PR111

w
10U/6.3V_6 0.1U/25V_4 1U/6.3V_4 PC91 10K/F_4

1.05V_PCH_PW RGD [49]
2
0.047U/10V_4
2
2
w
A A
VOUT = 0.6(1+R1/R2)

PROJECT : JWA
1A
VCCSA (RT8241DZQW)
1
50 of 54
5 4 3 2 1
f ix
vina
1
D D
2
PR34 PC30 PC29 PR176
10_4 33NF/25V_4 2 1 PC32 PC35 PR177 220K_6 NTC
1 2 2 1 1000P/50V_4 470P/50V_4 75K/F_4
1
IMONA
0.1U/16V_4
6132AGND
2
PR29 PR42 1 2
24.3K/F_4
8.06K/F_4 806/F_4 2 1
m
TRBSTA# 1 2 1 2 PR33 PR35
165K/F_4
PR37 PC26 PUT COLSE
1
1 2 1 2 PC39 1 2 10P/50V_4
PC34 TO GT
10_4
33NF/25V_4 560P/50V_4
PR39
PC36 PR38 Inductor
2
1 2 1 2 82.5K/F_4
4.3K/F_4 1 2 SWN1A
1 2 2200P/50V_4
o
PR27 1K/F_4 [52]
CSREFA 100K_4 NTC
6132AGND
6132AGND
PR180
PUT COLSE
1 2 1 2
15.8K/F_4
2 1 TO V_GT
2/18
2
PR46 SJ0402 PC37 HOT SPOT
1
[9] 1000P/50V_4 PR179
VCC_AXG_SENSE
.c
[9] PC41 1 2
VSS_AXG_SENSE
+1.05V_PCH PR45 SJ0402 1000P/50V_4 13K/F_4
PR41
+5V_SUS
2
2 1
6132AGND
1
SJ1 1 2 PR40
6
1
SJ0402 5.1K/F_4
1 2 PC40 CSP1A 1 2
CSCOMPA
1 2 SWN1A [52]
TRBSTA#
DROOPA
CSSUMA
PC51 PR52 PR53 0.1U/16V_4
CSREFA
COMPA
1
IMONA
CSP1A
*1U/6.3V_4_NC 130_4 54.9/F_4
DIFFA
VSNA
VSPA
ILIMA
FBA
PC38
2
+5V_SUS 6132AGND PR43 25.5K/F_4 0.047U/10V_4
2
6132AGND VR_SVID_DATA PR55 1 2 CSREFA
x
C C
2_6
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VR_SVID_CLK +5V_SUS 1 2 PU3 PR47 PC45 PR75
NCP6132A 2.7_6 0.22U/25V_6 5.1K/F_4
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
EPAD
TRBSTA#
PC44 BSTA 1 2 1 2 CSP1 1 2 [52]
SWN1
2.2U/16V_6
1
2 1 VCC 1 45 SWA
6132AGND VCC PWMA SWA [52]
fi
2 44 [52] PC66
VDDBP BSTA HGA
Add GFX resister 3 42 [52] 0.047U/10V_4
LGA
2
4 VRDYA SWA 43 HGA PC48 CSREF
[38] IMVP_VR_ON EN HGA
[9] 5 41 LGA PR58 0_6 0.22U/25V_6
VR_SVID_DATA 6 SDIO LGA 40 BST2 1 2 1 2 PR81
[9] VR_SVID_ALERT# ALERT# BST2
[9] 7 38 SW2 [52] 5.1K/F_4
VR_SVID_CLK SCLK SW2 SW2
2 PR56 1 10K/F_4 VBOOT 8 39 HG2 [52] CSP2 1 2 [52]
VBOOT HG2 HG2 SWN2
6132AGND 2 PR57 1 64.9K/F_4 ROSC 9 37 LG2 [52]
ROSC LG2 LG2
1
+PWR_SRC 1 2 6132VRMP 10 36 +5V_SUS
VRMP PVCC
a
IMVP7_PROCHOT# 11 35 PC59
VRHOT# PGND
1
1
PR60 IMVP_PWRGD 12 34 LG1 0.047U/10V_4
6 LG1 [52]
2
1K/F_4 PC47 VSN 13 VRDY LG1 32 HG1 PC50 CSREF
VSN HG1 HG1 [52]
0.01U/25V_4 VSP 14 31 PC58 2.2U/16V_6
2
2
15 VSP BST1 33 PR67 0_6 0.22U/25V_6
CSCOMP
DIFF SW1
TRBST#
BST1 1 2 1 2
DROOP
CSSUM
DRVEN
CSREF
COMP
TSNS
6132AGND CSP3
CSP2
CSP1
PWM
IOUT
[7,38,53] IMVP7_PROCHOT#
ILIM
in
SW1
FB
SW1 [52]
[19,38,42] IMVP_PWRGD
PR72
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PR61 SJ0402 30 41.2K/F_4
2 1 1 2
COMP
TSENSE
CSCOMP
TRBST#
IMON
DROOP
FB
CSSUM
1
PC60
ILIM
CSP2
CSP1
VSSSENSE [9]
[9] PC52 0.1U/16V_4
VCCSENSE PR63 SJ0402 1000P/50V_4 1 2
6132AGND
2
2 1
PR167 100K_4 NTC

B
6 2/18
1
PR70
1K/F_4
2
22P/50V_4
PC67
1 2
1
PR166
1
h 2
2
13K/F_4
PUT COLSE
TO VCORE
HOT SPOT
B
.c
PR69 560P/50V_4
PR66 PC57 49.9/F_4 PC65 PC69
PR76 +5V_SUS
10_4 33N/25V_4 1 2 1 2 1 2 1 2
2 1 2 1 5.1K/F_4 CSREF [52]
CSREF
2200P/50V_4
1
PR65 PR68 PC62

8.06K/F_4 806/F_4 1000P/50V_4
2
TRBST# 1 2 1 2
1
6132AGND
w
PC68 PR77 CSSUM

1
PR74 12.4K/F_4
2
PC56 24.3K/F_4 PC61 1000P/50V_4

33N/25V_4 0.1U/16V_4 1 2 1 2 SWN1
2
PR83
PC64 330P/50V_4 140K/F_4
6132AGND 6132AGND 1 2 1 2 SWN2
w
PR82
140K/F_4
PR44 PC33 1 PR79 2 1 PR80 2
510/F_4 1000P/50V_4 75K/F_4 165K/F_4
CSCOMPA 1 2DROOPA 2 1 CSREFA
PUT COLSE
2 1
TO VCORE
w
A
CSCOMP 1 2DROOP 2 1 CSREF Phase 1 PR173 A
Inductor 220K_6 NTC

PR78 PC63
510/F_4 1000P/50V_4

PROJECT : JWA
1A
CPU_CORE (NCP6132)
http://vinafix.vn
5 4 3 2 1
5 4 3 2 1
f ix CPU Power +PWR_SRC
ina
6
v [51] HG1
HG1
[51] HG2
HG2 +PWR_SRC
1
2/18
1
EC11 EC9 PC146 PC145
0.1U/25V_6 10U/25V_8 10U/25V_8 EC8 EC7 PC139 PC140
2
D 2200P/50V_4 10U/25V_8 10U/25V_8 D
2
PQ31 2200P/50V_4 0.1U/25V_6
2
FDMS3660S PQ30
2
G1
D1
D1
D1
FDMS3660S
19
G1
D1
D1
D1
PL4 +VCC_CORE +VCC_CORE
0.24UH (FDUE0640-H-R24M=P3) PL3
19
2 1 0.24UH (FDUE0640-H-R24M=P3)
S1/D2
2 1
S1/D2
1
[51] SW1 9
SW1
1
PC42 [51] SW2 9
SW2
1
*1000P/50V_4_NC SJ13 SJ14 PC25
1
G2
1 2
S2
S2
S2
SJ0201 SJ0201 PC31 *1000P/50V_4_NC SJ11 SJ12
1
m G2
S2
S2
S2
1 2
1
2
2
0.1U/16V_4 SJ0201 SJ0201
2
PC28
5
PR48 0.1U/16V_4
2
*2.2_8_NC PR32
*2.2_8_NC
2
[51] LG1
LG1
2
[51] LG2
LG2
o
[51] SWN1
C [51] SWN2 C
PR85
10_4 PR84
.c
[51,52] CSREF 1 2 10_4
CSREF
[51,52] CSREF 1 2
+PWR_SRC CSREF
6
[51] HGA
HGA
1
EC54 EC51 PC149 PC150 2/18
10U/25V_8 10U/25V_8
2
PQ33 *2200P/50V_4_NC *0.1U/25V_6_NC
x
FDMS3660S
1
2
G1
D1
D1
D1
+VCC_GFX_CORE
PL7
19
0.24UH (FDUE0640-H-R24M=P3) +VCC_CORE
2 1
S1/D2
fi
1
B [51] SWA 9 B
SWA
1
PC70
1
1000P/50V_4 SJ18 SJ17 + +
1
G2
1 2
S2
S2
S2
SJ0201 SJ0201 PC82 PC166 PC158
2
0.1U/16V_4 330U/2V_7343 330U/2V_7343
8
1
2
2
PR86 + + + +
2.7_8 PC24 PC141 PC142 PC23
a
330U/2V_7343 330U/2V_7343 330U/2V_7343 330U/2V_7343
2
2
[51] LGA
LGA
[51] SWN1A
in
PR36
10_4
[51] CSREFA 1 2
CSREFA
A A
h Size Document Number

PROJECT : JWA
Rev
1A
.c
CPU_CORE (NCP6132)
Date: Wednesday, March 27, 2013 Sheet 52 of 54
5 4 3 2 1
w
w
w
http://vinafix.vn
A B C D E
fix
v ina
+PWR_SRC
PQ22
AON7403
1 8
2 7
PQ42 3 6
1 AON7403 PR193 5 1
0.01_12
1
8 1
6
4
+DC_IN_SS +DC_IN_SS 7 2 1 2 EC38 EC37
6 3 1P 1 2 2P *0.1U/25V_6_NC BATDIS_ID_DOD
2
5 1P 2P
REGN_LDO *2200P/50V_4_NC
m
2/18
1
4
PR191 PR192 PC175
1
10K_4 100K_4 1U/25V_6

PQ21
2
[45] 1 2 1 2
AC_OK PR141 PR136 PR137
Q1
PR127 1 2
10K/F_4 +VCHGR 1K_6 220K_4 220K_4
6 5
2
5 PQ19A PC117 3 4
o
[38,41] ACAV_IN +PWR_SRC
Q2
DMN66D0LDW-7 0.1U/16V_4
2 1 MMDT2907A BATDIS_ID_DOD
4
REGN_LDO
1
1
PC116 PC118 PR138 PR142
2
1
PR128 0.1U/25V_6 0.1U/25V_6 1M_4 1M_4
2
12.4K/F_4 PR198 PR200
.c
10K_4 10K_4
2
2
6
CMPOUT ACP ACN

PQ19B 2
1
DMN66D0LDW-7 PC119 1U/10V_6
1
PR201 REGN_LDO 1 2
1
1
12.4K/F_4 EC36 EC35 PC121
10U/25V_8
ACP
ACN
2
PC114 PD4 2200P/50V_4 0.1U/25V_6
+VCHGR
2
*100P/50V_NC SDM10K45-7-F
x
+DC_IN_SS
2
1 2 3
CMPOUT REGN
16 2 1
PC122
Fsw : 750K 2
PR134
PD3 0_6 0.047U/25V_4 TDC : 2.52A
PR129 10_12 CMPIN 4 17 VCHGR_BST 1 2 2 1
CMPIN BTST
5
6
7
8
2 1 1 2 PR130
220K/F_4 PQ43
fi
1SS355 VCHGR_PG 5 18 VCHGR_DH 4 AON7410
ACOK# HIDRV
1
PC120 +VCHGR
1U/25V_6 PR143
PR194 2 1 VCHGR_VCC 20 19 VCHGR_LX PL12 0.01_12
6
1
2
3
220K/F_4 VCC PHASE 4.7UH20%6A(TMPB0603M-4R7MN-Z01)
1 2 +VCHGR_P1 1 2
2
VCHGR_ACDET 6 15 VCHGR_DL 1P 1 2 2P
ACDET LODRV 1P 2P
5
6
7
8
1
1
2/18
a
1
1
+3.3V_ALW 8 14 4 PC123
[38,45] SMBDAT0 SDA GND
PR195 PC176 *1000P/50V_4_NC PC126 PC125
1 2
35.7K/F_4 0.01U/25V_4 10U/25V_8 10U/25V_8
2
2
[38,45] 9 13 SRP PQ44
2
1
2
3
SMBCLK0 SCL SRP AON7410 PR135 PC124
*2.2_8_NC 0.1U/16V_4
+3.3V_ALW 2 1 BQ24707_ILIM 10 12 SRN 1 2
in
PR197 ILIM SRN
1
316K/F_4 PR199
1
7 11 2 1 +3.3V_ALW PC179 PR140 PC178
[38] IINP IOUT IFAULT# 0.1U/25V_6 10_6 PR139 0.1U/25V_6
2
1
10K_4 7.5_6
1
PR196
GND
GND
GND
GND
GND
1
100K/F_4 PC177 PC115
2
0.01U/25V_4 100P/50V_4
2
BQ24707ARGRR
2
21
22
23
24
25
PU8
Adapter type 65W 90W

h 3
.c
+VCHGR
ADAPT_TRIP_SET 0 1
PR144
470/F_8
SETTING CURRENT 3.34A4.67A
2
PR131
39K/F_4 [7,38,51]
3
w
IMVP7_PROCHOT#
[38] 2 PQ23
BATSHIP
1
2N7002W
PR133
PR132
1
3
64.9K/F_4
1 2 CMPIN 1 2 CMPOUT 5 PQ20A
DMN66D0LDW-7
4
2M/F_4
6
[38] ADAPT_TRIP_SET 2 PQ20B

DMN66D0LDW-7
1
4 4

PROJECT : JWA
http://vinafix.vn
1A
Charger (BQ24707ARGRR)
A B C D E
5 4 3 2 1
f ix
vina +VCC_GFX_CORE
Fsw : 400K
Current : 27A
OCP : 50A
+VCC_DGFX_CORE
D D
m
+PWR_SRC
DGPU_VID0 [17]
DGPU_VID1 [17]
1
DGPU_VID2 [17]
1
+ PC13
DGPU_VID3 [17] EC6
o
[17] EC2 PC2 PC1
DGPU_VID4
0.1U/25V_6
330U/2V_7343
2200P/50V_4
10U/25V_8
10U/25V_8
DGPU_VID5 [17]
2
dGPU_DH1
+5V_SUS
2
G1
D1
D1
D1
+3V_GFX PQ26
FDMS3660S
.c
2
PR6 PL2
19
S1/D2
10_6 0.24UH (FDUE0640-H-R24M=P3)
PR8 2 1 1K_4 dGPU_LX1 9 2 1 +VCC_DGFX_CORE
1
+5V_SUS
G2
1
S2
S2
S2
SJ7 SJ10 + PC137
1
SJ0201 SJ0201 PC6
2
1U/6.3V_4
0.1U/16V_4
330U/2V_7343
PC8
2
1
PC10 *1000P/50V_4_NC
1 2
1
dGPU_DL1
2
PR4 PR158
+3V_GFX *2.2_8_NC 10_4
x
C C
3218_CSREF 2
48
47
46
45
44
43
42
41
40
39
38
37
1
Need confirm with EE

VID0
VID1
VID2
VID3
VID4
VID5
VID6
DPRSLP
PH0
PH1
PSI
VCC
or not have pull high 100K_4 PR7 PC12
PR9 0_6 0.22U/25V_6 3218_CS_PH1
resister for PG.
1 36 dGPU_BST11 2 2 1
fi
2
EN BST1
DGFX_VR_PWRGD 2 35
PWRGD DRVH1 +PWR_SRC
3 34
1
IMON SW1
4 33 2 PR12 1
1
PR10 CLKEN SWFB1 100_4
110K/F_4 5 32 EC3 EC4 PC132 PC3
FBRTN PVCC +5V_SUS
0.1U/25V_6
PU1 dGPU_DH2
2200P/50V_4
10U/25V_8
10U/25V_8
2
2
2 1 3218_FB 6 NCP3218MNR2G 31
FB DRVL1
a
1
2
PC15 PC16 3218_COMP 7 30 1 2
COMP PGND
G1
D1
D1
D1
150P/50V_4 22P/50V_4 PR15 PC17 4.7U/6.3V_6 PQ25
PR13 1 2 8 29 FDMS3660S
2
PC14 39.2K/F_4 5.1K/F_4 TRDET DRVL2

2 1 2 1 1 2 9 28 2 PR16 1
19
S1/D2
VARFREQ SWFB2 100_4 PL1
PR11 150P/50V_4 VGA_PWR_LEVEL_PWR 10 27 dGPU_LX2 9 0.24UH (FDUE0640-H-R24M=P3)
1.65K/F_4 VRTT SW2 2 1 +VCC_DGFX_CORE
in
+5V_SUS 11 26
G2
1
S2
S2
S2
TTSNS DRVH2 +3V_GFX
1
PR150 12 25 dGPU_BST21 2 2 1 SJ8 SJ9 + PC138
CSCOMP
1
8
5
1 2 AGND BST2 PC5
CSSUM
SJ0201 SJ0201
SWFB3
CSREF
PWM3
RAMP
LLINE
470U/2V_7343
49 PR18 PC18 PC9 0.1U/16V_4
IREF
RPM
OD3
ILIM
2
7.32K GND 0_6 0.22U/25V_6 *1000P/50V_4_NC PR203
RT
2
100_8
1
1
dGPU_DL2
13
14
15
16
17
18
19
20
21
22
23
24
1
20120209 PR5
1
PR151 Change PR217, PR224 to shortpad(short0603) *2.2_8_NC

3218_RAPM
3218_LLINE
PC20 PR160
3218_IREF
220K_6 NTC
3218_RPM
0.01U/25V_4 PR25 10_4

3218_RT
2
3
1.21K/F_4PR30 20K/F_4
2
2 1 3218_LLINE DGPU_PWR_ON# 2 PQ46
h 2N7002W
3218_CSREF
PR20
PR21
PR22
PR23
PR24
B PR156 SJ0402 B
2
1
1
VDD_SENSE1 1 2 [14] 3218_CSCOMP 3218_CS_PH2

VDD_SENSE
1
GND_SENSE1 1 2 [14]
GND_SENSE
1
PR157 SJ0402 PR164

80.6K_4
47.5K/F_4
162K/F_4
649K/F_4
20K/F_4 PC27 1000P/50V_4
PC21 PR165 220K_6 NTC

2
PC19 1000P/50V_4 75K/F_4 PUT COLSE TO

2
.c
1
PC11
+VCC_GFX_CORE
2
1000P/50V_4 PR31
1
3218_CSSUM 2 1 Phase 1 Inductor

2
+3V_GFX
PR28
*330P/50V_4_NC 165K/F_4
Current : 140mA
2
2
1 2
PR26 274K/F_4
1 2 +15V_ALW
+1.5V_GFX
1K/F_4
3218_CSREF PR19 274K/F_4 +5V_ALW2 +3.3V_ALW +3V_GFX

1
Current : 1.41A PQ24

AO6402A
1
6
w
VGA_PWR_LEVEL_PWR +15V_ALW +1.5V_SUS +1.5V_GFX PR163 5 4

VGA_PWR_LEVEL_PWR [17]
1
1
SJ2 PQ16 2
PC22 1 2 MDV1522URH 100K_4 1
1
4.7U/25V_8 1 2 8 3 PR159
+PWR_SRC
+1.05V_GFX
2
1
SJ0402 PR190 7 2 100K_4
3
Current : 937mA 220K_4 6 1 3.3V_GFX_ENABLE PC133
2
5 PC172 PC171 0.1U/16V_4
2
1
AGND_VCORE 50uA
2
3
PC143
4
1
1.5V_GFX_ENABLE PC104 *10U/6.3V_6_NC *10U/6.3V_6_NC DGPU_PWR_ON# 5 PQ28A
w
2
+1.05V_PCH +1.05V_GFX DMN66D0LDW-7 PC131
6
0.1U/16V_4 10U/6.3V_8 4700P/25V_4
2
3
+15V_ALW [22]
2 PQ28B
DGPU_PWR_EN
+5V_ALW2 PQ5 DGPU_PWR_ON# 2 PQ41 DMN66D0LDW-7
MDV1522URH 2N7002W
1
1
+VCC_DGFX_CORE +1.05V_GFX 8 3 PC99

1
7 2 0.047U/25V_4
PR171 6 1
1
6.2K_4 5
PR204 PR202
2
w
*100_4_NC 100_4 PR170

4
A 100K_4 1.0V_GFX_ENABLE A
1
2
PC43
3
50uA PC148 0.1U/16V_4

2
DGFX_VR_PWRGD# 5 PQ32A 0.047U/25V_4

2
3
DMN66D0LDW-7
DGPU_PWR_ON# 2 PQ47 DGFX_VR_PWRGD# 2 PQ45
4
6
*2N7002W_NC 2N7002W
DGFX_VR_PWRGD 2 PQ32B
1
DMN66D0LDW-7
1

PROJECT : JWA
http://vinafix.vn
1A
VGA_N11P-dGFX (NCP3218MNR2G)
Date: Wednesday, March 27, 2013 Sheet 54 of 54
5 4 3 2 1

Dell 5560 Daojwamb8c1 Rev C

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5 4 3 2 1

Power : PAGE 35 Platform LayController Hub USB3.0 Port x 1 TPS51216RUK

System BIOS 8M Embedded Controller

HALL Sensor Power Button 12.288MHz

Quanta Computer Inc.

USB0 External port#1 (USB3.0) SATA0 HDD PCIE 1 WLAN

Quanta Computer Inc.

+3.3V_SUS +5V_SUS +5V_RUN +1.5V_RUN +1.5V_GFX +1.5V_CPU +1.05V_GFX

Quanta Computer Inc.

1.8V GPU PWR 44 IMVP_PWRGD

Quanta Computer Inc.

D PEG_ICOMPO 12mil eDP_COMP R2671 2 24.9/F_4

PEG_ICOMPI, PEG_RCOMPO 4mil,

PCI EXPRESS -- GRAPHICS

G17 PEG_TXP7_C C122 2 1 0.1U/16V_4 PEG_TXP7 [14]

eDP_TX#[3] PEG_TX[11] K10

fix Ivy Bridge Processor (CLK,MISC,JTAG)

JTAG & BPM

Intel spec VinH min =VCCIO X 0.7 Boot S3 S3 RSM

Follow #DG1.5 471984 P128

4 SM_DRAMPW ROK_R 1 2 SM_DRAMPW ROK

DDR SYSTEM MEMORY B

M_A_DQ37 AR45 AT55 [12] M_B_DQ38 BD54 AK59 M_B_DQSN7

M_A_BS#1 SA_BS[1] SA_MA[8] M_B_BS#2 SB_BS[2] SB_MA[9]

M_A_W E# SA_WE# SA_MA[15]

Quanta Computer Inc.

10U/6.3V_6 10U/6.3V_8 A35 VCC[4] VCCIO[8] AJ43 AB59 VAXG[9]

PEG IO AND DDR IO

10U/6.3V_8 10U/6.3V_8 E32 AN45 P53 AR26

*10U/6.3V_8_NC E38 VCC[26] P61 VAXG[31] VDDQ[17] AR32

10U/6.3V_8 *10U/6.3V_8_NC F38 AA15 V48 BB28

H25 VCC[36] VCCIO[33] AC13 V52 VAXG[41]

10U/6.3V_6 10U/6.3V_6 H38 AF20 W52

J26 VCC[47] VCCIO[44] AG17 W56 VAXG[52]

10U/6.3V_6 10U/6.3V_6 J38 2 1

K26 VCC[57] W16 VCC_AXG_SENSE F45 VCCDQ[1] AN26

VCC[74] VCCPQE[1] +1.05V_PCH 10uF x 1 VSS_SENSE_VDDQ

G43 VSSSENSE IC,IVB_2CBGA,0P7

R249 R252 Quanta Computer Inc.

VR_SVID_DATA H_CPU_SVIDALRT# 1 2 VR_SVID_ALERT#

AJ34 VSS[64] VSS[154] BA11 L34 VSS[242] VSS_NCTF_6 BE58

AL40 VSS[80] VSS[170] BD32

AM26 VSS[87] VSS[177] BD8

M_A_A15 R133 36/F_4

+1.5V_SUS +M_VREF_DQ_MD +1.5V_SUS +M_VREF_CA_MD

C306 C226 C227 C244 C270 C264 C219 C233

Quanta Computer Inc.

NC#J1 RESET# DDR3_DRAMRST#[7,11,13] NC#L1

SDRAM DDR3 R140

Quanta Computer Inc.

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

Place these Caps near So-Dimm1.

0.1U/16V_4 0.1U/16V_4 10U/6.3V_6 *10U/6.3V_6_NC 10U/6.3V_8 1U/6.3V_4 *1U/6.3V_4_NC

Quanta Computer Inc.

PEX_RX6 AG12 [6]

PEX_TX7 AB16 C_PEG_RX7 C22 1 2 0.1U/16V_4 [6]

Quanta Computer Inc.

D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0 [18]

C1 22U/6.3VS_6 P22 FB_PLLAVDD

Quanta Computer Inc.

bga595-nvidia-n13p-gv2-s-a2 COMMON NC GF117

T7 IFPD_PLLVDD NC NC I2CX_SDA IFPD_AUX P4

0.1U/16V_4 0.1U/16V_4 10U/6.3V_6 10U/6.3V_6_NC 10U/6.3V_8 1U/6.3V_4 1U/6.3V_4_NC