Sifang Csc-211eb V1.00

CSC-211
Multifunction protection IED

Manual
CSC-211 系列数字式多功能保护装置
说明书（EB(VV)）
（英文）
编制：
李诚
校核：
罗焕
标准化审查：王莹
审定：杨文涛
V1.00
版本号：V1.00
0000705131
文件代号：
2022年11月
出版日期：2022 年 11 月
Version number: V1.00
Document code: 0000705131
Date of Publication: 2022.11
Copyright: Beijing Sifang Automation Co., Ltd
Notes: The company reserves the right to amend the introduction. If

equipment does not agree with the manual at anywhere, please contact
our Company in time. We will provide you with corresponding service.
®
is registered trademark of Beijing Sifang Automation Co., Ltd.
We reserve all rights to this document, even in the event that a patent is issued
and a different commercial proprietary right is registered. Please use it reasonably
and do not copy it and spread it to third parties.
This document has been carefully checked. If the user nevertheless detects any
errors, he is asked to notify us as soon as possible.
The data contained in this manual is intended solely for the product description
and is not to be deemed to be a statement of guaranteed properties. In the
interests of our customers, we constantly seek to ensure that our products are
developed to the latest technological standards as a result; It is possible that there
may be some differences between the hard-ware/software product and this
information product.
Manufacturer: Beijing Sifang Automation Co., Ltd.
Email: support@sf-auto.com
Website:http://www.sf-auto.com
Address: No. 9, Fourth Street, Shangdi Information Industry Base, Haidian District,
Beijing, China 100085
Preface
Purpose of this manual
This manual describes the functions, operation, installation, and placing
into service ofCSC-211digital multifunction protection IED. In particular,
one will find:
 Information on how to configure the device scope and a description of
the device functions and setting options;
 Installation and debugging specifications;
 technical data specifications;
 A compilation of the most significant data for experienced users in the
Appendix.
Target user
Protection engineers, commissioning engineers, personnel concerned with
adjustment, checking, and service of selective protective equipment,
automatic and control facilities, and personnel of electrical facilities and
power plants.
Applicability of this Manual

This manual is valid for CSC-211digital multifunction protection IEDfirmware
version V1.00 and higher.
Note: the password for this device is 8888.
Technical support
In case of further questions concerning CSC-211digital multifunction
protection IED, please contact SIFANG representative.
Safety information
Strictly follow the company and international safety regulations.

Working in a high voltage environment requires serious approach
to avoid human injuries and damage to equipment
Do not touch any circuitry during operation. Potentially lethal

voltages and currents are present
Avoid to touching the circuitry when covers are removed. The IED
contains electric circuits which can be damaged if exposed to
static electricity. Lethal high voltage circuits are also exposed
when covers are removed.
Using the isolated test pins when measuring signals in open
I
circuitry. Potentially lethal voltages and currents are present
Never connect or disconnect conducting wire and/or connector to

or from IED during normal operation. Dangerous voltages and
currents are present. Operation may be interrupted and IED and
measuring circuitry may be damaged
Always connect the IED to protective earth regardless of the

operating conditions. Operating the IED without proper earthing
may damage both IED and measuring circuitry and may cause
injuries in case of an accident.
Do not disconnect the secondary connection of current

transformer without short-circuiting the transformer’s secondary
winding. Operating a current transformer with the secondary
winding open will cause a high voltage that may damage the
transformer and may cause injuries to humans.
Do not remove the screw from a powered IED or from an IED

connected to power circuitry. Potentially lethal voltages and
currents are present.
Using the certified conductive bags to transport PCBs (modules).

Handling modules with a conductive wrist strap connected to
protective earth and on an antistatic surface. Electrostatic
discharge may cause damage to the module due to electronic
circuits are sensitive to this phenomenon
Do not connect live conducting wires to the IED, internal circuitry

may be damaged
When replacing modules using a conductive wrist strap

connected to protective earth. Electrostatic discharge may
damage the modules and IED circuitry
When installing and commissioning, take care to avoid electrical

shock if accessing conducting wires and connection IEDs
Changing the setting group will inevitably change the IEDs

operation. Be careful and check regulations before making the
change
II
CONTENTS
CHAPTER 1 INTRODUCTION ................................................................................................................... 1
1 IED OVERVIEW ....................................................................................................................................... 2
2 IED CHARACTERISTIC ................................................................................................................................ 2
3 BASIC FUNCTION ..................................................................................................................................... 3
3.1 Protection function ..................................................................................................................... 3
3.2 Monitoring function .................................................................................................................... 4
3.3 Measurement function ............................................................................................................... 4
3.4 Control function .......................................................................................................................... 4
3.5 Communication mode ................................................................................................................ 5
CHAPTER 2 GENERAL FUNCTIONS ......................................................................................................... 7
1 EVENT RECORD AND ANALYSIS .................................................................................................................... 8
1.1 Overview .................................................................................................................................... 8
1.2 Fault record................................................................................................................................. 8
1.3 disturbance and fault record ...................................................................................................... 8
1.4 Sequence of event (SOE) ............................................................................................................ 8
1.5 Operation record ........................................................................................................................ 9
2 DIAGNOSIS FUNCTION .............................................................................................................................. 9
2.1 Overview .................................................................................................................................... 9
2.2 Diagnostic principle .................................................................................................................... 9
3 TIME SYNCHRONIZATION FUNCTION ............................................................................................................ 9
3.1 Overview .................................................................................................................................... 9
3.2 Synchronization principle ......................................................................................................... 10
3.3 IRIG -B synchronization mode .................................................................................................. 10
3.4 PPS synchronization mode ....................................................................................................... 10
3.5 SNTP time synchronization mode ............................................................................................ 11
3.6 IEEE1588 time synchronization mode...................................................................................... 11
4 AUTHORIZATION ................................................................................................................................... 11
CHAPTER 3 OVERCURRENT PROTECTION (50, 51, 67) ......................................................................... 13
1 OVERVIEW ........................................................................................................................................... 14
2 FUNCTION MODULE DESCRIPTION ............................................................................................................. 14
3 DETAILED DESCRIPTION ........................................................................................................................... 15
3.1 Protection principle .................................................................................................................. 15
3.1.1 Inrush blocking components ...................................................................................... 15
3.1.2 Composited voltage blocking unit .............................................................................. 16
3.1.3 Directional component ................................................................................................ 17
3.1.4 Definite time.................................................................................................................. 18
3.1.5 Inverse time .................................................................................................................. 18
3.1.6 Trip characteristic ........................................................................................................ 19
3.1.7 Alarm characteristic ..................................................................................................... 19
3.1.8 Logic diagram............................................................................................................... 20
3.2 Setting list ................................................................................................................................. 21
3.3 Report list ................................................................................................................................. 23
3.4 Technical parameter ................................................................................................................. 24
CHAPTER 4 EARTH FAULT PROTECTION(50N, 51N, 67N) ..................................................................... 25
1 OVERVIEW ........................................................................................................................................... 26
3.1.1 Inrush blocking components ...................................................................................... 27
3.1.2 Definite time.................................................................................................................. 28
3.1.3 Inverse time .................................................................................................................. 28
3.1.5 Alarm characteristic ..................................................................................................... 29
3.2 Setting list ................................................................................................................................. 30
3.3 Report list ................................................................................................................................. 33
CHAPTER 5 HIGH SENSITIVE EARTH FAULT PROTECTION (50NS, 51NS, 67NS) .................................... 35
III
1 OVERVIEW ............................................................................................................................................ 36
2 FUNCTION MODULE DESCRIPTION .............................................................................................................. 36
3.1.1 Definite time .................................................................................................................. 37
3.1.2 Inverse time ................................................................................................................... 37
3.1.3 Trip characteristic ......................................................................................................... 38
3.2 Setting list.................................................................................................................................. 39
3.3 Report list .................................................................................................................................. 41
3.4 Technical parameter.................................................................................................................. 42
CHAPTER 6 NEGATIVE SEQUENCE CURRENT PROTECTION (46) ........................................................... 43
1 OVERVIEW ............................................................................................................................................ 44
3.1.1 Definite time .................................................................................................................. 45
3.1.2 Inverse time ................................................................................................................... 45
3.2 Setting list.................................................................................................................................. 47
3.3 Report list .................................................................................................................................. 48
CHAPTER 7 UNDERCURRENT PROTECTION (37) ................................................................................... 51
1 OVERVIEW ............................................................................................................................................ 52
3.2 Setting list.................................................................................................................................. 53
3.3 Report list .................................................................................................................................. 53
CHAPTER 8 OVERVOLTAGE PROTECTION (59) ...................................................................................... 55
1 OVERVIEW ............................................................................................................................................ 56
3.1.1 Definite time .................................................................................................................. 57
3.1.2 Inverse time ................................................................................................................... 57
3.1.4 Logic diagram ............................................................................................................... 58
3.2 Setting list.................................................................................................................................. 59
3.3 Report list .................................................................................................................................. 60
CHAPTER 9 NEGATIVE SEQUENCE VOLTAGE PROTECTION (47) ............................................................ 63
1 OVERVIEW ............................................................................................................................................ 64
3.1.1 Definite time .................................................................................................................. 64
3.1.2 Inverse time ................................................................................................................... 65
3.2 Setting list.................................................................................................................................. 66
3.3 Report list .................................................................................................................................. 68
CHAPTER 10 UNDERVOLTAGE PROTECTION (27).................................................................................... 71
1 OVERVIEW ............................................................................................................................................ 72
3.1.1 Blocking condition ....................................................................................................... 73
3.1.2 Definite time .................................................................................................................. 73
IV
3.1.3 Inverse time .................................................................................................................. 74
3.1.5 Logic diagram............................................................................................................... 75
3.2 Setting list ................................................................................................................................. 75
3.3 Report list ................................................................................................................................. 77
CHAPTER 11 THERMAL OVERLOAD PROTECTION (49)........................................................................... 79
1 OVERVIEW ........................................................................................................................................... 80
3.2 Setting list ................................................................................................................................. 82
3.3 Report list ................................................................................................................................. 82
CHAPTER 12 POWER PROTECTION (32F) ............................................................................................... 85
1 OVERVIEW ........................................................................................................................................... 86
3.2 Setting list ................................................................................................................................. 87
3.3 Report list ................................................................................................................................. 88
CHAPTER 13 CIRCUIT BREAKER FAILURE PROTECTION (50BF) ............................................................... 89
1 OVERVIEW ........................................................................................................................................... 90
3.1 Protection function .................................................................................................................. 91
3.1.1 Current detection ......................................................................................................... 91
3.1.2 Breaker auxiliary contact detection ............................................................................ 92
3.1.3 Circuit breaker failure protection trip logic diagram ................................................. 93
3.2 Setting list ................................................................................................................................. 94
3.3 Report list ................................................................................................................................. 94
CHAPTER 14 DEAD ZONE PROTECTION (50DZ) ...................................................................................... 97
1 OVERVIEW ........................................................................................................................................... 98
3 DETAILED DESCRIPTION ......................................................................................................................... 100
3.1 Protection principle ................................................................................................................ 100
3.2 Setting list ............................................................................................................................... 102
3.3 Report list ............................................................................................................................... 102
3.4 Technical parameter ............................................................................................................... 102
CHAPTER 15 STUB PROTECTION (50STUB) .......................................................................................... 103
1 OVERVIEW ......................................................................................................................................... 104
2 FUNCTION MODULE DESCRIPTION ........................................................................................................... 104
3.2 Setting list ............................................................................................................................... 106
3.3 Report list ............................................................................................................................... 106
CHAPTER 16 BROKEN CONDUCTOR PROTECTION (46BC).................................................................... 107
1 OVERVIEW ......................................................................................................................................... 108
3.2 Setting list ............................................................................................................................... 109
3.3 Report list ............................................................................................................................... 110
CHAPTER 17 OVEREXCITATION PROTECTION (24) ............................................................................... 111
V
1. OVERVIEW .......................................................................................................................................... 112
2. FUNCTION MODULE DESCRIPTION ............................................................................................................ 112
3. DETAILED DESCRIPTION ......................................................................................................................... 113
3.2 Setting list................................................................................................................................ 115
3.3 Report list ................................................................................................................................ 116
3.4 Technical parameter................................................................................................................ 117
CHAPTER 18 UNDERFREQUENCY PROTECTION (81UF) ........................................................................ 119
1 OVERVIEW .......................................................................................................................................... 120
2 FUNCTION MODULE DESCRIPTION ............................................................................................................ 120
3.1.1 Protection function introduction ............................................................................... 121
3.1.2 Logic diagram ............................................................................................................. 122
3.2 Setting list................................................................................................................................ 122
3.3 Report list ................................................................................................................................ 123
CHAPTER 19 OVERFREQUENCY PROTECTION (81OF) ........................................................................... 125
1 OVERVIEW .......................................................................................................................................... 126
3.1.2 Logic diagram ............................................................................................................. 127
3.2 Setting list................................................................................................................................ 127
3.3 Report list ................................................................................................................................ 128
CHAPTER 20 FREQUENCY CHANGE RATE PROTECTION (81DF) ............................................................ 129
1 OVERVIEW .......................................................................................................................................... 130
3.1.2 Logic diagram ............................................................................................................. 132
3.2 Setting list................................................................................................................................ 132
3.3 Report list ................................................................................................................................ 133
CHAPTER 21 SWITCH-ONTO-FAULT PROTECTION................................................................................. 135
1 OVERVIEW .......................................................................................................................................... 136
3.1.2 Logic diagram ............................................................................................................. 138
3.2 SETTING LIST ....................................................................................................................................... 139
3.3 REPORT LIST ....................................................................................................................................... 139
3.4 TECHNICAL PARAMETER ........................................................................................................................ 140
CHAPTER 22 NON-ELECTRIC PROTECTION ........................................................................................... 141
1 OVERVIEW .......................................................................................................................................... 142
3.2 Setting list................................................................................................................................ 143
3.3 Report list ................................................................................................................................ 143
CHAPTER 23 SYNCHRO-CHECK AND DEAD VOLTAGE CHECK (25) ......................................................... 145
1. OVERVIEW .......................................................................................................................................... 146
2. FUNCTION MODULE DESCRIPTION ............................................................................................................ 146
VI
3. DETAILED DESCRIPTION ......................................................................................................................... 147
3.1.1 Protection function introduction .............................................................................. 147
3.1.2 Synchronization check mode: .................................................................................. 148
3.1.3 Modes of dead voltage check: .................................................................................. 149
3.1.4 Override mode ............................................................................................................ 149
3.1.5 Logic diagram............................................................................................................. 149
3.2 Setting list ............................................................................................................................... 150
3.3 Report list ............................................................................................................................... 151
CHAPTER 24 AUTO-RECLOSING FUNCTION (79) .................................................................................. 153
1 OVERVIEW ......................................................................................................................................... 154
3.1.1 Auto-reclosing startup ............................................................................................... 156
3.1.2 Auto-reclosing logic .................................................................................................. 156
3.2 Setting list ............................................................................................................................... 158
3.3 Report list ............................................................................................................................... 159
CHAPTER 25 BLOCKING SIMPLE BUSBAR DIFFERENTIAL PROTECTION................................................ 161
1 PROTECTION PRINCIPLE......................................................................................................................... 162
2 SETTING LIST....................................................................................................................................... 163
3 REPORT LIST ....................................................................................................................................... 163
CHAPTER 26 SIMPLE BUSBAR DIFFERENTIAL PROTECTION ................................................................. 165
2 SETTING LIST....................................................................................................................................... 167
3 REPORT LIST ....................................................................................................................................... 167
CHAPTER 27 UNDERVOLTAGE LOAD SHEDDING PROTECTION ............................................................ 169
1 OVERVIEW ......................................................................................................................................... 170
3.1.2 Logic diagram............................................................................................................. 172
3.2 Setting list ............................................................................................................................... 172
3.3 Report list ............................................................................................................................... 172
CHAPTER 28 OVERLOAD LOAD SHEDDING PROTECTION ..................................................................... 175
1 OVERVIEW ......................................................................................................................................... 176
3.1.2 Logic diagram............................................................................................................. 177
3.2 SETTING LIST ...................................................................................................................................... 178
3.3 REPORT LIST ....................................................................................................................................... 178
3.4 TECHNICAL PARAMETER........................................................................................................................ 178
CHAPTER 29 COOLING LOAD STARTUP PROTECTION .......................................................................... 179
2 SETTING LIST....................................................................................................................................... 181
3 REPORT LIST ....................................................................................................................................... 182
CHAPTER 30 FREQUENCY AUTO-RECLOSING PROTECTION ................................................................. 183
1 OVERVIEW ......................................................................................................................................... 184
3.1 Protection principle ........................................................................................................... 185
3.2 Setting list ............................................................................................................................ 185
VII
3.3 Report list ............................................................................................................................. 186
3.4 Technical parameter .......................................................................................................... 186
CHAPTER 31 SECONDARY CIRCUIT MONITORING ................................................................................ 187
1 CT FAILURE ......................................................................................................................................... 188
1.1 Overview ................................................................................................................................. 188
1.2 Function module description .................................................................................................. 188
1.3 Detailed description ................................................................................................................ 188
1.3.1 Protection principle .................................................................................................... 188
1.3.2 Setting list ................................................................................................................... 189
1.3.3 Report list .................................................................................................................... 189
2 VT FAILURE ......................................................................................................................................... 189
2.1 Overview ................................................................................................................................. 189
2.2 Function module description .................................................................................................. 189
2.3 Detailed description ................................................................................................................ 190
2.3.1 Protection principle .................................................................................................... 190
2.3.2 Setting list ................................................................................................................... 191
2.3.3 Report list .................................................................................................................... 191
CHAPTER 32 USER-DEFINED FUNCTION ............................................................................................... 193
1 OVERVIEW .......................................................................................................................................... 194
2 USER-DEFINED CONFIGURATION.............................................................................................................. 194
2.1 Open project ........................................................................................................................... 194
2.2 Binary input configuration ....................................................................................................... 194
2.3 Binary output configuration ................................................................................................... 195
2.4 LED configuration .................................................................................................................... 196
2.5 IO Matrix configuration .......................................................................................................... 197
2.5.1 AC IO configuration .................................................................................................... 197
2.5.2 Digital IO configuration .............................................................................................. 197
2.6 Binary input switches setting group ....................................................................................... 198
2.6.1 Function description .................................................................................................. 198
2.6.2 Setting list ................................................................................................................... 199
2.7 Startup configuration .............................................................................................................. 199
2.8 Other configurations................................................................................................................ 200
2.9 Defined logic ........................................................................................................................... 201
2.10Connector attribute change .................................................................................................... 201
CHAPTER 33 CONTROL FUNCTION ....................................................................................................... 203
1 CB/ISOLATOR CONTROL................................................................................................................. 204
1.1 Overview ............................................................................................................................... 204
1.2 Function module description .......................................................................................... 204
1.3 Detailed description ........................................................................................................... 204
2 DIRECT CONTROL ........................................................................................................................... 205
2.1 Overview ............................................................................................................................... 205
3 TAP CONTROL ................................................................................................................................. 205
3.1 Overview ............................................................................................................................... 205
4 REPORT LIST ................................................................................................................................... 206
CHAPTER 34 SUBSTATION COMMUNICATION ...................................................................................... 207
1 OVERVIEW .......................................................................................................................................... 208
1.1 Communication protocol ........................................................................................................ 208
1.1.1 IEC 61850-8-1 communication protocol ........................................................................ 208
1.1.2 Communication protocol IEC 60870-5-103 ................................................................... 208
1.2 Communication port ............................................................................................................... 208
1.2.1 Faceplate communication port .................................................................................. 208
1.2.2 RS485 communication port........................................................................................... 208
1.2.3 Synchronization port ..................................................................................................... 208
1.2.4 Ethernet communication port .................................................................................... 208
VIII
1.4 Typical substation communication mode .............................................................................. 210
1.5 Typical time synchronization mode ....................................................................................... 210
CHAPTER 35 MAN-MACHINE INTERFACE (MMI) AND OPERATION ..................................................... 211
1 OVERVIEW ......................................................................................................................................... 212
2 FUNCTION DESCRIPTION........................................................................................................................ 212
2.1 Liquid crystal display (LCD) ............................................................................................ 212
2.2 Man-machine interface (MMI) .......................................................................................... 212
2.3 Menu structure.................................................................................................................... 214
CHAPTER 36 HARDWARE ..................................................................................................................... 219
1 OVERVIEW ......................................................................................................................................... 220
1.1 IED structure ........................................................................................................................... 220
1.2 Module arrangement diagram ................................................................................................ 221
2 ANALOG INPUT MODULE ....................................................................................................................... 221
2.1 Overview ................................................................................................................................ 221
2.2 Analog input moduleintroduction ......................................................................................... 221
3 BINARY INPUT AND OUTPUT MODULE ...................................................................................................... 223
3.1 Overview ................................................................................................................................ 223
3.2 Binary input and output moduleintroduction ....................................................................... 223
4 CPU MODULE..................................................................................................................................... 226
4.1 Overview ................................................................................................................................ 226
4.2 CPU moduleintroduction ....................................................................................................... 226
5 POWER SUPPLY MODULE ....................................................................................................................... 229
5.1 Overview ................................................................................................................................ 229
5.2 Power moduleintroduction .................................................................................................... 229
6 TCS MODULE ..................................................................................................................................... 231
6.1 Overview ................................................................................................................................ 231
6.2 Instruction of TCS module ...................................................................................................... 231
6.2.1 TCS trip monitoring circuit ........................................................................................ 233
6.2.2 Binary output circuit with high-capacity .................................................................. 234
6.2.3 Ordinary BO circuit .................................................................................................... 234
7 TEST MODE ........................................................................................................................................ 236
8 STRUCTURAL DESIGN ............................................................................................................................ 238
9 CE CERTIFICATE .................................................................................................................................. 238
10 ENVIRONMENTAL PARAMETERS .............................................................................................................. 238
CHAPTER 37 APPENDIX ........................................................................................................................ 239
1 SETTING LIST....................................................................................................................................... 240
2 REPORT LIST ....................................................................................................................................... 240
2.1 Alarm report ........................................................................................................................... 240
2.2 Operation report .................................................................................................................... 242
3 TYPICAL WIRING .................................................................................................................................. 243
3.1 As to incoming and outlet line feeder protection and line backup protection .................... 243
3.2 As for transformer backup protection IED ............................................................................. 248
3.3 As for synchronization function ............................................................................................. 251
3.4 As for capacitor protection .................................................................................................... 252
4 INVERSE TIME CHARACTERISTIC ............................................................................................................... 255
4.1 Twelve types of inverse time characteristic of IEC and inverse time characteristic curve of
ANSI ............................................................................................................................................... 255
4.2 User-defined properties ......................................................................................................... 256
5 CPU MODULE UPGRADING INTRODUCTION ............................................................................................... 256
6 CONNECTOR LIST ................................................................................................................................. 257
IX
Chapter 1 Introduction
About this chapter

This chapter gives an overview of SIFANG Digital
multifunction protection IED.
1
1 IED overview
CSC-211 digital multifunction protection IED is used for factory power
system of 110kV or below power grid and power plant. It has perfect
protection, measurement, control and monitoring function. It provides a
integrated scheme for feeder, capacitor, circuit breaker, etc., at the same
time, it can be used as a backup protection device for a circuit and a
transformer
Table 1 CSC-211 Application Description
Type Sub-type Description

Main and backup protection in one device, protection
measurement and control solution for feeder and
CSC-211 CSC-211-EB(VV) capacitor;
main and backup protection are independent, backup
protection device for a circuit and a transformer solutions.
This series of IEDs use the new design concept, all the IEDs are
established in a general hardware and software platform. All functions are
modulized designed and at the same time diagnosis and debugging tools
are also provided. According to the actual needs of the field, through the
visual chart logic, users can customize all kinds of protection and control
logic. The equipment is highly reliable, flexible and maintainable and can
be adapted to the different site conditions.
CSC-211 digital multifunctionprotection IED has leading multiple features,
integrated protection, measurement, it supports the IEC 61850 standard
communication and achieves the interface with substation automation system
and protection information management system; it provides the device
description file that meets the requirements of IEC 61850 to support network
services that IEC 61850 defines. It fully supports GOOSE functions to meet
the needs of various configurations of the substation. It can be installed in
the switchgear panel at site.
2 IED characteristic
CSC-326 IED contains selectivity, reliability and speed, and the application
range is as follow:
1) Integrated protection function and bay control unit function
2) Meeting demands for three-phase tripping in transmission and
distribution grid;
3) Circuit breaker position status monitoring;
4) Also equipped with module self-check function；
5) The device can provide complete report records, including operation
report, alarm report and tripping report. Up to 2000 reports can be
stored, and the reports can be saved, even there is a power outage;
6) It provides two electric/optical Ethernet ports, and communicates with
substation automation system by choosing protocol IEC 61850 or IEC
60870-5-103 (TCP103);
7) RS485 is provided to communicate with substation automatic system
by protocol IEC 60870-5-103.
8) It supports PRP protocol based on IEC 62439-3, the device can be set
2
to PRP mode, and the dual network ports adopt redundant mode to
send and receive information in parallel;
9) Simple network time protocol (SNTP), pulse, IRIG-B or 1588
synchronizing modes can be selected to time synchronization;
10) A friendly MMI
11) Can be centrally installed in the switchgear panel or be installed on the
switchgear indoors or outdoors.
3 Basic function
3.1 Protection function
Typical configurations are used in low-voltage feeder, capacitor,
transformer backup protection, etc.
Table 2 Typical configuration 1
IEC 61850
Description ANSI code
Logic node name
Overcurrent protection (with inrush current,
50,51,67
direction, voltage)
Earth fault protection (with inrush current,
50N,51N,67N
direction)
High sensitive earth fault protection (with
50Ns,51Ns,67Ns
direction)
Negative sequence current protection 46 PPBR
Undercurrent protection 37 PUCP
Overvoltage protection 59 PTOV
Negative sequence voltage protection 47 PPBV
Undervoltage protection 27 PTUV
Voltage unbalance protection 59NU59C
Current imbalance protection
Thermal overload protection 49 PTTR
Power protection 32F
Circuit breaker failure protection 50BF RBRF
Dead zone protection 50DZ
Stub protection 50STUB
Broken conductor protection 46BC
Overexcitationprotection 24
Underfrequency protection 81UF
Overfrequency protection 81OF
Frequency change rate protection 81DF
Switch-onto-fault protection SOTF
Overload load shedding
Undervoltage load shedding
Non-electric protection 32
3
IEC 61850
Description ANSI code
Logic node name
Synchro-check and dead voltage check 25 RSYN
Auto-reclosing 79 RREC
Simple busbar protection
Blocking simple busbar protection
Cooling load startup protection
CT failure
VT failure 97FF
3.2 Monitoring function

Table 3 Monitoring function
Description
Position of circuit breaker, isolator and other switching devices monitoring
Position of circuit breaker monitoring
Auxiliary contacts monitoring of circuit breaker
Self-diagnosis function
Disturbance and fault record
3.3 Measurement function

Measurement through the acquisition of dedicated measurement
channels.
Table 4 Measurement function
Description
Current: Ia, Ib, Ic
Voltage: Ua, Ub, Uc, Uab, Ubc, Uca
Active power : P
Reactive power:Q
Power factor: COSφ
Frequency: F
3.4 Control function

Table 5 Control function
Description
Position of circuit breaker, isolator and other switching devices control
4
3.5 Communication mode

Table 6 Communication mode
Communication port on the faceplate

RJ45 Ethernet communication port
Communication port on the backplate
Isolated RS232 port
Ethernet electrical/optical communication port
Time synchronization port
Communication protocol
IEC61850 Protocol
IEC60870-5-103 Protocol
DNP3.0 (supported by Master above 4.0)
MODBUS (supported by Master above 4.0)
5
Chapter 2 General functions
About this chapter

The chapter describes the general IED functions.
7
1 Event record and analysis

1.1 Overview
To get fast, complete and reliable information about fault current, voltage,
binary signal and other disturbances in the power system is very important.
Through record function of fault data, operators can make better analysis
about the related primary and secondary devices during and after the fault.
Operational personnel can acquire valuable information to explain the
cause of the fault and modify the IED configuration in accordance with the
conclusion to improve IED reliability.
Disturbance data includes devices samples and calculated analogs, BI
and BO signals.
1.2 Fault record

IED can save the latest 2000 disturbance and fault records (which will not
loss during power failure). The records can be viewed through operation
interface of device, communication port or debugging software. The types
of fault reports include startup report, trip report, alarm report, operation
report and binary input state change report.
Main information of fault records includes:
1) Fault time: date and time
2) Time list: trip component and time
3) Running data: current, voltage, frequency and phase
1.3 disturbance and fault record

Disturbance and fault record function is used to capture the sampling data,
analog data and status data of predefined length before and after an event
(analog data is only applicable for the middle node, mid file), and replay
the protected equipment running track before and after the event. Any
logic component and binary input and output of the device can be used to
trigger disturbance and fault record function.
Disturbance and fault record contains analog channel, digital channel (BI,
BO and protection component states) as well as time label sequence
information.
IED makes data record according to each cycle. Each record can reach up
to 20s, and the latest 16 times of protection trips and 16 times startups, 32
records can be saved totally.
Disturbance and fault record can be exported through the Ethernet
debugging port (COMTRADE format) by using the debugging tool software,
and it can also be uploaded to engineer station through the substation
communication network and used to analyze IED trip.
1.4 Sequence of event (SOE)

IED monitors and records a total of 2000 state change events of the
position change of binary input and output, state change of disturbance
and fault record and connector enable/disable tripping in real time; it also
records event time scale, reason and present state. These real-time data
are transferred to the station control center through communication port.
8
Users can view the protection SOE report through the local MMI or
debugging software.
1.5 Operation record

IED records the latest 2000 important modification of operating parameters
and the operation object, operation time, data modifications or operational
reasons will be recorded, which can provide bases for event tracing.
Operation information is saved in operation record of the IED. Users can
view the report information through the local MMI or debugging software.
2 Diagnosis function
2.1 Overview
The IED can be self diagnosis and self monitoring operation is achieved by
means of soft hardware self-test and monitoring, to ensure the high
reliability of operation through the Power on. Self checking objects include
key components of hardware (such as analog sampling circuit, output
circuit of binary input and output, RAM and ROM) and hardware
accessories (such as backup battery, communication interface) and
important running parameters (such as setting, soft connectors), in
addition, the embedded two level software monitor can be used to monitor
the operation conditions of the software. When the device detects any
abnormal conditions, the device will record the abnormal events and drive
signal node and LED lights. For the key abnormal conditions, the device
will block the protection function and the important output circuit to prevent
the device from maloperations.
The user can also check the important hardware circuit of the device
through the test command provided by the device, such as the AC circuit,
BI circuit and BO circuit, etc..
In order to cooperate with automation system engineering implementation,
the device provides telecontrol point check function, so the local SCADA
and telecontrol master database can be checked, the complicated manual
point check operation between the SCADA operator and telecontrol
operator is avoided. Mainly includes the telesignalisation check, telemetry
check and so on.
2.2 Diagnostic principle

1) Measurement device power;
2) Check zero drift and zero drift out-of-limits;
3) Confirm alarm circuit;
4) Check setting and parameter.
3 Time synchronization function

3.1 Overview
The IED, as a part of the protection system, can be time synchronized by
time synchronization source. In the security automation intelligent system,
through the time synchronization, IED and other devices in the system
have the same clock source. When the system fault or abnormal, there is a
unified clock reference between the various devices.
9
3.2 Synchronization principle

Definition of time
The error of a clock is the difference between the actual time and the
synchronized clock. The rate accuracy of a clock is normally called the
clock accuracy. When the clock deviation is too large, the clock will
re-synchronize to ensure clock accuracy is within the set range.
Synchronization principle
Generally speaking, synchronization can be seen as a hierarchical
structure. A module is synchronized from a higher level and provides
synchronization to lower levels.
Upper structure
synchronizing signal
Module
The available lower structure

synchronizing signal
Figure 1 Synchronization principle diagram

A module of the system is synchronized when it receives synchronization
signal from a higher level and this module is time synchronization module.
The less the time synchronization level, the higher the final time
synchronization accuracy is. The same module may have several options
of time synchronization sources with different errors, this module can
choose the best time source and adjust the internal clock, according to the
time synchronization source. The maximum error of a clock can be defined
as:
1) The maximum error of the last synchronization information;
2) The calculated time from last time synchronization information;
3) The rate accuracy of the internal clock in the module.
Time synchronization system provides three synchronization methods:
IRIG-IRIG-B, IEEE1588 and net synchronization and second pulse
synchronization.
3.3 IRIG -B synchronization mode

CPU module of the device supports RS485 level IRIG-B (DC) time
synchronization.
3.4 PPS synchronization mode

CPU module of the device supports RS485 level PPS signal. If the
substation time is not synchronized with the standard time, the present
time of the substation will be regarded as valid time and the IED time is
synchronized with it. After receiving the pulse signal, the CPU can
automatically adapt to the positive and negative pulses.
10
3.5 SNTP time synchronization mode

Synchronization via SNTP is implemented on a request-response basis
The IED sends a synchronization request message to a SNTP server. The
SNTP server resets time message after handling transmission delay, and
then send the time information to the device. SNTP time synchronization
mode is synchronized through Ethernet. In order to ensure SNTP time
synchronization is normal, one SNTP server must be set, it is suggested
that one server can be set at one substation. The accuracy of SNTP time
synchronization method for binary input quantity is 1 ms. The IED itself can
be set as a SNTP time synchronization server.
3.6 IEEE1588 time synchronization mode

It supports IEEE1588 high precision network synchronization.
4 Authorization
To safeguard the interests of customers, accesses to the IED and the
debugging software are restricted in terms of authorization. In fact, the use
of device and related debugging software should pay attention to the
following issues:
1) Two methods are provided for debugging the IED:
a) Local: debugging through the local MMI;
b) Remote: debugging through the communication ports.
2) Different users have different authority to access or operate devices
and debug software.
11
Chapter 3 Overcurrent protection (50,51, 67)
Chapter 3 Overcurrent Protection (50,

51, 67)
About this chapter

This chapter describes the overcurrent principle, the input
and output signals, setting value parameters, messages and
technical parameters.
13
1 Overview
When the power system fault occurs, the current of the system increases,
and the overcurrent protection can avoid the damage of the fault current to
the equipment. The device provides 4 stages of overcurrent protection,
each stage provides options of overcurrent definite time protection or
inverse time protection. Each stage of overcurrent protection has the same
logic criterion,and each stage can be enabled or disabled independently.
Each stage of the overcurrent protection can be selectively enabled
harmonic blocking component and directional component, and overcurrent
can trip based on the phase measurement of the current. In addition, each
stage of the definite-time overcurrent protection can be selectively input
the composited voltage blocking component.
Main characteristics of overcurrent protection:
1) The device provides 4 stages of overcurrent protection, each stage
adopts definite time-lag or 12 IEC and ANSI standard curve of inverse
time characteristic, and it adopts user-defined characteristic curve as
well.
2) The flow direction sensitive angle can be adjusted to meet different
application occasions;
3) Each stage of the overcurrent protection can be respectively set whether
it enables direction component, whether the trip area is "forward" or
"reverse" trip is set by the logic switch;
4) Each stage of the overcurrent protection can be respectively set
whether it’s through harmonic locking;
5) Harmonic blocking can lock across;
6) Each stage of the overcurrent protection can be respectively set
whether it’s blocked by composited voltage;
7) The protection of the input direction component needs to detect whether
the VT secondary circuit disconnects. If VT is disconnected, the
protection of the input direction component can be set as VT failure
protection or VT failure protection blocking.
8) The protective function can be disabled through the function connector.
The connector properties can be configured as soft connector, hard
connector, soft-hard series, soft-hard parallel, and the default is
soft-hard parallel.
9) 4 stages of overcurrent protection can adopt current calculated by
full-wave root mean square or fundamental wave current.
2 Function module description

The I/O signals described herein only reflect the visible engineering part.
The input and output signals of overcurrent protection function diagram are
shown as follow:
14
Directional / Non-directional Overcurrent Protection

1 1
BIBlk Start
2 2
ENA_OC Operation
3
Alarm
4
PhaseA 5
PhaseB 6
PhaseC
Figure 2 The input and output signals of overcurrent protection function diagram
The left side is the input and the right is the output, parameter description
is shown in the following table.
Table 7 Parameter description
Function Logo Description

Input:
BIBlk BI blocking
Output:
Start IED startup
Protection alarm (only for the
OC Alarm
configuration of alarm stage)
Operation Protection trip
PhaseA Phase A trip
PhaseB Phase B trip
PhaseC Phase C trip
Input:
ENA The total connector of overcurrent
ENA_OC protection, the corresponding hard
connector is Ena_OE_5.
3 Detailed description
IED is equipped with 4 stages overcurrent protection, please refer to the
setting list for details. The overvoltage protection stage 1 will be taken as
an example below and the principle will be introduced.
3.1 Protection principle

3.1.1 Inrush blocking components
When “OC1BlkBy2ndH”=1, inrush is detected and the criteria are:
I∅2
> “OC2ndHI2/I1Ratio”, (∅ = 𝑎𝑎, 𝑏𝑏, 𝑐𝑐)
I∅
When it is detected that the ratio of second harmonic and fundamental
wave is greater than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase.
When it is detected that there is inrush condition, within the
"HarmCrossBlkTime", one phase inrush protection fails and three phase
15
protection; after the "HarmCrossBlkTime", one phase inrush protection

fails and one phase protection; when the inrush criterion returns, release
each blocking.
When the maximum fundamental wave current of the three phases is
greater than "OCHarmUnblkCurr", unblocking
The output blocking state of each phase is caused by inrush blocking of
overcurrent stage 1 phase A, phase B and phase C. Schematic diagram is
shown as follow:
PhAI2/I1Ratio>OC2ndHI2/I1Ratio
≥1
&
PhBI2/I1Ratio>OC2ndHI2/I1Ratio
3PhInrushBlk
PhCI2/I1Ratio>OC2ndHI2/I1Ratio
Time<“HarmCrossBlkTime”
3PhInrushBlk
&
OCS1 3PhInrushBlk
“OC1BlkBy2ndH”=1
PhAI2/I1Ratio>OC2ndHI2/I1Ratio &
Time>“HarmCrossBlkTime”
&
OCS1PhAInrushBlk
&
PhBI2/I1Ratio>OC2ndHI2/I1Ratio
&
OCS1PhBInrushBlk
PhCI2/I1Ratio>OC2ndHI2/I1Ratio &
&
“OC1BlkBy2ndH”=1 OCS1PhCInrushBlk
Figure 3 Inrush blocking logic diagram
3.1.2 Composited voltage blocking unit

“OCStage1BlkByVolt” =1, check the voltage. The voltage blocking
component is composited voltage component, including undervoltage and
negative sequence voltage components, composited voltage criterion:
min(Uab, Ubc, Uca) < “PPVoltBlkSet” OR U2 > “U2BlkSet”
16
≥1
min(Uab,Ubc,Uca)<“PPVoltBlkSet”
Composited voltage
Negative sequence voltage>“U2BlkSet” component satisfied
Composited voltage
&
component satisfied
≥1
Overcurrent Stage1 composited
“OCStage1BlkByVolt”=1 voltage component satisfied
“OCStage1BlkByVolt”=0
Figure 4 Logic diagram of the characteristics of composited voltage component
3.1.3 Directional component

When "DirOCStg1"=1, direction check. Directional components are
connected with a 90° angle, the fault phase direction is determined by the
fault phase current and the phase-to-phase voltage of the unfaulted phase.
Table 8 Fault phase direction detection
Phase Current Voltage

A Ia U bc
B Ib U ca
C Ic U ab
When the three-phase fault occurs, there is no unfaulted phase voltage,
which is not enough to detect the fault current direction, so memory
voltage is adopted. Diagram forward and reverse direction characteristics of
phase A current:
FWD 90° IA 90° IA
Bisector Bisector
RVD
Φ Φ
0° 0°
U BC_Ref U BC_Ref
5°
-IA -IA 5°
Figure 5 Forward or reverse direction interval

Overcurrent direction sensitive angle Φ =Angle:Adjustable.
Forward direction overcurrent range: (-85°~ +85°), reverse direction
overcurrent range: (+95°~ +265°).
Direction detection logic diagram is shown as follow:
17
Directional component of
phase φ meets the condition
&
≥1
Overcurrent stage 1 directional
“DirOCStage1”=1 component satisfied
“DirOCStage1”=0
Φ=a,b,c
Figure 6 Direction detection logic diagram

In the process of direction detection and voltage detection, the VT failure
may lead to trips or alarms that are not consistent with the flow direction
detection or the voltage detection along overcurrent protection stages.
When VT fails, the trip mode is decided according to "VTFailProtOff"; if
“VTFailProtOff” is set to 1, earth fault protection with voltage or directional
component is blocked; if “VTFailProtOff” is set to 0, voltage blocking
component and directional component exit and act in a pure overcurrent
mode.
When "3PhVoltConnect" is set 0, the direction is satisfied automatically.
3.1.4 Definite time

When "OCStg1Curve"=0, overvoltage is the definite time characteristic,
inverse time function is disabled.
I∅ > “OCStage1CurrSet”, (∅ = 𝑎𝑎, 𝑏𝑏, 𝑐𝑐)
When the phase-to-earth current is greater than "OCStage1CurrSet", timing
component starts, overcurrent protection trips when "OCStg1Time"; when
the phase-to-earth currentI∅ < Dropout × “OCStage1CurrSet”, Dropout is
dropoff coefficient, timing component and overcurrent protection resets.
3.1.5 Inverse time
When "OCStg1Curve"=1~13, overvoltage is the definite time characteristic,
 
 
A
=t  + B  ⋅T
  IΦ  P 
  − 1 
  Iset  
Where:
A: "InvTimeOCStg1A"
P: "InvTimeOCStg1P"
B: "InvTimeOCStg1B"
T: "InvTimeOCStg1T"
Iφ: Phase current value in the system
Iset: "OCStg1CurrSet"
If the phase-to-earth current exceeds "OCStg1CurrSet", the timing component
starts, inverse time characteristic curve is selected by curve. A, P, B are
determined when the value is from 1 to 12, see the curve definition table.
When the value is 13, it is user-defined, calculate tripping delay according
to the setting of A, P, B, T, when the time is up, overcurrent protection trips.
18
When the delay is less than the "InvTimeOCMinTime", the component trips
according to the "InvTimeOCMinTime".
Table 9 Curve definition
Curve Inverse time characteristic A P B

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
3 IEC EXTERMELY INV. 80.0 2.0 0
4 IEC SHORT TIME INV. 0.05 0.04 0
5 IEC LONG TIME INV. 120.0 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
9 ANSI MODERATELY INV. 0.0103 0.02 0.0228
10 ANSI VERY INV. 3.922 2.0 0.0982
11 ANSI EXTERMELY INV. 5.64 2.0 0.02434
12 ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13 USER DEFINE
3.1.6 Trip characteristic

When overcurrent protection function is enabled (En=1) and no BI blocking,
if the "OCStg1On"=1, the overcurrent protection of the corresponding
stage is enabled.
If the trip conditions are met, time component starts; take stage 1
protection for example, when time is over, "OCStg1Trip" is issued. When
IED trips, at the same time, each phase trip states will be displayed. LED,
IED output and others can be configured by AESP.
When "OC1BlkBy2ndH"=1, the harmonic locking component is put into
operation,when the trip timer is time out, the inrush current is checked, and
if the current is not locked, unblock overcurrent trip, otherwise it will output
“InrushBlk” report.
When "OCStg1BlkByVolt"=1, the composited voltage locking component is
put into the device.When the protection is started, the device checks the
composited voltage locking condition, unblock overcurrent protection if the
it meets the conditions, otherwise the protection is locked.
When “DirOCStg1"=1, overcurrent protection is with the directional
component, and choose the forward or reverse direction characteristic
according to "OCStg1FwdDir", when the directional component is not
satisfied, overcurrent protection is blocked.
When the overcurrent component trips, at the same time, three-phase
current value of Ia, Ib and Ic will also be displayed.
3.1.7 Alarm characteristic
When overcurrent protection function is enabled (En=1) and no open
blocking, if the "OCStg1AlmOn"=1 of overcurrent stage 1, the
19
corresponding overcurrent protection stage is enabled. If phase current is

greater than the setting "OCStg1AlmSet", the timer component starts, if
the fault time is greater than the setting "OCStg1TimeAlmSet" and
"OCStg1Alm" is issued. LED and output can be configured by AESP.
When the phase currentI∅ < Dropout × “OCStage1AlarmSet”, Dropout is
dropoff coefficient, timing component and overcurrent protection resets.
The alarm feature is BI blocked, and is not blocked by inrush current,
composited voltage , and direction .
3.1.8 Logic diagram
Taking the stage 1 of the overcurrent as an example, the logic diagram of
definite time is shown below:
Iφ>“OCStage1CurrSet”
VT failure blocking &

≥1
&
“VTFailProtOff”=1 OCS1PhφStartup
“VTFailProtOff”=0
Overcurrent stage 1 directional

component satisfied
Overcurrent Stage1 composited

voltage component satisfied
overcurrent protection fucntion is enabled
OCS1PhφStartup &
T1 &
&
BI blocking OCStage1Trip
OCS1 3PhInrushBlk
“OCStage1On”=1
T1：“OCSatge1Time”
Φ=a,b,c
Figure 7 Stage1 of the overcurrent definite time logic diagram

OCS1PhφStartup &
T1Alm &
OCStage1Alarm
BI blocking
“OCStage1AlarmOn”=1
T1Alm：“OCStage1TimeAlarmSet”
Φ=a,b,c
Figure 8 Logic diagram of overcurrent stage 1 alarm
20
3.2 Setting list

Table 10 Overcurrent setting
Default
Number Setting name Range Step Unit Remark
value
1 OCStage1CurrSet 0.05In～40In 40 0.01 A
2 OCSatge1Time 0.00～300.00 100 0.01 s
3 OCStage1AlarmSet 0.05In～40In 40 0.01 A
4 OCStage1TimeAlarmSet 0.00～100.00 100 0.01 s
5 OCStage1Curve 0～13 0 1
6 InvTimeOCStage1CoefA 0.001～1000 10 0.001
7 InvTimeOCStage1IndexP 0.01～10.00 10 0.01
8 InvTimeOCStage1TimeB 0.000～100.00 100 0.01
9 InvTimeOCStage1ConstT 0.025～1.5 0.025 0.001
11 OCSatge2Time 0.00～300.00 100 0.01 s
18 OCStage3Time 0.00～300.00 100 0.01 s
25 OCStage4Time 0.00～300.00 100 0.01 s
31 InvTimeOCMinTime 0.100～100.00 0.1 0.01 s
32 PPVoltBlkSet 1.00～120.0 30 0.01 V
One time of
negative
33 U2BlkSet 0.05～100.0 3 0.01 V
sequence
voltage
34 DirOCSensitiveAngle 0.00～90.00 30 0.01 degree
21
Default
value
35 OCHarmUnblkCurr 0.05In～40In 40 0.01 A
36 OC2ndHI2/I1Ratio 0.07～0.50 0.07 0.01
37 HarmCrossBlkTime 0.000～100.00 100 0.01 s
Table 11 Overcurrent protection logic switch

Logic switch Setting Default
Number Remark
description Mode value
1-Enable stage 1 of overcurrent,
1 OCStage1On 1/0 0
0-Disable stage 1 of overcurrent;
1-Overcurrent stage 1 alarm on;
2 OCStage1AlarmOn 1/0 0
0-overcurrent stage 1 alarm off
1-overcurrent stage 1 Dir on,
3 DirOCStage1 1/0 0
0-Overcurrent stage 1 Dir off
1-overcurrent stage 1 forward
4 OCStage1FwdDir 1/0 0 direction, 0-overcurrent stage 1
reverse direction
1-overcurrent stage 1 voltage on,
5 OCStage1BlkByVolt 1/0 0
0-Overcurrent stage 1 voltage off
1-overcurrent stage 1 secondary
6 OC1BlkBy2ndH 1/0 0 harmonic on, 0-Overcurrent stage 1
secondary harmonic off
0-adopt fundamental component in
7 OCStage1RMSOn 1/0 0 stage 1 of overcurrent;1-adopt root
mean source in stage 1 of overcurrent
8 OCStage2On 1/0 0
9 DirOCStage2 1/0 0
reverse direction
14 OCStage3On 1/0 0
15 DirOCStage3 1/0 0
reverse direction
20 OCStage4On 1/0 0
22

Number Remark
21 DirOCStage4 1/0 0
reverse direction
1-VT failure protection off, 0-VT failure
26 VTFailProtOff 1/0 0
protection on
3.3 Report list

Table 12 Report list
Number Report name Remark

Trip report:
1 OCStage1Trip /
2 OCStage2Trip /
3 OCStage3Trip /
4 OCStage4Trip /
5 OCStage1PhATrip /
6 OCStage1PhBTrip /
7 OCStage1PhCTrip /
8 OCStage2PhATrip /
9 OCStage2PhBTrip /
10 OCStage2PhCTrip /
11 OCStage3PhATrip /
12 OCStage3PhBTrip /
14 OCStage4PhATrip /
15 OCStage4PhBTrip /
Inrush conditions meet the
17 InrushBlk requirements of blocking
overcurrent protection
Alarm report:
1. OCStage1Alarm
23
3.4 Technical parameter

Table 13 Overcurrent protection technical data
Content Range and value Error

Definite time characteristic
Current 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
≤ ± 1% times of setting or
Time delay 0.00s～300.00s +40ms,
At 2 times of trip current
Inverse time characteristic
Normal inverse time
Very inverse time IEC60255-151
IEC standard Extreme inverse time ≤ ±5% setting or +40ms,
Short inverse time when 2<I/ISETTING<20
Long inverse time
Inverse time
Short inverse time
Long inverse time ANSI IEEEC37.112,
ANSI Medium inverse time ≤ ±5% setting or +40ms,
Very inverse time when 2<I/ISETTING<20
Extreme inverse time
Definite inverse time
 
  IEC60255-151
A
User defined characteristic
= t  + B  ⋅T ≤ ±5% setting or +40ms,
curve   IΦ  P  when 2<I/ISETTING<20
  −1 
  Iset  
Time coefficient of inverse
0.001～1000
time A
Time delay of inverse time B 0.000～100.00
Inverse time index P 0.01～10.00
Inverse time constant T 0.025～1.5
Minimum trip time 20ms
Return mode Instantaneous return
Directional component
Trip angle range 170° ≤ ±3°,
when phase-to-phase
Sensitive Angle 0°～90° voltage >2V
Inrush blocking
Maximum current of open
magnetizing inrush current 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
blocking
The ratio of secondary
harmonic and fundamental 0.07～0.5
wave current
Crossing blocking
(IL1,IL2,IL3) ( time setting 0.00s～100.00s ≤ ±1% setting or +40 ms
can be set)
24
Chapter 4 Earth fault protection(50N, 51N, 67N)
Chapter 4 Earth fault protection(50N,

51N, 67N)
About this chapter

This chapter describes the earth fault protection principle, the
input and output signals, setting parameters, messages and
technical parameters.
25
1 Overview
Under the condition of high resistance earthing fault in the neutral point
earthing system, the calculated impedance located out of the distance
impedance zone and the IED maloperate. Therefore, other protection trips
are needed to isolate the fault, earth fault protection can reliably identify
high resistance earthing fault.
The characteristics of earth fault protection are listed as follow:
1) Definite-time of 4 stage, inverse-time limit (including all IEC/ANSI
standard inverse-time characteristic);
2) The inrush locking feature of each stage is independently selectable;
3) Inrush locking is distinguished by secondary harmonic currents;
4) The maximum current of open magnetizing inrush current can be
adjusted;
soft-hard parallel.
6) Zero current external connection of stage 4 and self-produced zero
current support can adopt root mean source calculated current or
fundamental current.

The input and output signals of earth fault protection function are shown as
follow:
Directional / Non-directional Zero
Overcurrent Protection
1 1
BIBlk Start
2 2
ENA_EF Operation
3
Alarm
Figure 9 The input and output signals diagram of earth fault protection function
The input signals are on the left side and the output signals are on the
right.

Input:
BIBlk BI blocking
Output:
EF
Start IED startup
Protection alarm (only for the
Alarm
configuration of alarm stage)
ENA Input:
26

The total connector of earth fault
ENA_EF protection, the corresponding hard
connector is ENA_EF_5.
IED is equipped with 4 stages earth fault protection, please refer to the
setting list for details. The earth fault protection stage 1 will be taken as an
example below and the principle will be introduced.

3.1.1 Inrush blocking components
When "3I0Stage1BlkBy2ndH"=1, inrush will be detected. There are two inrush
criteria:
Check phase current harmonics and external zero sequence current
harmonic.
1) Only when "3I0HarmonChkExtI02/I01"=1, and "Extr3I0Stage1"=1, earth
fault protection harmonic is detected. When it is detected that the ratio
of second harmonic and fundamental wave is greater than
"3I02ndHI02/I01" and there is zero sequence current, then the zero
sequence inrush condition is satisfied. When the maximum
fundamental wave zero sequence current is greater than
"3I0HarmUnblkCurr", release each blocking.
2) In addition to the first case, detect the phase current harmonic. When it
is detected that the ratio of second harmonic and fundamental wave is
greater than "OC2ndHI2/I1Ratio" and there is a current, then the inrush
condition is satisfied. When the maximum fundamental wave of phase
current is greater than "OCHarmUnblkCurr", release each blocking.
Output locking statue when any of the above second harmonic check
method is satisfied, the secondary harmonic current is high.
3I0>“3I0HarmUnblkCurr” &
&
3I02/3I0>“3I02ndHI02/I01Ratio”
“Extr3I0Stage1”=0 & ≥1
secondary harmonic
current is high
“3I0HarmonChkExtrI02/I01”=1
&
Imax>“HarmUnblkPhCurr”
Ia2/Ia1>“OC2ndHI2/I1Ratio”
≥1
Ib2/Ib1>“OC2ndHI2/I1Ratio”
Ic2/Ic1>“OC2ndHI2/I1Ratio”
3I02/3I0:3I02ndH/3I0FundWave
Ia2/Ia1：PhACurr2ndH/PhACurrFundWave
Ib2/Ib1：PhBCurr2ndH/PhBCurrFundWave
Ic2/Ic1：PhCCurr2ndH/PhCCurrFundWave
Figure 10 Logic diagram of the secondary harmonic blocking of earth fault protection
27
3.1.2 Definite time

When "3I0Stage1Curve"=0, earth fault protection is the definite time
characteristic, inverse time function is disabled.
3I0 > “3I0Stage1CurrSet”
When the earth fault protection is greater than "3I0Stage1CurrSet", timing
component starts and until "3I0Stage1Time“, earth fault protection trips,
when 3I0 < Dropout × “3I0Stage1CurrSet”, Dropout is dropoff coefficient,
timing component returns, earth fault protection resets.
3.1.3 Inverse time
When "3I0Stage1Curve"=1~13, earth fault protection is the definite time
 
 
 A 
=t  P
+ B ⋅T
  3I 0  − 1 
  3I 0set  
Where:
A: "InvTime3I0Stage1CoefA"
P: "InvTime3I0Stage1IndexP"
B: "InvTime3I0Stage1TimeB"
T: "InvTime3I0Stage1ConstT"
3I 0 : Zero sequence current setting value
3I 0set : "3I0Stage1CurrSet"
If the current is greater than "3I0Stage1CurrSet", the timing component starts,
inverse time characteristic curve is selected by "3I0Stage1Curve", A, P, B are
determined when the value is from 1 to 12, see the Table 2; when the value is
13, it is user defined characteristics, calculate the trip delay according to the
setting of the A, P, B, T. While timing is up, earth fault protection trips. When
the calculated delay is less than the minimum trip delay time
"3I0InvTimeMinTripTime", the component trips according to the
"3I0InvTimeMinTripTime".

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
28

10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

When earth fault protection function is enabled and no BI blocking, if the
"3I0Stage1On"=1, the earth fault protection of the corresponding stage is
enabled.
If the trip conditions are met, time component starts; take stage 1 protection
for example, when time is over, "3I0Stg1Trip" is issued. LED and output can
be configured by AESP. When IED trips, at the same time, each phase trip
states will be displayed.
When "3I0Stage1BlkBy2ndH"=1, the harmonic locking component is put into
operation, when the trip timer is time out, the inrush current is checked, and if
the current is not blocked, unblock overcurrent trip, otherwise it will output
“InrushBlocking” report.
When "CTFailAlmOn"=1, input “CTFailBlk3I0” logic switch, then the CT failure
blocking earth fault protection, otherwise unblocking earth fault protection.
component trip triggers trip or alarm, meanwhile output analog quantity of
trip time, when the component is based on the self-produce zero sequence
current judgment, self-produce zero sequence current is output; when it is
based on the external zero sequence current, external zero sequence
current is output.
3I0>“3I0Stage1CurrSet”
BI block
&
& T1
CTFailBlk
“CTFailBlk3I0”=1
&
secondary harmonic 3I0Stage1Trip
current is high &
“3I0Stage1BlkBy2ndH”=1
“3I0Stage1On”=1
Earth fault protection stage 1

protection function enabled
T1：“3I0Stage1Time”
Figure 11 Logic diagram of earth fault protection function
3.1.5 Alarm characteristic

When earth fault protection function is enabled and no BI blocking, if
"3I0Stg1AlmOn"=1, the earth fault protection alarm of stage 1 is enabled. If
the current exceeds the setting ""3I0Stg1AlmSet", the timer starts, when
29
"3I0Stg1TimeAlmSet" is time out, "3I0Stg1Alm" will be issued. LED and

output can be configured by AESP. When
3I0 < Dropout × “3I0Stage1AlarmSet”, Dropout is dropoff coefficient, timing
component and overcurrent protection resets.
The alarm feature is BI blocked, and is not blocked by inrush .
3I0>”3I0Stage1CurrSet” &
T1Alm &
3I0Stage1Alarm
BI blocking
“3I0Stage1AlarmOn”=1
T1Alm：“3I0Stage1TimeAlarmSet”
Figure 12 Logic diagram of earth fault protection alarm
3.2 Setting list

Table 16 Earth fault protection setting
Default
value
Three times of zero
1 3I0Stage1CurrSet 0.05～200 40 0.01 A
sequence current
2 3I0Stage1Time 0.00～300.00 100 0.01 s
Three times of zero
3 3I0Stage1AlarmSet 0.05～200 40 0.01 A
sequence current
4 3I0Stage1TimeAlarmSet 0.00～100.00 100 0.01 s
0: Definite time
1：IECINV.
2：IEC VERY INV.
3：IEC
EXTERMELY INV.
4：IEC SHORT
TIME INV.
5：IEC LONG TIME
INV.
6：ANSI INV.
5 3I0Stage1Curve 0 1 7：ANSI SHORT
0～13
INV.
8：ANSI LONG INV.
9：ANSI
MODERATELY INV.
10：ANSI VERY
INV.
11：ANSI
EXTERMELY INV.
12：ANSI
DEFINITE INV.
13: User defined
6 InvTime3I0Stage1CoefA 0.001～1000 10 0.001
7 InvTime3I0Stage1IndexP 0.01～10.00 10 0.01
0.000～
8 InvTime3I0Stage1TimeB 100 0.01
100.00
9 InvTime3I0Stage1ConstT 0.025～1.5 0.025 0.001
30
Default
value
Three times of zero
10 3I0Stage2CurrSet 0.05～200 40 0.01 A
sequence current
11 3I0Stage2Time 0.00～300.00 100 0.01 s
12 3I0Stage2Curve 0～13 0 1
0.000～
100.00
Three times of zero
17 3I0Stage3CurrSet 0.05～200 40 0.01 A
sequence current
18 3I0Stage3Time 0.00～300.00 100 0.01 s
0.000～
100.00
Three times of zero
24 3I0Stage4CurrSet 0.05～200 40 0.01 A
sequence current
25 3I0Stage4Time 0.00～300.00 100 0.01 s
0.000～
100.00
0.100～
31 3I0InvTimeMinTripTime 0.1 0.01 s
100.00
32 HarmUnblkPhCurr 0.05In～40In 40 0.01 A
33 3I0HarmUnblkCurr 0.05In～40In 40 0.01 A
34 OC2ndHI2/I1Ratio 0.07～0.50 0.07 0.01
35 3I02ndHI02/I01Ratio 0.07～0.50 0.07 0.01
Note: If two earth fault protection channels are configured, the setting of earth
fault protection side 2 is the same as this table.
Table 17 Earth fault protection logic switch
Number Remark
1-Enable stage 1 of earth fault
1 3I0Stage1On 1/0 0 protection:;
0-earth fault stage 1 off
1-Enable stage 1 alarm of earth fault
protection;
2 3I0Stage1AlarmOn 1/0 0
0-Disable stage 1 alarm of earth fault
protection
31

Number Remark
1-earth fault protection stage 1
secondary harmonic blocking on,
3 3I0Stage1BlkBy2ndH 1/0 0
secondary harmonic blocking off
1-3I0 external connection; 0-3I0
4 Extr3I0Stage1 1/0 0
calculated
stage 1 of zero current
5 3I0Stage1RMSOn 1/0 0
1-adopt root mean source in stage 1
of zero current
blocked by secondary harmonic;
0-earth fault protection stage 2 is not
blocked by secondary harmonic
calculated
of zero current
calculated
of zero current
calculated
of zero current
1-Earth fault protection harmonics
check I02/I01
18 3I0HarmonChkI02/I01 1/0 0
0-Earth fault protection harmonics
check I2/I1
19 CTFailBlk3I0 1/0 0 0-open; 1-lock.
Note: If two earth fault protection channels are configured, the logic switch of
earth fault protection side 2 is the same as this table.
32
3.3 Report list


Trip report:
1 3I0Stage1Trip /
2 3I0Stage2Trip /
3 3I0Stage3Trip /
4 3I0Stage4Trip /
Alarm report:
1 3I0Stage1Alarm
2 3I0Stage1InrushBlk
Note: If two earth fault protection channels are configured, the report of earth
fault protection side 2 is the same as this table.

Table 19 Earth fault protection technical data

≤ ±1% setting or +40 ms, at
Time delay 0.00s～300.00s
2 times of operating current
Normal inverse time IEC60255-151
Very inverse time ≤ ± 5% times of setting or
IEC standard Extreme inverse time +40ms, in the case of
Short inverse time
2 < 3I 0 / 3I 0set<20
Long inverse time
Inverse time
Short inverse time ANSI IEEEC37.112,
Long inverse time ≤ ± 5% times of setting or
ANSI Medium inverse time +40ms, in the case of
Very inverse time 2 < 3I 0 / 3I 0set<20
Definite inverse time
 
  IEC60255-151
User defined characteristic  A  ≤ ± 5% times of setting or
= t  P
+ B ⋅T +40ms, in the case of
curve
  3I 0  − 1  2 < 3I 0 / 3I 0set<20
  3I 0set  
0.001～1000
time A
33

34
Chapter 5 High sensitive earth fault protection (50Ns,
51Ns, 67Ns)
Chapter 5 High sensitive earth fault

protection (50Ns, 51Ns,
67Ns)
About this chapter

This chapter describes the high sensitive zero sequence
current principle, the input and output signals, setting
parameters, messages and technical parameters.
35
51Ns, 67Ns)
1 Overview
High sensitive earth fault protection can be used to detect and give
selective trip of phase to earth faults in isolated or compensated networks.
The protection function also can be applied to neutral point direct earthing
system or large transition resistance earthing fault of neutral point through
small resistance earthing system.
High sensitive earth fault protection integrated in the IED provides
following features:
1) Provides 4-stage high sensitive earth fault protection, and definite time
and inverse time limit is optional;
2) Dedicated sensitive CT
3) Direction component needs to detect whether the VT secondary circuit
disconnects.
soft-hard parallel.

The input and output signals of high sensitive earth fault protection
function are shown as follow:
Directional / Non-directional Sensitive Zero Overcurrent Protection
1 1
BIBlk Start
2 2
ENA_SEF Operation
Figure 13 The input and output signal graphs of high sensitive earth fault protection
function
right.

Input:
BIBlk BI blocking
Output:
SEF
High sensitive earth fault protection
Start
start-up
High sensitive earth fault protection
Operation
trip
Input:
The total connector of high
ENA sensitive earth fault protection, the
ENA_SEF
corresponding hard connector is
ENA_SEF_5.
36
51Ns, 67Ns)
IED is equipped with 4 stages high sensitive earth fault protection, please
refer to the setting list for details. The SEF/REF overcurrent protection
stage 1 will be taken as an example below and the principle will be
introduced.

3.1.1 Definite time
When "SEF/REFStage1Curve"=0, high sensitive zero sequence current
trips as the definite time characteristic, inverse time function is disabled.
Is0 > “SEF/REFStage1CurrSet”
When the current is greater than setting "SEF/REFStage1CurrSet", timing
component starts and until timing to the setting "SEF/REFStage1Time",
high sensitive earth fault protection trips, when the currentIs0 < Dropout ×
“SEF/REFStage1CurrSet”, Dropout is dropoff coefficient, timing component
and high sensitive earth fault protection resets.
3.1.2 Inverse time
When "SEF/REF1Curve"=1~13, high sensitive earth fault trips as the inverse
time characteristic, definite time function is disabled.
 
 
 A 
=t  P
+ B ⋅T
  Is0  −1 
  I s 0set  
If the current exceeds "SEF/REFStage1CurrSet", timing component starts,

inverse time characteristic curve is selected by curve, A, P and B are
determined when the value ranges 1~12; when the value is 13, it is
user-defined, calculate tripping delay according to the setting of A, P, B, T.
When time is up, high sensitive earth fault protection trips.
Where:
A: "InvTimeSEF/REFStage1CoefA"
P: "InvTimeSEF/REFStage1IndexP"
B: "InvTimeSEF/REFStage1B"
T: "InvTimeSEF/REFStage1ConstT"
I s 0 : Zero sequence current setting value of high voltage side
I s 0 set : "SEF/REFStage1CurrSet"
When "SEF/REFStage1Curve"=14, high sensitive earth fault trips with the
characteristics of the epatr curve. The primary current ISEF curve is:
0.5～6A，t=432*T/(ISEF0.655)；
6～200A，t=800*T/ISEF；
200A 以上，t=4*T；
Where:
37
51Ns, 67Ns)
ISEF: Primary current value (A)
t：Inverse time trip time
T: "InvTimeSEF/REFStage1ConstT"
EPATR curve
Time（s）
Primary current value (A)，CT ratio 100:1
Figure 14 EPATR curve


0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE
14 epatr curve

When high sensitive earth fault protection function is enabled and no BI
blocking, if "SEF/REFStage1On"=1, high sensitive earth fault protection of the
corresponding stage is enabled.
If high sensitive earth fault protection trip is enabled and the tripping conditions
are met, time component starts; take stage 1 protection as an example, when
time is over, "SEF/REFStage1Trip" is issued. LED and output can be
configured by AESP.
38
51Ns, 67Ns)
The component trip triggers the protection trip, and outputs the high
sensitive zero sequence current value at the same time of the trip time.
Is0>“SEF/REFStage1CurrSet”
&
T1
BI blocking
&
SEF/REFStage1Trip
“SEF/REFStage1On”=1
Enable SEF/REF stage 1 protection function
T1：“SEF/REFStage1Time”
Figure 15 SEF/REF protection function logic diagram
3.2 Setting list

Table 22 High sensitive earth fault protection setting
Default
value
If 1.2/3.53 AC
module is used, the
setting range is
0.005～ 0.005~1.00;
1 SEF/REFStage1CurrSet 1 0.001 A
1.00 If 6/3.53 AC module
is used, the setting
range is
0.005~5.00;
2 SEF/REFStage1Time 0.00～300 100 0.01 s
0: Definite time
1: IEC INV.
2: IEC VERY INV.
3: IEC
EXTERMELY INV.
4: IEC SHORT
TIME INV.
5: IEC LONG TIME
INV.
6: ANSI INV.
7:ANSI SHORT
INV.
3 SEF/REFStage1Curve 0～14 0 1 8: ANSI LONG INV.
9: ANSI
MODERATELY INV.
10: ANSI VERY
INV.
11: ANSI
EXTERMELY INV.
12: ANSI DEFINITE
INV.
13: User defined
14: Apply only to
the Kotter epatr
curve
0.001～
4 InvTimeSEF/REFStage1CoefA 10 0.001
1000
39
51Ns, 67Ns)
Default
value
0.01～
5 InvTimeSEF/REFStage1IndexP 10 0.01
10.00
0.000～
6 InvTimeSEF/REFStage1ConstB 100 0.01
100.00
0.025～
7 InvTimeSEF/REFStage1ConstT 0.025 0.001
1.5
If 1.2/3.53 AC
module is used, the
setting range is
0.005～ 0.005~1.00;
range is
0.005~5.00;
10 SEF/REFStage2Curve 0～14 0 1
0.001～
1000
0.01～
10.00
0.000～
13 InvTimeSEF/REF2ConstB 100 0.01
100.00
0.025～
1.5
If 1.2/3.53 AC
module is used, the
setting range is
0.005～ 0.005~1.00;
range is
0.005~5.00;
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
If 1.2/3.53 AC
module is used, the
setting range is
0.005～ 0.005~1.00;
range is
0.005~5.00;
40
51Ns, 67Ns)
Default
value
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
0.100～
29 InvTimeSEF/REFMinTime 0.1 0.01 s
100.00
Note: If two high sensitive earth fault protection channels are configured, the
setting of high sensitive earth fault protection side 2 is the same as this table.
Table 23 High sensitive earth fault protection logic switch
Number Remark
1 SEF/REFStage1On 1/0 0
logic switch of high sensitive earth fault protection side 2 is the same as this
table.
3.3 Report list


Trip report:
1 SEF/REFStage1Trip /
report of high sensitive earth fault protection side 2 is the same as this table.
41
51Ns, 67Ns)
Table 25 High sensitive earth fault protection technical data
Items Setting range Trip value error

High sensitive CT
0.005A～5.000A ≤ ±2.5 % setting or 1mA
current input setting
≤ ±1.5% setting or +40ms, when trip
Time setting 0.00s～300.00s
current is set as 200% setting
When I/In≥0.5, it is about
Dropoff coefficient
0.95
Reset time About 40 ms
High sensitive CT
0.005A～1.000A ≤ ±2.5 % setting or 1mA
current input setting
Normal inverse time
Very inverse time ≤ ±5% setting or +40ms, when
IEC standard curve Extreme inverse time 2 < I s 0 / I s 0set<20 , it meets
Short inverse time IEC60255-151 standard
Long inverse time
Standard inverse time;
Short inverse time
Long inverse time ≤ ±5% setting or +40ms, when
ANSI standard curve Normal inverse time 2 < I s 0 / I s 0set<20 , it meets
Very inverse time ANSI/IEEEC37.112 standard
User-defined inverse time;
 
  ≤ ±5% setting or +40ms, when
 A 
User defined curve = t  P
+ B ⋅T 2 < I s 0 / I s 0set<20 , it meets
  Is0  −1  IEC60255-151 standard
  I s 0set  
Time coefficient of
0.001～1000
inverse time A
Time delay of inverse
0.000～100.00
time B
42
Chapter 6 Negative sequence current protection (46)
Chapter 6 Negative sequence

current protection (46)
About this chapter

This chapter describes the negative sequence current
principle, the input and output signals, setting parameters,
messages and technical parameters.
43
1 Overview
Negative sequence current protection can detect the unbalance of power
system load. When the generator connect unbalanced load, negative
sequence current protection is particularly useful. Because the unbalanced
load will produce a reverse magnetic field in the three-phase induction
motor, resulting in overheating of the rotor end. Secondly, the negative
sequence current protection can also be used to detect the disconnection,
short circuit and polarity of current transformer. Besides, the negative
sequence current protection can also detect the single-phase or
phase-to-phase faults in the system, and the fault statue when the fault
current is less than the load current.
The main characteristics of the negative sequence current protection is:
offer four stages of negative sequence current protection, and definite time
or inverse time can be selected.
The protective function can be disabled through the function connector.
connector, soft-hard series, soft-hard parallel, and the default is soft-hard
parallel.

The input and output signals of negative sequence current protection
Negative Sequence Over Current
Protection
1 1
BIBlk Start
2 2
ENA_NSOC Operation
Figure 16 The input and output signals diagram of negative sequence current
protection function
right.

Input:
BIBlk BI blocking
NSOC Output:
Start IED startup
Input:
The total connector of negative
ENA sequence current protection, the
ENA_NSOC
ENA_NSOC_5.
44
IED is equipped with 4 stages negative sequence current protection,
please refer to the setting list for details. The negative sequence current
protection stage 1 will be taken as an example below and the principle will
be introduced.

3.1.1 Definite time
When "3I2Stg1Curve"=0, negative sequence current is the definite time
The negative sequence current protection trip current is calculated by the
three-phase current as follow:
3İ 2 = İA + a2 İB + aİC
3I2 > “3I2Stage1CurrSet”
When the current is greater than "3I2Stage1CurrSet", timing component starts
and until "3I2Stage1Time“, negative sequence current protection trips, when
current 3I2 < Dropout × “3I2Stage1CurrSet” , timing component returns,
negative sequence current protection resets.
Where:
I 2 : Negative sequence current;
I 2 set :“3I2Stage1CurrSet”
Dropoff: Dropoff coefficient
3.1.2 Inverse time
When "3I2Stg1Curve"=1~13, negative sequence current is the inverse time
characteristic, definite time function is disabled.
 
 
 A 
=t  P
+ B ⋅T
  I2  −1 
  I 2set  
If the negative sequence current exceeds "3I2Stage1CurrSet", the timing

component starts, inverse time characteristic curve is selected by curve, A, P,
B are determined when the value is from 1 to 12, see the Table 3; when the
value is 13, it is user defined characteristics, calculate the trip delay according
to the setting of the A, P, B, T. While timing is up, earth fault protection trips.
When the calculated delay time is less than the "InvTimeI2MinTime", the
component trips in accordance with the "InvTimeI2MinTime".
Where:
A: "InvTime3I2Stg1A"
P: "InvTime3I2Stg1P"
B: "InvTime3I2Stg1B"
T: "InvTime3I2Stg1T"
45
I 2 : Negative sequence current
I 2set : "3I2Stg1CurrSet"

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

When negative sequence current protection function is enabled and there is
no binary input blocking, if "3I2Stage1On"=1, then the negative sequence
current protection of the corresponding stage is enabled.
Negative sequence current protection is tripped, after the starting of protection
trip, if the trip conditions are met, timing component starts, take stage 1 for
example, when time is over, "3I2Stage1Trip" is issued. LED and protection
trip can be configured by AESP. When the zero sequence current
component trips, at the same time, negative sequence current value will
also be displayed.
Enable the protection function of
negative sequence current stage 1
&
&
“3I2Stage1On”=1 T1
3I2Stage1Trip
3I2>“3I2Stage1CurrSet”
BI blocking
T1：“3I2Stage1Time”
Figure 17 Logic diagram of negative sequence current protection function
46
3.2 Setting list

Table 28 Negative sequence current protection setting
Default
value
Three times of
0.05In～
1 3I2Stage1CurrSet 40 0.01 A negative sequence
40In
current
0.00～ Negative sequence
2 3I2Stage1Time 100 0.01 s
100.00 current stage 1 time
0: Definite time
1: IEC INV.
2: IEC VERY INV.
3: IEC EXTERMELY
INV.
4: IEC SHORT TIME
INV.
5: IEC LONG TIME
INV.
6: ANSI INV.
7:ANSI SHORT INV.
8: ANSI LONG INV.
9: ANSI
MODERATELY INV.
10: ANSI VERY INV.
11: ANSI
EXTERMELY INV.
12: ANSI DEFINITE
INV.
13: User defined
0.001～
4 InvTime3I2Stage1CoefA 10 0.001
1000
0.01～
5 InvTime3I2Stage1IndexP 10 0.01
10.00
0.000～
100.00
0.025～
7 InvTime3I2Stage1ConstT 0.025 0.001
1.5
Three times of
0.05In～
40In
current
0.00～
100.00
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
Three times of
0.05In～
40In current
0.00～
100.00
47
Default
value
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
Three times of
0.05In～
40In current
0.00～
100.00
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
0.100～
29 InvTimeI2MinTime 0.1 0.01 s
100.00
Table 29 Negative sequence current protection logic switch
Number Remark
1 3I2Stage1On 1/0 0 1: On; 0: Off
2 3I2Stage2On 1/0 0 1: On; 0: Off
3 3I2Stage3On 1/0 0 1: On; 0: Off
4 3I2Stage4On 1/0 0 1: On; 0: Off
3.3 Report list

Trip report:
1 3I2Stage1Trip /
2 3I2Stage2Trip /
3 3I2Stage3Trip /
4 3I2Stage4Trip /
48

Table 31 Negative sequence current protection technical data

Current setting 0.05In～40In ≤ ±2.5% setting or ±0.02In
≤ ±1% setting or +40ms,
Time setting 0.00s～100.00s when trip current is set as
200% setting
Dropoff coefficient When I/In>0.5, it is about 0.95
Current setting 0.05In～40In ≤ ±2.5% setting or ±0.02In
Normal inverse time; ≤ ±5% setting or +40ms,
Very inverse time; when 2 < I 2 / I 2set<20 , it
IEC standard curve Extreme inverse time;
Short inverse time meets IEC60255-151
Long inverse time; standard
Short inverse time ≤ ±5% setting or +40ms,
Long inverse time; when 2 < I 2 / I 2set<20 , it
ANSI standard curve Normal inverse time;
Very inverse time; meets ANSI/IEEEC37.112
Extreme inverse time; standard
 
  ≤ ±5% setting or +40ms,
 A  when 2 < I 2 / I 2set<20 , it
+ B ⋅T
  I2  −1
meets IEC60255-151

  I 2set   standard

0.001～1000
time A
Time delay of inverse time
0.000～100.00
B
49
Chapter 7 Undercurrent protection (37)
Chapter 7 Undercurrent protection

(37)
About this chapter

This chapter describes the undercurrent protection principle,
the input and output signals, setting parameters, messages
and technical parameters.
51
1 Overview
Undercurrent protection is to prevent the charging capacitor bank
supplying power to the power grid, when the voltage drops,
The device provides one stage of undercurrent protection.
parallel.

The input and output signals of undercurrent protection function diagram
are shown as follow:
Under Current protection

1 1
En Start
2 2
BIBlk Operation
3
ENA_UI
Figure 18 The input and output signals of undercurrent protection function diagram
right.

Input:
BinaryInput
CBOpen Circuit breaker trip position
Input:
BIBlk BI blocking
UI Output:
Start IED startup
Input:
The total connector of
ENA undercurrent protection, the
ENA_UI
ENA_UI_5.
When undercurrent protection function is enabled and no BI blocking, if
"UCOn"=1, undercurrent protection is enabled.
When undercurrent protection is input and the circuit breaker is in close
52
position, if the three-phase current is lower than the setting of the "UCSet",
then the protection is started, and after the "UCTime" is delayed, the
protection trips.
Undercurrent protection trip is enabled and the trip conditions are satisfied,
timing component starts, time up, IED issues "UCTrip". LED and output
can be configured by AESP.
Ia<“UCSet”
&
Ib<“UCSet”
Ic<“UCSet”
&
Circuit breaker trip position &
T
UCTrip
BI blocking
Enable undercurrent
protection function
“UCOn”=1
T：“UCTime”
Figure 19 Logic diagram of undercurrent protection
3.2 Setting list

Table 33 Undercurrent protection setting
Default
value
1 UCSet 0.05In～40In 0.25 0.01 A
2 UCTime 0～100 100 0.01 s
Table 34 Logic switch of undercurrent protection

Number Remark
1 UCOn 1/0 0 1: On; 0: Off
3.3 Report list


Trip report:
1 UCTrip /

Table 36 Undercurrent protection technical parameter

Current setting 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
≤ ± 1% setting or +40 ms, when
Time setting 0.00s～100.00s the tripping value is below 0.5
times of the current setting
53
Chapter 8 Overvoltage protection (59)
Chapter 8 Overvoltage protection

(59)
About this chapter

This chapter describes the overvoltage principle, the input
and output signals, setting parameters, reports and technical
parameters.
55
1 Overview
Overvoltage protection is used to prevent the impact of overvoltage on
electrical equipment. The abnormal overvoltage often occurs in low load,
long transmission line, generator voltage regulation fails in the islanded
system, or the load shedding of the generator in the system. Even if the
compensating capacitor can compensate line capacitive reactance, lower
the overvoltage of the lines, when the compensating capacitor fails,
overvoltage will endanger the line insulation system, here the circuit must
be removed.
Overvoltage protection has the following characteristics:
1) Definite time and reverse time are selective on stage 4
2) Measure voltage and select phase-to-phase voltage
3) The protection dropoff coefficient of stage 4 can be adjusted
separately;
soft-hard parallel.

The input and output signals of overvoltage protection function are shown
as follow:
Overvoltage Protection
1 1
BIBlk Start
2 2
ENA_OV Operation
Figure 20 The input and output signals of overvoltage protection function diagram
right.

Input:
BIBlk BI blocking
OV Output:
Start IED startup
Input:
ENA The total connector of overvoltage
ENA_OV protection,the corresponding hard
connector is ENA_OV_5.
56
Overvoltage protection select phase-to-phase voltage UA-B,UB-C,UC-A.
The overvoltage protection of stage 1 will be taken as an example in below
and the principle will be introduced.
3.1.1 Definite time
When "OVStage1Curve"=0, overvoltage is the definite time characteristic,
U∅ > “OVStage1VoltSet”, (∅ = 𝑎𝑎𝑎𝑎, 𝑏𝑏𝑏𝑏, 𝑐𝑐𝑐𝑐)
When the phase-to-phase voltage setting is greater than "OVStage1VoltSet",
timing component starts and until timing to the "OVStage1Time", overvoltage
protection trips, when the phase-to-phase voltage U∅ < OVDropoffCoef ×
“OVStage1VoltSet”, timing component returns, overvoltage protection resets.
3.1.2 Inverse time
When "OVStg1Curve"=1-13, the overvoltage trips as definite time
 
 
 A 
=t  P
+ B ⋅T
  UΦ  −1 
 U set  
Where:
A：“InvTimeOVStage1CoefA”
P：“InvTimeOVStage1IndexP”
B：“InvTimeOVStage1TimeB”
T：“InvTimeOVStage1ConstT”
U Φ :Phase-to-phase voltage
U set : "OVStage1VoltSet"
If the phase-to-phase voltage is greater than "OVStg1VoltSet", the timing

component starts, inverse time characteristic curve is selected by curve, A, P,
B are determined when the value is from 1 to 12, see Table 3, when the value
is 13, it is user defined characteristics, calculate the trip delay according to the
setting of the A, P, B, T. While timing is up, overvoltage protection trips. When
the calculated delay time is less than the "InvTimeOVMinTime", the
component trips in accordance with the "InvTimeOVMinTime".
57

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
4 IEC SHORT INV 0.05 0.04 0
5 IEC LONG INV. 120.0 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 User defined

When overvoltage protection is enabled and there is no binary input
blocking, if "OVStg1On"=1, then overvoltage protection of the
corresponding stage is enabled.
After the starting of protection trip, if the trip conditions are met, timing
component starts, take stage 1 for example, when time is over,
"OVStg1Trip" is issued. LED and output can be configured by AESP.
When the Overvoltage protection trips, the three-phase phase-to-phase
voltage at the time of trip is output.
3.1.4 Logic diagram
The logic diagram of overvoltage protection is shown in following figure.
max(Uab,Ubc,Uca)>“OVStage1VoltSet” &
“OVChk1Ph”=1 ≥1
min(Uab,Ubc,Uca)>“OVStage1VoltSet” &
&
T1
OVStage1Trip
“OVChk1Ph”=0
Enable the stage 1 of

undervoltage protection function
“OVStage1On”=1
T1：“OVStage1Time”
Figure 21 The logic diagram of overvoltage protection
58
3.2 Setting list

Table 39 Overvoltage protection setting
Default
value
40.00～
1 OVStage1VoltSet 110 0.01 V
200.0
0.00～
2 OVStage1Time 120 0.01 s
120.00
0: Definite time
1: IEC INV.
2: IEC VERY INV.
3: IEC EXTERMELY
INV.
4: IEC SHORT TIME
INV.
5: IEC LONG TIME
INV.
6: ANSI INV.
3 OVStage1Curve 0～13 0 1
7:ANSI SHORT INV.
8: ANSI LONG INV.
9: ANSI
MODERATELY INV.
10: ANSI VERY INV.
11: ANSI
EXTERMELY INV.
12: ANSI DEFINITE
INV.
13: User defined
0.001～ Inverse time
4 InvTimeOVStage1CoefA 10 0.001
1000 characteristic
0.01～
5 InvTimeOVStage1IndexP 10 0.01
10.00
0.000～
6 InvTimeOVStage1TimeB 100 0.01
100.00
0.025～
7 InvTimeOVStage1ConstT 0.025 0.001
1.5
40.00～
200.0
0.00～
9 OVStage2Time 120 0.01 S
120.00
1000 characteristic
0.01～
10.00
0.000～
100.00
0.025～
1.5
40.00～
200.0
0.00～
120.00
59
Default
value
1000 characteristic
0.01～
10.00
0.000～
100.00
0.025～
1.5
40.00～
200.0
0.00～
120.00
1000 characteristic
0.01～
10.00
0.000～
100.00
0.025～
1.5
0.100～
29 InvTimeOVMinTime 0.1 0.01 s
100.00
30 OVStage1DropoffCoef 0.95～1 1 0.01
Table 40 Overvoltage protection logic switch

Number Remark
1-check phase 1; 0-check phase 3
1 OVChk1Ph 1/0 0 When "3PhVoltConnect" is 0, only
"OVChk1Ph" can be enabled
2 OVStage1On 1/0 0 /
3.3 Report list


Trip report:
1 OVStage1Trip /
2 OVStage2Trip /
3 OVStage3Trip /
4 OVStage4Trip /
60

Table 42 Overvoltage protection technical parameter

Phase-to-phase voltage
80V～200V ≤ ±2.5% setting or ±1V
setting
Dropoff coefficient 0.95～1 ≤ ±3% setting
≤ ±1% setting or +60 ms
Time delay setting 0.00s～120.00s
At 1.2 times of trip voltage
Reset time <40ms
Phase-to-phase voltage
80V～200V ≤ ±2.5% setting or ±1V
setting
Normal inverse time;
Very inverse time; In the case of 2 < U / Uset<20 ,
IEC standard curve Extreme inverse time; the allowable trip time error is:
Short inverse time ± 5% or +60 ms;
Long inverse time;
Short inverse time
Long inverse time; In the case of 2 < U / Uset<20 ,
ANSI standard curve Normal inverse time; the allowable trip time error is:
Very inverse time; ± 5% or +60 ms;
Extreme inverse time;
 
  In the case of
A
User defined curve =t  + B  ⋅T 2 < U / Uset<20 , it meets the
  U P  IEC60255-151 standard
  −1 
 Uset  
0.001～1000
time A
61
Chapter 9 Negative sequence voltage protection (47)
Chapter 9 Negative sequence

voltage protection (47)
About this chapter

This chapter describes the negative sequence voltage
principle, the input and output signals,setting parameters,
63
1 Overview
In normal operating three-phase system, the negative sequence voltage is
almost 0, and the negative sequence voltage will occur when there is
asymmetrical situation in the system. Negative sequence voltage
protection trips by checking negative sequence voltage.
Main characteristics of the negative sequence voltage protection are as follow:
offer 4 stages of protection, definite time or inverse time can be selected.
parallel.

The input and output signals of negative sequence voltage protection
Negative Sequence Over Voltage
Protection
1 1
BIBlk Start
2 2
ENA_NSOV Operation
Figure 22 The input and output signals diagram of negative sequence voltage
protection function
right.

Input:
BIBlk BI blocking
NSOV Output:
Start IED startup
Input:
The total connector of negative
ENA sequence voltage protection, the
ENA_NSOV
ENA_NSOV_5.
The negative sequence voltage protection stage 1 will be taken as an
example below and the principle will be introduced.
3.1.1 Definite time
When "U2Stage1Curve"=0, negative sequence voltage is the definite time
64

The negative sequence voltage protection trip voltage is calculated by the
three-phase voltage as follow:
3U̇ 2 = U̇ A + a2 U̇ B + aU̇ C
3U2 > “3U2Stage1VoltSet”
If the voltage is greater than "3U2Stage1VoltSet", timing component starts and
until timing to "3U2Stage1Time", negative sequence voltage protection trips.
Where:
U 2 : Negative sequence voltage
3.1.2 Inverse time

When "3U2Stage1Curve"=1~13, negative sequence voltage is the inverse
time characteristic, definite time function is disabled.
 
 
 A 
=t  P
+ B ⋅T
  U2  −1 
 U 2set  
If the voltage exceeds "3U2Stage1VoltSet", the timing component starts,

inverse time characteristic curve is selected by inverse time characteristic
curve, A, P, B are determined when the value is from 1 to 12, see Table 3;
when the value is 13, it is the user defined characteristics, calculate the trip
delay in accordance with the setting of the A, P, B, T. While timing is up,
negative sequence voltage protection trips. When the calculated delay time
is less than the "InvTimeU2MinTime", the component trips in accordance
with the "InvTimeU2MinTime“.
Where:
A: "InvTime3U2Stage1CoefA"
P: "InvTime3U2Stage1IndexP"
B: "InvTime3U2Stage1TimeB"
T: "InvTime3U2Stage1ConstT"
U 2 : Negative sequence voltage
U 2 set :"3U2Stg1VoltSet"

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
65

7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

When negative sequence voltage protection function is enabled and there
is no binary input blocking, if "3U2Stg1On"=1, then the negative sequence
overvoltage protection is enabled.
After the protection trip starts, if the trip conditions are satisfied, timing
component starts, and works till the IED issues "3U2Stage1Trip" LED and
output can be configured by AESP.
3.2 Setting list

Table 45 Negative sequence voltage protection setting
Default
value
40～ 3 times of negative
1 3U2Stage1VoltSet 100 0.01 V
100.00 sequence voltage
0.00～
2 3U2Stage1Time 100 0.01 s
100.00
0: Definite time
1: IEC INV.
2: IEC VERY INV.
3: IEC
EXTERMELY INV.
4: IEC SHORT
TIME INV.
5: IEC LONG TIME
INV.
6: ANSI INV.
7:ANSI SHORT
3 3U2Stage1Curve 0～13 0 1 INV.
8: ANSI LONG INV.
9: ANSI
MODERATELY
INV.
10: ANSI VERY
INV.
11: ANSI
EXTERMELY INV.
12: ANSI DEFINITE
INV.
13: User defined
0.001～
4 InvTime3U2Stage1CoefA 10 0.001
1000
0.01～
5 InvTime3U2Stage1IndexP 10 0.01
10.00
66
Default
value
0.000～
6 InvTime3U2Stage1TimeB 100 0.01
100.00
0.025～
7 InvTime3U2Stage1ConstT 0.025 0.001
1.5
0.00～
100.00
10 InvTime3U2Stage2Curve 0～13 0 1
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
0.100～
15 InvTimeU2MinTime 0.1 0.01 s
100.00
0.00～
100.00
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
0.00～
100.00
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
Table 46 Negative sequence voltage protection logic switch
Number Remark
1 3U2Stage1On 1/0 0 1: On; 0: Off
2 3U2Stage2On 1/0 0 1: On; 0: Off
67

Number Remark
3 3U2Stage3On 1/0 0 1: On; 0: Off
4 3U2Stage4On 1/0 0 1: On; 0: Off
3.3 Report list


Trip report:
1 3U2Stage1Trip /
2 3U2Stage2Trip /
3 3U2Stage3Trip /
4 3U2Stage4Trip /

Table 48 Negative sequence voltage protection technical data

≤ ±5% times of setting or
Trip voltage 3U2 (calculated) 40V～100V
±1V
Time setting 0.00s～100.00s when trip voltage is set as
120% of setting
Dropoff coefficient About 0.95
Trip voltage 3U2 (calculated) 40V～100V
±1V
Normal inverse time; In the case of
Very inverse time; 2 < U 2 / U 2set<20 , the
IEC standard curve Extreme inverse time;
Short inverse time allowable trip time error is: ±
Long inverse time; 5% or +60 ms
Short inverse time In the case of
Long inverse time; 2 < U 2 / U 2set<20 , the
ANSI standard curve Normal inverse time;
Very inverse time; allowable trip time error is: ±
Extreme inverse time; 5% or +60 ms
 
  In the case of
 A 
+ B  ⋅T 2 < U 2 / U 2set<20 , it meets
  U  
2
−1 the IEC60255-151 standard
 U 2set  
0.001～1000
time A
68

69
Chapter 10 Undervoltage protection (27)
Chapter 10 Undervoltage protection

(27)
About this chapter

This chapter describes the undervoltage protection principle,
the input and output signals, setting parameters, messages
and technical parameters.
71
1 Overview
Undervoltage protection can effectively protect the power equipment from
the impact of voltage drop.
The main features of undervoltage protection are as follow:
1) It provides 4 stages of protection, definite and inverse time can be
selected.
2) Undervoltage protection voltage is phase-to-phase voltage
3) Undervoltage blocking current check;
4) State check of circuit breaker;
5) VT failure check, VT failure blocking undervoltage protection;
6) Dropoff coefficient is adjustable;
soft-hard parallel.

The input and output signals of undervoltage protection function are shown
as follow:
Undervoltage Protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_UV
Figure 23 The input and output signal diagram of undervoltage protection function
right.

Input:
BinaryInput
Input:
BIBlk BI blocking
UV Output:
Start IED startup
Input:
ENA undervoltage protection,the
ENA_UV
ENA_UV_5.
72
IED consists of four stages of undervoltage protection, definite time or
inverse time characteristic are selectable, please refer to setting list for details.
The undervoltage protection stage 1 will be taken as an example below
and the principle will be introduced.

Undervoltage protection can provide 4 stages of protection, with selectable
definite/inverse time. Take the undervoltage 1 stage as the example, it can
be enabled or disabled via the enabled/disabled connector "UVStg1On".
With the limit of field condition, the voltage transformer of the circuit
breaker may be connected to the power supply side or the load side. The
installation position of VT is different, and the operation characteristics of
undervoltage protection are different. As the undervoltage protection starts
tripping and the circuit breaker is open, the voltage beside power supply
latches unchangeable but the voltage beside load drops to zero, now
undervoltage protection resets. If the voltage transformer is installed on
the power supply side, and does not want to protect the undervoltage
detection current, the setting of "UVChkCurrOn" can be set to 0. In addition,
the undervoltage protection can enable and disable logic swtich
"UVChkCBState" to choose whether the trip logic is to detect the circuit
breaker status. When the undervoltage protection is required to check the
circuit breaker state, the undervoltage protection sends out the trip
command only when the circuit breaker is closed. If the voltage
transformer is installed on the power supply side, and undervoltage
protection does not check circuit breaker status, the logic switch
"UVChkCBState" is set to 0.
3.1.1 Blocking condition
When "UVChkCBState"=1, circuit breaker will be checked at blocking
protection during the trip, with non-blocking protection starting and
blocking protection delaying.
When the maximum value of the three-phase current is less than
"UVCurrSet", the blocking is protected, the non-blocking protection starts,
and the blocking is delayed.
As VT failure blocking is 1, the blocking is protected, the non-blocking
protection starts, and the blocking is delayed.
When the three-phase phase-to-phase voltages is lower than 1.732 times
of the setting value "t3PhUVBlkSet" at the same time, the blocking is
protected, and the blocking protection starts.
3.1.2 Definite time
When "UVStg1CurveSel"=0, undervoltage is the definite time
characteristic, and inverse time function is disabled.
𝑈 < ’’UVStage1VoltSet”
When the voltage is lower than the setting"UVStage1VoltSet", timing
component starts and works until the setting "UVStage1Time", and
undervoltage protection trips. When voltage
𝑈 > 𝐷𝑟𝑜𝑝𝑜𝑢𝑡 × “UVStage1VoltSet” , timing component drops out,
undervoltage protection drops out.
73
3.1.3 Inverse time

When "UVStg1CurveSel"=1~4, undervoltage is the inverse time characteristic,
definite time function is disabled.
 
 
A
=t  + B  ⋅T
  U P 
1 −   
 Uset  
If the voltage is lower than "UVStg1VoltSet", the timing component starts,
inverse time characteristic curve is selected by curve, A, P, B are
determined when the value is from 1 to 3, see Table 3; when the value is 4, it
is the user defined characteristics, calculate the trip delay in accordance with
the setting of the A, P, B, T. While timing is up, undervoltage protection trips.
When the calculated delay time is less than the "InvTimeUVMinTime", the
component trips in accordance with the "InvTimeUVMinTime".
Where:
A: "InvTimeUVStg1A"
P: "InvTimeUVStg1P"
B: "InvTimeUVStg1B"
T: "InvTimeUVStg1T"
U :Voltage
Uset :"UVStg1VoltSet"

Inverse time
Curve A P B
characteristic
0 Definite time
1 Curve1 1 1 0
2 Curve 2 40 2 1
3 Curve 3 5 2 2
4 User defined

When undervoltage protection is enabled and there is no binary input
blocking, if "UVStg1On"=1, then undervoltage protection is enabled.
Three phases can be configured as "OR" logic and the protection stars
while at least one voltage is lower than the setting; it can be configured as
"AND" logic, and the protection starts while three voltages are all lower
than the setting.
After the starting of protection trip, if the trip conditions are met, timing
component starts, take stage 1 for example, when time is over, "UVStg1Trip"
is issued. LED and output can be configured by AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the undervoltage protection trips.
74
3.1.5 Logic diagram

VoltProtFcnOn
Uab<“UVStage1VoltSet”
≥1
& &
Ubc<“UVStage1VoltSet”
UVStage1Startup
Uca<“UVStage1VoltSet”
“UVChk1Ph”=1
≥1
“UVChk1Ph”=0
Uab<“UVStage1VoltSet”
&
&
Ubc<“UVStage1VoltSet”
Uca<“UVStage1VoltSet”
“UVStage1On”=1
UVStage1Startup
BI blocking

≥1
“UVChkCBState”=1 &
T1
UVStage1Trip
“UVChkCBState”=0
max(Ia,Ib,Ic)>“UVCurrSet” &
≥1
&
“UVChkCurrOn”=1
“UVChkCurrOn”=0
VTFailBlk
Uab<“1.732×3PhUVBlkSet”
&
Ubc<“1.732×3PhUVBlkSet”
Uca<“1.732×3PhUVBlkSet”
T1：“UVStage1Time”
Figure 24 Low current protection logic diagram
3.2 Setting list

Table 51 Settings of undervoltage protection
Default
value
1 UVStage1VoltSet 5.00～150 100 0.01 V
0.00～
2 UVStage1Time 120 0.01 s
120.0
0: Definite time
1: A-1;P-1;B-0
3 UVStage1CurveSel 0～4 0 1 2: A-40;P-2;B-1
3: A-5;P-2;B-2
4: User defined
0.001～
4 InvTimeUVStage1CoefA 10 0.001
1000
75
Default
value
0.01～
5 InvTimeUVStage1IndexP 10 0.01
10.00
0.000～
6 InvTimeUVStage1TimeB 100 0.01
100.00
0.025～
7 InvTimeUVStage1ConstT 0.025 0.001
1.5
0.00～
120.0
0: Definite time
1: A-1;P-1;B-0
3: A-5;P-2;B-2
4: User defined
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
0.00～
120.0
0: Definite time
1: A-1;P-1;B-0
3: A-5;P-2;B-2
4: User defined
0.001～
1000
0.01～
10.00
0.000～
100.00
0.025～
1.5
0.00～
120.0
0: Definite time
1: A-1;P-1;B-0
3: A-5;P-2;B-2
4: User defined
0.001～
1000
0.01～
10.00
0.000～
100.00
76
Default
value
0.025～
1.5
0.100～
29 InvTimeUVMinTime 0.1 0.01 s
100.00
0.04In～
30 UVCurrSet 10 0.01 A
40In
31 UVStage1DropoffCoef 1.0～2.00 1.02 0.01
35 3PhUVBlkSet 0-40 2 0.01 V
Table 52 Undervoltage protection logic switch

Number Remark
1-Enable undervoltage stage 1;
1 UVStage1On 1/0 0
0-Disable undervoltage stage 1
2 UVStage2On 1/0 0
3 UVStage3On 1/0 0
4 UVStage4On 1/0 0
1-undervoltage check CB state on;
5 UVChkCBState 1/0 0
0-undervoltage check CB state off
1- undervoltage check phase 1 voltage;
6 UVChk1Ph 1/0 0
0- undervoltage check phase 3 voltage
7 UVChkCurrOn 1/0 0 1-check current on; 0-check current off
3.3 Report list


Trip report:
1 UVStage1Trip /
2 UVStage2Trip /
3 UVStage3Trip /
4 UVStage4Trip /
77

Table 54 Undervoltage protection technical data

≤ ±2.5% times of setting or
Accessed voltage Phase-to-phase voltage
±1V
Phase-to-phase voltage ≤ ±2.5% times of setting or
10V～150V
setting ±1V
Dropoff coefficient 1.00～1.05 ≤ ±3% setting
Time setting 0.00s～120.00s +60ms, when trip value is set
at 80% of setting
Reset time ≤50ms
Phase-to-phase voltage ≤ ±2.5% times of setting or
10V～150V
setting ±1V
In the case of
0.05 < U / Uset<0.5 , the
IEC60255-127
allowable trip time error is: ±
5% or +60 ms
 
  ≤ ±5% setting or +60ms,
A
User defined curve =t  + B  ⋅T when 0.05 < U / Uset<0.5 , it
  U P  meets IEC60255-151
1 −    standard
 Uset  
0.001～1000
time A
Time delay of inverse time
0.000～100.00
B
78
Chapter 11 Thermal overload protection (49)
Chapter 11 Thermal overload

protection (49)
About this chapter

This chapter describes the thermal overload protection
79
1 Overview
Thermal overload protection protects the device against overheating
caused by overload. Overheating can affect insulation characteristics of
insulation material between transformers, lines and other electrical
equipment. In fact, if the device temperature exceeds the allowable
operating temperature, the insulation material will accelerate aging.
Therefore, special protection should be provided to prevent the protected
equipment from excessive temperature. Since the temperature is
proportional to the square of the current, the thermal overload protection is
based on the square of the measured current flowing through the
protected device. In addition, due to the cumulative effect of over
temperature, the thermal overload protection needs to consider the
historical thermal effect of the device. The device realizes the above
functions by providing a thermal model of the simulated protected device.
In this way, the thermal overload protection of the device has the ability of
memory, which can consider the historical overload and heat loss.
parallel.

The input and output signals of thermal overload protection function
diagram are shown as follow:
Thermal Overload Protection
1 1
ENA_TOL Start
2
Act1
3
Act2
4
Act3
Figure 25 The input and output signals of thermal overload protection function
diagram
right.

Output:
Start IED startup
When the thermal overload is accumulated
Act1
Thermol to RatioAct1, the alarm is sent.
When the thermal overload is accumulated
Act2
to RatioAct2, the alarm is sent.
When the thermal overlaod is accumulated
Act3
to 100%, the trip is sent.
ENA Input:
80

The total connector of thermal overload
ENA_TOL protection, the corresponding hard
connector is ENA_TOL_5.
The device provides 1 stage thermal overload trip stage and stage 2
thermal overload alarm stage. The alarm stage needs to adjust the alarm
coefficient of thermal overload, which means that the value of the alarm
stage trip setting is the product of the setting of the trip stage and the
overload alarm coefficient. The thermal overload protection function is
realized by a temperature model equivalent to the protected device.
Temperature model (low temperature curve or high temperature curve) is
selected from IEC60255-8 standard. Temperature model can be used to
calculate the temperature rise of each phase current. The maximum
temperature rise calculated from the three-phase current is the trip value of
thermal overload protection.

The temperature rise of each phase is calculated by the following formula:
dΘ I
τ + Θ = ( )2
dτ Iϑ
In which, τ is "ThermalTimeConst", and s is the unit; Iθ is

"ThermalOLCurrSet" that is the maximum permissible continuous thermal
overload current, Θ is the temperature rise of unit per unit time under
maximum allowable thermal overload current, I is the fundamental current
that is measured through the phases of the protected device.
Based on the difference model, the calculation formula of overload trip
time:
 I 2  I 2 
   −  P  
 I 
τ = τ ln   ϑ  2 ϑ  
I
  I  − 1 
  I ϑ  
 
Where IP is the stable current before the overload, the formula is the heat
curve in the IEC60255-8 specification, and the trip time is calculated
according to the cold curve is as follow:
  I 2 
   
  Iϑ  
τ = τ ln  2 
  I  − 1
  I ϑ  
 
Thermal overload protection can reflect the current fundamental wave or RMS
value trip, which are divided into stage 1 trip and stage 2 alarm, when𝐼 >
“ThermalOLCurrSet” , over heat protection starts, take stage 1 alarm for
81
example, when the thermal overload percentage reaches

"ThermalOLAlmCoef1", the report "ThermalOLStg1Alm" is sent out; when the
thermal load percentage reaches 100%, the report "ThermalOLTrip" is sent
out. LED, IED output and others can be configured by AESP after the
alarm or trip report is issued.
While alarming or tripping, three-phase current value Ia, Ib, Ic of trip moment
and each phase of trip moment are sent out.
Three phase thermal accumulative percentage is sent out timely by
TermalA, TermalB, and TermalC in the case of overheating protection.
The shutdown load current is 0, and the time coefficient of the equipment in
the process of heat dissipation is the product of "ThermalOLCoolCoef" and
“ThermalTimeConst".
3.2 Setting list

Table 56 Thermal overload protection setting
Default
value
0.05In～
1 ThermalOLCurrSet 40 0.01 A
40In
2 ThermalTimeConst 6～9999 60 0.01 s
3 ThermalOLCoolingCoef 0.1～10 10 0.01
4 ThermalOLAlarmCoef1 0.5～1 1 0.01
5 ThermalOLAlarmCoef2 0.5～1 1 0.01
Table 57 Thermal overload logic switch

Number Remark
Enabled or disabled thermal
1 ThermalOLOn 1/0 0
overload
Enabled and disabled
2 ThermalOLAlarm1On 1/0 0 thermal overload alarm
stage
Enabled and disabled
3 ThermalOLAlarm2On 1/0 0 thermal overload alarm
stage
4 ThermalCurve 1/0 0 1: hot curve; 0: cool curve
3.3 Report list


Trip report:
Thermal overload protection
1 ThermalOLTrip
issues trip command
Alarm report:
1 ThermalOLStage1Alarm
sends off alarm 1 command
2 ThermalOLStage2Alarm
sends off alarm 2 command
82

Table 59 Thermal overload protection technical data

Current setting 0.05In～40.00In
±0.02In
6s～9999s
thermal time constant
Cooling coefficient of thermal
0.1～10
overload
 I eq2  IEC 60255–8,
IEC low temperature curve τ = τ ln  2 2 
 I eq − I θ  +40ms,
 I eq2 − I P2  IEC 60255–8,

IEC high temperature curve τ = τ ln  2 2
 I eq − I θ  +40ms,
83
Chapter 12 Power protection (32F)
About this chapter

This chapter describes the power protection principle, input
and output signals, setting parameter, IED report and
technical data.
85
1 Overview
Generally, the power direction of generator is from generator to bus bar.
However, as long as generator losses excitation or something
dysfunctional, generator is like to operate with motor, which means that the
generator will absorb from system, or inverse power. Inverse protection
plays a role in preventing blade damage caused from overheated turbine
as the steam turbine suddenly shutdowns and shifts to operate with motor.
Power direction protection, over power stage 2, power direction can select
positive or opposite direction through logic switch.
parallel.

Power protection function input and output signals are shown as follow:
Directional power/reverse power protection

1 1
BIBlk Start
2 2
ENA_POWER Operation
Figure 26 The input and output signal diagram of power protection function
right.

Input:
BIBlk BI blocking
OP Output:
Start IED startup
Input:
ENA The total connector of thermal
ENA_POWER overload protection, the corresponding
hard connector is ENA_POWER_5.
Stage 1 power protection will be taken as an example.

When the logic switch "OutgoLineRvsPowerStage1On" is 1, it can judges
that the incoming line is under inverse power.
86
𝑃 < 0 and |𝑃| > “PowerProtStage1PowerSet”

When the logic switch "OutgoLineRvsPowerStage1On" is 0, it can judges
that the outgoing line is under inverse power.
𝑃 > 0 and |𝑃| > “PowerProtStage1PowerSet”
When power protection function is enabled and no BI blocking, if
"PowerProtStage1On"=1, then the power protection is enabled.
if VT failure or CT failure occurs, the power protection will be blocked.
After starting power protection, and BI blocking is zero, the time delay
capacitor will be on. If the requirements of trip are met,start timing
components until "PowerProStage1Trip" is on. LED and output can be
configured by AESP.
As the trip signal is output, the power value at the time of outputting is P
(absolute value).
Power<0
&
“OutgoLineRvsPowerStage1On”=1
≥1
Absolute value of &
power>“PowerProtStage1PowerSet” T1
PowerProtStage1Trip
&
“OutgoLineRvsPowerStage1On”=0
Power>0
BI blocking
≥1
InstantVTFail
CTFail
power protection function is enabled
“PowerProtStage1On”=1
T1：“PowerProtStage1Time”
Figure 27 Power protection function logic diagram
3.2 Setting list

Table 61 Power protection setting
Default
value
1 PowerProtStage1PowerSet 0～500 500 0.01 W
2 PowerProtStage1Time 0～100 100 0.01 s
3 PowerProtStage2PowerSet 0～500 500 0.01 W
4 PowerProtStage2Time 0～100 100 0.01 s
Table 62 Power protection logic switch

Setting Default
Number Logic switch description Remark
Mode value
1 PowerProtStage1On 1/0 0 1: On, 0: Off
87
Setting Default
Mode value
2 OutgoLineRvsPowerStage1On 1/0 0 1: On, 0: Off
3 PowerProtStage2On 1/0 0 1: On, 0: Off
4 OutgoLineRvsPowerStage2On 1/0 0 1: On, 0: Off
3.3 Report list


Trip report:
1 PowerProtStage1Trip /
2 PowerProtStage2Trip /

Table 64 Power protection technical parameter

Power characteristics
Allowable error of power trip value: ±3%
Power setting 0W～500W
or ±0.5 Pn;
Reset time Less than 55 ms
88
Chapter 13 Circuit breaker failure protection (50BF)
Chapter 13 Circuit breaker failure

protection (50BF)
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
circuit breaker failure protection function.
89
1 Overview
Circuit breaker fault protection can detect the operation of circuit breaker
during the fault isolation. This protection can isolate the fault by tripping the
circuit breaker of corresponding bus bars as fast backup protection. Once
there is a circuit breaker failure on feeder or transformer, the connected
busbar can be isolated from the power grid by circuit breaker failure
protection. In addition, the device sends out a trip command to the
protection of other end of the feeder. In the event of a circuit breaker failure
with a busbar fault, IED sends the trip command to the opposite of the
feeder.
In order to improve the reliability of circuit breaker failure protection, the
current criterion is added. Three phase current, zero sequence current and
negative sequence current are available.
In order to avoid the other around circuit breaker trip caused by the error of
judgment, circuit breaker failure protection can be set to issue a trip
command to the local circuit breaker once again.
Circuit breaker failure protection has the characteristics as below:
1) 2 trip stages (local circuit breaker retrip and trip the busbar);
2) Transfer trip command to the remote line end in stage 2;
3) Internal/ external initiation;
4) Three-phase initiating circuit breaker failure;
5) Breaker auxiliary contact check;
6) Current criteria (including phase-to-earth current, zero and negative
sequence currents).
soft-hard parallel.

Circuit breaker failure protection function input and output signal diagram
is shown as follow:
Circuit-Breaker Failure Protection

1
BIBlk
2 1
CBOpen CBF_Init
3 2
CBClose BIAlarm
4 3
CBClose3P Trip1
5 4
BIInitCBFDZ Trip2
6
CBFail
7
TrInit3P
8
ENA_CBF
Figure 28 Circuit breaker failure protection function input and output signal diagram
90
right.

Input:
BinaryInput
CBClose Circuit breaker close position
BIInitCBFDZ External BI Initiation CBF
Input:
BIBlk BI blocking
Circuit breaker failure Spring
CBFail
discharge binary input
TrInit3P Internal initiating failure signal
CBF_3Trip Output:
CBF_Init Circuit breaker failure startup signal
Circuit breaker failure binary input is
BIAlarm
abnormal
Trip1 Failure I stage trip
Trip2 Failure II stage trip
Input:
ENA The total connector of circuit breaker
ENA_CBF failure protection, the corresponding
hard connector is ENA_CBF_5.
3.1 Protection function
Circuit breaker failure protection can be enabled or disabled by setting the
logic switch In the case of the protection function is enabled, the protection
function trips, the relevant protection function start failure protection, and the
timing of the counter works until to setting time delay, and the time delay is set
to“CBFTime1". If the circuit breaker is not switched off after the setting time,
the circuit breaker failure protection sends off the trip order to trip the
circuit breaker (e.g., through a second two trip coil). If the circuit breaker
has no response when the other time delay "CBFTime2", then IED will
send off trip command to trip the corresponding circuit breakers to isolate
the fault (e.g. other circuit breakers on the same busbar connected with
the failure circuit breaker). LED and output can be configured by AESP.
The internal and external protection function can both start circuit breaker
failure protection. If the external initiating circuit breaker failure is enabled,
then "3PhCBFStartup" needs to be configurated. The startup of circuit
breaker failure protection and disturbance and fault record of trip need
engineering configuration.
Circuit breaker failure detection includes two criteria. The first criterion is
detecting the disappeared current after issuing the trip command. The
second criterion is detecting the auxiliary contacts of circuit breaker.
3.1.1 Current detection
When the current is disappeared, then the circuit breaker is considered to
91
be on the open position. So the first criterion (current criterion) is the most
effective way to detect the position of circuit breaker. The current check is
used to detect the circuit breaker position in circuit breaker failure
protection. At this time, the current measurement of each phase compares
with the setting of 'I_Circuit breaker failure'. Besides, the zero sequence
(3İ0 = İA + İB + İC ) or negative sequence (I2=IA+a2IB+aIC) current can
also be used as current criteria by setting the logic switch. If the IED is set
to detect zero and negative sequence currents, then the zero and negative
currents should be compared with the corresponding settings respectively.
Breaker current detection logic diagram is shown as follow:
&
Ia >“CBFCurrSet”
Calc3I0 >“CBF3I0Set” ≥1
&
≥1 &
3I2 > “CBF3I2Set”
Ib >“CBFCurrSet”
Ic >“CBFCurrSet”
“CBFChk3I0/3I2”=1
&
Calc3I0 >“CBF3I0Set” ≥1 ≥1
& CBF current criterion
≥1 & three-phase has live current
&
Calc3I0 >“CBF3I0Set” ≥1
&
≥1 &
Figure 29 Logic diagram of circuit breaker current detection
3.1.2 Breaker auxiliary contact detection

The IED trip logic does not take the current component as the criterion and
the current criterion is not suitable for CBF protection. Circuit breaker
auxiliary contact position can be used to judge whether the circuit breaker
trips or not. If set logic switch "CBFChkPosn" is 1, criterion for auxiliary
contact of circuit breaker will be enabled. If the current criterion is not used in
the IED, then circuit breaker auxiliary contact criterion is used to judge
circuit breaker position. In the delay of circuit breaker failure protection,
once the current criterion starts and the identified current disappears, even
if the auxiliary contact of the circuit breaker does not identify that the circuit
breaker has been disconnected, the protection also considers that the
circuit breaker is disconnected. More reliable current criteria have higher
priority to avoid signal errors caused by auxiliary contact mechanism or
circuit failures.
92
The criterion of circuit breaker auxiliary contact is as follow:

Circuit breaker trip position
Circuit breaker close position &

3PhCBClosePosn
&
Internal or external three-phase initiating failure
CBF current criterion three-phase ≥1

has live current
&
≥1
“CBFChkCBAndPhaseI”=0
Figure 30 Breaker auxiliary contact judgment logic diagram
3.1.3 Circuit breaker failure protection trip logic diagram

1) The internal and external initiating logic is shown as follow:
Circuit breaker failure
binary input is abnormal
External initiating T_alarm &
failure signal
≥1
Three-phase initiating
Internal initiating circuit breaker failure
failure signal
Figure 31 Logic diagram of internal and external initiating circuit breaker failure
2) Initiating circuit breaker failure logic diagram is shown as follow:
“CBFChkCBAndPhaseI”=1 &
&
“CBFChkPosn” &
≥1
3PhCBClosePosn
≥1
CBF current criterion
three-phase has live current &
&
3PhInitCBF 3PhCBFStartup
Figure 32 Logic diagram of initiating circuit breaker failure

3) CBF state 1 trip logic diagram is shown as follow:
T1
3PhCBFStartup CBFStage1Trip
T1：“CBFTime1”
Figure 33 Logic diagram of CBF stage 1 trip
93
4) CBF stage 2 trip logic diagram is shown as follow:

T2
3PhCBFStartup
≥1
CBFStage2Trip
&
0
CBFail input
T2：“CBFTime2”
Figure 34 Logic diagram of CBF stage 2 trip
3.2 Setting list

Table 66 The setting of circuit breaker failure protection
Default
value
1 CBFCurrSet 0.05In～40In 40 0.01 A
Three times of
2 CBF3I0Set 0.05In～40In 40 0.01 A zero sequence
current
Three times of
negative
3 CBF3I2Set 0.05In～40In 40 0.01 A
sequence
current
4 CBFTime1 0.00～100.00 100 0.01 s
5 CBFTime2 0.00～100.00 100 0.01 s
6 CBF BIAlarmTime 0.00～100.00 100 0.01 s
Table 67 Circuit breaker failure logic switch

Number Remark
Enable/disable circuit breaker
1 CBFOn 1/0 0
failure protection
Circuit breaker failure checks zero
2 CBFChk3I0/3I2 1/0 0 and negative sequence
current/disable
Enable/disable circuit breaker
3 CBFChkPosn 1/0 0
failure check open position
0: check switch position or
current ; 1: check switch position
or current
4 CBFChkCBAndPhaseI 1/0 0
The check current here is the
criterion of checking failure and
condition of three-phase current.
3.3 Report list


Trip report:
1 IntrInitCBF /
2 ExtrInitCBF /
3 CBFStage1Trip /
94

4 CBFStage2Trip /
Alarm report:
1 CBF BIErr /

Table 69 Circuit breaker failure protection technical data

Current setting
Setting of negative sequence
current 0.05In～40.00In
±0.02In
Zero sequence current
setting
Time 1 of circuit breaker
0.00s～100.00s ≤ ± 1% times of setting or
failure
+40s, when trip current is set
Time 2 of circuit breaker
0.00s～100.00s as 200% setting
failure
Reset time Less than 20 ms
95
Chapter 14 Dead zone protection (50DZ)
Chapter 14 Dead zone protection

(50DZ)
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
dead zone protection.
97
1 Overview
IED provides dead zone protection to detect dead zone fault, i.e. when
circuit breaker is in open position, a fault occurs between CT and circuit
breaker. So, when circuit breaker auxiliary contact shows that the circuit
breaker is in open position, IED can detect fault current of dead zone.
parallel.
For busbar side CT, when dead zone fault occurs, IED trips all circuit breakers
on the busbar where the fault bay is located. Trip logic is shown as follow:
Trip
Busbar
IFAULT
Line
Line 1 Line 2
N
Example:
CB open position
CB close position
Figure 35 Busbar side trip logic diagram

For line side CT, when dead zone fault occurs, IED sends remote trip
command to the other IED which located on the opposite side. Trip logic is
shown as follow:
98
Internal
trip Busbar
IFAULT
Line
Line 2 Line N
1
Trip
Device
Example:
CB open position
CB closse position
Figure 36 Line side trip logic diagram

The input and output signals of dead zone protection function diagram are
shown as follow:
Dead Zone Protection

1 1
BIBlk Start
2 2
CBOpen Operation
3 3
CBClose Alarm
4
BI_InitCBFDZ
5
SigIntDZ
6
ENA_DZ
Figure 37 The input and output signals of dead zone protection function diagram
right.

Input:
BinaryInput
BI_InitCBFDZ External initiating dead zone BI
Input:
DZ BIBlk BI blocking
SigIntDZ Internal startup dead zone
99

Output:
Start IED startup
Alarm Abnormal alarm of external BI
Input:
ENA The total connector of dead zone
ENA_DZ protection, the corresponding hard
connector is ENA_DZ_5.
When dead zone protection function is enabled (En=1) and binary input
blocking is disabled, if "DZProtOn"=1, then the corresponding dead zone
protection is enabled.
The trip conditions are shown as follow:
1) Trip initiates dead zone protection sign is 1, or external BI initiates
dead zone is 1 and no abnormal alarm of external BI;
2) There should be open position but no close position;
3) I∅ > “DZCurrSet”, (∅ = a, b, c)；
4) Enabled or disabled the criterion of zero current and negative sequence
current by setting the logic switch "DZChk3I0/3I2". If the logic switch is set
as 1, the zero or negative sequence current is also necessary to be
greater than the corresponding setting.
If the trip conditions are met, time component starts, when time is over,
"DZTrip" is issued. LED and output can be configured by AESP. At the
same time, the fundamental current values Ia, Ib, Ic, zero and negative
sequence current of trip time are output. When current or circuit breaker
position is not satisfied, timing component returns, dead zone protection
resets. When the existing time of external BI initiating dead zone is greater
than the alarm time settings, "DZBIErrAlarm”will be issued. LED and
output can be configured by AESP.
100
&
DeadZoneProtectCheckZ&NSC=0
Ia>DeadZoneCurrSetting
Ib>DeadZoneCurrSetting
& ≥1
≥1 &
Ic>DeadZoneCurrSetting
3I0>DeadZoneProtectZSCurrSet
3I2>DeadZoneProtectNSCSetting
DeadZoneProtectCheckZ&NSC=0 &
& ≥1 ≥1
≥1 & Dean Zone Current
Ia>DeadZoneCurrSetting is satisfied
DeadZoneProtectCheckZ&NSC=0 &
& ≥1
≥1 &
Ia>DeadZoneCurrSetting
DeadZone Protection On
BI Blocking
Dean Zone Current is satisfied

&
&
3 phase trip T
Deadzone Protection
Protection startup dead zone ≥1
&
T_BIEr
ExternalStartupDeadZoneBI r
DeadZoneBIAbnormalAlarm
DeadZoneProtectionOn=1
T：“DeadZoneTimeSetting”
T_BIErr：“BIErrAlarmTimeSetting”
Figure 38 Dead zone logic diagram
101
3.2 Setting list

Table 71 Dead zone protection setting
Default
value
1 DZCurrSet 0.05In～40In 40 0.01 A
2 DZTime 0～100 100 0.01 s
Three times of
3 DZProt3I0Set 0.05In～40In 40 0.01 A zero sequence
current
Three times of
4 DZProt3I2Set 0.05In～40In 40 0.01 A negative
sequence current
5 BIErrAlarmTime 0.00～100 100 0.01 s
Table 72 Dead zone logic switch

Number Remark
1 DZProtOn 1/0 0
2 DZChk3I0/3I2 1/0 0
3.3 Report list


Trip report:
1 DZTrip /
Alarm report:
1 DZ BIErrAlarm /

Table 74 Dead zone protection technical data

±0.02In
Time setting 0.00s～100.00s when trip current is set as
200% setting
102
Chapter 15 Stub protection (50STUB)
About this chapter

This chapter describes the protection principle, the input and
output signals, setting parameters, messages and technical
parameters for stub protection.
103
1 Overview
The stub protection protects the zone between the CTs and the open
isoloator. The stub protection is enabled when the open position of the
dis-connector is informed to the IED through connected binary input.
The function is equipped with stage 1 time limit settings.
parallel.

Stub protection function input and output signals are shown as follow:
STUB-Bus Overcurrent Stage

1 1
DSOpen Start
2 2
BIBlk Operation
3
ENA_STUB
Figure 39 The input and output signals of stub protection function diagram
right.

Input:
BinaryInput
DSOpen Isolation position signal input
Input:
BIBlk BI blocking
STUB Output:
Start IED startup
Input:
ENA The total connector of stub
ENA_STUB protection, the corresponding hard
connector is ENA_STUB_5.
104
The stub protection is an overcurrent protection which is only in service if
the status of the line isolator indicates the open condition. Stub protection
is disabled while the isolator is at the close position. The stub protection
provides definite time stage with changeable time delay. CBF protection
can be enabled or disabled by setting the logic switch. Corresponding
current setting can be inserted in setting. When the current is greater than
the setting and the time delay is over, the IED sends out "StubTrip". LED
and output can be configured by AESP.
Ia>“StubCurrSet”
≥1
Ib>“StubCurrSet”
Ic>“StubCurrSet”
&
Isolator open T
StubTrip
BI blocking
“StubOn”=1
Enable stub protection function
T：“StubTime”
Figure 40 Stub protection function logic

Logic diagram of application scenarios:
Bus line A
CB1
STUB-Bus
CT1 Overcurrent fault
Line1
Switch1
CB3
CT3
Line2
Switch2
CT2
CB2
Bus line B
Figure 41 3/2 Connection mode Stub protection
105
3.2 Setting list

Table 76 Setting of stub protection
Default
value
Current setting of
1 StubCurrSet 0.05In～40In 40 0.01 A
stub protection
Time of stub
2 StubTime 0～100 100 0.01 s
protection
Table 77 ProtBinSet
Number Remark
1 StubOn 0，1 0 0: disable; 1: enable
3.3 Report list


Trip report:
1 StubTrip /

Table 79 Stub protection technical parameters

±0.02In
≤ ±1% setting or +40ms, when trip
106
Chapter 16 Broken conductor protection (46BC)
Chapter 16 Broken conductor

protection (46BC)
About this chapter

parameters for disconnection protection.
107
1 Overview
The system will monitor the volume of load in real time.
This protection function has the following characteristics:
1) Be able to test the negative sequence current
2) Detect the ratio of negative and positive sequence current
soft-hard parallel.

Input and output signals of broken conductor protection are shown as
follow:
Broken Conductor
1 1
BIBlk Start
2 2
CBOpen Operation
3 3
ENA_BC Alarm
Figure 42 The input and output signals of broken conductor protection function
diagram
right.
Input:
BinaryInput
Input:
BIBlk BI blocking
Output:
BC
Start IED startup
Alarm IED alarm
Input:
ENA The total connector of broken conductor
ENA_BC protection, the corresponding hard
connector is ENA_BC_5.
108
The logic diagram of broken conductor protection is shown in as follow
figure:
Enable failure protection function
&
BI blocking

≥1
“BrokenConductorChkCBPosn”=1
&
T
“BrokenConductorChkCBPosn”=0 BrokenConductorTrip
3I2>“BrokenConductor3I2Set” &
“BrokenConductorChk3I2”=1 ≥1
“BrokenConductorChk3I2”=0 &
3I2>3I1×“I2/I1Coef”
“BrokenConductorOn”=1
“BrokenConductorTripOn”=1
T：“BrokenConductorTime”
Figure 43 Broken conductor protection logic diagram

Where:
f3I1:secondary side positive sequence current value
f3I2:secondary side negative sequence current value
I2_Set:“BrokenConductor3I2Set”;
I2_I1_Set: "I1/I2Coef";
Tset: “BrokenConductorTime”
After IED outputs "BrokenConductorTrip", LED, IED output and others can be
configured by AESP.
If "BrokenConductorTripOn" is 0, after IED outputs "BrokenConductorAlarm",
LED, IED output and others can be configured by AESP.
3.2 Setting list

Table 81 Broken conductor protection setting
Default
value
Three times of
0.05In～
1 BrokenConductor3I2Set 40 0.01 A negative
40In
sequence current
2 I2/I1Coef 0.2～1 1 0.01
3 BrokenConductorTime 0～100 100 0.01 s
109
Table 82 Broken conductor protection logic switch

Setting Default
Mode value
1 BrokenConductorOn 1/0 0 0: disable; 1: enable
2 BrokenConductorTripOn 1/0 0 1: trip; 0: alarm
1: test the negative
sequence current
3 BrokenConductorChk3I2 1/0 0
0: test positive sequence
ratio value
0: non-check circuit breaker
position
4 BrokenConductorChkCBPosn 1/0 0
1: check circuit breaker
position
3.3 Report list


Trip report:
1 BrokenConductorTrip /
2 BrokenConductorAlarm /

Table 84 Technical parameters

±0.02In
≤ ±1% setting or +40ms, when trip
110
Chapter 17 Overexcitation protection (24)
Chapter 17 Overexcitation protection

(24)
About this chapter

parameters for overexcitation protection.
111
1. Overview
The overexcitation protection is used to detect impermissible
overexcitation conditions which can endanger power transformers. The
saturation of the iron core and large eddy current losses led by the
situation that the transformer flux exceeds the related values can cause
impermissible temperature rise in transformer core.
This protection function has the following characteristics:
1) The alarm or trip of the three stages of definite time can be selected
respectively, the alarm or trip of one stage of inverse time can be selected
respectively.
2) Adopt phase-to-phase voltage
soft-hard parallel.
2. Function module description

The input and output signals of overexcitation protection function are
shown as follow:
Overexcitation Protection
1 1
BIBlk bDefStart
2 2
ENA_OE bDefAlarm
3
bDefOp
4
bInvStart
5
bInvAlarm
6
bInvOp
Figure 44 The input and output signals of overexcitation protection function diagram
right.

Input:
BIBlk BI blocking
Output:
bDefStart Definite time startup
bDefAlarm Definite time Alarm
OFlux bDefOp Definite time trip
Inverse time startup (used only to
bInvStart configure the number of inverse time
stages)
Inverse time alarm (used only to configure
bInvAlarm
the number of inverse time stages)
Inverse time trip (used only to configure
bInvOp
the number of inverse time stages)
112

Input:
ENA The total connector of over excitation
ENA_OE protection, the corresponding hard
connector is ENA_OE_5.
3. Detailed description
When the load is disconnected from the system and the voltage regulator
cannot control the voltage rise quickly, overexcitation may occur. Similarly,
the overexcitation condition may occur as result of a decrease in frequency,
e.g. in island system. To protect the power transformer in such conditions,
the overexcitation protection function should pick up when the permissible
limit of flux is exceeded in the transformer core. To do so, the
overexcitation protection function measures the voltage/frequency (U/f)
ratio which is proportional to the flux density B in transformer core,
compared with rated magnetic flux density BN. The decision is then made
based on the calculated ratio as is shown in as follow equation.
B U f
N = =
BN UN f N
Where:
N is the ratio of voltage to frequency calculated by the device.
U and f are the measured voltage and frequency
UN and fN are the rated voltage and frequency of the device.
While the rated frequency is fixed to 50Hz or 60Hz in software, device is
informed about rated voltage by setting “ReferenceVolt” which corresponds to
nominal phase-neutral voltage of the protected transformer when is
transferred to secondary value, using the turn ratio of voltage transformer.
Thus, the use of the overexcitation protection presumes that measured
voltage is connected to the device. The calculation of the above
voltage/frequency is based on the maximum voltage of the phase to
phase voltage.
The overexcitation protection includes two definite characteristics (alarm and
trip) and one thermal characteristic. The latter characteristic provides an
approximate replica of the temperature rise caused by overexcitation in the
protected object. The definite alarm stage can be enabled or disabled by
using logic switch "DefTimeOEStage1On". Thermal characteristic can be
enabled or disabled by "InvTimeOExcitOn". It should be mentioned that
the overexcitation protection can be applied at HV, MV or LV side of the
protected transformer. However, it is not recommended to apply the
function on the transformer side with variable winding turns such as the
transformer side with an installed tap changer.
Take protection stage 1 as an example, if the definite time alarm is enabled,
and the calculated volt/hertz ration exceeds the setting, then a report
“DefTimeOEStage1Alarm” will be sent by the device after the time delay
setting. Similarly, if the trip definite time is enabled, and the calculated
volt/hertz ration exceeds the setting, a report “DefTimeOEStage1Trip” will
be sent by the device after the time delay expiration. LED, IED output and
113
others can be configured by AESP.

If thermal characteristic is set to “1-on” in one of transformer sides, it uses
the measured voltage and frequency of the corresponding side (depending
on the setting applied at Control word “V/F Voltage (0-VPP,1-VPN)”),
together with ten points derived from the manufacturer data. The
corresponding trip time parallels to the ratio of voltage / frequency.
Intermediate values are determined by performing linear interpolation by
the device. The overexcitation 1 stage factor can be set to 1.05, and the
rest stages increases by differential 0.05. Ratio range is
1.05~1.70(“InvTimeOEStage14Time”,1.70)The inverse times are set as below:
"InverseTimeOEStage1Time", "InverseTimeOEStage2Time",
"InverseTimeOEStage13Time", "InverseTimeOEStage14Time". These points
are used to draw the inverse time characteristic curve, as shown in the
following figure:
u/f
V/F(T14)
V/F( T13)
V/F( T12)
V/F( T11)
V/F( T10)
V/F( T9)
V/F( T8)
V/F( T7)
V/F( T6)
V/F( T5)
V/F( T4)
V/F( T3)
V/F( T2)
V/F(T1)
T 14 T 13 T 12 T 11 T 10 T 9 T8 T7 T6 T5 T4 T3 T2 T1
t( s)
Figure 45 Overexcitation characteristics
It can be observed from the above picture that N=1.05, which is the
starting threshold of thermal characteristics stage; the calculated ratio of
voltage to frequency exceeds the starting threshold and the thermal model
increases from 0% to 100% through the counter in the device. If the
counter reaches to 100%, then IED trips. When the voltage / frequency
ratio is lower than the start threshold, the trip signal will be canceled.
According to the transformer cooling time, the counter will be reduced to
zero (thermal model counter is from 100% to 0%). The cooling time is set
as "OECoolingTime".
Inverse time limit characteristics is up to 14 points, may be less than 14
114
points. If the time delay setting of T1-T3 are set as 9999 seconds, then the
inverse time characteristic from the setting stage to stage T14 will be
disabled.
3.2 Setting list

Table 86 Overexcitation protection setting
Default
Number Setting Range Step Unit Description
value
1 DefTimeOEStage1TripSet 1～1.4 1.1 0.01
0～
2 DefTimeOEStage1Time 100 0.01 s
9999
3 DefTimeOEStage2TripSet 1～1.4 1.1 0.01
0～
9999
5 DefTimeOE3TripSet 1～1.4 1.1 0.01
0～
9999
0～ Voltage frequency
7 VoltFreqT1Time 10 0.01 s
9999 T1 time
9999 T2 time
9999 T3 time
9999 T4 time
9999 T5 time
9999 T6 time
9999 T7 time
9999 T8 time
9999 T9 time
9999 T10 time
9999 T11 time
9999 T12 time
9999 T13 time
9999 T14 time
0.1～ Cooling time of
21 OECoolingTime 25 0.01 s
9999 overexcitation
0.95～
22 OEDropoffCoef 1.0 0.01
1.0
Rated value of
10～
23 OERatedVoltVal 57.74 0.01 V phase-to-phase
120 voltage
0.0～
24 DefTimeOERstTime 0.04 0.01 s
3.00
115
Default
Number Setting Range Step Unit Description
value
0.0～
25 InvTimeOERstTime 0.04 0.01 s
3.00
Table 87 Overflux protection logic switch
Number Remark
Enable the definite time stage 1
1 DefTimeOEStage1On 1/0 0
1-Enable, 0-Disable
Enable definite time stage 1
2 DefTimeOEStage1Alarm 1/0 0 alarm
1-alarm, 0-trip
1-Enable, 0-Disable
1-alarm, 0-trip
1-Enable, 0-Disable
1-alarm, 0-trip
Enable the inverse time
7 InvTimeOExcitOn 1/0 0
1-Enable, 0-Disable
Enable inverse time alarm
8 InvTimeOEAlarm 1/0 0
1-alarm, 0-trip
3.3 Report list


Trip report:
1 DefTimeOEStage1Trip /
4 InvTimeOETrip /
Alarm report:
1 DefTimeOEStage1Alarm /
4 InvTimeOEAlarm /
5 OEFrequcncyOverLmt /
116

Table 89 Overcurrent protection technical data

Reference voltage UN 10V～120V ≤ ±3% setting or ±1V
Time delay 0.1s～9999s ≤ ±5% setting or ±70ms
1.05/1.10/1.15/1.20/1.25/1.30/1.35
V/F characteristics ≤ ±5% setting or ±70ms
/1.40/1.45/1.50/1.55/1.60/1.65/1.7
Reset time about 70ms
Dropout ratio ≥0.96
Ratio: 1.00～1.40 ≤±2.5% setting or 0.01
≤±5% setting or ±70ms, under
time delay T 0.1s～9999s
the circumstance of twice trip
Reset time about 70ms
Dropout ratio ≥0.96
117
Chapter 18 Underfrequency protection (81UF)
Chapter 18 Underfrequency
protection (81UF)
About this chapter

output signals, setting parameters, reports and technical
parameters for underfrequency load shedding protection.
119
1 Overview
Infrequency and load shedding protection monitors the performance of
grid by testing the decreasing frequency. Underfrequency load shedding
will trip and certain load will be eliminated as the frequency is lower than
the setting of underfrequency load shedding protection or other conditions.
The main features of underfrequency load shedding protection are as
follow:
1) Undervoltage blocking
2) Frequency change rate (df/dt) blocking
3) Circuit breaker position check and loaded current blocking;
4) VT secondary circuit failure blocking;
There are four stages of underfrequency load shedding protection and
each stage can be enabled and disabled separately.
parallel.

The input and output signals of underfrequency load shedding protection
Under Frequency protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_UF
Figure 46 The input and output signals of underfrequency load shedding protection
diagram
right.

Input:
BinaryInput
Input:
BIBlk BI blocking
UF Output:
Start IED startup
ENA Input:
120

The total connector of underfrequency
ENA_UF protection,the corresponding hard
connector is ENA_UF_5.
3.1.1 Protection function introduction
The principle of underfrequency load shedding protection is "load shedding
by bay". Specifically, the principle means that each bay will be configured
with underfrequency load shedding protection rather than the incoming line
bay will be configured with underfrequency load shedding protection and
send off tripping command through outlet line bay. As a result, each bay
can be set to the appropriate frequency setting to make the protection start,
and the appropriate time setting to make the protection trip. Based on "the
principle of shedding in the line of bays", the device will be offered with 4
stages underfrequency load shedding protection. Each stage will be
enabled or disabled through corresponding plate and underfrequency
load shedding protection will be enabled and disabled by principal plate,
companying with each plate to enable and disable. Trip frequency of
underfrequency load shedding protection can be tested by input
phase-to-phase voltage. Take underfrequency load shedding stage 1 as
example, as the measured frequency is lower than settings
"UFLSStg1FreqSet", the timing component will start working; however, as
it delays to the definite time "UFLSStg1Time ", the IED will send out a
command "UFStg1Trip". LED and output can be configured by AESP.
As the trip frequency of underfrequency load shedding protection is
calculated by measuring voltage, underfrequency load shedding protection
will be blocked with meeting the following requirement.
1) When the lowest phase-to-phase voltage is lower than setting
"LSVoltBlkSet";
2) VT failure is detected by IED ;
3) When "UFLSChkCurrOn", check current meets the blocking condition.
Loaded current is lower than settings "LSCurrBlkSet". As voltage
transformer is configured at the side of power supply, it is useful to
detect current setting. As the circuit is blocking, "LSCurrBlkSet" refers
to as the smallest loaded current.
4) Circuit breaker is at open position. If it is in the same case, as voltage
detect current setting. Meanwhile, although the frequency is lower
than the underfrequency load shedding setting, the protection will not
send off trip command.
5) The frequency change rate (Δf/Δt) is greater than setting
"Df/dtBlkSet".
121
3.1.2 Logic diagram

Enable underfrequency protection
“GenlUFLSOn”=1
&
“UFStage1On”=1
Frequency<“UFLSStage1FreqSet”
Frequency<54Hz or Frequency>66Hz &
System frequency=60Hz ≥1
Frequency<45Hzor Frequency>55Hz &
System frequency=50Hz
VT failure blocking
≥1
Three-phase trip position
BI blocking
&
≥1 T1
max(Ia,Ib,Ic)<“LoadShedCurrBlkSet” & UFLSStage1Trip
“UFLSChkCurrOn”=1
≥1
min(Uab,Ubc,Uca)<“LoadShedVoltBlkSet”
absolute value of change Rate

of frequency >“Df/dtBlkSet” &
“UFLSChkDf/dt”=1
T1：“UFLSStage1Time”
Figure 47 Underfrequency load shedding stage 1 protection logic diagram
3.2 Setting list

Table 91 Settings of underfrequency load shedding protection
Default
value
The frequency is
greater than the
1 Df/dtBlkFreqSet 0.9Fn～1.0Fn 49.5 0.01 Hz
setting, slippage
locking returns
2 UFLSStage1FreqSet 0.9Fn～1.0Fn 49.5 0.01 Hz
3 UFLSStage1Time 0.00～100.00 100 0.01 s
5 UFLSStage2Time 0.00～100.00 100 0.01 s
7 UFLSStage3Time 0.00～100.00 100 0.01 s
9 UFLSStage4Time 0.00～100.00 100 0.01 s
10 Df/dtBlkSet 0.10～20.00 20 0.01 Hz/s
10.00～
11 LoadShedVoltBlkSet 120 0.01 V
120.00
12 LoadShedCurrBlkSet 0.05In～10In 10 0.01 A
122
Table 92 Logic switch of underfrequency load shedding

Number Remark
Enable or disable underfrequency
1 GenlUFLSOn 1/0 0
load shedding protection
2 UFStage1On 1/0 0
load shedding stage 1 protection
3 UFStage2On 1/0 0
4 UFStage3On 1/0 0
5 UFStage4On 1/0 0
6 Chkdf/dt 1/0 0 0: no check df/dt; 1: check df/dt
0: no check dead current blocking;
7 UFLSChkCurrOn 1/0 0
1: check dead current blocking
0: Single phase access; 1:
8 3PhVoltConnect 1/0 1
three-phase access
3.3 Report list


Trip report:
1 UFStage1Trip /
2 UFStage2Trip /
3 UFStage3Trip /
4 UFStage4Trip /

Table 94 Underfrequency load shedding protection technical parameter

Underfrequency load shedding
Rated frequency fn=50Hz 45.00Hz～50.00Hz ≤±20mHz
+60ms
Blocking condition
Frequency change rate
0.3Hz/s～20Hz/s ≤±0.5Hz/s
Δf/Δt
Blocking voltage 10V～120V ≤ ±2.5% times of setting or ±1V
Blocking current setting 0In～10In
±0.01In
123
Chapter 19 Overfrequency protection (81OF)
Chapter 19 Overfrequency protection

(81OF)
About this chapter

parameters for overfrequency protection.
125
1 Overview
Overfrequency protection is used to monitor whether the network is normal
by detecting the increase in frequency. When the frequency is higher than
the overfrequency protection setting and also meets other conditions, the
overfrequency protection trips to remove the specified load.
Main characteristics of overfrequency protection are as follow:
2) VT secondary circuit failure blocking;
3) There are four stages of overfrequency protection and each stage can
be enabled or disabled separately.
soft-hard parallel.

The input and output signals of overfrequency protection function diagram
Over Frequency protection
1 1
BIBlk Start
2 2
ENA_OF Operation
Figure 48 The input and output signals of overfrequency protection function diagram
right.

Input:
BIBlk BI blocking
OF Output:
Start IED startup
Input:
ENA The total connector of overfrequency
ENA_OF protection,the corresponding hard
connector is ENA_OF_5.
126
The device provides 4 stages overfrequency protection, and each stage of
protection is enabled and disabled through the corresponding logic switch.
Trip frequency of overfrequency protection can be tested by input
phase-to-phase voltage. Take overfrequency stage 1 as an example, if the
measured frequency is higher than "OFStg1FreqSet", the timing
component will start timing. As time delay reaches "OFStg1Time", the
device will issue a command "OFStg1Trip". LED and output can be
configured by AESP.
As the trip frequency of overfrequency protection is calculated by
measuring voltage, overfrequency protection will be blocked with meeting
the following requirement.
"LSVoltBlkSet";
2) VT failure is detected by IED.
3.1.2 Logic diagram

Enable overfrequency
protection function
&
“OFStage1On”=1
frequency>“OFSatge1FreqSet”
frequency<54Hz or frequency>66Hz &
frequency<45Hz or frequency>55Hz &
VT failure blocking
&
≥1 ≥1 T1
OFStage1Trip
Three-phase trip position
BI blocking
min(Uab,Ubc,Uca)<“LoadShedVoltBlkSet”
T1：“OFStage1Time”
Figure 49 Logic diagram of overfrequency stage 1 protection
3.2 Setting list

Table 96 Overfrequency protection setting
Default
value
1 OFSatge1FreqSet 1.00Fn～1.10Fn 50.5 0.01 Hz
2 OFStage1Time 0.00～100.00 100 0.01 s
4 OFStage2Time 0.00～100.00 100 0.01 s
127
Default
value
6 OFStage3Time 0.00～100.00 100 0.01 s
7 OFStage4FreqSet 1.00Fn～1.10Fn 50.5 0.01 Hz
8 OFStage4Time 0.00～100.00 100 0.01 s
9 LoadShedVoltBlkSet 10.00～120.00 10 0.01 V
Table 97 Logic switch of overfrequency protection

Number Remark
Enable or disable overfrequency stage
1 OFStage1On 1/0 0
1 protection
2 OFStage2On 1/0 0
2 protection
3 OFStage3On 1/0 0
3 protection
4 OFStage4On 1/0 0
4 protection
3.3 Report list


Trip report:
1 OFStage1Trip /
2 OFStage2Trip /
3 OFStage3Trip /
4 OFStage4Trip /

Table 99 Overfrequency protection technical parameter

Overfrequency
+60ms
Blocking condition
Blocking voltage 10V～120V ≤ ±2.5% times of setting or ±1V
128
Chapter 20 Frequency change rate protection (81DF)
Chapter 20 Frequency change rate

protection (81DF)
About this chapter

This chapter describes the frequency change rate protection
principle, input and output signals, setting parameter, IED
report and technical parameter.
129
1 Overview
Frequency change rate protection is used to monitor whether the network
is normal by detecting the frequency. Device provides 4 stages frequency
change rate protection. If frequency change rate exceeds the setting of
frequency change rate protection and meets the other conditions at the
same time, frequency change rate protection will trip.
parallel.

Frequency change rate protection function input and output signal diagram
is shown as follow:
Frequency rate of change protection

1 1
BIBlk Start
2 2
ENA_DF Operation
Figure 50 Frequency change rate protection function input and output signal diagram
right.

Input:
BIBlk BI blocking
DF Output:
Start IED startup
Input:
The total connector of frequency
ENA change rate protection , the
ENA_DF
ENA_DF_5.
130
The device offers 4 stages frequency change rate protection. Each stage
will be enabled or disabled through corresponding logic switch and
frequency change rate protection will be enabled and disabled by principal
logic switch and function of each stage will be enabled or disabled through
logic switch of each stage. The trip frequency of frequency frequency
change rate protection can be measured by the input the phase-to-phase
voltage. Take frequency change rate stage 1 as example, if the absolute
value of the measured frequency change rate is higher than setting,
"FreqDf/dtStage1Set", the timing component will start timing. As time delay
reaches "FreqDf/dtStage1Time", the IED will send out a command
"FrequencyDf/dtStage1Trip". LED and output can be configured by AESP.
As the trip frequency of frequency frequency change rate protection is
calculated by measuring voltage, frequency change rate protection will be
blocked with meeting the following requirement.
1) When logic switch "FreqDf/dtStage1DetectVolt"=1, three-phase voltage
are connected, the minimum phase-to-phase voltage is lower than
settings "LSVoltBlkSet";
2) The IED can trip, when the frequency is in a certain range, when the logic
switch "Df/dtStage1ChkFreq"=1, and the frequency is not in the range
("Df/dtStage1LFThreshold"~Df/dtStage1HFThreshold), the IED will be
blocked;
3) The frequency changing rate is in a certain range, and if the frequency is
not in the range ("Df/dtLowThresh"~ “Df/dtHighThresh”), the protection
will be blocked;
4) If the frequency is in the valid range (±15Hz of rated frequency), the
protection will be unblocked after 2 seconds.
131
3.1.2 Logic diagram

“Df/dtOn=1”
“FreqDf/dtStage1On”=1
&
“DirModeDf/dtStage1”=3
Frequency change ratio absolute setting

>“FreqDf/dtStage1Set”
Frequency change ratio>0

&
“DirModeDf/dtStage1”=1 ≥1 & T1
FreqDf/dtStage1Trip
Frequency change ratio<0

&
“DirModeDf/dtStage1”=2
45Hz<frequency<75Hz &
2s
35Hz<frequency<65Hz &
BI Blocking
≥1
Frequency change ratio absolute setting ≥1
>“FreqDf/dtHighThreshold”

<“FreqDf/dtLowThreshold”
&
“Df/dtStage1ChkFreq”=1
≥1
frequency>“Df/dtStage1HFThreshold”
frequency<“Df/dtStage1LFThreshold”
min(Uab,Ubc,Uca)<“FreqDf/dtVoltThreshold” &
“FreqDf/dtStage1DetectVolt”=1
Enable frequency rate changing protection function
T1：“FreqDf/dtStage1Time”
Figure 51 Logic diagram of frequency change rate protection stage 1
3.2 Setting list

Table 101 Frequency change rate protection setting (81DF)
Default
value
1 FreqDf/dtStage1Set 0.1～20 20 0.01 Hz/s
2 FreqDf/dtStage1Time 0.00～100.00 100 0.01 s
3 Df/dtStage1LFThreshold 45～55 45 0.01 Hz
4 Df/dtStage1HFThreshold 45～55 55 0.01 Hz
132
Default
value
30.00～
17 FreqDf/dtVoltThreshold 50 0.01 V
120.00
18 FreqDf/dtHighThreshold 0～20 20 0.01 Hz/s
19 FreqDf/dtLowThreshold 0～20 0.1 0.01 Hz/s
Table 102 Frequency change rate protection logic switch

Setting Default
Mode value
1 GenlFreqDf/dtOn 1/0 0
2 FreqDf/dtStage1On 1/0 0
1: Forward; 2: Reverse; 3:
3 DirModeDf/dtStage1 1～3 1
Non-direction
4 FreqDf/dtStage1DetectVolt 1/0 0
5 Df/dtStage1ChkFreq 1/0 0
Non-direction
Non-direction
Non-direction
3.3 Report list


Trip report:
1 FreqDf/dtStage1Trip /
133


Table 104 Technical parameter of frequency change rate protection

0.3Hz/s～20Hz/s ≤±0.5Hz/s
setting Δf/Δt
+60ms
Blocking condition
Upper limit of frequency
0Hz/s～50Hz/s ≤±0.5Hz/s
change rate
Lower limit of frequency
0Hz/s～50Hz/s ≤±0.5Hz/s
change rate
Blocking voltage 30V～120V
±1V
134
Chapter 21 Switch-onto-fault protection
Chapter 21 Switch-onto-fault
protection
About this chapter

This chapter describes the principles of switch-onto-fault
protection, input and output signals, setting parameter,
135
1 Overview
Switch-onto-fault protection is the sub-protection of overcurrent and earth
fault protection. The function shares similarity in logic trip, trip principle and
trip report. Switch-onto-fault protection will not work if circuit breaker is
closed. The trip time will start function after validity. It is mean that
switch-onto-fault protection will not open in short time.
parallel.

The input and output signals of switch-onto-fault protection function
Switch-Onto-Fault Protection
1 1
BIBlkOC Start
2 2
BIBlkEF OCOp
3 3
BI_SOTF EFOp
4 4
CBOpen SOTFErr
5
CBClose
6
ENA_SOTF
Figure 52 The input and output signals of Switch-onto-fault protection function

diagram
right.

Input:
BI_SOTF Manual close binary input
BinaryInput
Input:
BIBlkOC Binary input blocking overcurrent
Binary input blocking earth fault
BIBlkEF
protection
Output:
SOTF
Start IED startup
Trip of switching on to fault
OCOp
overcurrent
Trip of switch-on-to-fault zero
EFOp
sequence current
SOTFErr Error of manual close binary input
136

Input:
ENA switch-on-to-fault protection,the
ENA_SOTF
ENA_SOTF_5.
As circuit breaker is closed for a while, switch-onto-fault protection needs
to be detected that if there is any fault in line through detecting current
value.
As logic switch "SOTFChkBI" is set to 1 and "SOTF BI" appears falling
edge, then within the delay time "SOTFStateLatchedTime", if 3-phase
current is greater than "SOTFOCSet" and experience "SOTFOCTime" or
zero sequence current is greater than "SOTF3I0Set" and experiences
"SOTF3I0Time", switch-onto-fault trips. If the time of "SOTF BI" as high
voltage level is greater than "BIErrTimeSet", the device will send an alarm
and a report "SOTF BIErrAlarm". LED and output can be configured by
AESP.
As logic switch "SOTFChkCBPosn" is 1, and if circuit breaker stays open
position an delay time is greater than "OpenPosnConfirmTime" and if
three-phase current is greater than "SOTFOCSet", it will experience
"SOTFOCTime" or zero sequence current is greater than "SOTF3I0Set"
and experience "SOTF3I0Time", switch-onto-fault will trip. LED and output
Blocking requirement: 2nd harmonic blocking The second harmonic check
is carried out when the logic switch "SOTFFaultChk2ndH" is set 1.
137
3.1.2 Logic diagram

Logic diagram is shown as follow:
“SOTFChkBI/Posn”=0
&
≥1
“SOTF BIErrAlarm”
T1 &
SOTF BI
&
&
BI changes from 1 to 0
T2
≥1
switch-onto-fault permission
“SOTFChkBI”=1
“SOTFChkPosn”=1
& &
CBOpenPosn &
T3
CBClosePosn
&
BI changes from 1 to 0
T2
“SOTFChkBI/Posn”=1
Enable switch-onto-fault protection function
“SOTFOn”=1
& &
& T4
SOTF OCTrip
BIBlk_OC
Ia（Ib，Ic）>“SOTF OCSet”
“SOTFFaultChk2ndH”=1 &
≥1
3PhInrushBlk
“SOTFFaultChk2ndH”=0
&
&
“SOTFOn”=1 T5 SOTF 3I0Trip
&
BIBlk3I0
3I0>“SOTF3I0Set”
Enable switch-onto-fault protection function
T1：“BIErrTime”
T2：“SOTFStateLatchedTime”
T3：“OpenPosnConfirmTime”
T4：“SOTFOCTime”
T5：“SOTF3I0Time”
Figure 53 Logic diagram of switch-onto-fault function
138
3.2 Setting list

Table 106 Switch-onto-fault protection
Default
value
1 SOTF OCSet 0.05In～40In 40 0.01 A
Three times
of zero
2 SOTF3I0Set 0.05In～40In 40 0.01 A
sequence
current
3 SOTFOCTime 0.00～100.0 100 0.01 s
4 SOTF3I0Time 0.00～100.0 100 0.01 s
5 OpenPosnConfirmTime 0.00～100.0 1 0.01 s
6 SOTFStateLatchedTime 0.00～100.0 0.04 0.01 s
7 BIErrTime 0.00～100.0 10 0.01 s
8 OC2ndHI2/I1Ratio 0.07～0.50 0.07 0.01
Table 107 Switch-onto-fault protection

Number Remark
Enable or disable
1 SOTFOn 1/0 0
switch-onto-fault protection
0: check position or BI, while
"SOTFChkPosn" is 1 or
"SOTFChkBI" is 1;
2 SOTFChkBI/Posn 1/0 0
1: check position and BI, while
"SOTFChkPosn" is 1 and
"SOTFChkBI" is 1.
3 SOTFChkPosn 1/0 0
4 SOTFChkBI 1/0 0
5 SOTFFaultChk2ndH 1/0 0
3.3 Report list


Trip report:
1 SOTF OCTrip /
2 SOTF 3I0Trip /
Alarm report:
1 SOTF BIErrAlarm /
139

Table 109 Technical parameters of switch-onto-fault protection

±0.01In
≤ ±1% setting or +40ms, when
Time setting 0.00s～100.00s trip current is set as 200%
setting
Dropoff coefficient When I/In≥0.5, it is about 0.95
140
Chapter 22 Non-electric protection
About this chapter

parameters for non-electric protection.
141
1 Overview
Non-electric protection supports four groups of user-defined non-electric
protection trip.

The input and output signals of non-electric protection function are shown
as follow:
External trip initiation

1 1
BI Start
2
Operation
Figure 54 The input and output signals of non-electric protection function diagram
right.
No. Input Description

Input:
BI Binary input output
ExtBI Output:
Start IED startup
Latched time of external binary input reaches non-electric time setting,
protection will trip. LED and output can be configured by AESP.
Enable non-electric
protection function
&
T1
“NonElectricGrp1On”=1 NonElectric1Trip
NonElectricBI1
T1：“NonElectricGrp1Time”
Figure 55 Non-electric protection 1 logic diagram
142
3.2 Setting list

Table 111 Non-electric protection setting
Default
value
1 NonElectricGrp1Time 0～100 100 0.01 s
Table 112 Non-electric protection logic switch

Number Remark
1 NonElectricGrp1On 1/0 0 1: On, 0: Off
3.3 Report list


Trip report:
1 NonElectric1Trip /

Table 114 Non-electric protection technical parameters

Time setting 0.00s～100.00s ≤±1% or+40ms
143
Chapter 23 Synchro-check and dead voltage check (25)
Chapter 23 Synchro-check and dead

voltage check (25)
About this chapter

parameters for synchronization and voltage check.
145
1. Overview
Synchronization voltage check ensures that when line is connected with
busbar, electricity system will latch stable. If the difference between the
charging line voltage and the bus voltage, phase difference and the
frequency difference are in allowable range, the function of voltage
synchronization will be met.
Synchronization check function need to detect that the voltage beside
circuit breaker properbly meet the synchronization function or at least one
side is non-electric power which can ensure the safety of closing.
When the voltage on both sides is needed to be detected, the voltage
selected for synchronization is the busbar side voltage or the line side
voltage. If the voltage transformer used by protection is connected with line
sides, the reference voltage must adopt busbar voltage.
2. Function module description

The input and output signals of synchronization voltage check function
Synchro-Check with Live/Dead
Line/Bus Measurement
1 1
BIBlk syn_Req
2 2
CBOpen syn_meet
3 3
BI_MC syn_time
4
Override
5
LowU_meet
6
LDBL_meet
7
LLBD_meet
8
LDBD_meet
9
MCOut
Figure 56 Input and output signals of synchronization voltage check function diagram
right.

Input:
BinaryInput CBOpen Circuit breaker trip position
BI_MC Manual close binary input
Input:
BIBlk BI blocking
MC
Output:
syn_Req Synchronization Request
146

syn_meet Synchronization satisfied
syn_time Synchronization timeout
Override Manual close override mode
LowU_meet Synchronization undervoltage satisfied
Switch-onto-fault dead line live busbar
LDBL_meet
output
Switch-onto-fault live line dead busbar
LLBD_meet
output
Switch-onto-fault dead line dead busbar
LDBD_meet
output
MCOut Manual close condition is met
3. Detailed description
Synchronization function is suitable for auto-reclosing function or manual
close function or both of them. Therefore, the following situation needs
synchronization check function:
1) Internal or external auto-reclosing request;
2) Switch-onto-request.
Internal or external auto-reclosing signal and manual close signal will be
connected with synchronization function signal. If the device receives the
synchronization signal, the device can be closed through different
synchronization modes. Automatic closing and switch-onto-closing is on
the choice list. Synchronization closing mode of auto-reclosing includes
"SyncChkModeOn", "OverrideModeOn", "ChkDLLBOn", "ChkLLDBOn"
and "ChkDLDBOn". Manual synchronization closing mode includes
"MCOverrideModeOn", "MCSyncChk", "MCChkDLLBOn",
"MCChkLLDBOn" and "MCChkDLDBOn". Different switching modes can
be configured through AESP for lights and outputs. The above
synchronization closing modes can be explained as follow:
1) Synchronization check: as soon as choose this kind of synchronization
closing modes, the device will receive synchronization request singles
and then continually check whether it is satisfied the requirement of
synchronization or not.
2) \Override: when this kind of synchronization closing mode is chosen,
the device will receive synchronization request signals and continually
check whether it is satisfied the synchronization requirement;
3) Check line non-voltage busbar voltage: as soon as this kind of
synchronization closing modes are chosen, the device will receive
synchronization request singles and check whether the line side has
no voltage, and busbar has voltage.
4) Check line voltage busbar non-voltage: as soon as this kind of
synchronization request singles and check whether the line side has
voltage, and busbar has no voltage.
147
5) Check line voltage busbar voltage: as soon as this kind of

synchronization request singles and check that the line side has no
voltage, and busbar has not voltage.
The reference voltage U4 is the phase-to-phase voltage, synchronization
setting: "SelLineVT"=0 means that voltage transformer protection is
connected with busbar side, then reference voltage U4 is line voltage.
"SelLineVT"=1 means that voltage transformer protection is connected
with line side, then reference voltage U4 is phase-to-phase voltage.
Under the condition of check line busbar voltage and non-voltage: if dead
line live bus and dead line dead bus are both enabled at the same time,
the device is "check line non-voltage and close" mode, when live line
dead bus and dead line dead bus are enabled at the same time, the device
is "check busbar non-voltage and close".
Note: When the sampled voltage is greater than the minimum
phase-to-phase voltage (i.e., 1.732* "SyncChkMinVolt"), it is considered
that the sampled voltage UX is connected to the phase-to-phase voltage.
When judging synchronization voltage abnormal and phase voltage
difference is calculated for the same period, it should be noted that UX is
calculated as the phase-to-phase voltage. Manual close synchronization is
the same.
While synchronization or non-voltage is detected, compare the minimum
value of three-phase voltage with the sampled voltage.
3.1.2 Synchronization check mode:
Synchronization check function can use device to measure the voltage
amplitude difference, frequency difference and phase difference. Device
will receive synchronization request signals and continually check whether
it is satisfied the synchronization requirement. When the line voltage and
busbar voltage are all larger than "SyncChkMinVolt" and meets the
synchronization check requirements, the auto-reclosing will trip.
At equal synchronization time, the device will receive synchronization
request signals and continually check whether it is satisfied the
synchronization requirements. However, when "WaitSyncTime" is over,
the device stops checking synchronization requirement. If during
"WaitSyncTime", synchronization check requirement is satisfied, timing
component will stop timing and start closing. Manual closing check
synchronization difference and auto-reclosing phase difference will be set
by "SyncPh".
If synchronization check is applied to manual close function, the
corresponding BI should be high power level, and timing component will
start timing“MCWaitSyncTime”. During "MCWaitSyncTime", if
synchronization requirement is satisfied and the time is greater than
"CheckSyncTime", timing component will stop timing and start closing and
output "MCSyncMet". "MCSyncMet" signal will latch the same in the
following situations:
1) Synchronization check requirements are satisfied;
2) Manual close synchronization requests high power level;
3) Time delay "WaitMCTime" is not arrived;
4) Synchronization check sends off closing command, the following
148
requirements should be satisfied.

a） Reference voltage ratio is greater than "SyncChkMinVolt";
b） Voltage amplitude difference is less than "SyncVoltDiffSet";
c） Phase difference of voltage is less than "SyncAngleDiffSet";
d） Voltage frequency difference is less than "SyncFreqDiffSet".
3.1.3 Modes of dead voltage check:
Non-voltage check sends off closing command, the following requirements
should be satisfied.
1) If logic switch "ChkDLLBOn" is set to 1, the line voltage that is
detected by check dead voltage is lower than dead voltage setting,
and busbar voltage is higher than live voltage setting;
2) If logic switch "ChkLLDBOn" is set to 1, the line voltage that is
detected by check dead voltage is higher than live voltage setting, and
busbar voltage is lower than dead voltage setting;
3) If logic switch "ChkDLDBOn" is set to 1, both the line voltage that is
detected by check dead voltage and busbar voltage are lower than
dead voltage setting.
3.1.4 Override mode
During non synchronization mode, receiving synchronization request at
any time, synchronization requirements will be satisfied and it is suitable to
relclosing function and switch-onto function.
When auto-reclosing override mode is auto-reclosing, the device will send
off "AROverrideMode" alarm report.
The setting of auto-reclosing mode synchronization is set wrongly, the
device will send off "ARSyncChkModeErr" alarm report; take the manual
close synchronization mode as example, auto-reclosing synchronization
check modes are similar. As shown in logic diagram.
3.1.5 Logic diagram
“OverrideModeOn”
“SyncChkModeOn”
“ChkDLLBOn”
&
≥1
“ChkLLDBOn”
≥1
“ChkDLDBOn” ARLSErr
&
≥1
Figure 57 Logic diagram of auto-reclosing synchronization check function
149
Uab(Ubc,Uca) >1.732×“MCSyncChkMinVolt”
Ux>1.732×“MCSyncChkMinVolt”
Phase difference of voltage
<“MCSyncAngleDiffSet”
Voltage frequency difference &
<“MCSyncFreqDiffSet” ≥1
Voltage amplitude difference &
<“MCSyncVoltDiffSet” & T1 Synchro-check or energizing
check is satisfied
“MCSyncOn”=1
CBOpenPosn
SOTF BI T2 Synchronization check timeout

or Check dead voltage failure
“ChkDLLBOn”
Ux <1.732×“MCChkDeadVoltMaxVolt” & &

≥1
“SelLineVT”=1
&
Uab(Ubc,Uca) <1.732×“MCChkDeadVoltMaxVolt” &
“MCLiveLineAndDeadBus”=1
&
Ux<1.732×“MCChkDeadVoltMaxVolt” &
Uab(Ubc,Uca) <1.732×“MCChkDeadVoltMaxVolt”
“MCChkDLDBOn”=1
&
“MCChkDLDBOn”=1
&
Uab(Ubc,Uca) <1.732×“MCChkDeadVoltMaxVolt”
“SelLineVT”=1
&
&
Ux <1.732×“MCChkDeadVoltMaxVolt”
“MCLiveLineAndDeadBus”=1
T1：“MCSyncChkTime”
T2：“MCWaitSyncTime”
Figure 58 Synchronization check logic diagram
3.2 Setting list

Table 116 Settingof synchronization check and dead voltage check
Default
value
1 SyncDetectTime 0.02～100.00 0.05 0.01 s
2 WaitSyncTime 0.05～100.00 0.05 0.01 s
3 MCSyncChkTime 0.02～100.00 0.05 0.01 s
4 MCWaitSyncTime 0.05～100.00 0.05 0.01 s
5 SyncAngleDiffSet 1.00～10.00 10 0.01 degree
6 SyncVoltDiffSet 1.00～40.00 40 0.01 V
7 SyncFreqDiffSet 0.02～2.00 2 0.01 Hz
8 ChkDeadVoltMaxVolt 10.00～50.0 30 0.01 V
9 SyncChkMinVolt 30.00～65.00 40 0.01 V
4：Uab
10 SyncPh 4-6 4 1 5：Ubc
6：Uca
150
Table 117 Manual close synchronization setting

Default
Number Setting name Range Unit Remark
value
1 MCSyncChkTime 0.05～100.00 0.05 s
2 MCWaitSyncTime 0.05～100.00 0.05 s
3 MCSyncAngleDiffSet 1.00～10.00 10 degree
4 MCSyncVoltDiffSet 1.00～40.00 40 V
5 MCSyncFreqDiffSet 0.02～2.00 2 Hz
6 MCChkDeadVoltMaxVolt 10.00～50.0 30 V
7 MCSyncChkMinVolt 30.00～65.00 40 V
4：Uab
8 SyncPh 4-6 4 5：Ubc
6：Uca
Table 118 Logic switch of manual close synchronization check and dead voltage check
Number Remark
1 SelLineVT 1/0 0
2 SyncChkModeOn 1/0 0
3 OverrideModeOn 1/0 0
4 ChkDLLBOn 1/0 0
5 ChkLLDBOn 1/0 0
6 ChkDLDBOn 1/0 0
7 MCSyncOn 1/0 0
8 MCOverrideModeOn 1/0 0
9 MCSyncChk 1/0 0
10 MCDeadLineAndLiveBus 1/0 0
11 MCLiveLineAndDeadBus 1/0 0
12 MCChkDLDBOn 1/0 0
3.3 Report list


Trip report:
1 MCVoltDiffFail /
2 MCFreqDiffFail /
3 MCAngleDiffFail /
4 MCDeadVoltChkFail /
5 MCSyncRequest /
6 MCSyncMet /
7 MCSyncUVMet /
8 MCSyncTimeout /
151

9 MCOverrideMode /
10 MCMet /
11 MCChkDLLBMet /
12 MCChkLLDBMet /
13 MCChkDLDBMet /
Alarm report:
1. MCSyncVoltExchg /
2. MCSyncVoltErr /
Alarm of auto-reclosing
synchronization phase
difference and manual
3. SyncPhSelConflict
close synchronization
phase difference choosing
differently

Table 120 Synchronization check and dead voltage check technical parameters

Synchronization check mode
1) Check synchronization
2) Check dead voltage, if the check
dead voltage is failure, it is the check
synchronization.
3) Override
Trip mode Modes of dead voltage check:
1) Line (V4) non-voltage busbar
(V3Ph) non-voltage
2) Line (V4) non-voltage busbar
(V3Ph) voltage
3) Line 4(V4) voltage busbar (V3Ph)
non-voltage
The setting of line or
busbar dead voltage 10V to 50V (phase-to-earth voltage)
1V
setting
The live voltage
setting of line or 30V to 65V (phase-to-earth voltage)
1V
busbar
∆V-voltage difference 1V to 40V (phase-to-earth voltage) ≤±1V
Δf-frequency
difference (f2>f1; 0.02Hz～2.00Hz ≤±20mHz
f2<f1)
Δα- angle difference
1°～10° ≤ ±3°
(α2>α1; α2<α1)
Minimum ≤ ±1.5% times of setting or
0.02s～100.00s
measurement time +60ms
The largest
broadening time of 0.05s～100.00s ≤ ± 1% setting or +50ms
synchronization check
152
Chapter 24 Auto-reclosing function (79)
Chapter 24 Auto-reclosing function

(79)
About this chapter

This chapter describes the principles of auto-reclosing
function, the input and output signals, setting parameters,
reports and technical parameters.
153
1 Overview
When transient faults occurs to lines, auto-reclosing function can be reset
to operate. Statistics show that 85% of the faults are transient faults, after
auto-reclosing, these faults will disappear. Therefore, temporal short circuit
may occur in the line. After auto-reclosing function tripping, the line will be
charged again. If the fault is permanent or short circuit arc current has not
disappeared, the protection will trip circuit breaker again.
Main features of auto-reclosing function are shown as follow:
1) There are 4 times of auto-reclosing (available);
2) Each auto-reclosingtime can be set respectively;
3) Externally enable auto-reclosing/protection trip start auto-reclosing;
4) Three-phase auto-reclosing;
5) monitoring of circuit breaker position;
6) To coordinate with auto-reclosing check synchronization function.
soft-hard parallel.

Auto-reclosing function input and output signals are shown as follow:
Three-Pole Auto-Reclosure
1 1
BIBlk ChkARFail
2 2
CBOpen Ph3TripInitAR
3 3
AR_BLOCK Ph3CBOTripInitAR
4 4
AR_OFF AR_IN
5 5
CB_FAULTY Ph3TripBlkAR
6 6
PH3_INIT_AR ARFail
7 7
ENA_AR ARSucc
8
AR_FinalTrip
9
syn_Req
10
syn_meet
11
LowU_meet
12
AR_Trip
13
AR_Block
14
syn_time
15
FirstARTrip
16
SecondARTrip
17
ThirdARTrip
18
FourthARTrip
Figure 59 auto-reclosing function input and output signal diagram
154
right.

Input:
BinaryInput CBOpen Circuit breaker trip position
AR_BLOCK Block auto-reclosing binary input
Input:
BIBlk BI blocking
AR_OFF Enable or disable auto-reclosing
CB_FAULTY Spring discharge binary input
Three-phase Initiating
PH3_INIT_AR
auto-reclosing binary input
Output:
Check auto-reclosing
ChkARFail
unsuccessfully
Three-phase trip initiates
Ph3TripInitAR
auto-reclosing
Three-phase spontaneous trip
Ph3CBOTripInitAR
initiates auto-reclosing
AR_IN Auto-reclosing is in process
Three-phase trip blocking
Ph3TripBlkAR
auto-reclosing
AR_3C ARFail Auto-reclosing unsuccessfully
ARSucc Auto-reclosing is successful
Auto-reclosing trip three-phase and
AR_FinalTrip
blocking auto-reclosing
Auto-reclosing synchronization
syn_Req
request
Auto-reclosing synchronization is
syn_meet
met
LowU_meet Undervoltage conditions are met
AR_Trip Auto-reclosing trip
AR_Block Auto-reclosing blocking
syn_time Synchronization timeout
FirstARTrip Trip of first-shot auto-reclosing
SecondARTrip Trip of second-shot auto-reclosing
ThirdARTrip Trip of third-shot auto-reclosing
FourthARTrip Trip of fourth-shot auto-reclosing
Input:
The total connector of automatic
ENA reclosing protection , the
ENA_AR
ENA_AR_5.
155
3.1.1 Auto-reclosing startup
Auto-reclosingcould be initiated by protection or by external BI
auto-reclosing.
The protections that can start auto-reclosing include: overcurrent stage 1,
overcurrent stage 2, overcurrent stage 3, overcurrnt stage 4, zero
sequence current stage 1, zero sequence stage 2, zero sequence stage 3,
zero sequence stage 4, high voltage side zero sequence current stage 1,
high voltage side zero sequence current stage 2, high voltage side zero
sequence current stage 3, high voltage side zero sequence current stage 4,
negative sequence current stage 1, negative sequence current stage 2,
negative sequence current stage 3, negative sequence current stage 4. If
external binary input startup is reclosed, then the corresponding binary input
will be configured to three-phase startup auto-reclosing binary input of
auto-reclosing startup pin. If the signal of starting auto-reclosing protection
that is configured in IO Matrix is sent to the pin of ARFinalTrip->FinalTrip, then
the corresponding section is protected by blocking auto-reclosing. Reclosing
output signal recording requires engineering configuration.
After other protections tripping, auto-reclosing logic is blocked.
Three-phase Initiating auto-reclosing ≥1
binary input,falling edge
Three-phase internal start

reclosing,falling edge &
Three-phase has dead current ≥1
CB OpenPosn
≥1
CB OpenPosn & 3PhFaultInitAR
“3PhSpontaneousTripInitAR”=1
Figure 60 Auto-reclosing startup logic diagram
3.1.2 Auto-reclosing logic

In order to avoid equipment maintenance or circuit breaker open position
in the state of maintenance starts auto-reclosing, only does the
auto-reclosing experience the circuit breaker close position and the
"ARBlkTime" is delayed, the auto-reclosing can be started again. Then
auto-reclosing will start and the fault will disappear without current or with
tripping. The first auto-reclosing will start timing. Actually, one time of
auto-reclosing time delay delays the setting "WaitSyncTime". During this
time, an long as circuit breaker is tripping, one-time auto-reclosingtime
start timing. If equal synchronization timing is tested finished and the
device cannot test circuit breaker is tripping, auto-reclosing function will be
blocked at the time of auto-reclosing blocking time and report
auto-reclosing failure alarm.
If the circuit breaker failure protection is used to (internal or external) circuit
breaker, the setting of "WaitSyncTime" should be set shorter than the time
of fault protection time delay, to protect each stage of auto-reclosing will
not affect fault circuit breaker. After failure protection tripping, the
156
auto-reclosingfunction will be blocked.

As showed above, after starting auto-reclosing, auto-reclosing time starts
timing and will be delayed by time setting, "3PhARTime1" will begin the
first time auto-reclosing (or "3PhARTime2", "3PhARTime3", and
"3PhARTime4" begin the 2nd, 3rd and 4th stage auto-reclosing). After the
first auto-reclosingtime, equal synchronization time will start timing. In fact,
the first reclosing time is stretched by the equal synchronization time. After
the first reclosing time, the device start synchronization check detection.
During equal synchronization time, if the synchronization check succeeds
within the time, which means synchronization time is over, and the device
will send off the reclosing command. However, if the synchronization
success is not detected within synchronization time, the auto-reclosing will
be blocked within the "ARBlkTime", and send off auto-reclosing failure
alarm.
As for reclosing command, the maximum broadening of closing pulse is
500ms. In general, the device does not detect synchronization check in the
pulse broadening time. During this time, if the circuit breaker auxiliary
contact position bianry input CBOpen is set to“0” or the device detects the
current, closing pulse returns.
Once closing command disappears, auto-reclosing will confirm the time
and begin to timing, to detect whether there is fault arrival during this
period of time. If there is no fault in the auto-reclosing time, the device
thinks that the fault disappears. Therefore, after the confirmation of the
time delay, the auto-reclosingstarted timing. In the blocking time of
auto-reclosing, the auto-reclosing function is blocked. In the definite time
of auto-reclosing, if the fault still exists, the protection will trip and the next
stage of auto-reclosing logic will start. This process is repeated until the
maximum number of reclosing.
If all wheels of auto-reclosing does not succeed, the fault still exists and
the protection trip. After the last auto-reclosing, if the protection still trips,
the device thinks that the auto-reclosing trips and reports the
"ARTrip3Ph/BlkAR" alarm. Besides, during the blocking time of
auto-reclosing, auto-reclosing blocking function will be protected and
auto-reclosing failure alarm will be issued.
Manual close binary input blocking auto-reclosing. When manual close
binary input is in high power level, the manual close binary input function
works, therefore, the auto-reclosing function will be blocked within the
setting "ARBlkTime".
In the process of auto-reclosing, if the spring discharge binary input is in
high power level and "SpringDischAlmTime" is still disappeared, the circuit
breaker fails and auto-reclosing function is blocked.
1) Single auto-reclosing
When the protection or external BI start auto-reclosing, the auto-reclosing
logic will be enabled. After the start condition is satisfied, through the time
setting "3PhARTime1" delay, the device begins to time of "WaitSyncTime".
In the synchronization time, if the setting "SyncChkTime" meets the
synchronization conditions, closing pulse signal will be triggered, and the
"ARConfTime" start timing. During this period of time, if the
auto-reclosingcondition is satisfied, the auto-reclosingwill block and the
auto-reclosingfails; if there is no block condition is satisfied during this
period and there is no fault, the coincidence is successful.
157
Auto-reclosingreturn waiting for next auto-reclosing.

2) Multiple auto-reclosing
After the first trip of autoreclosing, multiple auto-reclosing logic resumes
with single auto-reclosing. if the first auto-reclosing fails, the protection will
start the next wheel of auto-reclosing logic. Therefor, during "ARConfTime",
if there exits failures, the next auto-reclosing logic will be started and will
experience the next wheel of auto-reclosing time. This process will be
repeated according to the number of auto-reclosing until all wheels of
auto-reclosing times have been finished. All stages of auto-reclosing time
can be set through "3PhARTime1", "3PhARTime2", "3PhARTime3" and
"3PhARTime4". If any of these stages is successful, the auto-reclosing
function returns; and if all the four stages auto-reclosing fail, then the
whole auto-reclosing logic fails and finally the protection will trip. The
following diagram is a schematic diagram of two shots of auto-reclosing.
Fault
Trip command
Circuit breaker
trip position
Initiating auto-
reclosing binary input
Time 1 of Time 2 of
three-phase three-phase
Time delay setting auto-reclosing auto-reclosing
of three-phase
auto-reclosing
Synchronization check
or three phase voltage
check successful Auto- Auto-
reclosing reclosing
Close circuit pulse pulse
breaker command time time
Auto-reclosing
success time
Auto-reclosing
charging time
Figure 61 Trip and blocking auto-reclosing after two shots of auto-reclosing
3.2 Setting list

Table 122 Auto-reclosing setting
Default
value
1 3PhARTime1 0～600 600.00 0.01 s
2 3PhARTime2 0～600 600.00 0.01 s
3 3PhARTime3 0～600 600.00 0.01 s
4 3PhARTime4 0～600 600.00 0.01 s
5 ARPulse 0.08～0.5 0.5 0.01 s
6 ARTimes 1～4 1 1
7 ARConfirmTime 0.1～100 100.00 0.01 s
158
Default
value
8 ARBlkTime 0.05～100 100.00 0.01 s
9 SyncDetectTime 0.02～100 0.05 0.01 s
10 WaitSyncTime 0.05～100 60.00 0.01 s
11 SpringDischargeAlarmTime 0.10～100 10.00 0.01 s
12 SyncAngleDiffSet 1.00～10.00 10 0.01 degree
13 SyncVoltDiffSet 1.00～40.00 40 0.01 V
14 SyncFreqDiffSet 0.02～2.00 2 0.01 Hz
15 ChkDeadVoltMaxVolt 10.00～50.0 30 0.01 V
30.00～
16 SyncChkMinVolt 40 0.01 V
65.00
Table 123 Auto-reclosing logic switch
Setting Default
Mode value
1 AROn 1/0 0
2 StopModeOn 1/0 0
3 ARTrip3Ph/BlkAR 1/0 0
4 3PhSpontaneousTripInitAR 1/0 0
5 OverrideModeOn 1/0 0
6 SyncChkModeOn 1/0 0
7 ChkDLLBOn 1/0 0
8 ChkLLDBOn 1/0 0
9 ChkDLDBOn 1/0 0
3.3 Report list


Trip report:
1 ChkARFail /
2 3PhTripInitAR /
3 3PhSpontaneousTripInitAR /
4 ARProcessing /
5 3PhTripBlkAR /
6 ARFail /
7 ARSuccess /
8 ARChkVoltDiffFail /
9 ARChkFreqDiffFail /
10 ARChkAngleDiffFail /
11 ARDeadVoltChkFail /
159

12 ARTrip3Ph/BlkAR /
13 ARSyncRequest /
14 ARSyncMet /
15 UVCondMet /
16 BlkAR /
17 SyncTimeout /
18 AROverrideMode /
19 1stARTrip /
20 2ndARTrip /
21 3rdARTrip /
22 4thARTrip /
Alarm report:
1 ARSyncChkModeErr /

Table 125 Auto-reclosing technical parameters
Items Reference value error range (V)

Auto-reclosing times 4
Protection startup or
Auto-reclosing startup
auto-reclosingexternal
function
startup BI
Every wheel of auto-reclosing
0.05s～600.00s
time
Auto-reclosing confirmation
0.10s～100.00s ≤ ± 1.5% times of setting or
time
+60ms
Auto-reclosing blocking time 0.50s～100.00s
Waiting synchronization time 0.050s～100.00s
160
Chapter 25 Blocking simple busbar differential
protection
Chapter 25 Blocking simple busbar

differential protection
About this chapter

This chapter describes the principles of blocking simple
busbar differential protection function, the input and output
signals, setting parameters, messages and technical
parameters.
161
Chapter 25 Blocking simple busbar differential
protection
1 Protection principle
The function cooperates with simple busbar differential protection function
that is installed to the low voltage side of transformer or at the sectionalizer
(bus coupler) to complete the protection of busbar. If the fault occurs at
outlets, protection starts and sends off blocking simple busbar differential
protection signal, simple busbar differential protection which is at low
voltage side of blocking transformer or at the sectionalizer (bus coupler)
trips fault through line protection trip; if the fault occurs at the busbars,
simple busbar differential protection function that is installed to the low
voltage side of transformer or at the sectionalizer (bus coupler) is
unblocked, and the faults can be isolated in a short time.
When overcurrent protection any stage 1 starts, IED sends out GOOSE
blocking signal, the signal will return after the fault is cut off; if the fault is
not still cut off until the protection lasts for 500ms, the signal will return
automatically to realize simple busbar differential protection.
If the simple busbar differential protection is blocked by direction, then
overcurrent protection must be blocked by direction, and the direction is
forward.
The input and output signals of simple busbar differential protection
BlkSimpleDiff
1 1
ENA_BSBus BlkSDiff_BO
Figure 62 Input and output signal diagram of simple busbar differential protection
function
right.

Output:
BOConfig Trip of blocking simple busbar
BlkSDiff_BO
differential
Input:
The total connector of blocking
ENA simple busbar differential
ENA_BSBus
protection,the corresponding hard
connector is ENA_BSBus_5.
162
Chapter 29 Blocking simple busbar differential prote
ction
2 Setting list
Table 127 Logic switch of blocking simple busbar differential protection
Number Remark
1 BlkSimpleBusDiffOn 1/0 0
1-Judge overcurrent
2 DirBlkSimpleBusDiff 1/0 0 protection in direction area;
0-don't judge direction
3 Report list

Trip report:
1 BlkSimpleBusDiffTrip /
163
Chapter 26 Simple busbar differential protection
Chapter 26 Simple busbar differential

protection
About this chapter

This chapter describes the principles of blocking simple
busbar differential protection function, the input and output
signals, setting parameters, messages and technical
parameters.
165
The input and output signals of simple busbar differential protection
SimpleDiff
1 1
BIBlk Start
2 2
ENA_SBus Operation
Figure 63 Input and output signal diagram of simple busbar differential protection
function
right.

Input:
BIBlk BI blocking
SimpleDiff Output:
Start IED startup
Input:
The total connector of simple busbar
ENA differential protection,the
ENA_SBus
ENA_SBus_5.
Simple busbar differential protection logic diagram:
Ia>SimpleBusDiffCurrSet
≥1
&
Ib>SimpleBusDiffCurrSet T
SimpleBusDiffTrip
Ic>SimpleBusDiffCurrSet
BI blocking
“SimpleBusDiffOn”=1
Enable simple busbar differential

protection function
T：“SimpleBusDiffTime”
Figure 64 Simple busbar differential protection logic
166
2 Setting list
Table 130 Time setting of simple busbar differential protection
Default
value
1 SimpleBusDiffCurrSet 0.05In～40In 40 0.01 A
2 SimpleBusDiffTime 0～100 100 0.01 s
Table 131 Simple busbar differential logic switch

Number Remark
1 SimpleBusDiffOn 1/0 0
3 Report list

Trip report:
1 SimpleBusDiffTrip /
167
Chapter 27 Undervoltage load shedding protection
Chapter 27 Undervoltage load

shedding protection
About this chapter

This chapter describes the principles of undervoltage load
shedding protection, the input and output signals, setting
169
1 Overview
Undervoltage load shedding is necessary when the power grid is
connected with a huge system with vast power capacity. Under this
condition, “underfrequency load shedding scheme” cannot work properly.
Undervoltage load shedding scheme would be a useful criterion whenever
Automatic Voltages Regulator (AVR) is out of service. The main features
of underfrequency load shedding protection are as follow:
1) Negative sequence voltage blocking;
2) Sliding pressure (du/dt) blocking;
3) circuit breaker position checking;
4) Load current blocking;
5) VT secondary circuit failure supervision.
soft-hard parallel.

The input and output signals of undervoltage load shedding protection are
shown as follow:
Load Shedding Under Voltage protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
ENA_LSUV
Figure 65 Input and output signals of multi-round of undervoltage load shedding

protection diagram
right.

Input:
BinaryInput
Input:
BIBlk BI blocking
LSUV Output:
Start IED startup
ENA Input:
170

The total connector of undervoltage
load shedding protection,the
ENA_LSUV
ENA_LSUV_5.
Undervoltage load shedding is provided based on bay load shedding
principle. This means that the protection function is implemented in each
bay separately, instead of being applied in an incoming bay and sending
trip command to various outgoing bays. In this regard, coordination
between the undervoltage load shedding protection functions applied at
various bays can be achieved by selecting appropriate settings for pickup
threshold and time delay of the protection in various bays. Based on the
bay load shedding principle, one trip stage is provided for the protection.
Trip voltage of undervoltage load shedding protection can be tested by
input phase-to-phase voltage. If all the voltages are lower than setting
"UVLSVoltSet", timing component starts, when the delay runs toward
"UVLSTime", the load shedding command is issued. It is noted that
"UVLSVoltSet" is phase-to-phase voltage setting.
Since the protection operates based on measured voltages, the protection
should be blocked if some conditions are satisfied as following:
1) The device will detect VT failure or switch tripping.
"LSVoltBlkSet";
3) The current blocking conditions can be enabled and disabled through
logic switch "UVLSChkCurrOn". If the voltage transformer is installed
on the power supply side, and does not want to protect the
undervoltage protection check current, the setting of
"UVLSheddingCheckCurrOn" can be set to 0;
4) Circuit breaker is at open position. If it is in the same case, as voltage
detect current setting. Meanwhile, although the voltage is lower than
undervoltage load shedding voltage setting, the protection will not send
off trip command;
5) Sliding pressure (Δu/Δt) is greater than "LoadShedDv/dtBlkSet".
Setting is phase-to-phase voltage Δu/Δt;
6) Negative sequence voltage is greater than 5V.
171
3.1.2 Logic diagram

min(Uab,Ubc,Uca)<“UVLSVoltSet”
&
“UVLSOn=1”
Enable undervoltage
load shedding function
InstantVTFail
≥1
CB OpenPosn
BI blocking
&
min(Uab,Ubc,Uca)<LoadShedVoltBlkSet” ≥1 T
≥1
UVLSTrip
Negative sequence voltage>5V
max(Ia,Ib,Ic)<“LoadShedCurrBlkSet” &
“UVLSChkCurrOn”=1
Maximum absolute value of voltage

&
change rate>“LoadShedDv/dtBlkSet”
“Chkdu/dt”=1
T：“UVLSTime”
Figure 66 logic diagram of undervoltage load shedding protection
3.2 Setting list

Table 134 Settings of undervoltage load shedding protection
Default
value
1 UVLSVoltSet 50～120 80 0.01 V
2 UVLSTime 0.1～100 100 0.01 s
3 LoadShedVoltBlkSet 10.00～120.00 120 0.01 V
4 LoadShedCurrBlkSet 0.05In～10In 10 0.01 A
5 LoadShedDv/dtBlkSet 2～200 100 0.01 V/s
Table 135 Logic switch of undervoltage load shedding

Number Remark
1-Enabled;
1 UVLSOn 1/0 0
0-Disabled;
1-Enabled;
2 Chkdu/dt 1/0 0
0-Disabled;
1-Enabled;
3 UVLSChkCurrOn 1/0 0
0-Disabled;
3.3 Report list


Trip report:
1 UVLSTrip /
172

Table 137 Undervoltage load shedding protection technical parameter
Name Scope and step Error

Undervoltage load shedding
Voltage 50V～110V ≤ ±3% setting or ±1V
Time 0.1s～100.00s ≤ ± 1.5% setting or +60ms
Blocking condition
Rate of change of voltage Δu/Δt 2V/s～200V/s ≤ ±3% setting or ±1V/s
1 to 200 V/s, step 0.01 V/s 10V～120V ≤ ±3% setting or ±1V
173
Chapter 28 Overload load shedding protection
Chapter 28 Overload load shedding

protection
About this chapter

This chapter describes the principles of overload load
shedding protection, the input and output signals, setting
175
1 Overview
The IED provides a load shedding function based on the load current
passing through feeder. This function will be essential in conditions that
feeder is connected to a huge network with constant frequency and
additional AVR is continuously used for voltage regulation. In this case,
load shedding protection should come into effect based on load current
measured in following conditions.
1) dV/dt Blk (in the case of voltage is connected);
2) dF/dt Blk (in the case of voltage is connected);
4) VT secondary circuit failure supervision (in the case of voltage is
connected).
soft-hard parallel.

The input and output signals of the overload load shedding protection
function diagram are shown as follow:
Load Shedding Overcurrent protection
1 1
BIBlk Start
2 2
ENA_LSOL Operation
Figure 67 The input and output signals of the overload load shedding protection
diagram
right.

Input:
BIBlk BI blocking
LSOL Output:
Start IED startup
Input:
ENA The total connector of overload load
ENA_LSOL shedding protection, the corresponding
hard connector is ENA_LSOL_5.
176
Overload load shedding is provided based on “bay load shedding” principle.
This means that the protection function is implemented in each bay
separately, instead of being applied in an incoming bay and sending trip
command to various outgoing bays. In this regard, coordination between
load shedding protection functions applied at various bays can be
achieved by selecting appropriate settings for pickup threshold and time
delay of the protection in various bays. Based on the bay load shedding
principle, if all of the measured phase currents exceed setting
"OLLSCurrSet", timing component starts, when the delay runs toward
""OLLSCurrTime", the command "OLLSTrip" is issued. LED and output
If the device is accessed to the voltage, and the logic switch
"OLLSChkVolt" is set to 1, then when the following conditions are met, the
blocking overload shed is blocked.
1) Sliding pressure (Δu/Δt) is greater than "LoadShedDv/dtBlkSet".
2) The Δf/Δt exceeds "Df/dtBlkSet";
3) The device will detect VT failure or switch tripping.
"LoadShedVoltBlkSet".
3.1.2 Logic diagram
max(Ia,Ib,Ic)>“OLLSCurrSet”
“OLLSOn=1” &
Enable overload load

shedding function
BI blocking ≥1
CB OpenPosn
InstantVTFail
≥1
min(Uab,Ubc,Uca)<”LoadShedVoltBlkSet” & &
≥1 T
OLLSTrip
Absolute value of frequency
&
change rate>“Df/dtBlkSet”
“Chkdf/dt”=1
Maximum absolute value of voltage

&
change rate>“LoadShedDv/dtBlkSet”
“Chkdf/dt”=1
“OLLSChkVolt”=1
“OLLSChkVolt”=0
T：“OLLSTime”
Figure 68 Logic diagram of overload load shedding protection
177
3.2 Setting list

Table 139 Overload load shedding protection setting
Setting Default
name value
(0.05～
1 LSOL_ISet OLLSCurrSet 40 0.01 A
40)In
2 LSOL_TSet OLLSTime 0.1～100 100 0.01 s
0.10～
3 dfdt_Set Df/dtBlkSet 20 0.01 Hz/s
20.00
4 LS_dudtSet LoadShedDv/dtBlkSet 2～200 100 0.01 V/s
10.00～
5 LS_UBlk LoadShedVoltBlkSet 120 0.01 V
120.00
Table 140 Logic switch of undervoltage load shedding
Logic switch Logic switch Setting Default
Number Remark
mark description Mode value
1-Enabled;
1 LSOL_On OLLSOn 1/0 0
0-Disabled;
1-Enabled;
2 LSOL_ChkU OLLSChkVolt 1/0 0
0-Disabled;
1-Enabled;
3 LS_Chkdudt Chkdu/dt 1/0 0
0-Disabled;
1-Enabled;
4 LS_Chkdfdt Chkdf/dt 1/0 0
0-Disabled;
3.3 Report list


Trip report:
1 OLLSTrip /

Table 142 Overload load shedding protection technical parameter
Name Scope and step Error

Overload load shedding
Current 0.05In～40InA ≤ ±3 % setting or ±0.02Ir
Time 0.1s～100.00s ≤ ± 1.5% setting or +60ms
Blocking condition
Frequency change rate Δf/Δt 0.3Hz/s～20Hz/s ≤±0.5Hz/s
Rate of change of voltage Δu/Δt 2V/s～200V/s ≤ ±3% setting or ±1V/s
1 to 200 V/s, step 0.01 V/s 10V～120V ≤ ±3% setting or ±1V
178
Chapter 29 Cooling load startup protection
Chapter 29 Cooling load startup

protection
About this chapter

This chapter describes the cooling overload protection
179
Input and output signals of cooling load startup protection function are
shown as follow:
CLP
1
BIBlk
2
Init
3
ShortRst
4
CBOpen
5
ENA_CLP
Figure 69 Input and output signal diagram of cooling load startup protection function
right.

Input:
BinaryInput
Input:
BIBlk BI blocking
CLP
Init External trigger
ShortRst Fast reset binary input
Input:
The total connector of cooling
ENA load startup protection,the
ENA_CLP
corresponding hard connector
is ENA_CLP_5.
The device provides cooling load startup logic which can be used as the
designed protection component within a specified time and also can
improve the setting of designed protection component, therefore, the
protection setting can be set in accordance with load curve, and the setting
is automatically higher to prevent maloperation in the process of excitation
circuit. Cooling load startup logic provides protection functions that are
stable and easy to maintain for startup process.
Cooling load startup logic is used for overcurrent protection and earth fault
protection, and the output of cooling load startup logic can be used as
blocking signals for these protections.
The logic diagram of cooling load startup function is shown as follow. After
the circuit breaker open state continues to exceed "CoolLoadTripTime",
the startup logic of cooling load is enabled while the circuit breaker close
state is detected. After circuit breaker close position state exceeds
"CoolLoadStartRstTime", the cooling load startup logic is disabled; if the
quick reset function is enabled, after circuit breaker open position state
exceeds "CoolLoadStartFastRstTime", cooling load startup logic will be
disabled. There are two ways of detecting open state of circuit breaker,
when "CoolLoadStartLogicSel" =0, check whether there is no current in
180
three-phase circuit to detect open state of circuit breaker. When

"CoolLoadStartLogicSel" =1, only the auxiliary position signal of switch
needs to be checked.
When the output of cooling load startup logic is 1, related setting of cooling
load startup logic is enabled, and the overcurrent protection and zero
sequence current trip in accordance with the setting judgment; when the
output of cooling load startup logic is 0, related setting of cooling load
startup logic is disabled, and overcurrent protection and zero sequence
current trip in accordance with the function setting that is respectively set.
Circuit breaker
&
trip position
≥1
“CoolLoadStartLogicSel”=1 T1 S Q
there is no current in >
three-phase circuit &
R Q
“CoolLoadStartLogicSel”=0
T2 ≥1
& ≥1
≥1
T3
Fast reset binary input
IED Startup
External startup CLP function input
&
BI blocking
CoolLoadStart
Enable cooling load startup

protection function
“CoolLoadStartProtOn”=1
T1：“CoolLoadTripTime”
T2：“CoolLoadStartRstTime”
T3：“CoolLoadStartFastRstTime”
Figure 70 Cooling load startup protection function logic diagram
2 Setting list
Table 144 Cooling load startup protection setting
Default
value
1 CoolLoadTripTime 0～4000 4000 0.01 s
2 CoolLoadStartRstTime 0～4000 4000 0.01 s
3 CoolLoadStartFastRstTime 0～600 600 0.01 s
4 CoolLoadStartOC1Multiple 1～10 10 0.01
5 CoolLoadStartOCStage1Time 0～100 100 0.01 s
6 CoolLoadStartInvTimeOC1T 0.05～100 100 0.01
181
Default
value
16 CoolLoadStart3I01Multiple 1～10 10 0.01
17 CoolLoadStart3I0Stage1Time 0～100 100 0.01 s
18 CoolLoadStartInvTime3I01T 0.05～100 100 0.01
Table 145 Cooling load startup logic switch

Number Remark
1: check current to detect the
position of circuit breaker;
1 CoolLoadStartLogicSel 1/0 0
0: check position of auxiliary
contact of circuit breaker.
2 CoolLoadStartProtOn 1/0 0
3 Report list

Trip report:
1 IEDStartup /
182
Chapter 30 Frequency auto-reclosing protection
Chapter 30 Frequency auto-reclosing

protection
About this chapter

This chapter describes the frequency auto-reclosing
protection principle, input and output signals, setting
parameter, IED report and technical data.
183
1 Overview
According to the installation rules of electrical equipment, frequency
auto-reclosing device is used for power reserve realization of power
generation, on the basis of re-synchronization of the disconnected power
line or on the basis of synchronization and on the condition of frequency
recovery, reduce the customers number of power outage.
When allocate equipment and distribute load in sequence, frequency
auto-reclosing function should consider the importance level of the uses.
Generally speaking, the load connection sequence of frequency
auto-reclosing is opposite to the sequency of frequency load shedding.
parallel.

The input and output signals of frequency auto-reclosing protection
function diagram are shown as follow:
FAR Protection
1 1
BIBlk Start
2 2
ENA_FAR Operation
Figure 71 The input and output signal diagram of frequency auto-reclosing protection
right.

Input:
BIBlk BI blocking
FAR Output:
Start IED startup
Input:
The total connector of frequency
ENA auto-reclosing protection, the
ENA_FAR
ENA_FAR_5.
184
Take the stage 1 of frequency auto-reclosing as an example, when the stage 1
of underfrequency trips, it triggers the RS trigger, and the signal is triggered
continuously during the "AutoFreqCloseCBRstTime". During this period of
time, if the normal frequency is detected, and the voltage is greater than
live voltage setting, the frequency auto-reclosing 1 trips; if the frequency is
not recovered to normal, the triggering signal resets, then even though the
frequency is recovered, there is no aut0-reclosing.
If the auto-reclosing conditions are met, in order to prevent the repeated
auto-reclosing after cutting off the load, in the period of
"AutoFreqCloseCBBlkTime", protection is blocked. During this period of time,
the stage 1 of frequency auto-closing cannot trip for the second time. After
the blocking time, the trip of stage 1 of underfrequency should be detected
again, and the auto-reclosing can trip again.
On the basis of the above principle, the setting of
"AutoFreqCloseCBBlkTime" should be greater than the setting of
"AutoFreqCloseCBRstTime" to ensure the auto-reclosing trips for the
second time. After tripping, LED, IED output and others can be configured by
AESP.
Enable frequency auto-
reclosing function
“FreqARStage1On
”=1
UFLSStage1Trip S Q &
>
FreqARStage1Trip R Q
f>”FreqARStage
1Set”
&
T1 Tp FreqARStage1Trip
Umin>”FreqARLi
veVoltSet”
T1:FreqARStage1Time
Tp:FreqARPulseSet
Figure 72 Logic diagram of frequency auto-reclosing
3.2 Setting list

Table 148 Settings of frequency auto-reclosing protection
Default
value
1 FreqARStage1Set 0.90Fn～1.00Fn 49.5 0.01 Hz
2 FreqARStage1Time 0.10～100.00 100 0.01 s
185
Default
value
9 FreqARLiveVoltSet 0.25～120 80 0.01 V
10 FreqARPulseSet 0.08～0.5 0.5 0.01 s
11 FreqARRstTime 1～1200 1200 0.01 s
12 FreqARBlkTime 1～1200 1 0.01 s
Table 149 Frequency auto-reclosing logic switch

Default
Number Logic switch description Setting Remark
value
1 FreqARStage1On 1/0 0
3.3 Report list


Trip report:
1 FreqARStage1Trip /

Table 151 Technical parameter list

+60ms
186
Chapter 31 Secondary circuit monitoring
Chapter 31 Secondary circuit

monitoring
About this chapter

This chapter describes CT failure and VT failure secondary
circuit monitoring function.
187
1 CT failure
1.1 Overview
Current transformer failure or short circuit can cause earth fault protection
and negative sequence current protection maloperation.
If there is no protection trip when CT disconnection occurs, it will produce a
very high voltage to cause damage to the secondary circuit. In order to
prevent the device from maloperation, the device monitors the sudden
change of the current of the secondary circuit of the current transformer
and alarms.
1.2 Function module description

CT failure check function input and output signal diagram is shown as
follow:
CT-Secondary Current Supervision
1
CTFail
Figure 73 Diagram of input and output signals of CT failure check function

right.

Output:
CTFail
Alarm IED alarm
1.3 Detailed description

1.3.1 Protection principle
When the self-produce zero sequence current exceeds "CTFail3I0Set ", it
sends off the report "CTFailAlm" and the earth fault protection is blocking
through the delay of "CTFailTime". LED, IED output and others can be
configured by AESP after the alarm report is issued.
Enable CT failure protection function
“CTFailAlarmOn”=1
&
T
CTFailureAlarm
InstantVTFail
calculated 3I0>“CTFail3I0Set”
T：“CTFailTime”
Figure 74 CT failure protection logic diagram
188
1.3.2 Setting list

Table 153 CT failure detection setting
Default
value
1 CTFail3I0Set 0.05In～10In 1 0.01 A
2 CTFailTime 0.1～100 100 0.01 s
Table 154 CT failure detection logic switch

Number Remark
Enabled and disabled CT
1 CTFailAlarmOn 1/0 0
failure alarm function
1.3.3 Report list


Alarm report:
1 CTFailureAlarm /
2 VT failure
2.1 Overview
When the secondary circuit of the voltage transformer is broken or short
circuit, the measured voltage is zero by the protections based on the
undervoltage criterion and this can cause the maloperation of IED. VT
failure check provides voltage monitoring for such protections. VT
monitoring is used to monitor the voltage transformer circuit, single-phase
VT failure, 2-phase VT failure and three-phase VT failure. Main
characteristics are as follow:
1) Symmetric / asymmetric VT failure;
2) Three-phase AC voltage miniature transformer failure monitoring;
3) It is used in earthing system, non-direct earthing system and
unearthinged system.

VT failure check function input and output signal diagram is shown as
follow:
Symmetrical and asymmetrical
VT Fuse Fail Detection
1 1
V3P_BI VTFail_TI
2
VTFail
3
V3P_BI_Err
Figure 75 VT failure detection function input and output signal diagram

right.
189

Input:
V3P_BI Three-phase VT failure BI
VTFail Output:
VTFail_TI Instantaneous VT failure
VTFail VT failure alarm

2.3.1 Protection principle
2.3.1.1 VT abnormal detection at busbar side
Busbar side VT anomaly check is used to detect single phase fault, two phase
fault or three phase dead voltage fault in busbar VT circuit. When one of the
two conditions is satisfied, the device delay confirmation report "VTFail", the
default time setting is 10s.
a) The positive sequence voltage U1 is less than 18V and the current is
greater than the dead current threshold;
b) Negative sequence voltage U2 is greater than 8V;
Any phase has live

current
&
Positive sequence
voltageU1<18V
>=1 InstantVTFail
&
Negative sequence
voltageU2>8V
>=1 VTFailOn=1
T VTFailAlarm
IED startup
3PhVTFailBI &
PPVoltMinVal>VTFailPPVoltSet
T:“VTFailAlarmTime”
Figure 76 Logic diagram of busbar side VT failure protection
3PhVTFailBI &
T_Err 3PhVTFailErrBIAlarm
PPVoltMinVal>VTFailPPVoltSet
T_Err:“VTFailBIErrAlarmTime”
Figure 77 Logic diagram of busbar side binary input VT failure protection

VT failure function can be enabled or disable by setting the logic switch
"VTFailOn", when the logic switch "VTFailOn" is set as 1, VT failure protection
is enabled.
190
2.3.1.2 Extraction line side VT anomaly detection

If the logic switch "VTFailOn" is enabled and U4 VT failure input, then
"U4VTFailAlarm" will be sent through "VTFailAlarmTime".
2.3.2 Setting list

Table 157 VT failure setting
Default
value
1 VTFailAlarmTime 0.04～100 10 0.01 s
2 VTFailBIErrAlarmTime 0~100 10 0.01 s
3 VTFailPPVoltSet 10～30 16 0.01 V
Table 158 VT failure detection logic switch

Number Remark
1 VTFailOn 1/0 0 VT failure on or off
To 0: VT failure blocking requirement
2 VTFailProtOff 1/0 0 retreat
To 1: VT failure blocking protection
2.3.3 Report list


Alarm report:
1 InstantVTFail /
2 VTFailAlarm /
3 3PhVTFailErrBIAlarm /
4 InstantU4VTFailAlarm /
5 U4VTFailAlarm /
191
Chapter 32 User-defined function
About this chapter

This chapter describes BI, BO, LED configuration and user
defined logic function.
193
1 Overview
The BI, BO, report, LED of device can be enacted secondary user defined
by engineer according to demand. According to the actual situation of the
project, the user can define the logic. This chapter mainly describes the
function of the AESPStudio tool software which may be used in
engineering application to perform the user defined function and the
matters needing attention.
2 User-defined configuration
2.1 Open project
Click the file→open, in the open file dialog box, open the file named
aespro.
2.2 Binary input configuration

The title of BI can be modified by engineering example. The property of
each binary input can be set in binary input configuration according to
demand.
Table 160 Binary input configuration
Binary input configuration

Configuration item Description
Excitation changes from 0 to 1, close position of binary input 1 is
Binary input time delay 1
confirmed after binary input time 1
Excitation changes from 0 to 1, open position of binary input 1 is
Binary input time delay 2
confirmed after binary input time 2
Set of disturbance and
Configure "DFR", "RisingEdgeTrigger" and "FallingEdgeTrigger"
fault record
Configuration "SirenBit", "BellBit", "PulseQuantity", "SendSOE",
Property 1
"DualPosnBI", "ACInput" and "BCUProtocol"
Configure "NonSmartModule", "24V", "48V", "110V", "125V",
Property 2
"220V", "250V".
Property 3 Configure "OrdinaryBI", "MaintState", "Rmt/Local", "Invalid"
Bay control unit and
Configure "Prot", "BCU"
protection property
Note: when disturbance and fault record setting, the configuration of "DFR"
means that the BI will be in disturbance and fault record. If
"RisingEdgeTrigger" is configured, when the BI changes from 0 into 1, the
disturbance and fault record will be generated. If "FallingEdgeTrigger" is
configured, when the BI changes from 1 into 0, the disturbance and fault
record will be generated. The generated disturbance and fault record file
will be saved into the list of startup disturbance and fault records.
The work voltage can only be configured within ranges defined by this
module unit. Hardware module contains high power voltage level and low
power voltage level, respectively marked with the work voltage of DC "110V",
"125V", "220V", "250V" and "24V", "48V".
The explanation of time sequence of "BITime1" and "BITime2" is shown as
follow.
194
Excitation
Binary input time

delay1
Binary input
Binary input time delay2
Figure 78 Binary input time delay sequence

Configuration way of double position binary input:
Two single-position binary inputs can be used to describe the
double-position binary input, and the close position of single input
accesses to the n hardware binary input, and then the open position of
single input accesses to the n+1 hardware binary input. "DualPosnBI" can
be selected for the property 1 of binary input n; but it cannot be selected for
the property 1 of binary input n+1; and "Invalid" can be selected for the
property 3.
The logic state of a pair of binary inputs (binary input n and n+1)
configured with double-position will no longer be that of the hardware
binary input. Only when (hardware binary input n, n+1) = (1, 0), the logic
binary input n refers to the close position state; only when (hardware
binary input n, n+1) = (0, 0) or (1, 1), the property of double-position of
binary input is 1, which means the invalid state.
Both the BI state and BI state in IO Matrix of double-position hardware BI
and logic BI are shown as follow:
Table 161 State list for hardware binary input of double position and logic binary input
Binary input of hardware (binary
0，0 0，1 1，0 1，1
input n, binary input n+1)
Logic binary input (binary input n,
0，1 0，0 1，0 0，1
binary input n+1)
2.3 Binary output configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand.
Table 162 Binary output configuration
Binary output configuration

Configuration item Description
Latched time Excitation resets and binary output also resets after latched time.
Set of disturbance
Configure "DFR", "RisingEdgeTrigger" and "FallingEdgeTrigger"
and fault record
Binary output Configure "ElectricLatched", "TripRedundancy",
property "ReclaimRedundancy", "BlkedByStartup", "NCContact"
To configure "ElectricLatched" property, the electric relay will return only
after the signals reset. The movement sequence is shown as follow. When
the device is deenergized and then reenergized, the electric relay can
recover the state before power down.
195
Excitation
Reset
Relay
Figure 79 Electric latched relay trip sequence

Configuration is the node of electric retention, which can't
"BlkedByStartup" ; otherwise startup relay will return and so does BI.
Non "ElectricLatched" binary output can configure "LatchedTime",
excitation will return, after the set time, the relay returns.
Excitation
Relay
Figure 80 Non-electric latched relay trip sequence

Please configure in line with the hardware jumper of BO, and determine
whether BO is "BlkedByStartup" or not, and whether "NCContact" or not.
As CPU and other redundant CPU will send off command; the
configuration as "BORedundancy" of node relay trips; as CPU and other
redundant CPU retreat all the command, the configuration as
"ReclaimRedundancy" of node relay will trip. If the protection configuration
does not configure redundancy, "ReclaimRedundancy" and
"BORedundancy" can't be set.
See Figure 81 , one of configuration properties of BO "BlkedByStartup"
must be linked with the contact of hardware, and every three BOs shall
form a group to be configured similarly. Which means BO1, BO2 and BO3
shall form a group; BO4, BO5 and BO6 form a group and so on.
Figure 81 Diagram of binary output configuration
2.4 LED configuration

The title of LED can be modified by engineering example. On control plate,
the calibrated LED indicator light tag can be embedded into the
corresponding position of the indicator light . The property of each LED
can be set in LED configuration according to demand.
196
Table 163 Light configuration.
Light configuration.
Configuration
Description
item
Latched Configure "Latched" and "Unlatched", and when the configuration is
property "Latched", reset operation should be performed to clear the LED state.
LED color The colors of LED are "yellow", "green" and "red"
The LED is flashing or constant on, n represents the flash frequency is
Flashing
n*50ms; when it is 0 or 1, the LED is always on.
As the configuration is "Redundancy" property, multiple CPU will trigger
Redundancy
light at the same time and the LED will be lit.
As CPU and other redundant CPU all send out lighting commands, the
LED configured with "Redundancy" can be lit. If LED does not have
redundancy property, "Redundancy" property cannot be set.
2.5 IO Matrix configuration

The IO Matrix achieves a fast correlation between virtual and real points in
the software. Virtual point comes from the application software,
corresponding to the functional software to modify the data points, the real
point from the limited resources provided by the device.
2.5.1 AC IO configuration
AC IO configuration is used to specify the source of the required input
information for the application, the AC or DC excitation of the device is
configured as AC module sampling or SV data.
“X” refers to the valid selection.
Figure 82 Diagram of channel configuration
2.5.2 Digital IO configuration

The digital IO configuration is used to specify the protection trip of the
device. External binary input signal that each function of the device
depends on and external manifestations of trip including the binary output
and the lights, etc., are achieved through the configuration.
“H” refers to the valid high power level, “L” refers to the valid low power
197
level.
Figure 83 Diagram of function configuration
2.6 Binary input switches setting group

2.6.1 Function description
IED can switch the setting group in two ways. When the setting
"BISwitchSetGrp" is set as 0, IED will response to the faceplate or SCADA
to switch the setting group; when the setting "BISwitchSetGrp" is set as 1,
IED will not response to the faceplate or SCADA to switch the setting
group, it will switch the setting group automatically according to the status
of binary input.
The device provides four default configurable binary inputs to switch
setting group, in BIToSetGrp, BI1, BI2, BI3, and BI4 can be set by users in
the engineering research and development version
Table 164 Four binary input switch setting group configuration examples
Number BIToSetGrp4/2/1 Setting group

1 0000 1
2 0001 2
3 0010 3
4 0011 4
5 0100 5
6 0101 6
7 0110 7
8 0111 8
9 1000 9
10 1001 10
11 1010 11
12 1011 12
13 1100 13
14 1101 14
15 1110 15
16 1111 16
If the various BI groups designate target setting group randomly, and the
user-defined logic of engineering research and development is realized,
then write the target setting group to **::ChangeSettingGrp.InSettingZone.
198
IED provides up to 32 setting groups.
Figure 84 Diagram of binary input switch setting group configuration
2.6.2 Setting list

Table 165 Logic switch of binary input switching setting group diagram
Logic switch Logic switch Setting Default
Number Remark
mark description Mode value
Binary input switches
1 BISetGrp 1/0 0
setting group
2.7 Startup configuration

The configuration of digital IO offers a settable startup trip to decide
whether the protection trip of IED should be blocked by starting. Taking the
overcurrent stage 1 as an example, see Figure 85 :
Figure 85 Diagram of initiated blocking configuration

Protection trip of overcurrent stage 1 is configured via startup relay
blocking:
The corresponding Start of OC1 is the startup trip of overcurrent stage 1,
which is connected with the node PickupContact of startup relay, and the
output of binary input and output module is set as initiated by jumper.
199
Figure 86 Diagram of non-initiating blocking configuration

Protection trip of overcurrent stage 1 is configured without startup relay
blocking:
The corresponding Start of OC1 does not connect with the node
PickupContact of startup relay, and the output of binary input and output
module is not set as initiated by jumper.
If the IED trip of overcurrent stage 1 does not connect with the node
PickupContact of startup relay, but the output of binary input and output
module is set as initiated by jumper, then the output of overcurrent stage 1
will be blocked.
2.8 Other configurations

The name of the device can be changed according to the requirements of
the project, and it can be named in accordance with the project schedule,
so as to facilitate the maintenance of the project.
The default length of waveform recording file generated by IED is 2.5
cycles before fault and 20 cycles before and after the fault together. It
supports to instantiate RS_WAVEPARAM by AESP tool and the users can
define the length of waveform records according to their needs. The length
of single waveform record cannot be greater than 200ms before fault, the
total length of waveform records cannot be greater than 20s. Single
disturbance and fault record cannot be greater than 512k.
Figure 87 Setting configuration figure
200
2.9 Defined logic

The AESP tool provides the basic elements of the module to support
user-defined simple engineering logic. The intermediate data and the
intermediate nodes in the application software which is open to the user
can be used conveniently in the configuration interface, and the logical
application of the project is realized.
Figure 88 AESPStudio working interface
2.10 Connector attribute change

The AESP tool provides the basic elements of the module to support
user-defined simple engineering logic. The intermediate data and the
intermediate nodes in the application software which is open to the user
can be used conveniently in the configuration interface, and the logical
application of the project is realized.
The stabilization time of all hard connector is 10s, which is not
configurable.
Figure 89 Example of connector attribute change
201
Chapter 33 Control function
About this chapter

This chapter describes the control functions, including the
select before operation and control functions. The required
control functions can be configured according to the
requirements of the project.
203
1 CB/Isolator control
1.1 Overview
The CB/Isolator control function is used to control the opening and closing
operation of the circuit breaker or the isolator or the earth switch, and the
control objects can be added according to the different bay requirement.

Input and output signals of telecontrol function of circuit breaker and
isolator are shown below:
CB/Isolator Control
1 1
OpenPermit OpenBO
2 2
ClosePermit CloseBO
3
BIState
Figure 90 The diagram of input and output signals of CB/Isolator control function
right.

Input:
OpenPermit Open permission of object
ClosePermit Close permission of object
CB/ISO Control BIState Binary input state of double position
Output:
OpenBO Open command
CloseBO Close command

Object pre-selection operation is required before executing the SBO
(Select before operation) command.
The Object is blocked by the remote/local state. When the device is in the
remote state, it is only remotely controllable; when the device is in the local
state, it is only locally controllable.
The opening of object permission and closing of object permission can be
connected to the interlock signal or the permission logic of user-defined
opening/closing object.
The object can be configured for position check. When using the check
function, the input state of dual position needs to be connected to the
function block. If the check is not selected, it can provide open and close
command without the position check.
204
When using position check, if the input position state match with control
command send, IED will return success, if not return fail after 30s.
2 Direct control
2.1 Overview
Direct control can be used for directly controlled objects, such as
intermediate relay reset or any free output command without pre-selection.

Input and output signals of direct control function are shown as follow:
Direct Control
1
OpenBO
2
CloseBO
Figure 91 The diagram of input and output signals of direct control function
right.

Output:
Direct Control OpenBO Open command
CloseBO Close command

The direct control does not require a pre-selection and is directly execute
operation.
The direct control is blocked by the remote/local state. When the device is
in the remote state, it is only remotely controllable; when the device is in
the local state, it is only locally controllable.
3 Tap control
3.1 Overview
The tap control is used to control the tap position of the transformer to
perform the operation of rise, low and stop.

Input and output signals of direct control function are shown as follow:
205
Tap Control
1 1
Permit TapUpBO
2 2
ATap TapDnBO
3 3
BTap TapStopBO
4
CTap
Figure 92 Input and output signal diagram of tap control

right.

Input:
Permit Allowable voltage adjustment
ATap Phase A position
BTap Phase B position
Tap Control CTap Phase C position
Output:
TapUpBO Tap rise
TapDnBO Tap low
TapStopBO Tap stop

The tap control is blocked by the remote/local state. When the device is in
the remote state, it is only remotely controllable; when the device is in the
local state, it is only locally controllable.
4 Report list

Operation report:
1 TelectrlObject /
2 TelectrlCmdSrc /
3 TelectrlResult /
4 TelectrlCmd /
5 TelectrlType /
6 FailReason /
206
Chapter 34 Substation communication
Chapter 34 Substation
communication
About this chapter

This chapter describes functions such as substation
communication interface and protocol, time synchronization
and so on.
207
1 Overview
Each IED provides communication port to communicate with one or more
substation system. IED supports following communication protocols:
1) Communication protocol IEC 61850-8-1;
2) IEC 60870-5-103 communication protocol;
3) DNP 3.0
4) MODBUS。
1.1 Communication protocol

1.1.1 IEC 61850-8-1 communication protocol
Protocol IEC61850-8 allows two or more IED in one or more factories to
communicate and cooperate on the basis of their functions.
Standard IEC 61850-8-1 rules GOOSE (generic object of substation event).
By publishing and subscribing mechanism, GOOSE standardizes
communication state and control information between IEDs. That is to say,
if fault is detected to happen, IED shall send information to devices which
have subscribed the event by multi cast.
1.1.2 Communication protocol IEC 60870-5-103
Protocol IEC 60870-5-103 belongs to master-slave mode and
communicates to control system through serial port. According to IEC rules,
main station is the master and substation is the slave. Communication is
carried out on the basis of point-to-point principle. Main station should be
equipped with the software that is able to receive IEC 60870-5-103
communication report. For a more comprehensive understanding of the
IEC60870-5-103 protocol, you can refer to the fifth part of " IEC60870
standard": 103 section of "communication protocol": "the standard of
information communication interface for IED protection".
1.2 Communication port

1.2.1 Faceplate communication port
Faceplates of all IEDs have a RJ45 communication port respectively. By
this port, users can use PC to operate Sifang debug software to connect
IED for setting, testing, configuring and so on.
1.2.2 RS485 communication port
The IED provides two electric RS485 communication ports to connect
substation automatic system. The port supports protocol IEC60870-5-103.
1.2.3 Synchronization port
IED provides one Ethernet port as time synchronization port.
1.2.4 Ethernet communication port
IED provides two Ethernet ports to connect to substation automatic
system.
208
Table 170 Faceplate communication port
Items Data
Number 1
Connection mode RJ45 port for debugging software
Communication rate 100Mbit/s
Table 171 RS485 communication port
Items Data
Number 2
By two conducting wires
Connection mode
Communication port of backplate
Maximum communication distance 1.0km
Test voltage 500V AC earthing
Supporting protocol IEC 60870-5-103
Parameter is set as 9600 baud,
Communication rate Minimum 1200 baud rate, maximum 19200
baud rate
Table 172 Ethernet communication port
Items Data
Ethernet communication port
Number 2
Cable or optical fibers/backplate
Connection mode
communication port
Maximum communication distance 100m
Support IEC 61850 protocol
Supporting protocol IEC 60870-5-103
Table 173 Time synchronization port
Items Data
Time synchronization mode Pulse or optical signal time synchronization
IRIG-B signal format IRIG-B000
Connected by two conductors or optical fibers
Connection mode
Communication port of backplate
Voltage level Differential signal
209
1.4 Typical substation communication mode

Through communication protocols supported by communication port, IED
is able to communicate with one or more substation system or device.
Figure 93 Multiple network substation automatic system connection case
1.5 Typical time synchronization mode

All IEDs provide a time synchronization port, it is able to choose
IRIG-IRIG-B or pulse time synchronization. For pulse time synchronization,
IED can automatically adapt to second or minute pulse time
synchronization mode. Meanwhile IED could adopt SNTP mode to
synchronize.
Figure 94 Time synchronization mode
210
Chapter 35 Man-machine interface (MMI) and operation
Chapter 35 Man-machine interface

(MMI) and operation
About this chapter

This chapter describes the relative display of man-machine
interface and its operation.
211
1 Overview
The MMI is composed of liquid crystal display (LCD), LED, faceplate
buttons and faceplate Ethernet port. Users can view information, set
parameters and debug through MMI.
2 Function description
2.1 Liquid crystal display (LCD)
The LCD back light of HMI is blue, 9 lines can be displayed. When
operating Sifang key or IED issuing alarm or trip report, background blue
light automatically lights up. Soon after the latest trip or alarm, background
blue light dies out after 5 minutes of time setting.
2.2 Man-machine interface (MMI)

MMI is man-machine interface. LCD screen displays the device running
information, such as measured value for current and voltage, connector
state and BI, BO and bay signal line diagram.
If there is no key operation, the MMI main cycle interface shows part of
device information in a cycle way. Users can press “ ” button to lock the
present display and press “ ” again to return to the cycle display state.
Take 19/2 inches enclosure of multi-fuction protection IED as an example,
the description of faceplate area is as follow: zone one is for the
user-defined indicator light area; zone two is for the key area of the
control function; zone three is for the debugging of net port; zone four is for
the key district of the basic key.
CSC-211
Figure 95 MMI module schematic diagram
212
The customized indicator light area consists of 24 lights, where the position
of running lights and alarm light are fixed, and the functions of other 22 lamps
can carry out the configuration of light color, light property according to the
needs of the user; in key areas, there is indicator light indicating device state
on each of the remote, local and blocking key respectively.
RUN: When running indicator light, the green light is lightened during the
normal operation, while the running light is off if there is an alarm of class
1.
ALARM: alarm indicator light . The device alarm lightens the red light.
The faceplate uses the Ethernet port to connect PC and device, which
supports setting device parameter, measuring function, downloading
programs and analyzing data. The debugging IP address of Ethernet port is
196.178.111.1 which is unchangeable.
The key includes basic key and control functional key. Basic keys are on the
right of the screen and control functional keys are below the screen to realize
human-computer interaction. Keys for IED of CSC series contain the same
appearance and operation mode, for details in the table as follow.
Table 174 IED MMI key
Key Function
Move to the next line in menu
Move to the next line in menu
Move left in the menu
Move right in the menu
 Reset LED light

 Directly back to normal circulation display interface
 Entering main menu or sub-menu

 Confirm that you want to change the settings.
 Back to up one level

 Exiting and revising setting
 Back to circulation display interface
 Locking or unlocking circulation display interface (when
locking, top right corner of LCD displays an icon of a small key)
 Value adds 1
+ 

Page down
Logic switch shift from the present value to the opposite value;
namely "1" to "0", or "0" to "1"
 Value minus 1
- 

Page up
Logic switch shift from the present value to the opposite value;
namely "1" to "0", or "0" to "1"
213
Key Function
F1 F2  User-defined function key

 The shortcuts for menu options are able to set to relate with
menu items to execute functions of this menu.
F3 F4  as the input signal to participate in logic
 Switching to remote operation mode, and earthing control

shall be blocked.
 Switching to earthing control mode, remote operation shall be
blocked.
 It is used for locking and unlocking control key and
user-defined key so as to prevent mistakenly touching.
 Breaker closes
 Breaker opens
2.3 Menu structure

Through the MMI key, you can enter the IED menu, view information or
perform related operations. Due to the differences in the function of
various type of IED, the following lists show the maximum menu
configuration; the value of related setting information and various type of
IED is on the basis of actual display.
Table 175 Device menu
L1 menu L2 menu L3 menu L4 menu Description

Read the measure input
PriVal
primary-value of the IED
Analog quantity
SecVal
second-value of the IED
PriVal
primary-value of the IED
Measure
SecVal
second-value of the IED
Read the analog input of the
AnalogInput
IED
Read the power metering of
PowerMeter
the IED
Read the binary input of the
IEDState ConventionalBI
IED
ViewInfo Read the original binary input
BIO GOOSE OriginBI
state of GOOSE
Read the binary output of the
ConventionalBO
IED
Read state information of
GOOSESubState
GOOSE subscription
GOState
Read state information of
GOOSEPubState
GOOSE publishing
Read state information of the
StateMon
IED
Read the current alarm
AlarmInfo
information
ProtSet Read the IED setting
ViewSet Read the equipment
EquipParm
parameters
214
Read the parameter of bay
BCUParm
control unit
Read the function connector
FcnConn
information
Read connector state
GOOSEPubSoftConn information of GOOSE
ConnState
publishing
Read connector state
GOOSESubSoftConn information of GOOSE
subscription
IED IDCode Read the unique code of IED
Read the version information
VerInfo IEDVer
of IED
Read the check code of
VrTrmlChkCode
virtual terminal
Read the synchronization
TimeSyncMode
mode of IED
IEDSet
Read the Ethernet
CommParm EthernetSet
information of IED
FcnConn Set function connector state
Set state information of
ConnOn/Off GOOSEPubSoftConn
GOOSE publishing
Set state information of
GOOSESubSoftConn
GOOSE subscription
Switch present operation
RunOper SwitchSetGrp
setting group
Local control telecontrol
LocalCtrl
object
Bay single line diagram
Bay0
SLDCtrl control
…
GenlRpt Read general report
StartupRpt Read the startup report
TripRpt Read the trip report
AlarmRpt Read the alarm report
ViewRpt
OperRpt Read the operation report
BIChgRpt Read the BI change report
Startup disturbance and fault
StartupDFRList
record shown in list
Trip disturbance and fault
TripDFRList
record shown in list
ProtSet ProtSet Setting the ProtSet
CopySetGroup Copy setting of setting group
Set substation name. It uses
Unicode encoding, with a
StationName
maximum input of 24
characters.
WriteSet Set the protected equipment
EquipParm
name. It uses Unicode
ProtEquipName
encoding, with a maximum
input of 24 characters.
EquipParm Set equipment parameters
Set parameter of bay control
BCUParm
unit
TestMenu BOTest ConventionalBO Test the BO contacts
215
GOOSE BO Test GOOSE signal
FnAlarmChk
TripRepChk
GOAlarmChk
BIChk
CommChk Test communication signal
MSTAlarmChk
ConnChk
AnalogChk
MeasureChk
LEDTest Test LED light
Manual triggering to
MC DFR generate fault and
disturbance record
ViewZeroDrift
ViewScale
FactoryTest AdjZeroDrift
AdjScale
AngleCorrection
ProtSet
SoftConn
Analog quantity
SampleVal
IEDState BIO
ConnState
Print VerInfo Print various information
StartupRpt
TripRpt
Rpt AlarmRpt
OperRpt
BIChgRpt
IEDSet
SetClock Set time
Choose synchronization
TimeSyncMode
mode
NetTimeSyncIPSet
TimeSet
SetTimeZone
IEDSet
Mode 1
DST Set daylight saving time
Mode 2
Set the Ethernet information
EthernetSet
CommParm of IED
IEDAddr Set IED address
216
SetSerial1
SetSerialPort SetSerial2 Set serial port parameters
SetSerial3
ProtocolSet Set the protocol information
PRPSet
Set IED name. It uses
Unicode encoding, with a
IEDName
maximum input of 24
characters.
SetPassword Set IED password
Contrast Set the contrast
Set report parameters and
OtherSet the mode that sending
DisplayMode
primary-secondary value to
SCADA
PowerMeterZeroing Set the power metering as 0
CHN Confirm
SetLanguage ENG Confirm Language
RUS Confirm
Click the key in the recycle main interface, the menu tree will be
shown in the MMI interface; click the key or to select menu items,
when the cursor stays in the corresponding menu item, if there is a symbol
"" behind this menu item, it can click the key or to enter the next
menu; if there is no signal "", it can click the key to enter the menu
items.
SIFANG 2017-10-01 21:30:1D
IEDState  Calc  ConventionalBI

GOOriginBI
ViewSet  Measure 
ConventionalBO
ConState  Analog
VerInfo  PowerMetr
BIO 
ViewInfo  IEDSet 
GOOSEState
Operate  StateMon
ViewRpt  AlarmInfo
WriteSet 
TestMenu
IEDSet 
Language 
PresentSetGrpNo.:
Figure 96 Menu tree diagram

The following diagram is an example of "ConventionalBO" menu.
217
BO 1/2
IEDFaultAlarm 0
RunErrAlarm 0
X9_BO3 0
X9_BO4 0
X8_BO1 0
X8_BO2 0
X8_BO3 0
X8_BO4 0
X8_BO5 0
Figure 97 Menu diagram
218
Chapter 36 Hardware
Chapter 36 Hardware
About this chapter

This chapter describes hardware for device.
219
Chapter 36 Hardware
1 Overview
1.1 IED structure
Height for IED crate is 4U and width is 19 2 inches. The whole is for
embedded installation with back-wiring mode.
Figure 98 Installation size diagram (unit mm)

1) Faceplate for IED is casted by aluminum alloy and able to downward
turn. LCD, LED and setting keys are mounted on the plate. There is a
RJ45 interface on the faceplate suitable for connecting a PC;
2) Plug in or plug out the module on the backplate, module is fixed by
screw spike;
3) Module is connected through bus of backplate.
220
Chapter 36 Hardware
1.2 Module arrangement diagram
Figure 99 IED backplate module layout diagram
2 Analog input module

2.1 Overview
AC module contains voltage and current transformers. The module
converts two-side current and voltage to processable signal for IED data
acquisition system and serves as electrical isolation. IED in different type
shall be with different current and voltage transformers. The module is
optional according to different project requirements.
2.2 Analog input moduleintroduction

The following figure shows the AC module terminal diagram of a certain
type of configuration, the module supports the access of four channels of
protective current, one measuring voltage and four channels of voltage.
The 4 channels of protection current channels Ia, Ib, Ic, I0 support 1A or
rated 5A current access, and each current channel provides 3 wiring terminals.
The terminal identification without ' suffix is shared inlet positive terminal, while
that with' suffix is the outlet negative terminal. For example, the use of rated
1A shift of Ia should access the amount of current from the Ia terminal to
the Ia_1’ terminal, with Ia_5 ' terminal suspended; the use of rated 5A shift
should access the amount of current from the Ia terminal to Ia_5' terminal
with the Ia_1' terminal suspended; the wiring principle of other protection
type of current channels is same.
The Is is below figure is the measurement type of current channel, which is
automatically compatible rated input of 1A/5A, and the terminal identification
without ' suffix is shared inlet positive terminal, while that with' suffix is the
outlet negative terminal, which should access the amount of current from the
Is terminal to Is' terminal.
221
Chapter 36 Hardware
U4, Ua, Ub, Uc in the following figure are voltage channels, and the terminal
identification without ' suffix is shared inlet positive terminal, while that with'
suffix is the outlet negative terminal. During VV wiring, b10~b12 and a11 are
short connected, and phase b voltage is connected to b10.
Figure 100 AC module terminal diagram

Table 176 Current transformer parameter
Implementation
Items Data
standards
Rated current IEC 60255-1 1A or 5A:
Sampling range for Protection CT is 0.05 In to 40
conventional current In, while measurement CT is
transformer 0.05 In to 2 In.
Sampling range for high
0.005 to 1.2A
sensitive current transformer
Power consumption (each ≤ 0.05VA when In=1A;
phase) ≤0.25VA when In=1A;
Thermal overload capacity of
IEC 60255-1 100In overload 1s:
conventional current
IEC 60255-27 Continuous 4 In
transformer
Thermal overload capacity for
IEC 60255-27 80A, load for 1S
high sensitive current
DL/T 478-2013 2A, continuous
transformer
222
Chapter 36 Hardware
Table 177 Voltage transformer parameter
Implementation
Items Data
standards
Rated voltage Vr
IEC 60255-1 100V/110V
(phase-to-phase voltage)
Sampling range
0.4V～180V
(phase-to-earth voltage)
Power consumption (Vr = IEC 60255-27
≤0.05VA each phase
110V) DL/T 478-2013
Thermal overload capacity IEC 60255-27 400V overload 60s
(phase voltage) DL/T 478-2013 200V, continuous
3 Binary input and output module

3.1 Overview
Binary input and output module provides certain of protection tripping and
closing control so as to realize tele-control opening and closing of the circuit
breaker and isolator.
The BI and BO of the hardware of binary input and output module include two
types of soldering : 1) Strong power level, self-adapting 110V, 220V, 125V,
250V and 2) low power voltage level, adaptive 24V and 48V. Work rated
power source of device BI is modified by configuration file before applying.
3.2 Binary input and output moduleintroduction

There are three indicator lights on the binary input and output faceplate to
show the status of the board, the indicator light definition is shown in the
following table.
Table 178 Definition of binary input and output module indicator light
The serial number Indicator light
Introduction of indicator light state
of indicator light function
1 Power supply light Light is on when device is energized
2 Running light Flash when work properly
3 Reserved Off
According to the different slot locations of the binary input and output
module, different module addresses need to be set, and address is set
through jumper J6. Take the side away from single board as L side, the
side near single board as H side, from bottom to top are AD0, AD1, AD2
and AD3.
Table 179 Definition of binary input and output module address
Slot
Jumper Control content Jumper settings
location
Binary input and
BIO1 J6 AD3~AD0 are short connected to the L side
output1 address
Binary input and AD3~AD1 are short connected to the L side,
BIO2 J6
output2 address AD0 is short connected to the H side
Binary input and AD3, AD2, AD0 are short connected to the L
BIO3 J6
output3 address side, AD1 is short connected to the H side
Binary input and AD3 and AD2 are connected to the L side,
BIO4 J6
output4 address AD1 and AD0 are connected to the H side
Each binary input and output board has 6 binary inputs and 12 binary
223
Chapter 36 Hardware
outputs. 6 BIs are divided into 2 groups, and each of 3 BIs shares a
common terminal.
12 binary outputs are divided into 4 groups, each group can be set
as startup blocking or not startup blocking by changing the jumper position,
there are total four groups of jumpers J11~J14. The jumper inserting into 1,
2 pin represents that binary output is blocked by startup relay, inserting
into 2, 3 pin represents that binary output is unblocked by startup relay.
Table 180 Description 1 for jumper of binary input and output module
The definition of
address jumper of
Binary output 1 and 2 pin 2 and 3 pin
binary input and
output module
J11 BO1～BO3 Startup blocking Not startup blocking
BO12 can switch normally open or normally closed contact by JP1 jumper,
when the jumper jumps to NC side, it is normally closed contact, when the
jumper jumps to NO side, it is normally open contact.
Table 181 Description 2 for jumper of binary input and output module
Jumper Binary output NC NO

JP1 BO12 Normally closed contact Normally open contact
224
Chapter 36 Hardware
BIO
1 2 3
c a
2 BO1
4 BO2
6 BO3
BINARY OUTPUT
8 BO4
10 BO5
12 BO6
14 BO7
16 BO8
18 BO9
20 BO10
22 BO11
24 BO12
26 BI4 BI1
BINARY INPUT
28 BI5 BI2
30 BI6 BI3
32 COM2 COM1
Figure 101 Binary input and output module terminal diagram

Table 182 BI parameter
Implementation
Items Data
standards
110V/125V/220V/250V DC
Rated voltage IEC 60255-1
24V/48V DC
Startup voltage IEC 60255-1 70%Ur, rated DC 24V/48V, 110V/125V/220V/250V;
Return voltage IEC 60255-1 55%Ur, rated DC 24V/48V, 110V/125V/220V/250V;

The maximum BI 286V, rated DC voltage 110V/125V/220V/250V;
IEC 60255-1
voltage 62V, rated DC voltage 24V/48V;
Maximum 0.5W/input, typical 0.15W/input, 110V
Power consumption IEC 60255-1 DC
Maximum 1W/input, typical 0.6W/input, 220V DC
Table 183 BO parameter
Implementation
Items Data
standards
Maximum work voltage IEC 60255-1 250V AC
5A continuous,
Impact overcurrent capacity IEC 60255-1
30A, 200msON,15sOFF
225
Chapter 36 Hardware
Implementation
Items Data
standards
1100W(DC) at inductive load L/R>40 ms
Closing capacity IEC 60255-1
1000VA(AC)
220V(DC), 0.15A, L/R≤40ms
Arc breaking capacity IEC 60255-1
110V(AC),0.30A, L/R≤40ms
50,000,000 times (switching frequency is
Electrical life IEC 60255-1
3HZ)
Opening times IEC 60255-1 ≥1000 times
Closing times IEC 60255-1 ≥1000 times
IEC 60255-1
Authentication IEC 60255-23 UL/CSA, TŰV
IEC 61810-1
IEC 60255-1
Contact circuit resistance IEC 60255-23 30mΩ
IEC 61810-1
Contact insulation test (AC IEC 60255-1
AC1000V, 1min
dielectric strength ) IEC 60255-27
Maximum temperature
IEC 60255-1 70℃
operation allows
4 CPU module
4.1 Overview
CPU module is core of the IED and responsible for running all protection
logic, hardware self-check and device communication for external devices
such as MMI, PC, measurement, substation automatic system, working
station, RTU, printers and so on. Besides, CPU module sends telemetry,
telesignalisation, SOE, event report and recorded wave to backstage, it
provides time synchronization and communication port.
CPU module provides multiple configuration for user's need. Differences
lie in quantities for Ethernet port, optical/electric port, time synchronization
mode, storage capacity and so on.
4.2 CPU moduleintroduction

The CPU module faceplate has six indication light to indicate the operation
state of the board and the definition of indication light is shown as follow
table.
Table 184 Definition of indication light of CPU module
The serial number
Indicator light function Introduction of indicator light state
of indicator light
Faceplate Ethernet 1 Flash when communicating normally while
1
indicator light close when communicating abnormally
Faceplate Ethernet 2 Flash when communicating normally while
2
indicator light close when communicating abnormally
3 Reserved /
Flash when operating normally while close
4 Running LED of CPU
when operating abnormally
5 Reserved /
6 Reserved /
226
Chapter 36 Hardware
CPU
1 2 3
4 5 6
ETH1
ETH2
PULSE- 1
PULSE+ 2
PULSE-GND 3
4
RS485-1A 5
RS485-1B 6
RS485-1GND 7
8
RS485-2A 9
RS485-2B 10
RS485-2GND 11
Figure 102 CPU module terminal diagram

The serial port 1 of the standard CPU is only used as the time
synchronization port, and the protocol of serial port 1 needs to be set to
none.
227
Chapter 36 Hardware
Table 185 Definition of CPU module in serial communication terminal
Terminals Definition Remark
01 PULSE-
02 PULSE+ Serial port 1
03 PULSE-GND
04
05 485-1A
06 485-1B Serial port 2
07 485-1GND
08
09 485-2A
11 485-2GND
Table 186 Net port configuration
Number Configuration
1 RJ45 electrical port+RJ45 electrical port
2 Optical port+optical port

Table 187 RS485 communication port
Items Data
Quantity 2
Extract twisted pair. On the bottom plate of
Port type
CPU1 module
Maximum transmission distance 1.0km
Voltage withstand test 500V earthing AC voltage
Used for protocol IEC 60870-5-103
Default setting 9600bps
Transmission rate
Minimum: 1200bps; maximum: 19200bps
Table 188 Ethernet communication port
Items Data
Ethernet port
Quantity 2
RJ45 or optical Ethernet port. On the bottom
Port type
plate of CPU1 module
Maximum transmission distance 100m
Used for IEC 61850 protocol
Transmission rate 100Mbit/s
228
Chapter 36 Hardware
Items Data
Used for protocol IEC 60870-5-103
Transmission rate 100Mbit/s
Table 189 Time synchronization
Items Data
Synchronization mode IRIG-B time synchronization
IRIG-B signal format IRIG-B000
Twisted-pair connection or optical fibers On the
Port type
bottom plate of CPU1 module
Voltage level Differential signal input
5 Power supply module

5.1 Overview
The input of the power supply module is the working voltage of the device,
and the output is the working voltage of the other modules of the device.
The input and output circuits of the power supply module are not common,
which plays the electric isolation role. In order to improve anti-interference
ability for power supply module circuit, the power supply module is
equipped with anti-interference filter inside the device. What's more, the
module is equipped with sophisticated power protection function
(undervoltage, overvoltage, overcurrent, overpower, etc.) to prevent IED
breakdown from power supply module fault. Power supply module
provides 11 channels BI and 4 channels relay BO, and provides reliable
electric isolation.
5.2 Power moduleintroduction

There is a power indicator light on the power supply faceplate to indicate
the state of the module, it is always on when the module work properly.
BI10 on the power supply module is fixed defined as "IEDRst", BO1 is
fixed defined as "IEDFaultAlarm", BO2 is fixed defined as "RunErrAlarm".
Other binary inputs and binary outputs can be defined by the user,
according to different functional requirements of users. Each channel of
binary output has two groups of contacts, respectively corresponding to binary
output common port 1 and binary output common port 2, and binary output
relays are unlatched type.
Note: BO 1 is constant-closed contact, other BOs are normally open
contacts, BO 3 and BO 4 are fixed to trip not by starting relay.
229
Chapter 36 Hardware
POWER
PWR
c a
2 BI7 BI1
4 BI8 BI2
BINARY INPUT
6 BI9 BI3
8 BI10 BI4
10 BI11 BI5
12 BICOM BI6
SIGNAL CONTACT
14 COM2 COM1
16 FAIL 1 FAIL 2
18 ALARM 1 ALARM 2
20 BO3-1 BO3-2
22 BO4-1 BO4-2
24 IN+
POWER INPUT
26
28 IN-
30
32
Figure 103 Terminal diagram of POWER module

Table 190 The definition of power supply module terminals
Number c a
2 BI 7 BI 1
4 BI 8 BI 2
6 BI 9 BI 3
8 Device reset BI 4
10 BI 11 BI 5
12 Common terminal of binary input BI 6
Common terminal of binary output Common terminal of binary
14
2 output 1
16 IED fault alarm 1 IED fault alarm 2
18 Running abnormal alarm 1 Running abnormal alarm 2
20 BO 3-1 BO 3-2
22 BO 4-1 BO 4-2
24 Positive pole of power supply Positive pole of power supply
26 Undefined Undefined
28 Negative pole of power supply Negative pole of power supply
230
Chapter 36 Hardware
Number c a
30 Undefined Undefined
32 Grounding Grounding

Table 191 Technical parameter
Implementation
Item number Data
standards
Rated voltage Uaux IEC 60255-1 110Vto250V
Input voltage range IEC 60255-1 ±%20, Uaux
Steady-state burden (EB device) IEC 60255-1 ≤ 20W for each power module
Maximum load power
IEC 60255-1 ≤ 30W for each power module
consumption (EB device)
Steady-state burden (EBL device) IEC 60255-1 ≤ 30W for each power module
Maximum load power
consumption (EBL device)
Steady-state burden (EA device) IEC 60255-1 ≤ 40W for each power module
Maximum load power
consumption (EA device)
6 TCS module
6.1 Overview
It shall be noticed that the facia shall be assembled and welded according to
the different rated working power, please make sure before use.
The built-in TCS function is applicable to the occasion when the trip
contacts in device are used for trip directly; generally, it is applied to the
occasion when installing protection device with medium voltage level in
switchgear panel. In 80% occasions, only the trip circuit is monitored, the
closing circuit does not get monitored. Therefore, the device provides a
module with TCS circuit and trip relay cooperating with each other.
6.2 Instruction of TCS module

TCS plate provides one tripping monitoring circuit, two high-capacity BI
circuits and two pairs of relays and four outlet contacts.
231
Chapter 36 Hardware
Figure 104 TCS module terminal diagram

There are three indicator lights on the TCS faceplate to show the status of
the board, the indicator light definition is shown as follow.
Table 192 Definition of indicator light of TCS module
The serial number of
Indicator light function Introduction of indicator light state
indicator light
1 Power supply light Light is on when device is energized
2 Running light Flash when work properly
3 Reserved Off
232
Chapter 36 Hardware
6.2.1 TCS trip monitoring circuit

TCS module can monitor the open circuit of breaker the whole time, including
various operating conditions.
Figure 105 TCS circuit schematic diagram

Terminal a2, c4, a4 are connected with tripping circuit via auxiliary contact,
when failure occurs in circuit, K1 and K2 open simultaneously, and send
alarm signal; block can be realized through external circuit connection.
Figure 106 TCS circuit wiring diagram
233
Chapter 36 Hardware
6.2.2 Binary output circuit with high-capacity
Taking the binary output circuit with high-capacity PO1 as an example, the
schematic diagram and wiring instruction are as follows. Open PO1 to
drive trip coil or closing coil.
Figure 107 Binary output circuit with high-capacity schematic diagram

When the binary output current is greater than 6A, then the terminals of
column a and column c need to be connected in parallel.
6.2.3 Ordinary BO circuit
Figure 108 Ordinary BO circuit schematic diagram

Table 193 Binary output instruction
Relay BO name Terminals BO type

c26～a26 Normally open
RELAY3A BO1
RELAY4A BO2
c32～a32 Always close
234
Chapter 36 Hardware

Table 194 Binary output circuit with high-capacity parameters
Implementation
Items Data
standards
Maximum work voltage IEC 60255-1 250V, AC
8A continuous,
30A, 200msON,15sOFF
240W (DC)
Closing capacity IEC 60255-1
2000VA(AC)
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Electrical life IEC 60255-1 10100,000 times (resistive load)
IEC 60255-1
IEC 61810-1
IEC 60255-1
IEC 61810-1
AC1000V, 1min
Maximum temperature
IEC 60255-1 70℃
operation allows
Table 195 TCS circuit (binary input) parameter
Implementation
Items Data
standards
Rated voltage IEC 60255-1 110V, 220V DC
Startup voltage IEC 60255-1 70%Ur
Return voltage IEC 60255-1 55%Ur
143V, rated DC voltage 110V
The maximum BI voltage IEC 60255-1
286V, rated DC voltage 220V
Maximum 0.5W/input, 110V DC
Power consumption IEC 60255-1
Maximum 0.5W/input, 220V DC
Table 196 BO parameter
Implementation
Items Data
standards
Maximum work voltage IEC 60255-1 250V AC
8A continuous,
30A, 200ms, ON; 15s, OFF
240W(DC) at inductive load L/R>40
Closing capacity IEC 60255-1 ms
2000VA(AC)
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Electrical life IEC 60255-1 10100,000 times (resistive load)
235
Chapter 36 Hardware
Implementation
Items Data
standards
IEC 60255-1
IEC 61810-1
IEC 60255-1
IEC 61810-1
AC1000V, 1min
Maximum temperature
IEC 60255-1 70℃
operation allows
7 Test mode
Table 197 Insulation test
Implementation
Items Test method
standards
Faceplate: IP54
IEC 60255-27
Protection level (IP) Side plate: IP52
IEC 60529
Backplate: IP30
2KV, 50Hz (rated voltage >63V) tested
between the following circuits:
 Power supply
 CT / VT input
IEC 60255-5
 Binary input
EN 60255-5
Insulation  Binary output
ANSIC 37.90
withstanding Case grounding 500V, 50Hz (rated
GB/T 15145-2017
voltage ≤63V)
DL/T 478-2013
tested between the following circuits:
 Communication port
 Time synchronization port
 Case earthing
5kV (rated voltage>60V)
1kV (rated voltage≤60V)
1.2/50μs,0.5J
IEC 60255-5
tested between the following circuits:
IEC 60255-27
 Power supply
EN 60255-5
Impulse voltage  CT / VT input
ANSIC 37.90
 Binary input
GB/T 15145-2017
 Binary output
DL/T 478-2013
 Communication port
 Time synchronization port
 Case earthing
IEC 60255-5
IEC 60255-27
Insulation EN 60255-5
≥100MΩ, 500V, DC
resistance ANSIC 37.90
GB/T 15145-2017
DL/T 478-2013
Earthing resistance IEC 60255-27 ≤0.1Ω
Flame rating IEC 60255-27 Class V2
236
Chapter 36 Hardware
Table 198 EMC test
Implementation
Items Test method
standards
IEC 60255-22-1
IEC 60255-26 Class III
1MHz pulse group
IEC 61000-4-18 2.5kV, CM;
interference test
EN 60255-22-1 1kV, DM
ANSI/IEEEC 37.90.1
IEC 60255-22-2 Class IV
Immunity degree of
IEC 61000-4-2 ±8kV electro-contact discharge;
electrostatic discharge
EN 60255-22-2 15kV air discharge;
IV class;
Radiated electromagnetic IEC 60255-22-3
10V/m、80MHz～1GHz、1.4GHz～
field immunity EN 60255-22-3
2.7GHz
IEC 60255-22-4,
Immunity degree of Class IV
IEC 61000-4-4
electrical fast transient pulse Communication port: 2KV
EN 60255-22-4
group Other ports: 4KV
ANSI/IEEEC37.90.1
Class IV
IEC 60255-22-5
Surge (impact) immunity 4.0kV, CM;
IEC 61000-4-5
2.0kV, DM
Frequency scanning: 150kHz–80MHz
Calibration frequency: 27MHz and
Radio frequency IEC 60255-22-6
68MHz
interference test IEC 61000-4-6
10V/m
AM,80%,1kHz
Class A
Power frequency immunity
IEC 60255-22-7 300V, CM
test
150V, DM
Class V
Power frequency magnetic
IEC 61000-4-8 100A / m 大于 30s
field immunity test
1000A/m, from 1s to 3s
Class III
100KHz pulse-group noise
IEC 61000-4-18 Communication port: 2KV
immunity
Other ports: 4KV
Damped oscillation Class V
IEC 61000-4-10
magnetic field immunity 100A/m
Pulse magnetic field Class V
IEC 61000-4-9
immunity test 1000A/m
Conducted emission IEC 60255-25 0.15MHz～30MHz，classA
Radiated emission IEC 60255-25 30MHz~30MHz, classA
Table 199 Mechanical test

Implementation
Items Test method
standards
Sinusoidal vibration IEC 60255-21-1
Class 1
response test EN 60255-21-1
Sinusoidal vibration and IEC 60255-21-1
Class 1
endurance test EN 60255-21-1
IEC 60255-21-2
Impact response test Class 1
EN 60255-21-2
IEC 60255-21-2
Impact and endurance test Class 1
EN 60255-21-2
Collision test IEC 60255-21-2 Class 1
Seismic test IEC 60255-21-3 Class 1
237
Chapter 36 Hardware
Table 200 Environmental test
Items Data
High and low temperature test -40°C to +70°C
Temperature storage test -40°C to +70°C
Maximum relative humidity 95%, no
Humidity test
condensation
8 Structural design
Table 201 Structural design
Items Data
Dimension 4U×1/2, 19 inches
Weight ≤ 9kg
9 CE Certificate
Table 202 CE Certificate
Items Data
EN 61000-6-2 and EN61000-6-4(EMC guide
EMC
committee 2004/108/EC)
LVD EN 60255-27(LVD2006/95EC)
10 Environmental parameters
Table 203 Environmental parameters (IEC 60255-1:2009)
Environmental parameters Condition
Normal operating temperature range -40 ℃ -+70 ℃ (except LCD)
Storage temperature range -40℃ - + 70℃
Relative humidity 5% - 95%
Altitude ≤ 2 000 m
Anti-pollution grade 2
Mechanical performance Level 1
EMC launch class A
EMC Immunity level A
238
Chapter 37 Appendix
Chapter 37 Appendix
239
Chapter 37 Appendix
1 Setting list
Table 204 Equipment parameter
Number Name Range Unit Default Remark

1 IEDCTPriVal 0～9999 A 8000
2 IEDCTSecVal 1～5 A 1
3 3I0CTPriVal 0～9999 A 8000
4 3I0CTSecVal 1～5 A 1
5 SEF/REFCTPriVal 0～9999 A 8000
6 SEF/REFCTSecVal 1 A 1
7 VTPriVal 0～1000 V 110
8 VTSecVal 0～120 V 100
9 U4VTPriVal 0～1000 V 110
10 U4VTSecVal 0～120 V 100
11 MeasureCTPriVal 0～9999 A 8000
12 MeasureCTSecVal 1～5 A 5
13 BISwitchSetGrp 0/1 0
14 4～20mAScaleVal 4～20 mA 20
2 Report list
About operation report and protection alarm report please see the
report list in the protection chapter.
2.1 Alarm report

IED contains three kinds of alarm reports, showing as follow:
1) Class 1 alarm belongs to IED alarm. When class 1 alarm happens, the
alarm LED on the faceplate of the IED will be on, all of protection
function will be out of service and the trip power of protection will be
blocked.
2) Class 2 alarm belongs to other alarm. When class 2 alarm happens,
the alarm LED on the front panel of the IED will flash. Class II alarm
won't block protection function.
Table 205 Report list of class 1 alarm
Number Report name Alarm code Description

1 SampleValErr 32769
2 IEDParmErr 32770
3 ROMSumChkErr 32771
4 SetErr 32772 Need to write setting again
5 UnconfirmConnMode 32773
6 SoftConnErr 32774
7 SystemCfgErr 32775
8 IED CPUModuleErr 32778
240
Chapter 37 Appendix
9 SetGrpPointerErr 32780
Need to download sf and esdc files
10 LogicFileErr 32798
again
11 CfgFileErr 35769
12 CfgFileInconsist 35770
Need to download sf and esdc files
13 IOMatrixErr 35771
again
Jumper setting on the BO module
is inconsistent with the software
14 BOChkNoResponse 33769
configuration, need to set the
jumper again
15 BOBreakdown 33770
16 BIBreakdown 33784
17 BIO CPUErr 33789
18 BIO ROMSumErr 33790
BI or BO module is not defined,
19 BIO EEPROMErr 32779
need to define it again
20 BIOCfgErr 32777
21 BISelfChkCircuitErr 33787
22 BOLatchedPropertyCfgErr 33793
Need to confirm the address
jumper of the module, insert the
23 BICommInterrupt 33781
module firmly and confirm that the
binary input program is correct
Need to confirm the address
jumper of the module, insert the
24 BOCommInterrupt 33782
module firmly and confirm that the
binary output program is correct
Table 206 Report list of system class 2 alarm

1 SRAMSelfChkErr 33771
2 TestStateNotRst 33772
3 OperFail 33773
4 CanCommInterrupt 33775
5 FLASHSelfChkErr 33776
6 WorkInTestSetGrp 33783
7 BIInputErr 33785
8 DualPosnInputInconsist 33786
9 BIOInputPowerErr 33788
241
Chapter 37 Appendix
2.2 Operation report

Table 207 Operation report list
Number Report name Alarm code
1 SwitchSetGrpSuccess 32769
2 CopySetGrpSuccess 32789
3 WriteIEDSetSuccess 32770
4 WriteParmSuccess 32771
5 WriteCfgSuccess 32772
6 AdjScaleSuccess 32773
7 AdjAngleSuccess 32788
8 HardConnOn/OffSuccess 32774
9 SoftConnOn/OffSuccess 32775
10 ClearCfg 32776
11 IEDRst(CPUReboot) 32778
12 FactoryRst 32779
13 BOTestSuccess 32780
14 ZeroDriftAdjSuccess 32782
15 ClearAllRptSuccess 32783
16 MaintModeOn 32785
17 MaintModeOff 32786
18 AutoRebootAfterCfg 32868
242
Chapter 37 Appendix
3 Typical wiring
The CT rated value of 1A will be taken as the example in the following wiring
diagrams. For CT of 5A, just switch its earthing end to the corresponding
earthing terminal of 5A.
3.1 As to incoming and outlet line feeder protection

and line backup protection
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 109 Apply to feeder protection measurement three phase earth current
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 110 Apply to feeder protection measurement three phase earth current and three
phase earth voltage beside busbar
243
Chapter 37 Appendix
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
Figure 111 Apply to feeder protection measurement three phase earth current and three
phase voltage beside line
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 112 Apply to feeder protection measurement three phase earth current and one
phase-to-phase voltage beside busbar
244
Chapter 37 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 113 Apply to feeder protection measurement three phase earth current and
single phase voltage beside busbar
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
a7
*
I1
b7
Figure 114 Apply to feeder protection measurement line three phase, zero sequence
and highly sensitive zero sequence current
245
Chapter 37 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6
IN
AIM1
a7
*
I1
b7
and highly sensitive zero sequence current and three phase voltage beside busbar
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM1
* a7
I1
b7
and highly sensitive zero sequence current and three phase voltage beside line
246
Chapter 37 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
I1
b7
and highly sensitive zero sequence current and one phase-to-phase voltage beside
busbar
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
I1
b7
and highly sensitive zero sequence current and single phase voltage beside busbar
247
Chapter 37 Appendix
3.2 As for transformer backup protection IED
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7
I1
Figure 119 Apply to transformer backup protection measurement three phase current,
zero sequence current and neutral point earth current
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7 I1
zero sequence current and neutral point earth current and three phase voltage beside
busbar
248
Chapter 37 Appendix
A
B
C
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM1
* a7
b7 I1
zero sequence current and neutral point earth current and three phase voltage beside line
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7 I1
zero sequence current and neutral point earth current and single phase-to-phase voltage
beside busbar
249
Chapter 37 Appendix
A
B
C
AIM2
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
AIM1
* a7
b7 I1
zero sequence current and neutral point earth current and single phase voltage beside
busbar
250
Chapter 37 Appendix
3.3 As for synchronization function
A
B
C
A
B
C
AIM2
a9
U4
b9
a10
UA
a11
UB
a12
UC
b10b11b12
UN
Figure 124 Double busbar performance synchronization application typical wiring

A
B
C
AIM2
a9
U4
b9
a10
UA
a11
UB
a12
UC
b10b11b12
UN
AIM2
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
a6
b6 IN
Figure 125 Feeder current protection synchronization application typical wiring
251
Chapter 37 Appendix
3.4 As for capacitor protection

A
B
C
Capacitor bank AIM1

* a6
b6 IC1
* a7
b7
IC2
* a9
b9 IC3
Figure 126 Capacitor unbalance protection three line unbalance connection mode of
current connection
A
B
C
Capacitor bank AIM1

a6
b6 I1
*
Figure 127 Capacitor unbalance protection single line unbalance connection mode of
current connection
252
Chapter 37 Appendix
A A
B
B C
C
I1 I1
I2
I3
Figure 128 On earth capacitor suits Figure 131 On earth Capacitor suits
single line unbalance current protection single line unbalance current protection
connection mode connection mode
A A
B B
C C
U1
I1
Figure 132 Not on earth Y-pattern
Figure 129 On earth Y-pattern connection capacitor suits neutral points
connection capacitor suits neutral points voltage protection connection mode
differential current protection connection
mode A
B
A C
B
C
U1
I1
Figure 133 On earth Y-pattern
Figure 130 Not on earth Y-pattern connection capacitor suits neutral points
connection capacitor suits neutral points voltage protection connection mode
current protection connection mode
253
Chapter 37 Appendix
A A
B B
C
C
U1 U1
connection capacitor suits neutral points
connection capacitor suits neutral
unbalance voltage protection connection
position three phase unbalance voltage
mode
A A
B B
C C
U1
U1
U2
U3
Figure 135 Non on earth Y-pattern
Figure 137 Capacitor suits three phase
connection capacitor suits three PT
unbalance voltage measurement
measurement neutral points current
connection mode
connection mode
254
43Appendix
CSC-211
Figure 138 As for load shedding protection function typical wiring
4 Inverse time characteristic

4.1 Twelve types of inverse time
characteristic of IEC and inverse time
characteristic curve of ANSI
In setting, if inverse time characteristic curve is set, the corresponding
curve will be related. To support IEC and ANSI inverse time curve.
Table 208 Twelve types of inverse time characteristic of IEC and inverse time
characteristics of ANSI
Serial
number of Inverse time curve Parameter A Parameter P Parameter B
curve
1 IEC inverse time 0.14 0.02 0
2 IEC very inverse time 13.5 1.0 0
IEC extreme inverse
3 80.0 2.0 0
time
4 IEC short inverse time 0.05 0.04 0
5 IEC long inverse time 120.0 1.0 0
6 ANSI inverse time 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
ANSI moderate inverse
9 0.0103 0.02 0.0228
time
10 ANSI very inverse time 3.922 2.0 0.0982
ANSI extreme inverse
11 5.64 2.0 0.02434
time
ANSI definite inverse
12 0.4797 1.5625 0.21359
time
255
Chapter 37 Appendix
4.2 User-defined properties

As for inverse time characteristic, if curve order is set 13, it belongs to
consumer set characteristic.
A
t=� i p
+ B�T
� � −1
I
Where:
A: time coefficient of inverse time
B: time delay of inverse time
P: inverse time index
T: inverse time constant
5 CPU module upgrading introduction

CPU
1 2 3
4 5 6
ETH1
ETH2
ETH3
1
RS485-1A/PULSE-
2
RS485-1B/PULSE+
RS485-1GND 3
4
RS485-2A 5
RS485-2B 6
RS485-2GND 7
8
RS232-TXD 9
RS232-RXD 10
RS232-GND 11
Figure 139 CPU module terminal diagram

The enhanced CPU supports serial port 1 and time synchronization
multiplex hardware ports. The functions are switched by software. When
used as time synchronization port, the protocol of serial port 1 needs to be
set to none.
256
43Appendix
Table 209 Definition of CPU module in serial communication terminal
Terminals Definition Remark

01 485-1A
03 485-1GND
04
05 485-2A
07 485-2GND
08
09 RS232-TXD
10 RS232-RXD Serial port 3
11 RS232-GND
6 Connector list
connector, soft-hard series, soft-hard parallel, and soft-hard parallel by
default.
Table 210 SC-211-EBConnector list
Number Connector name Description Remark

1. MaintConn 0-disable, 1-enable
2. OCConn 0-disable, 1-enable
3. 3I0Conn 0-disable, 1-enable
4. SEF/REFConn 0-disable, 1-enable
5. I2Conn 0-disable, 1-enable
6. UnderCurrentConn 0-disable, 1-enable
7. ThermalOLConn 0-disable, 1-enable
8. CBFConn 0-disable, 1-enable
9. DZConn 0-disable, 1-enable
10. StubConn 0-disable, 1-enable
11. BCConn 0-disable, 1-enable
12. FreqDf/dtConn 0-disable, 1-enable
13. SOFTConn 0-disable, 1-enable
14. OLLoadShedConn 0-disable, 1-enable
15. UVLoadShedConn 0-disable, 1-enable
16. ARConn 0-disable, 1-enable
17. SimpleBusDiffConn 0-disable, 1-enable
18. BlkSimpleBusDiffConn 0-disable, 1-enable
19. CoolLoadStartConn 0-disable, 1-enable
20. OVConn 0-disable, 1-enable
257
Chapter 37 Appendix
Number Connector name Description Remark

21. U2Conn 0-disable, 1-enable
22. UVConn 0-disable, 1-enable
23. PowerProtConn 0-disable, 1-enable
24. OEConn 0-disable, 1-enable
25. HVSideUFConn 0-disable, 1-enable
26. HVSideOFConn 0-disable, 1-enable
Armenia Custom
27. FreqCloseConn 0-disable, 1-enable
Version
258

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CSC-211

Multifunction protection IED

Notes: The company reserves the right to amend the introduction. If

Applicability of this Manual

Strictly follow the company and international safety regulations.

Do not touch any circuitry during operation. Potentially lethal

Using the isolated test pins when measuring signals in open

Never connect or disconnect conducting wire and/or connector to

Always connect the IED to protective earth regardless of the

Do not disconnect the secondary connection of current

Do not remove the screw from a powered IED or from an IED

Using the certified conductive bags to transport PCBs (modules).

Do not connect live conducting wires to the IED, internal circuitry

When replacing modules using a conductive wrist strap

When installing and commissioning, take care to avoid electrical

Changing the setting group will inevitably change the IEDs

About this chapter

Type Sub-type Description

3.2 Monitoring function

3.3 Measurement function

3.4 Control function

3.5 Communication mode

Communication port on the faceplate

Chapter 2 General functions

About this chapter

1 Event record and analysis

1.2 Fault record

1.3 disturbance and fault record

1.4 Sequence of event (SOE)

1.5 Operation record

2.2 Diagnostic principle

3 Time synchronization function

3.2 Synchronization principle

The available lower structure

Figure 1 Synchronization principle diagram

3.3 IRIG -B synchronization mode

3.4 PPS synchronization mode

3.5 SNTP time synchronization mode

3.6 IEEE1588 time synchronization mode

Chapter 3 Overcurrent Protection (50,

About this chapter

2 Function module description

Directional / Non-directional Overcurrent Protection

Function Logo Description

3.1 Protection principle

protection; after the "HarmCrossBlkTime", one phase inrush protection

Figure 3 Inrush blocking logic diagram

3.1.2 Composited voltage blocking unit

Figure 4 Logic diagram of the characteristics of composited voltage component

3.1.3 Directional component

Phase Current Voltage

FWD 90° IA 90° IA

Figure 5 Forward or reverse direction interval

Figure 6 Direction detection logic diagram

3.1.4 Definite time

Curve Inverse time characteristic A P B

3.1.6 Trip characteristic

corresponding overcurrent protection stage is enabled. If phase current is

VT failure blocking &

Overcurrent stage 1 directional

Overcurrent Stage1 composited

overcurrent protection fucntion is enabled

Figure 7 Stage1 of the overcurrent definite time logic diagram