SIFANG CSC-100EB Line Protection

CSC-100
Line Protection IED

Manual
杨帆
赵月
刘晓丰
孙娴
V1.07
0000189068
2020年10月
CSC-100 系列数字式线路保护装置
说明书
(英文)
编制
校核:
标准化审查:
审定:
版本号: V1.07
文件代号: 0000189068
出版日期: 2020 年 10 月
Version: V1.07
Document code: 0000189068
Issued Date: 2020.10
Copyright: Beijing Sifang Automation Co., Ltd
Notes: the company reserves the right to amend the introduction. If

equipment does not agree with the manual at anywhere, please contact
our Company in time. We will provide you with corresponding service.
is registered trademark of Beijing Sifang Automation Co., Ltd.
We reserve all rights to this document, even in the event that a patent is issued and a
different commercial proprietary right is registered. Improper use, in particular reproduction
and dis-semination to third parties, is not permitted.
This document has been carefully checked. If the user nevertheless detects any errors, he
is asked to notify us as soon as possible.
The data contained in this manual is intended solely for the product description and is not to
be deemed to be a statement of guaranteed properties. In the interests of our customers,
we constantly seek to ensure that our products are developed to the latest technological
standards as a result; It is possible that there may be some differences between the
hard-ware/software product and this information product.
Manufacturer: Beijing Sifang Automation Co., Ltd.

Email: support@sf-auto.com
Website: http://www.sf-auto.com
Add: Number9, Shangdi 4th Street, Haidian District, Beijing, P.R.C.100085
Preface
Purpose of this manual
This manual describes the functions, operation, installation, and placing
into service of device CSC-100. In particular, one will find:
 Information on how to configure the device scope and a description of
the device functions and setting options;
 Installation and debugging specifications;
 technical data specifications;
 A compilation of the most significant data for experienced users in the
Appendix.
Target user
Protection engineers, commissioning engineers, personnel concerned with
adjustment, checking, and service of selective protective equipment,
automatic and control facilities, and personnel of electrical facilities and
power plants.
Applicability of this Manual

This manual is valid for SIFANG busbar protection IED CSC-100.
Note: the password for this device is 8888.
Technical support
In case of further questions concerning IED CSC-100 system, please
contact SIFANG representative.
Safety information
Strictly follow the company and international safety regulations.

Working in a high voltage environment requires serious approach
to avoid human injuries and damage to equipment.
Do not touch any circuitry during operation. Potentially lethal

voltages and currents are present.
Avoid to touching the circuitry when covers are removed. The IED
contains electric circuits which can be damaged if exposed to
static electricity. Lethal high voltage circuits are also exposed
when covers are removed.
Using the isolated test pins when measuring signals in open

circuitry. Potentially lethal voltages and currents are present.
Never connect or disconnect wire and/or connector to or from IED

during normal operation. Dangerous voltages and currents are
present. Operation may be interrupted and IED and measuring
circuitry may be damaged.
I
Always connect the IED to protective earth regardless of the
operating conditions. Operating the IED without proper earthing
may damage both IED and measuring circuitry and may cause
injuries in case of an accident.
Do not disconnect the secondary connection of current

transformer without short-circuiting the transformer’s secondary
winding. Operating a current transformer with the secondary
winding open will cause a high voltage that may damage the
transformer and may cause injuries to humans.
Do not remove the screw from a powered IED or from an IED

connected to power circuitry. Potentially lethal voltages and
currents are present.
Using the certified conductive bags to transport PCBs (modules).

Handling modules with a conductive wrist strap connected to
protective earth and on an antistatic surface. Electrostatic
discharge may cause damage to the module due to electronic
circuits are sensitive to this phenomenon.
Do not connect live wires to the IED, internal circuitry may be

damaged.
When replacing modules using a conductive wrist strap

connected to protective earth. Electrostatic discharge may
damage the modules and IED circuitry.
When installing and commissioning, take care to avoid electrical

shock if accessing wiring and connection IEDs.
Changing the setting group will inevitably change the IEDs

operation. Be careful and check regulations before making the
change.
The hazardous wastes of lead and printed circuit are in the device,
when it is scrapped, please refer to The Law of The Peoples’
Republic of China on Prevention and Control of Environment
Pollution by Solid Waste or the related laws and regulations and
the wastes should be processed by the qualified cooperation.
II
Contents
CHAPTER 1 INTRODUCTION ................................................................................................ 1
1 IED OVERVIEW ..................................................................................................................... 2
2 IED CHARACTERISTIC ........................................................................................................... 2
3 BASIC FUNCTION .................................................................................................................. 4
3.1 Protection function...................................................................................................... 4
3.2 Monitoring function ..................................................................................................... 6
3.3 Measurement function ................................................................................................ 6
3.4 Control function .......................................................................................................... 6
3.5 Substation communication ......................................................................................... 7
3.6 Remote communication ............................................................................................. 7
CHAPTER 2 GENERAL FUNCTIONS .................................................................................... 9
1 EVENT RECORD AND ANALYSIS ............................................................................................ 10
1.1 Introduction............................................................................................................... 10
1.2 Fault record .............................................................................................................. 10
1.3 disturbance and fault record..................................................................................... 10
1.4 Sequence of event (SOE) ........................................................................................ 10
1.5 Operation record .......................................................................................................11
2 DIAGNOSIS FUNCTION ..........................................................................................................11
2.1 Introduction................................................................................................................11
2.2 Diagnostic principle ...................................................................................................11
3 TIME SYNCHRONIZATION FUNCTION ......................................................................................11
3.1 Introduction................................................................................................................11
3.2 Synchronization principle ......................................................................................... 12
3.3 IRIG-IRIG-B synchronization mode.......................................................................... 12
3.4 PPS synchronization mode ...................................................................................... 13
3.5 SNTP time synchronization mode ............................................................................ 13
3.6 IEEE1588 synchronization mode ............................................................................. 13
4 MONITORING FUNCTION ...................................................................................................... 13
4.1 Check of phase sequence of phase voltage and phase current .............................. 13
4.2 3I0 polarity check ..................................................................................................... 13
4.3 Third harmonic voltage check .................................................................................. 13
4.4 Breaker auxiliary contact detection .......................................................................... 13
4.5 Fault locater.............................................................................................................. 14
5 AUTHORIZATION ................................................................................................................. 16
CHAPTER 3 BASIC PROTECTION COMPONENT .............................................................. 17
1 STARTUP COMPONENT ........................................................................................................ 18
1.1 Introduction............................................................................................................... 18
1.2 Abrupt-change current startup component .............................................................. 18
1.3 Zero sequence current startup component .............................................................. 18
1.4 Overcurrent startup component ............................................................................... 19
1.5 Steady state losing stability startup component ....................................................... 19
1.6 Pilot protection undervoltage startup component (for weak infeed systems) .......... 20
1.7 Weak infeed startup component of differential protection (for weak infeed system) 20
1.8 Distant calling startup component of differential protection (for weak infeed system)
20
2 PHASE SELECTOR COMPONENT ........................................................................................... 21
2.1 Introduction............................................................................................................... 21
2.2 Function module description .................................................................................... 21
2.3 Abrupt-change current phase selector component .................................................. 22
2.4 Phase selector component of steady state sequence component .......................... 23
2.5 Undervoltage phase selector component ................................................................ 24
2.6 Cross line fault phase selector component .............................................................. 24
3 DIRECTIONAL COMPONENT.................................................................................................. 24
3.1 Introduction............................................................................................................... 24
3.2 Memory voltage direction component ...................................................................... 24
3.3 Zero sequence direction component ........................................................................ 25
3.4 Negative sequence direction component ................................................................. 25
3.5 Impedance directional component ........................................................................... 26
III
4
COMMON SETTING .............................................................................................................. 27
4.1 Common setting list .................................................................................................. 27
4.2 Setting description .................................................................................................... 28
5 BINARY INPUT DESCRIPTION FOR TRIP POSITION ................................................................... 31
CHAPTER 4 LINE DIFFERENTIAL PROTECTION (87L) ..................................................... 33
1 INTRODUCTION ................................................................................................................... 34
2 FUNCTION MODULE DESCRIPTION ........................................................................................ 34
3 DETAILED DESCRIPTION ...................................................................................................... 36
3.1 Protection principle ................................................................................................... 36
3.1.1 Phase-segregated differential protection function .............................................................. 36
3.1.2 Abrupt change current differential protection ..................................................................... 38
3.1.3 Zero sequence current differential protection ..................................................................... 39
3.1.4 Other principles .................................................................................................................. 41
3.1.5 Logic diagram .................................................................................................................... 52
3.2 Configurable nodes by the user ............................................................................... 56
3.3 Setting list ................................................................................................................. 57
3.3.1 Setting list .......................................................................................................................... 57
3.3.2 Setting description ............................................................................................................. 58
3.4 Report list ................................................................................................................. 62
3.5 Technical parameter ................................................................................................. 66
CHAPTER 5 LINE DISTANCE PROTECTION (21/ 21N) ...................................................... 67
1 INTRODUCTION ................................................................................................................... 68
2 FUNCTION MODULE DESCRIPTION ........................................................................................ 69
3 DETAILED DESCRIPTION ...................................................................................................... 71
3.1 Protection principle ................................................................................................... 71
3.1.1 Distance protection polygonal characteristics .................................................................... 71
3.1.2 Distance protection MHO characteristics ........................................................................... 75
3.1.3 Minimum operating current ................................................................................................ 79
3.1.4 Distance measurement components.................................................................................. 79
3.1.5 Distance polygonal direction component ........................................................................... 81
3.1.6 Instruction of extension zone 1 .......................................................................................... 83
3.1.7 Power swing blocking ........................................................................................................ 83
3.1.8 Phase-to-earth fault determination ..................................................................................... 90
3.1.9 Logic of series compensation capacity .............................................................................. 90
3.1.10 Logic diagram ................................................................................................................ 91
3.2 Configurable nodes by the user ............................................................................... 99
3.3 Setting list ............................................................................................................... 100
3.3.1 Setting instruction ............................................................................................................ 107
3.3.2 Distance setting ............................................................................................................... 110
3.3.3 Load encroachment cleared area .................................................................................... 116
3.3.4 Swing unblocking characteristic ....................................................................................... 119
3.3.5 Description of relevant setting and control bit of series capacitance compensation ........ 119
3.4 Report list ............................................................................................................... 121
3.5 Technical parameter ............................................................................................... 122
CHAPTER 6 PILOT DISTANCE PROTECTION (85-21/21N) ............................................. 123
1 INTRODUCTION ................................................................................................................. 124
2 FUNCTION MODULE DESCRIPTION ...................................................................................... 124
3 DETAILED DESCRIPTION .................................................................................................... 128
3.1 Protection principle ................................................................................................. 128
3.1.1 Permissive underreach transfer trip (PUTT) .................................................................... 128
3.1.2 Permissive overreach transfer trip (POTT) scheme ......................................................... 130
3.1.3 Blocking mode ................................................................................................................. 131
3.1.4 Additional pilot logics ....................................................................................................... 132
3.1.5 Remote transmission and direct transfer trip logic of using optical fiber channel ............. 135
3.2 Pilot protection tripping logic .................................................................................. 136
3.3 Configurable nodes by the user ............................................................................. 137
3.4 Setting list ............................................................................................................... 139
3.4.1 Setting list ........................................................................................................................ 139
3.4.2 Setting description ........................................................................................................... 140
3.5 Report list ............................................................................................................... 141
CHAPTER 7 DIRECTIONAL PILOT EARTH FAULT PROTECTION (85–67N).................. 145
1 INTRODUCTION ................................................................................................................. 146
IV
3.1.1 Permissive ....................................................................................................................... 150
3.1.2 Blocking mode ................................................................................................................. 152
3.1.3 Direction reversing for external fault ................................................................................ 152
3.1.4 Pilot zero sequence open position sending message logic ............................................. 152
3.1.5 Pilot zero sequence trip sending message logic ............................................................. 153
3.1.6 Weak infeed function ....................................................................................................... 153
3.1.7 DTT Direct transfer trip logic ........................................................................................... 153
3.1.8 Double-circuit parallel transmission lines ........................................................................ 153
3.1.9 Remote transmission and direct transfer trip logic of using optical fiber channel ............ 154
3.3 Setting list ............................................................................................................... 156
3.4 Report list ............................................................................................................... 158
CHAPTER 8 OVERCURRENT PROTECTION (50,51,67) .................................................. 161
1 INTRODUCTION ................................................................................................................. 162
3.1.1 Inrush blocking components ............................................................................................ 164
3.1.2 Composited voltage blocking unit .................................................................................... 165
3.1.3 Directional component ..................................................................................................... 165
3.1.4 Definite time .................................................................................................................... 167
3.1.5 Inverse time ..................................................................................................................... 167
3.1.6 Trip characteristic ............................................................................................................ 168
3.1.7 Logic diagram .................................................................................................................. 168
3.3 Setting list ............................................................................................................... 170
3.4 Report list ............................................................................................................... 172
CHAPTER 9 EARTH FAULT PROTECTION(50N, 51N, 67N) ............................................ 175
1 INTRODUCTION ................................................................................................................. 176
3.1.1 Inrush blocking components ............................................................................................ 177
3.1.2 Directional component ..................................................................................................... 178
3.1.3 Definite time .................................................................................................................... 180
3.1.4 Inverse time ..................................................................................................................... 180
3.1.7 Logic diagram .................................................................................................................. 182
3.3 Setting list ............................................................................................................... 184
3.4 Report list ............................................................................................................... 188
CHAPTER 10 EMERGENCY OVERCURRENT PROTECTION（50,51）........................... 191
1 INTRODUCTION ................................................................................................................. 192
3.1.2 Definite time .................................................................................................................... 194
3.1.3 Inverse time ..................................................................................................................... 195
3.1.5 Logic diagram .................................................................................................................. 196
3.3 Setting list ............................................................................................................... 197
3.4 Report list ............................................................................................................... 198
CHAPTER 11 EMERGENCY EARTH FAULT PROTECTION（50N,51N） ........................ 201
1 INTRODUCTION ................................................................................................................. 202
V
3.1 Protection Principle ................................................................................................ 203
3.1.2 Definite time ..................................................................................................................... 204
3.1.3 Inverse time ..................................................................................................................... 204
3.1.4 Trip characteristic............................................................................................................. 205
3.1.5 Logic diagram .................................................................................................................. 205
3.2 Configuration nodes by the user ............................................................................ 206
3.3 Setting list ............................................................................................................... 206
3.4 Report list ............................................................................................................... 208
3.5 Techinical parameter .............................................................................................. 208
CHAPTER 12 NEGATIVE SEQUENCE CURRENT PROTECTION (46) ............................. 211
1 INTRODUCTION ................................................................................................................. 212
3.1.1 Definite time ..................................................................................................................... 213
3.1.2 Inverse time ..................................................................................................................... 213
3.1.4 Logic diagram .................................................................................................................. 215
3.3 Setting list ............................................................................................................... 215
3.4 Report list ............................................................................................................... 218
CHAPTER 13 OVERVOLTAGE PROTECTION (59) ............................................................ 221
1 INTRODUCTION ................................................................................................................. 222
3.1.1 Definite time ..................................................................................................................... 223
3.1.2 Inverse time ..................................................................................................................... 223
3.1.4 Logic diagram .................................................................................................................. 224
3.3 Setting list ............................................................................................................... 225
3.4 Report list ............................................................................................................... 228
CHAPTER 14 NEGATIVE SEQUENCE VOLTAGE PROTECTION (47) .............................. 231
1 INTRODUCTION ................................................................................................................. 232
3.1.1 Definite time ..................................................................................................................... 232
3.1.2 Inverse time ..................................................................................................................... 233
3.3 Setting list ............................................................................................................... 235
3.4 Report list ............................................................................................................... 237
CHAPTER 15 UNDERVOLTAGE PROTECTION (27) .......................................................... 239
1 INTRODUCTION ................................................................................................................. 240
3.1.1 Blocking condition ............................................................................................................ 241
3.1.2 Definite time ..................................................................................................................... 242
3.1.3 Inverse time ..................................................................................................................... 242
3.1.5 Logic diagram .................................................................................................................. 244
3.3 Setting list ............................................................................................................... 246
3.4 Report list ............................................................................................................... 249
CHAPTER 16 THERMAL OVERLOAD PROTECTION (49) ................................................. 251
VI
1 INTRODUCTION ................................................................................................................. 252
3.3 Setting list ............................................................................................................... 254
3.4 Report list ............................................................................................................... 255
CHAPTER 17 POWER PROTECTION (32D) ....................................................................... 257
1 INTRODUCTION ................................................................................................................. 258
3.3 Setting list ............................................................................................................... 260
3.4 Report list ............................................................................................................... 260
3.5 Technical parameter............................................................................................... 260
CHAPTER 18 CIRCUIT BREAKER FAILURE PROTECTION (50BF) .................................. 261
1 INTRODUCTION ................................................................................................................. 262
3.1 Protection function.................................................................................................. 264
3.1.1 Current detection ............................................................................................................. 264
3.1.2 Breaker auxiliary contact detection.................................................................................. 265
3.1.3 CBF protection trip logic .................................................................................................. 267
3.3 Setting list ............................................................................................................... 271
3.4 Report list ............................................................................................................... 272
CHAPTER 19 DEAD ZONE PROTECTION (50DZ) .............................................................. 273
1 INTRODUCTION ................................................................................................................. 274
3.3 Setting list ............................................................................................................... 278
3.4 Report list ............................................................................................................... 278
CHAPTER 20 STUB PROTECTION (50STUB) .................................................................... 281
1 INTRODUCTION ................................................................................................................. 282
3.3 Setting list ............................................................................................................... 284
3.4 Report list ............................................................................................................... 284
CHAPTER 21 POLE DISCREPANCY PROTECTION (62PD) .............................................. 285
1 INTRODUCTION ................................................................................................................. 286
3.2 Logic diagram ......................................................................................................... 287
3.4 Setting list ............................................................................................................... 288
3.5 Report list ............................................................................................................... 288
CHAPTER 22 BROKEN CONDUCTOR PROTECTION (46BC) ........................................... 291
1 INTRODUCTION ................................................................................................................. 292
VII
3.3 Setting list ............................................................................................................... 294
3.4 Report list ............................................................................................................... 294
CHAPTER 23 UNDERFREQUENCY PROTECTION (81UF) ............................................... 295
1 INTRODUCTION ................................................................................................................. 296
3.1.1 Protection function introduction ........................................................................................ 297
3.1.2 Logic diagram .................................................................................................................. 298
3.3 Setting list ............................................................................................................... 299
3.4 Report list ............................................................................................................... 300
CHAPTER 24 OVERFREQUENCY PROTECTION (81OF) .................................................. 301
1 INTRODUCTION ................................................................................................................. 302
3.1.2 Logic diagram .................................................................................................................. 303
3.3 Setting list ............................................................................................................... 304
3.4 Report list ............................................................................................................... 305
CHAPTER 25 FREQUENCY RATE PROTECTION (81DF).................................................. 307
1 INTRODUCTION ................................................................................................................. 308
3.1.2 Logic diagram .................................................................................................................. 309
3.3 Setting list ............................................................................................................... 311
3.4 Report list ............................................................................................................... 312
CHAPTER 26 OUT OF STEP PROTECTION (78) ................................................................ 315
1 INTRODUCTION ................................................................................................................. 316
3.1.1 Take generator protection as an example: ....................................................................... 316
3.1.2 Take line protection setting as an example: ..................................................................... 318
3.2 Configurable output nodes by the user .................................................................. 321
3.3 Setting list ............................................................................................................... 321
3.4 Report list ............................................................................................................... 322
CHAPTER 27 THE DIRECTION PROTECTION OF ZERO SEQUENCE POWER (32N) .... 323
1 OVERVIEW ....................................................................................................................... 324
3.1.1 Component of zero sequence power direction ................................................................. 325
3.1.2 Inverse time characteristic ............................................................................................... 325
3.1.3 The instruction of user-defined configuration ................................................................... 325
3.1.4 Other instructions ............................................................................................................. 326
3.1.5 Logic diagram .................................................................................................................. 326
3.3 Setting list ............................................................................................................... 327
VIII
3.4 Report list ............................................................................................................... 328
CHAPTER 28 SWITCH-ON-TO-FAULT PROTECTION (50SOTF) ...................................... 329
1 INTRODUCTION ................................................................................................................. 330
3.1.1 Protection function introduction ....................................................................................... 330
3.1.2 Logic diagram .................................................................................................................. 331
3.8 Setting list ............................................................................................................... 332
3.9 Report list ............................................................................................................... 333
CHAPTER 29 OVERLOAD ALARM (50OL) .......................................................................... 335
1 INTRODUCTION ................................................................................................................. 336
3.1.2 Logic diagram .................................................................................................................. 336
3.3 Setting list ............................................................................................................... 337
3.4 Report list ............................................................................................................... 337
CHAPTER 30 SYNCHRO-CHECK AND DEAD VOLTAGE CHECK (25) ............................. 339
1 INTRODUCTION ................................................................................................................. 340
3.1.2 Synchronization check mode: ......................................................................................... 344
3.1.3 Modes of dead voltage check: ......................................................................................... 345
3.1.4 Override mode................................................................................................................. 346
3.1.5 Logic diagram .................................................................................................................. 346
3.3 Setting list ............................................................................................................... 349
3.4 Report list ............................................................................................................... 351
CHAPTER 31 AUTO-RECLOSING (79) ................................................................................ 355
1 INTRODUCTION ................................................................................................................. 356
3.1.1 Auto-reclosing startup ..................................................................................................... 359
3.1.2 Single auto-reclosing ....................................................................................................... 360
3.1.3 Multiple auto-reclosing .................................................................................................... 361
3.1.4 AR coordination between tie CB and side CB ................................................................. 363
3.1.5 Auto-reclosing mode ....................................................................................................... 369
3.1.6 Auto-reclosing startup mode ........................................................................................... 371
3.1.7 Protection device coordination ........................................................................................ 371
3.1.8 Auto-reclosing logic ......................................................................................................... 371
3.1.9 Auto-reclosing blocking condition .................................................................................... 373
3.1.10 Logic diagram.............................................................................................................. 374
3.3 Setting list ............................................................................................................... 380
3.4 Report list ............................................................................................................... 382
CHAPTER 32 SECONDARY CIRCUIT MONITORING ......................................................... 385
1 CURRENT TRANSFORMER SECONDARY CIRCUIT SUPERVISION ............................................. 386
1.1 Introduction............................................................................................................. 386
1.2 Function module description .................................................................................. 386
1.3 Detailed description ................................................................................................ 386
IX
1.3.1 Protection principle .......................................................................................................... 386
1.3.2 Setting list ........................................................................................................................ 387
1.3.3 Report list ......................................................................................................................... 387
2 VT FAILURE ...................................................................................................................... 387
2.1 Introduction ............................................................................................................. 387
2.3.1 Protection principle .......................................................................................................... 388
2.3.2 Setting list ........................................................................................................................ 392
2.3.3 Report list ......................................................................................................................... 393
2.3.4 Technical parameter ........................................................................................................ 393
CHAPTER 33 USER-DEFINED FUNCTION ......................................................................... 395
1 INTRODUCTION ................................................................................................................. 396
2 USER-DEFINED CONFIGURATION ........................................................................................ 396
2.1 Open project ........................................................................................................... 396
2.2 Binary input configuration ....................................................................................... 396
2.3 Binary output configuration..................................................................................... 398
2.4 LED configuration ................................................................................................... 400
2.5 IO Matrix configuration ........................................................................................... 400
2.5.1 AC IO configuration.......................................................................................................... 401
2.5.2 Binary IO configuration .................................................................................................... 401
2.6 Binary input switches setting group ........................................................................ 401
2.6.1 Function description ......................................................................................................... 401
2.6.2 Setting list ........................................................................................................................ 403
2.7 Other configurations ............................................................................................... 403
2.8 Defined logic ........................................................................................................... 403
CHAPTER 34 CONTROL FUNCTION................................................................................... 405
1 ISOLATOR TELECONTROL OF CIRCUIT BREAKER ................................................................... 406
1.1 Introduction ............................................................................................................. 406
2 DIRECT CONTROL ............................................................................................................. 407
2.1 Introduction ............................................................................................................. 407
3 REPORT LIST .................................................................................................................... 407
CHAPTER 35 SUBSTATION COMMUNICATION ................................................................ 409
1 INTRODUCTION ................................................................................................................. 410
1.1 Communication protocol......................................................................................... 410
1.1.1 IEC61850-8 communication protocol ............................................................................... 410
1.1.2 IEC60870-5-103 communication protocol ........................................................................ 410
1.2 Communication port ............................................................................................... 410
1.2.1 Faceplate communication port ......................................................................................... 410
1.2.2 RS485 communication port .............................................................................................. 410
1.2.3 Ethernet communication port ........................................................................................... 410
1.4 Typical substation communication mode ............................................................... 412
1.5 Typical time synchronization mode ........................................................................ 412
CHAPTER 36 REMOTE COMMUNICATION ........................................................................ 413
1 BINARY SIGNAL TRANSMISSION ......................................................................................... 414
2 REMOTE COMMUNICATION CHANNEL ................................................................................. 414
2.1 Non-frame format ................................................................................................... 414
2.2 Frame format .......................................................................................................... 416
3 TECHNICAL PARAMETER .................................................................................................... 417
3.1 Non-frame format ................................................................................................... 417
3.2 C37.94 interface specification ................................................................................ 418
CHAPTER 37 MAN-MACHINE INTERFACE (MMI) AND OPERATION ............................... 419
1 INTRODUCTION ................................................................................................................. 420
2 FUNCTION DESCRIPTION ................................................................................................... 420
2.1 Liquid crystal display (LCD).................................................................................... 420
2.2 Man-machine interface (MMI) ................................................................................ 420
2.3 Menu structure ....................................................................................................... 422
X
CHAPTER 38 IED HARDWARE ............................................................................................ 427
1 INTRODUCTION ................................................................................................................. 428
1.1 IED structure .......................................................................................................... 428
19
1.1.1 4U, 2 inch device ..................................................................................................... 428
1.1.2 4U, 19 inches device ....................................................................................................... 428
1.2 Module arrangement diagram ................................................................................ 429
19
1.2.1 4U, 2 inch device ..................................................................................................... 429
1.2.2 4U, 19 inches device ....................................................................................................... 430
2 ANALOG INPUT MODULE .................................................................................................... 430
2.1 Introduction............................................................................................................. 430
2.2 Analog input module introduction ........................................................................... 430
3 BI MODULES..................................................................................................................... 433
3.1 Introduction............................................................................................................. 433
3.2 BI Module description ............................................................................................. 433
4 BO MODULES ................................................................................................................... 435
4.1 Introduction............................................................................................................. 435
4.2 BO module description ........................................................................................... 435
5 BINARY INPUT AND OUTPUT MODULE .................................................................................. 437
5.1 Introduction............................................................................................................. 437
5.2 Binary input and output module introduction.......................................................... 437
6 CPU MODULE .................................................................................................................. 440
6.1 Introduction............................................................................................................. 440
6.2 CPU module introduction ....................................................................................... 441
7 POWER SUPPLY MODULE................................................................................................... 443
7.1 Introduction............................................................................................................. 443
7.2 Power module introduction..................................................................................... 443
8 TCS MODULE ................................................................................................................... 445
8.1 Introduction............................................................................................................. 445
8.2 Instruction of TCS module ...................................................................................... 445
8.2.1 TCS trip monitoring circuit ............................................................................................... 447
8.2.2 Binary output circuit with high-capacity ........................................................................... 448
8.2.3 Ordinary BO circuit .......................................................................................................... 449
9 WIRE CONNECTION TERMINAL ........................................................................................... 450
10 TEST ............................................................................................................................... 451
11 STRUCTURAL DESIGN ....................................................................................................... 453
12 CE CERTIFICATE .............................................................................................................. 453
CHAPTER 39 APPENDIX...................................................................................................... 455
1 EQUIPMENT PARAMETER................................................................................................... 456
2 REPORT LIST .................................................................................................................... 457
2.1 Alarm report............................................................................................................ 457
2.2 Operation report ..................................................................................................... 458
3 ANALOG LIST .................................................................................................................... 459
4 TYPICAL WIRING ............................................................................................................... 462
5 INVERSE TIME CHARACTERISTIC ........................................................................................ 466
5.1 Twelve types of inverse time characteristic curve of IEC and ANSI ...................... 466
5.2 User-defined properties .......................................................................................... 466
6 EXPLANATION OF ABBREVIATIONS ..................................................................................... 467
6.1 Explanation of setting abbreviations ...................................................................... 467
6.2 Explanation of logic switch abbreviations .............................................................. 477
6.3 Explanation of trip report and alarm report ............................................................ 482
6.4 Explanation of operation report abbreviations ....................................................... 488
6.5 Explanation of device menu abbreviations ............................................................ 489
XI
XII
Chapter 1 Introduction
About this chapter

This chapter gives a brief introduction to the CSC-100 series
digital line protective device.
1
1 IED overview
The CSC-100 series digital line protective device features with high
sensitivity, high reliability and fast response, which are applicable to
overhead lines, cable lines or mixed lines. The description is applied to the
following table:
Table 1 Applicable IED
Type Sub-type Description
CSC-101-EB
CSC-101 It is equipped with pilot distance protection function
CSC-101-EBL
CSC-103-EB It is equipped with differential protection function and pilot
CSC-103 CSC-103-EBL distance protection function
The protective device is provided with many advanced functions, which

can be applied to:
1) Overhead lines or cable lines of all voltage classes;
2) Two-terminal, three-terminal and terminated lines;
3) All kinds of substation configurations, such as 3/2 connection,
single-bus or double-bus connection, etc;
4) Series compensation for extra-long lines;
5) Short lines;
6) Heavily loaded lines;
7) Integrated auto-reclosing;
8) It is able to communicate with substation automatic system.
Apply the method of “compensation by phases” to impedance
measurement, so as to provide the ground impedance relay with better
phase selection function. Combined with phase compensation, fast
filtering and fast calculation methods, a fast distance protection is formed.
The protective device may provide high-sensitive and reliable polygonal
and MHO characteristics distance protection. In addition to separated zone
extension functionality, five distance zones have fully independent
measuring and settings which gives high flexibility for all types of lines and
fault resistances. Many other functions are integrated to provide a
complete backup protection library.
The wide application flexibility makes the IED an excellent choice for both
new installations and retrofitting of the existing stations.
2 IED characteristic
1) Integrated protection function and bay control unit function;
2) With dual-CPU interlock function, so as to avoid protection
maloperation in case of material fault of in-built elements;
3) Single and/or three phase tripping/reclosing;
4) Circuit breaker position status monitoring;
5) High sensitive startup components, which enhance the IED sensitivity
and anti-interference performance and avoid maloperation:
2
a) Current sudden-change startup component;

b) Zero sequence current startup component;
c) Static stability startup component.
6) Three kinds of phase selectors of undervoltage startup component for
weak-infeed end of lines:
a) Current sudden-change phase selector;
b) Zero sequence and negative sequence phase selector;
c) Undervoltage phase selector.
7) Four kinds of directional components cooperate each other so as to
determine the fault direction correctly and promptly:
a) Memory voltage direction component;
b) Zero sequence direction component;
c) Negative sequence direction component;
d) Impedance directional component.
8) Differential protection (applicable to CSC-103 only, CSC-101 is not
provided with this function):
a) Fast split-phase current differential protection;
b) Capacitive current compensation;
c) Detection of CT circuit break and CT saturation;
d) CT ratio compensation;
e) Synchronous sampling;
f) No-delay two channels switch.
9) Full scheme phase-to-phase and phase-to-earth distance protection
with four quadrilateral protection zones and additional extension zone
and ohm characteristic (21, 21N);
10) Power oscillation monitoring interlock (68):
a) Proven and reliable principle of power swing logic;
b) Unblocking component of power swing.
11) Pilot channel fiber Interface supports both single-channel connection
and two-way channel connection;
12) Connect to the communication network and support the protocols of
C37.94 and G.703 (Application in optical fiber multifunction feeder
protection, that is, CSC-103 and CSC-101 with optical fiber pilot
protection);
13) Pilot protection configuration (85):
a) Permissive underreach transfer trip (PUTT);
b) Permissive overreach transfer trip (POTT) scheme;
c) Blocking mode;
d) Interactive tripping.
3
14) Special logic of pilot protection:

a) Power converse;
b) Weak feedback system;
c) Evolving fault;
d) Sequential tripping.
15) Also equipped with module self-check function;
16) The device can provide complete report records, including operation
report, alarm report and tripping report. Up to 2000 reports can be
stored, and the reports can be saved, even there is a power outage;
17) Up to three electrical /optical Ethernet ports can be selected to
communicate with substation automation system by IEC61850
protocol or TCP103 protocol;
18) Up to two electrical RS-485 ports can be selected to communicate
with substation automation system by IEC60870-5-103 protocol;
19) It supports PRP protocol based on IEC 62439-3, the device can be set
to PRP mode, and the dual network ports adopt redundant mode to
send and receive information in parallel;
20) Simple network time protocol (SNTP), pulse, IRIG-B or 1588
synchronizing modes can be selected to time synchronization;
21) Configurable LEDs (Light Emitting Diodes) and input or output relays
satisfied users’ requirement;
22) A friendly MMI;
23) The utility software AESPStudio is used for setting, protecting,
monitoring, fault analysis and function configuration, etc.
24) Support two groups of CT in 3/2 connection mode. The CTRatio of two
groups of CT must be consistent.
3 Basic function
3.1 Protection function
The protection device has a powerful database, providing two standard
feature configurations (CSC-101\103).
Table 2 Standard configuration of functions
IEC 61850
No. Function description ANSI code Logic node CSC-101 CSC-103
name
Line differential
1 87L PDIF × √
protection
Line distance
2 21,21N PDIS √ √
protection
Power swing
3 monitoring and 68 RPSB √ √
blocking
Pilot distance
4 85–21，21N PSCH √ √
protection
Zero sequence
5 protection of pilot 85–67N PSCH √ √
direction
4
IEC 61850
No. Function description ANSI code Logic node CSC-101 CSC-103
name
6 Overcurrent protection 50,51,67 PVOC √ √
7 Earth fault protection 50N,51N,67N PVOC √ √

Emergency
8 50，51 PVOC √ √
overcurrent protection
Emergency earth fault
9 50N，51N PVOC √ √
protection
Negative sequence
10 46 PTOC √ √
current protection
11 Overvoltage protection 59 PTOV √ √
Negative sequence
12 47 PTOV √ √
voltage protection
Undervoltage
13 27 PTUV √ √
protection
Thermal overload
14 49 PTTR √ √
protection
15 Power protection 32D √ √
Circuit breaker failure
16 50BF RBRF √ √
protection
17 Dead zone protection 50DZ √ √
18 Stub protection 50STUB PTOC √ √

Pole discrepancy
19 62PD PPDP √ √
protection
Disconnection
20 46BC √ √
protection
Loss of synchronism
21 78 √ √
protection
Underfrequency
22 81UF PTUF √ √
protection
Overfrequency
23 81OF PTOF √ √
protection
Frequency change rate
24 81DF PFRC √ √
protection
Zero sequence power
25 32N PVOC √ √
direction protection
26 Switch-on-to-fault 50SOTF PSOF √ √
27 Overload alarm 50OL √ √

Synchro-check and
28 25 RSYN √ √
dead voltage check
single/three-phase
29 79 RREC √ √
auto-reclosing
Current transformer
30 secondary circuit √ √
supervision
31 VT failure 97FF √ √
32 Fault locater FL √ √
Disturbance and fault
33 FR √ √
record
5
3.2 Monitoring function

Table 3 Monitoring function
Description
Redundant A/D sampling data self-check
Voltage current phase sequence monitoring
𝟑𝟑𝑰𝑰𝟎𝟎 Polarity monitoring
Three harmonic voltage monitoring
Check synchronization voltage monitor
Breaker auxiliary contacts monitoring
Primary broken circuit monitoring
Self-monitoring
Setting logic self-check
Fault phase display
Disturbance and fault record
Trip circuit monitoring
3.3 Measurement function

Measurement is acquired through the dedicated measurement channels.
Table 4 Measurement function
Description
Current: measurement Ia, measurement Ib, measurement Ic
Voltage: measurement Ua, measurement Ub, measurement Uc, measurement Ux, measurement
Uab, measurement Ubc, measurement Uca
Active power: P, Pa, Pb, Pc
Reactive power: Q, Qa, Qb, Qc
Power factor: COS
Frequency: F
3.4 Control function

Table 5 Control function
Description
Position of circuit breaker, isolator and other switching devices control
6
3.5 Substation communication

Table 6 Substation communication
Communication port on the faceplate
RJ45 Ethernet communication port

Communication port on the backplate
Isolated RS485 communication port
Ethernet electrical/optical communication port
Time synchronization port

Communication protocol
IEC 61850 protocol
IEC 60870-5-103 protocol
DNP3.0 (supported by Master above 4.0)
MODBUS (supported by Master above 4.0)
3.6 Remote communication

Table 7 Remote communication
Description
Communication port
Power line wave carrier interface

0-2Optical fiber communication port (only for CSC-103 and CSC-101 with optical fiber pilot
protection)
communication distance
100kM
Connection mode
Direct fiber connection (only for CSC-103 and CSC-101 with optical fiber pilot protection)
Digital communication network (through translator)
7
Chapter 2 General functions
About this chapter

The chapter describes the general IED functions.
9
1 Event record and analysis

1.1 Introduction
To get fast, complete and reliable information about fault current, voltage,
binary signal and other disturbances in the power system is very important.
Through record function of fault data, operators can make better analysis
about the related primary and secondary devices during and after the fault.
Operational personnel can acquire valuable information to explain the
cause of the fault and modify the IED configuration in accordance with the
conclusion to improve IED reliability.
Disturbance data includes devices samples and calculated analogs, BI
and BO signals.
1.2 Fault record

IED can save the latest 2000 disturbance and fault records (which will not
loss during power failure). The records can be viewed through operation
interface of device, communication port or debugging software. The types
of fault reports include startup report, trip report, alarm report, operation
report and binary input state change report.
Main information of fault records includes:
1) Fault time: date and time
2) Time list: trip component and time
3) Running data: current, voltage, frequency and phase
1.3 disturbance and fault record

Disturbance and fault record function is used to capture the sampling data,
analog data and status data of predefined length before and after an event
(analog data is only applicable for the middle node, mid file), and replay
the protected equipment running track before and after the event. Any
logic component and binary input and output of the device can be used to
trigger disturbance and fault record function.
Disturbance and fault record contains analog channel, digital channel (BI,
BO and protection component states) as well as time label sequence
information.
IED makes data record, according to each cycle. Each record total length
can reach up to 20s and the latest 16 protection trip and 16 times startup;
total 32 records can be saved.
Disturbance and fault record can be exported through the Ethernet
debugging port (COMTRADE format) by using the debugging tool software,
and it can also be uploaded to engineer station through the substation
communication network and used to analyze IED trip.
1.4 Sequence of event (SOE)

IED monitors and disturbance and fault records a total of 2000 state
change events of the position change of binary input and output, state
change of disturbance and fault record and connector enable/disable
tripping in real time; it also records event time scale, reason and present
state. These real-time data are transferred to the station control center
10
through communication port. The protection SOE reports can be viewed

by local MMI or debugging software.
1.5 Operation record

IED records the latest 2000 important modification of operating parameters
and the operation object, operation time, data modifications or operational
reasons will be recorded, which can provide bases for event tracing.
Operation information is saved in operation record of the IED. User can
view these report information through MMI or debugging software.
2 Diagnosis function
2.1 Introduction
The IED can be self-diagnosis and self-monitoring operation is achieved
by means of soft hardware self-test and monitoring, to ensure the high
reliability of operation through the Power on. Self-checking objects include
key components of hardware (such as analog sampling circuit, output
circuit of binary input and output, RAM and ROM) and hardware
accessories (such as backup battery, communication interface) and
important running parameters (such as setting, soft connectors), in
addition, the embedded two level software monitor can be used to monitor
the operation conditions of the software. When the device detects any
abnormal conditions, the device will record the abnormal events and drive
signal node and LED lights. For the key abnormal conditions, the device
will block the protection function and the important output circuit to prevent
the device from maloperations.
The user can also check the important hardware circuit of the device
through the test command provided by the device, such as the AC circuit,
BI circuit and BO circuit, etc.
In order to cooperate with automation system engineering implementation,
the device provides telecontrol point check function, so the local SCADA
and telecontrol master database can be check, the complicated manual
point check operation between the SCADA operator and telecontrol
operator is avoided. Mainly includes the telesignalisation check, telemetry
check and so on.
2.2 Diagnostic principle

1) Measurement device power;
2) Check zero drift and zero drift out-of-limits;
3) Confirm alarm circuit;
4) Check setting and parameter.
3 Time synchronization function

3.1 Introduction
The IED, as a part of the protection system, can be time synchronized by
time synchronization source. In the security automation intelligent system,
through the time synchronization, IED and other devices in the system
have the same clock source. When the system fault or abnormal, there is a
11
unified clock reference between the various devices.
3.2 Synchronization principle

Definition of time
The error of a clock is the difference between the actual time and the
synchronized clock. The rate accuracy of a clock is normally called the
clock accuracy. When the clock deviation is too large, the clock will
re-synchronize to ensure clock accuracy is within the set range.
Synchronization principle
Generally speaking, synchronization can be seen as a hierarchical
structure. A module is synchronized from a higher level and provides
synchronization to lower levels.
Synchronization from a higher level
Module
Optional synchronization of modules at

a lower level
Figure 1 Synchronization principle diagram

A module of the system is synchronized when it receives synchronization
signal from a higher level and this module is time synchronization module.
The less the time synchronization level, the higher the final time
synchronization accuracy is. The same module may have several options
of time synchronization sources with different errors, this module can
choose the best time source and adjust the internal clock, according to the
time synchronization source. The maximum error of a clock can be defined
as:
1) The maximum error of the last synchronization information;
2) The calculated time from last time synchronization information;
3) The rate accuracy of the internal clock in the module.
Time synchronization system provides three synchronization methods:
IRIG-IRIG-B, IEEE1588 and net synchronization and second pulse
synchronization.
3.3 IRIG-IRIG-B synchronization mode

CPU module of the device supports RS485 level IRIG-B (DC) time
synchronization.
12
3.4 PPS synchronization mode

CPU module of the device supports RS485 level PPS signal. If the
substation time is not synchronized with the standard time, the present
time of the substation will be regarded as valid time and the IED time is
synchronized with it. After receiving the pulse signal, the CPU can
automatically adapt to the positive and negative pulses. The electrical
interface is RS485.
3.5 SNTP time synchronization mode

Synchronization via SNTP is implemented on a request-response basis
The IED sends a synchronization request message to an SNTP server.
The SNTP server resets time message after handling transmission delay.
SNTP time synchronization mode is synchronized through Ethernet. In
order to ensure SNTP time synchronization is normal, one SNTP server
must be set, it is suggested that one server can be set at one substation.
The accuracy of SNTP time synchronization method for binary input
quantity is 1ms. The IED itself can be set as a SNTP time synchronization
server.
3.6 IEEE1588 synchronization mode

It supports IEEE1588 high precision network synchronization.
4 Monitoring function
4.1 Check of phase sequence of phase voltage and
phase current
In normal system, the correctness of three-phase sequence of the AC loop
can be checked by three-phase voltage and phase comparing of the
current, if it is wrong, send "3PhSeqUnmatch" report.
4.2 3I0 polarity check

Compare amplitude and phase angle of combined 𝟑𝟑𝑰𝑰𝟎𝟎 and external
𝟑𝟑𝑰𝑰𝟎𝟎 and check whether external 𝟑𝟑𝑰𝑰𝟎𝟎 is connected the other way round. If it
is reversed, send "Extr3I0RvsdPolarity" report.
4.3 Third harmonic voltage check

If the third harmonic voltage is more than 4V, send "3rdHOverReachAlarm"
after 10s but not carry out blocking protection.
4.4 Breaker auxiliary contact detection

If circuit breaker auxiliary contact shows that circuit breaker is at open
position and there is current, "TripPosnA/B/CBIErr" message should be
sent after 2s.
13
Phase A trip position &

2S
TripPosnABIErr
Ia>0.08In
Phase B trip position &

2S
TripPosnBBIErr
Ib>0.08In
Phase C trip position &

2S
TripPosnCBIErr
Ic>0.08In
Figure 2 Logic diagram of abnormal BI alarm of trip position A/B/C

In 3/2 connection mode and double CT Mode, add the second group of tripping
abnormal alarm message "Grp2TripPosnA/B/CBIErr".
Phase A trip position &

2S
TripPosnABIErr
Ia1>0.08In
Phase B trip position &

2S
TripPosnBBIErr
Ib1>0.08In
Phase C trip position &

2S
TripPosnCBIErr
Ic1>0.08In
Grp2 Phase A trip position &

2S
Grp2TripPosnABIErr
Ia2>0.08In
Grp2 Phase B trip position &

2S
Grp2TripPosnBBIErr
Ib2>0.08In
Grp2 Phase C trip position &

2S
Grp2TripPosnCBIErr
Ic3>0.08In
Figure 3 In 3/2 connection mode, Logic diagram of abnormal BI alarm of trip position
A/B/C
4.5 Fault locater

Fault location aims at locating the fault accurately. Fault location is one of
the main auxiliary functions of the protection device, and the fault location
algorithm is used to estimate the distance between the fault and protection
device.
IED will send location report after protection trip. This function is based on
fault phase wave measuring voltage and measuring current location fault.
At present, fundamental wave measuring voltage and line parameters are
the most popular method to local the fault.
14
In addition, fault impedance cannot be reflected exactly due to some

situations that affect the calculation. For example, the zero sequence
coupling compensation of adjacent lines of transmission line will affect the
fault location calculation of the device. Thus, induction of the double-loop
device should be taken into consideration, and connect to the neighbor
zero sequence current (Figure 4 ) from channel "IN(mutual)" (I4 in the
terminal figure).
L1
L2
L3
52 52
CSC-103
IA
IB
IC
IN
IN (M)
Figure 4 Fault located double-loop out-flowing current compensation

The following formula is applied to fault location with the consideration of
adjacent line induction and zero sequence current compensation.
𝑼𝑼𝑻𝑻(𝑩,𝑪𝑪)
𝒁𝒁 =
𝑰𝑰𝑻𝑻(𝑩,𝑪𝑪) + 𝑲𝑲𝑰𝑰 𝟑𝟑𝑰𝑰𝟎𝟎 + 𝒋𝒋𝑲𝑲𝒎𝒎 × 𝑰𝑰𝑰𝑰𝑴
Where:
𝒁𝒁𝟎𝟎 −𝒁𝒁𝟏𝟏 𝑿𝑿𝟎𝟎𝑴
𝑲𝑲𝑰𝑰 = ,𝑲𝑲𝑴 =
𝟑𝟑𝒁𝒁𝟏𝟏 𝑿𝑿𝟏𝟏
The other factor affecting fault location calculation is the introduction of the
terminal fault current, and correct compensation can make the fault
location as accurate as possible. For this reason, the imaginary part ZL1 of
𝒁𝒁𝑳𝑳𝟏𝟏 is derived from the following formula, and the real imaginary part is
computed independently.
𝑼𝑼𝑻𝑻 𝑰𝑰𝒎𝒎 𝒁𝒁𝑳𝑳𝟏𝟏 + 𝑰𝑰𝒌𝒌 𝑹𝑹𝒈 𝑰𝑰𝒌𝒌
𝒁𝒁𝒎𝒎𝟏𝟏 = = = 𝒁𝒁𝑳𝑳𝟏𝟏 + 𝑹𝑹 𝒆𝒆𝒋𝒋𝒂𝒂
𝑰𝑰𝒎𝒎 𝑰𝑰𝒎𝒎 𝑰𝑰𝒎𝒎 𝒈
15
M N
L1 L2
Im Ik Rg In
jX
Ik
R e jα
XL1
ZL1
Im g
XM1
ZM1
Figure 5 Auxiliary current compensation of remote feeder for fault location calculation
5 Authorization
To safeguard the interests of customers, accesses to the IED and the
debugging software are restricted in terms of authorization. In fact, the use
of device and related debugging software should pay attention to the
following issues:
1) Two methods are provided for debugging the IED:
a) Local: debugging through the local MMI;
b) Remote: debugging through the communication ports.
2) Different user has different authority to have access to or operate
device.
16
Chapter 3 Basic protection component
About this chapter

This chapter describes basic protection components
including startup components, phase selectors and
directional components.
17
1 Startup component
1.1 Introduction
The startup component is mainly used for fault monitoring, protection
startup and positive power switching on for outlet relay. Once action, the
startup component only can return during the protection of full resetting.
Once any startup component is actuated, the protection will be started up
and the positive power at the outlet relay will be switched on.
Startup component includes:
1) Abrupt-change current startup component;
2) Zero sequence current startup component;
3) Overcurrent startup component;
4) Undervoltage startup component in weak-source;
5) Steady state consistence loosing startup component.
1.2 Abrupt-change current startup component

Abrupt-change current startup component is the main startup component
that can sensitively detect most of faults. The equation is shown as follow:
∆𝒊𝒊𝝋𝝋 > 𝑰𝑰𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂
Or
∆𝟑𝟑𝟑𝟑𝟎𝟎 > 𝑰𝑰_𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂
Where:
1) ∆𝒊𝒊𝝋𝝋 is abrupt-change value of phase current sample;
2) ϕϕ refers to AB, BC or CA, e.g. 𝒊𝒊𝑻𝑻𝑩 = 𝒊𝒊𝑻𝑻 − 𝒊𝒊𝑩 ;
3) ∆𝟑𝟑𝟑𝟑𝟎𝟎 is abrupt-change value of zero sequence current sample.
4) 𝑰𝑰_𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂𝒂:"AbruptChgCurrSet".
The abrupt-change current component trips when the current
abrupt-change value ∆𝒊𝒊𝝋𝝋 or zero sequence current abrupt-change value
∆𝟑𝟑𝟑𝟑𝟎𝟎 among phases is greater than "AbruptChgCurrSet".
∆iϕϕ > I _ abrupt ≥1

Abrupt-change current startup
∆3i 0 > I _ abrupt
I_abrupt：“AbruptChgCurrSet”
Figure 6 Logic diagram of abrupt-change current startup
1.3 Zero sequence current startup component

In addition to the abrupt-change current startup component, the zero
sequence current startup components also have high sensitivity in
detecting high resistance grounding. As an auxiliary startup component, it
only works with 10s delay trip. The equation is shown as follow:
𝟑𝟑𝟑𝟑𝟎𝟎 > 𝒌𝒌 × 𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰
Where:
18
1) 𝟑𝟑𝟑𝟑𝟎𝟎 3I0 is the measured value of zero sequence current;

2) 𝒌𝒌K is internal coefficient;
3) 𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰 I0dz is the minimum value of "REFSet", "Pilot3I0Set",
"3I0Stage1(2,3,4)CurrSet", and "SOTF3I0Set";
4) "REFSet "will be valid as differential protection is enabled;
5) Pilot earth fault setting is the current setting of directional pilot earth
fault protection and will be valid as directional pilot earth fault
protection is enabled;
6) Earth fault each stage current setting is current setting of earth fault
protection of all enabled definite and inverse time limit;
7) "SOTF3I0Set" is the zero sequence current setting of switch-onto fault
overcurrent protection.
1.4 Overcurrent startup component

If overcurrent protection function is enabled, over current startup
component is also considered to improve fault detection sensitivity. Same
as zero sequence current startup and to get reliable action, overcurrent
startup operates with 30ms delay as an auxiliary startup component. The
equation is shown as follow:
𝑰𝑰𝒂𝒂 > 𝒌𝒌 × 𝑰𝑰𝑰𝑰𝑰𝑰
Or
𝑰𝑰𝒂𝒂 > 𝒌𝒌 × 𝑰𝑰𝑰𝑰𝑰𝑰
Or
𝑰𝑰𝑰𝑰 > 𝒌𝒌 × 𝑰𝑰𝑰𝑰𝑰𝑰
Where:
1) 𝑰𝑰𝒂𝒂(𝒂𝒂,𝑰𝑰) 3I0 is the measured value of phase current;
3) 𝑰𝑰𝑰𝑰𝑰𝑰It is the current setting for each stage of overcurrent, and the
minimum setting of "StubCurrSet" and "SOTFOCSet";
4) Each stage overcurrent setting is current setting of all enabled definite
and inverse time overcurrent protection;
5) "StubCurrSet" is the setting of stub protection;
6) "SOTFOCSet" is the current setting of switch-onto fault current
protection.
1.5 Steady state losing stability startup component

The logic of steady state losing stability startup is as follow:
1) 𝑰𝑰𝒂𝒂 > “𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒” ,
𝑰𝑰𝒃𝒃 > “𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒” ,
𝑰𝑰𝒄𝒄 > “𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒”, and the abrupt-change current
startup component is not operated;
2) All the phase-to-phase impedance of AB, BC and CA are located in
impedance areas of zone 3, zone 4 and zone 5 which is enabled, and
19
the abrupt-change current startup component hasn't operated.

If any of the conditions has continued for 30ms, steady state losing stability
startup component will operate.
1.6 Pilot protection undervoltage startup component

(for weak infeed systems)
In conditions that one end of the protected line has a weak-source and
accordingly the fault abrupt-change phase to phase current is too low to
startup the IED, low-voltage startup component can come into service to
startup the pilot protection communication scheme with weak infeed logic.
When IED receives signals from another side, its operation criteria are as
follows:
𝑼𝑼𝒂𝒂𝒂𝒂 _𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺
𝑼𝑼𝒂𝒂𝒆𝒆 < 𝒌𝒌 ×
√𝟑𝟑
Or
𝑼𝑼𝒂𝒂𝒂𝒂 < 𝒌𝒌 × 𝑼𝑼𝒂𝒂𝒂𝒂 _𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺
Where:
1) 𝑼𝑼𝒂𝒂𝒆𝒆 Upe is the phase-to-earth voltage;
2) 𝑼𝑼𝒂𝒂𝒂𝒂 Upp is the phase-to-phase voltage;
4) 𝑼𝑼𝒂𝒂𝒂𝒂 _𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺 It is "VTSecVal".
1.7 Weak infeed startup component of differential

protection (for weak infeed system)
If the end of the protected circuit is weak or no power supply, as circuit fault
occurs at protection forward direction of weak power supply end, the
current flowing through the weak supply end may be small, and device
cannot start. Therefore, the device has no weak-infeed startup (differential
current+undervoltage startup) function:
When the weak feed side receives the start signal of the opposite side, the
power supply side protection trip is allowed when the following conditions
are met, and the current side can also trip.
1) Receive the startup signal of opposite end;
2) At least one phase differential current is greater than the trip setting:
𝑰𝑰𝒂𝒂(𝒂𝒂,𝑰𝑰) _𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 > 𝑰𝑰_𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫;
3) Corresponding phase to earth voltage is less than 36V or interphase
voltage less than 60V.
1.8 Distant calling startup component of differential

protection (for weak infeed system)
If high resistance grounding occurs in the protected line, close fault side
protection can be reliably started. The current of remote side fault
protection may be small, and the device cannot start. Therefore, the device
is provided with the function of remote calling startup (differential current +
voltage abrupt-change startup) function. If the following conditions are met,
20
the distant calling startup component can start:

1) Receive the startup signal of opposite end;
2) Zero sequence differential current is greater than "REFSet":
𝑰𝑰𝟎𝟎𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑰𝑰_𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫; or the differential current is greater than the
trip setting:𝑰𝑰𝒂𝒂(𝒂𝒂,𝑰𝑰) _𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 > 𝑰𝑰_𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫;
3) This side∆𝑼𝑼𝒂𝒂𝒆𝒆 > 𝟖𝟖𝟖𝟖or∆𝟑𝟑𝑼𝑼𝟎𝟎 > 𝟏𝟏𝟏𝟏.
2 Phase selector component

2.1 Introduction
The phase selector for distance protection can detect the phase of fault,
and it is required to detect the faults through the comprehensive utilizing of
phase selection principles so as to meet the phase selector trip protection
requirements.
1) During the initial stage of fault after the startup of abrupt change, the
abrupt-change phase selector is used;
2) During the later stage of fault, the symmetric component phase
selector is used.
The abrupt-change current phase selector and symmetric component
phase selector are inapplicable to the weak power, small fault or dead
current of terminal substation where the low-voltage phase selector is
used
The trip of phase selectors mentioned above is not required in differential
protection. In such case, it is required to calculate the differential current
and break current according to the phase and trip off the fault category
according to the calculation results and combining with the rated
differential protection value.
2.2 Function module description

The I/O signals described herein only reflect the visible engineering part.
The input and output signal diagram of phase selection component is
shown as follow:
PhSel:
1
Phase_A
2
Phase_B
3
Phase_C Tripcom
4
Phase_AB 1
5 PhaseA_Fault
Phase_BC 2
6 PhaseB_Fault
Phase_CA
7 3
Phase_ABN PhaseC_Fault
8 4
Phase_BCN PhaseN_Fault
9
Phase_CAN
(1) (2)
Figure 7 The input and output signal diagram of phase selection component
The left side is the input and the right is the output, parameter description
is shown in the following table.
21
Table 8 Parameter description
Function Identifier Description
Output:
Phase_A Phase A is the fault phase
Phase_B Phase B is the fault phase
Phase_C Fault phase C
Phase_AB Phase AB is the fault phase

Diff_POU::PhSel
Phase_BC Phase BC is the fault phase
Phase_CA Phase CA is the fault phase
Phase_ABN Phase ABN is the fault phase
Phase_BCN Phase BCN is the fault phase
Phase_CAN Phase CAN is the fault phase
PhaseA_Fault Phase A fault
PhaseB_Fault Phase B fault

FAULT_POU::Tripcom
PhaseC_Fault Phase C fault
PhaseN_Fault Phase N fault
Light can be configured by AESP.
2.3 Abrupt-change current phase selector component

Abrupt-change current selects the fault phase difference by comparing the
difference of the abrupt-change current∆IAB, ∆IBC and ∆ICA (∆IXY=IX-IY).
The relative value of the phase-to-phase differential current ΔIAB, ΔIBC and
ΔICA at the various fault types is shown in following table. In this table “+”
means the larger value, “++” represents the largest one, and “-” indicates
the smaller one. For example, ∆IAB and ∆ICA are large while ∆IBC is small
(with regard to each other), IED will select fault type as phase A
phase-to-earth fault. Nevertheless, if ∆IAB is very large, while ∆IBC and ∆ICA
are small at the same time, IED will determine fault type as AB.
Table 9 Current abrupt-change phase selection scheme
Phase selection results
Aϕ Bϕ Cϕ AB BC CA ABC
∆Iϕϕ
∆IAB ＋＋ - ＋＋＋＋＋＋
∆IBC - ＋＋＋＋＋＋＋＋
∆ICA ＋ - ＋＋＋＋＋＋＋
22
2.4 Phase selector component of steady state

sequence component
As mentioned before, IED additionally applies symmetric component
phase selector. The stable status component phase selector selects the
phase through the angle between zero sequence current component and
negative sequence current components, and the phase impedance is used
to confirm whether the phase selection is correct.
According to the theoretical analysis, when the phase A connection or the
phase BC is short circuited and the smaller arc resistance is grounded,
based on the I0a, the I2a is located in the -30°to +30°zone, When both
phase B and C are short circuited and grounding resistance is increased,
I2a is more lagged behind I0a, which is more close to 90°, and is divided
into six phase regions according to the angle relation of I2a/I0a, and the
analysis is shown in the following diagram and table.
I0a
0 0
+30 AN,BCN -30
ABN BCN
0 0
+90 -90
CN,ABN BN,CAN
0 0
+150 CAN -150
Figure 8 Relationship diagram between zero sequence current component and negative
sequence current component angle of various faults
Table 10 Steady status component phase selector table
Phase area Angle range Phase selection results
1 +30°~-30° AN or BCN
2 +90°~+30° ABN
3 +150°~+90° CN or ABN
4 -150°~+150° CAN
5 -90°~-150° BN or CAN
6 -30°~-90° BCN
For example, the angle between the negative sequence component and
the zero sequence components is between -30 degrees and +30 degrees,
and the fault type is A phase grounding or fault between phase B and C or
grounding fault between phase B and C.
As shown in the table above, area 2, 4, and 6 directly reflect the relative
fault type, but area 1, 3, and 5 may reflect the existence of two types of
fault, at this point, it is distinguished through phase-to-phase impedance
calculation. If the phase-to-phase impedance is greater than that of the
23
impedance setting of phase-to-phase, the possibility of phase-to-phase

fault is eliminated, and it is judged to the corresponding single-phase
grounding fault, or it is judged to the corresponding phase-to-phase fault.
2.5 Undervoltage phase selector component

In the case of weak-infeed source, two previous phase selector cannot
operate reliably. Therefore low-voltage phase selector has been
considered in the weak-infeed sides. In this case the IED will monitor VT
Failure, while there is no problem with VT and IED receives startup signals
from the opposite side, the formula of undervoltage phase selector is as
follow:
𝑼𝑼𝒂𝒂𝒆𝒆 < 𝒌𝒌 × 𝑼𝑼𝒂𝒂𝒆𝒆 _𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺
or
𝑼𝑼𝒂𝒂𝒂𝒂 < 𝒌𝒌 × 𝑼𝑼𝒂𝒂𝒂𝒂 _𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺
Where:
1) 𝑼𝑼𝒂𝒂𝒆𝒆 and 𝑼𝑼𝒂𝒂𝒂𝒂 are phase-to-earth voltage and phase-to-phase
voltage respectively
2) 𝑼𝑼_𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺 is the system secondary rated voltage value
3) 𝒌𝒌K is internal coefficient
2.6 Cross line fault phase selector component

Cross line fault phase selector component applies comprehensive phase
selector component based on comparative fault voltage, current and
phase. The component first identifies the cross line phase, assumes that
the minimum phase voltage or the largest phase current is the fault phase;
then, according to the difference of phase current phase, please detect
that cross line fault or interphase fault at the same point.
3 Directional component
3.1 Introduction
To identify the direction of faults in a reliable manner, the device is
equipped with direction identification component. The protection modules
such as distance protection, HF protection, overcurrent protection and
earth fault protection take the detection of directional component as the trip
conditions for protection. The directional components mentioned above
are well coordinated with such protections.
3.2 Memory voltage direction component

The IED uses the memory voltage and fault current to determine the
direction of the fault. Therefore, transient voltage of short circuit conditions
won’t influence the direction detection. Additionally, it improves the
direction detection sensitivity for symmetrical or asymmetrical close-in
faults with extremely low voltage. But it should be noted that the memory
voltage cannot be effective for a long time. Therefore, the following
directional components will work as supplement to detect direction
correctly.
24
3.3 Zero sequence direction component

Zero sequence directional components have efficient features in the solidly
grounded system. The directional characteristic only relates to zero
sequence impedance angle of the zero sequence network of power
system, regardless of the quantity of load current and/or fault resistance
throughout the fault. The characteristic of the zero sequence direction is
illustrated in following figure.
90°
3I 0
0°
3U 0_Ref
Sensitive angle of zero

sequence direction
Range of zero
sequence direction
Vertical
Forward direction bisector
-3 I 0
Figure 9 Characteristics of zero sequence directional component

Where:
"3I0DirectSensitiveAngle": sensitive angle is settable
Scope of zero sequence direction: 80º
The angle of direction characteristic can be adjusted by Angle_Neg setting
to comply with different system condition. Fault direction is detected as
forward if the angle of −𝟑𝟑𝒊𝒊𝟎𝟎 is in shaded area of the figure above.
3.4 Negative sequence direction component

Negative sequence directional component can make accurate direction
discrimination in any asymmetric fault. The directional characteristic only
relates to negative sequence impedance angle of the negative sequence
network of power system, regardless the quantity of load current and/or
fault resistance throughout the fault. The characteristic of the negative
sequence directional component is illustrated in the following figure.
25
3I2 90°
0°
3 U 2_ Ref
Sensitive angle of
negative sequence
Range of negative direction
sequence direction
Forward direction Vertical bisector

-3 I 2
Figure 10 Characteristics of negative sequence directional component

Where:
"NegSeqDirSensitiveAngle": sensitive angle is settable
Scope of negative sequence direction: 80º
The angle of direction characteristic can be adjusted by Angle_Neg setting
to comply with different system condition. Fault direction is detected as
forward if the angle of −𝟑𝟑𝒊𝒊𝟐𝟐 is in shaded area of the figure above.
3.5 Impedance directional component

Impedance directional component characteristics of distance polygon.(as
shown in the figure below).
X
X_Set
Forward direction
-n∙R_Set
R_Set
R
Negative sequence
-n∙X_Set
Figure 11 Characteristic of impedance directional components

Where:
R_SET: The resistance setting of relevant zone of impedance protection
X_SET: The reactance setting of relevant zone of impedance protection
n: Multiplier for reverse directional component, which makes the reverse
directional component more sensitive than forward one. For distance
protection, n should be selected as 1; for pilot, n should be selected as
1.25.
26
4 Common setting
4.1 Common setting list
Table 11 Common setting list
Range Default value
No. Setting name Step Unit Remark
(In:5A/1A) (In:5A/1A)
Abrupt
change
1. AbruptChgCurrSet 0.01In~4In 4 0.01 A
current
setting
IED reset
time of the
2. IEDRstTime 0.5～10 10 0.01 s
whole
group
3. 3I0DirectSensitiveAngle 0.00～90.00 70.00 0.01 °
4. NSDSensitiveAngle 0.00～90.00 70.00 0.01 °

It is applied
to
overcurrent
protection
function,
5. OCHarmUnblkCurr 0.05In~40.00In 40.00 0.01 A earth fault
protection
function
and
distance
protection
It is applied
to
overcurrent
protection
function,
6. OC2ndHI2/I1Ratio 0.07～0.50 0.07 0.01 earth fault
protection
function
and
distance
function
It is applied
in
7. 3I02ndHI02/I01 0.07～0.50 0.07 0.01 overcurrent
protection
function
It is applied
in
8. 3I0HarmUnblkCurr 0.05In~40.00In 40.00 0.01 A overcurrent
protection
function
1: Ua
2: Ub
3: Uc
9. SyncPh 1-6 1 1
4: Uab
5: Ubc
6: Uca
27
Table 12 Common logic switch list
No. Logic switch setting list Setting Default value Remark

0: non-parallel line mode;
1. ParallelLineMode 1/0 0
1: parallel line mode
0: non-direct grounding
2. EarthSystem 1/0 1 system;
1: grounding system
1-voltage connection line
VT
3. VoltFromLineVT 1/0 0
0-voltage connection
busbar VT
1-phase-to-phase fault
initiates auto-reclosing
4. PPFaultInitAR 1/0 1 0-phase-to-phase fault
trips three phases and
block auto-reclosing
1-three phase fault
initiates auto-reclosing
5. 3PhFaultInitAR 1/0 1 0-three phase fault trips
three phases and block
auto-reclosing
1-trip mode of three-phase
6. 3PhTripMode 1/0 0
0-trip mode of three-phase
1-3/2 wiring type;
7. 3/2BreakerConnectMode 1/0 0 0-single busar or double
busbar wiring type
1-Three-phase voltage
connection;
8. 3PhVoltConnect 1/0 1
0-single-phase voltage
connection
1-VT failure protection off,
0-VT failure protection on
It is applied in overcurrent
9. VTFailProtOff 1/0 0
protection function and
earth fault protection
function
1-External zero sequence
current; 0-self-produced
zero sequence current
10. Extr3I0 1/0 0
It is applied in zero
sequence protection
function
4.2 Setting description

The setting is all secondary values if there is no special note. Impedance
setting is set according to impedance of line.
The zero sequence current mentioned in this manual is 𝟑𝟑𝟑𝟑𝟎𝟎 .
1) "AbruptChgCurrSet": 0.2In is generally recommended. In the places with
great load change, such as power plants, steel works and aluminum
manufacturers, the startup setting may be increased properly to avoid
the frequent startup of equipment. Normally, the “AbruptChgCurrSet”
on both sides of the protected line shall be consistent on the primary
side. However, if the difference in sensitivity of two sides of lines is too
large, difference in setting is allowed.
2) "IEDRstTime": 5s is generally recommended. It is important to note
28
that the full resetting time starts from the moment when all protection
components stop operation.
3) "3I0DirectSensitiveAngle": zero sequence direction component
setting.
4) "NSDSensitiveAngle": negative sequence direction component
setting.
5) "OCOpenHarmonicBlockingCurr": applied in overcurrent protection,
earth fault protection and distance protection.
6) OC2ndHI2/I1Ratio: applied to overcurrent protection and earth fault
protection.
7) "3I02ndHI02/I01": applied to earth fault protection.
8) "3I0HarmUnblkCurr": applied to earth fault protection.
9) "ParallelLineMode": it is used for parallel line mode, when the logic
switch is set to 1.
10) "EarthSystem": neutral point direct grounding system, this logic switch
is set to 1.
11) "VoltFromLineVT": This logic switch is set as 1 when the voltage takes
from the line VT.
12) "PPFaultInitAR": If this logic switch is disabled, IED trips three phases
and block auto-reclosing, when a phase-to-phase fault occurs; If this
logic switch is enabled, IED trips three phases, when a
phase-to-phase fault occurs.
13) "3PhFaultInitAR": If this logic switch is disabled, IED trips three
phases and block auto-reclosing, when a three-phase fault occurs; If
this logic switch is enabled, IED trips three phases, when a
three-phase fault occurs.
Notes: "PPFaultInitAR" needs to cooperate with "3PhFaultInitAR".
If both “PPFaultInitAR” and “3PhFaultInitAR” are set to 0, IED cannot
initiate auto-reclosing, when phase-to-phase or three-phase fault
occurs.
If both “PPFaultInitAR” and “3PhFaultInitAR” are set to 1, IED can
occurs.
If logic switch “PPFaultInitAR” is set to 1, and “3PhFaultInitAR” is set
to 0, IED can initiate auto-reclosing, when phase-to-phase occurs
If logic switch “PPFaultInitAR” is set to 0 and “3PhFaultInitAR” are set
to 1, IED cannot initiate auto-reclosing, when phase-to-phase or
14) "3PhTripMode": If this logic switch is enabled, trip three times when a
protection operation happens in case of any fault.
15) "3/2BreakerConnectMode": Support 3/2 wiring type.
16) "3PhVoltConnect": when three-phase voltage connecting, the logic
switch is 1.
17) "VTFailProtOff": is applied in overcurrent protection function and earth
29
fault protection function; as VT failure disables overcurrent protection

function and earth fault protection, logic switch is 1.
18) "Extr3I0": in zero sequence each stage protection, if zero sequence
current is external connection, logic control is 1.
30
5 Binary input description for trip position

Three-phase trip position can be configured by IO Matrix.
In 3/2 connection mode and double CT Mode , the second group of trip
position is required, which can also be configured by IO Matrix:
1
BI_PHASEA_TWJ
2
BI_PHASEB_TWJ
3
BI_PHASEC_TWJ
4
BI_PHASEA_TWJ2
5
BI_PHASEB_TWJ2
6
BI_PHASEC_TWJ2
Figure 12 Input signal diagram of trip position

Table 13 Binary input description for trip position
Input:
BI_CBOpenA1,Phase A trip
BI_PHASEA_TWJ
position
DIcom
BI_CBOpenB1,Phase B trip
BI_PHASEB_TWJ
position
BI_CBOpenC1,Phase C trip
BI_PHASEC_TWJ
position
BI_CBOpenA2,Grp2 Phase A
BI_PHASEA_TWJ2
trip position
BI_CBOpenB2,Grp2 Phase B
DITWJ_Grp2 BI_PHASEB_TWJ2
trip position
BI_CBOpenC2,Grp2 Phase C
BI_PHASEC_TWJ2
trip position
Note: Take Phase A as an example. Under 3/2 connection mode and

double CT Mode, two groups of circuit breaker positions are connected.
When both groups of circuit breaker positions are divided, the total circuit
breaker position BI_CBAOpen is quantile.
In addition, the auxiliary contact of the circuit breaker is inspected by the
corresponding phase current. When the auxiliary contact signal of the
circuit breaker is indicated as open, and there is current is in the phase,
alarm of corresponding trip position error will be sent. the reports are
"TripPosnABIErr", "TripPosnBBIErr" and "TripPosnCBIErr";In 3/2
connection mode and double CT Mode , the second group of abnormal
tripp position alarm message is added and the reports are "
Grp2TripPosnABIErr ", " Grp2TripPosnBBIErr " and " Grp2TripPosnCBIErr
".
31
Chapter 4 Line differential protection (87L)
Chapter 4 Line differential protection

(87L)
About this chapter

This chapter introduces the protection principle, I/O signals,
parameters, protection reports and technical data of line
differential protection function.
33
1 Introduction
There are three differential protection functions: phase-segregated
differential protection, abrupt change differential protection and restricted
earth fault protection. The differential protection can realize high sensitivity
and reliability in power system interferences by applying the capacitive
current compensation and reliable phase selection logic. The precise time
synchronization and sampling synchronization can ensure the reliable
functioning of differential protection on both sides.
2 Function module description

Line differential protection function input and output signal diagram is
shown as follow:
Line differential protection
1 1
BI_Diff_Tele_Trans1 Relay_StartUp
2 2
BI_Diff_Tele_Trans2 Relay_Trip
3 3
BI_Diff_Tele_Trans3 Relay_Trip_A
4 4
BI_Diff_Tele_Trans4 Relay_Trip_B
5 5
BI_Diff_Tele_Trans5 Relay_Trip_C
6 6
BI_Diff_Tele_Trans6 Trip_3ph
7 7
BI_Diff_Tele_Trans7 Relay_Block_AR
8 8
BI_Diff_Tele_Trans8 Curr_Diff_Trip
9 9
BI_Diff_DTT Diff_DTT
10 10
BI_Diff_Chan_A_Test Diff_Tele_Trans1
11 11
BI_Diff_Chan_B_Test Diff_Tele_Trans2
12 12
BLK_Diff Diff_Tele_Trans3
13
Diff_Tele_Trans4
14
Diff_Tele_Trans5
15
Diff_Tele_Trans6
16
Diff_Tele_Trans7
17
Diff_Tele_Trans8
18
Channel_A_Alarm
19
Channel_B_Alarm
20
ChannelACommuInterruption
21
ChannelBCommuInterruption
22
SOTF_Trip
23
Diffcurvalid
Figure 13 Line differential protection function input and output signal diagram
The input signals are on the left side and the output signals are on the
right.
Input:
DI_OpticalFiberChanl BI_Tele_Trans1 Remote transmission command1 input
BI_Tele_Trans2 Remote transmission command2 input
34
BI_DTT Remote trip signal input
BI_Chan_A_Test Channel A maintenance
BI_Chan_B_Test Channel B maintenance
Input:
Blocking_BI
BLK_Diff 1: differential binary input blocking
Output:
Relay_StartUp IED startup
Relay_Trip IED trip
Relay_Trip_A TripA
Relay_Trip_B TripB
Tripcom
Relay_Trip_C TripC
Trip_3ph TripABC
Trip three phases and block

Relay_Block_AR
auto-reclosing
SOTF_Trip Manual close trip
Output:
Split phase differential trip, restricted

Diff_Trip Curr_Diff_Trip
earth fault trip
Diffcur_valid Valid sign of differential protection
Output:
BO_DTT Trip of direct transmit trip

DO_OpticalFiberChanl
BO_Tele_Trans1 Remote transmission 1 output
35
Interruption of channel A (detect the

Channel_A_Alarm
communication of channel A)
Interruption of channel B (detect the

Channel_B_Alarm
communication of channel B)
Output:
Channel A alarm (associate single

ChannelAlarm channel and double channels)
Channel B alarm (associate single

ChannelBCommuinterruption
channel and double channels)
3 Detailed description
3.1 Protection principle
M N
CB TA TA CB
IM A、B、C IM A、B、C
CSC-103 Channel CSC-103
IN A、B、C IN A、B、C
Figure 14 Schematic diagram of differential protection

As shown above, M and N are two ends where CSC-103 digital EHV (extra
high voltage) line protection devices are installed. Protection and
communication terminal equipment are connected through cables. The
optical transceiver on the protection side is installed on the backplate of
the protection device. For multiplex channels, CSC-186 optical interface
boxes shall be installed on the communication terminal equipment side to
support the protection function.
3.1.1 Phase-segregated differential protection function
The phase-segregated differential protection has dual-slope percentage
differential protection characteristics, as shown as follow:
36
IDiff
Trip zone
K2
I_2Diff
K1
I_1Diff
I_1Res I_2Res IRes
Figure 15 Phase-segregated differential protection characteristics

Where:
𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 : Differential current, calculated by each phase
𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 : Restricted current, calculated by of each phase
K1=0.6
K2=0.8
I_1Diff=1I_Set
I_2Diff=3I_Set
I_1Res=5/3I_Set
I_2Res=5I_Set
WhenI_Set=“SplitPhDiffHighSet”, it is the high setting of differential current
WhenI_Set=“SplitPhDiffLowSet”, it is the low setting of differential current
The protection zone of low setting of phase-segregated differential current
shall act after a delay of 40ms.
The differential current 𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 and the braking current 𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 are calculated
from the current Acquired from both ends (M end and N end) according to
the following formula:
𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 = ��𝑰𝑰̇𝑴 − 𝑰𝑰̇𝑴𝑪𝑪 � + �𝑰𝑰̇𝑰𝑰 − 𝑰𝑰̇𝑰𝑰𝑪𝑪 ��
𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 = ��𝑰𝑰̇𝑴 − 𝑰𝑰̇𝑴𝑪𝑪 � − �𝑰𝑰̇𝑰𝑰 − 𝑰𝑰̇𝑰𝑰𝑪𝑪 ��
Where:
𝑰𝑰̇𝑴𝑪𝑪 and 𝑰𝑰̇𝑰𝑰𝑪𝑪 : Capacitive current of each phase of the protected line
calculated from the voltage measured from each end.
The following is the protective operation characteristic equation:
𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑰𝑰𝒔𝒔𝒆𝒆𝒂𝒂
𝑰𝑰
� 𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑲𝑲𝑲𝑲 × 𝑰𝑰 𝑹𝑹𝒆𝒆𝒔𝒔 , 𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝟎𝟎 < 𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 < 𝟑𝟑𝑰𝑰𝒔𝒔𝒆𝒆𝒂𝒂
𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑲𝑲𝑲𝑲 × 𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 − 𝑰𝑰𝒔𝒔𝒆𝒆𝒂𝒂 , 𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰 𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 ≥ 𝟑𝟑𝑰𝑰𝒔𝒔𝒆𝒆𝒂𝒂
37
PhADiffCurr>I_set
&
PhADiffCurr＞0.6×PhARestrCurr & Phase A meets split phase
differential high setting
0＜PhADiffCurr＜3×I_set ≥1
PhADiffCurr≥3×I_set &
PhADiffCurr＞0.8×PhARestrCurr- I_set
I_set:“SplitPhDiffHighSet”
Figure 16 Logic diagram of high setting differential satisfaction of phase A
PhADiffCurr>3×I_set
& &
PhADiffCurr＞0.6×PhARestrCurr Phase A meets split phase
differential low setting
0＜PhADiffCurr＜3×I_set ≥1
PhADiffCurr≥3×I_set &
I_set:“SplitPhDiffLowSet”
Figure 17 Logic diagram of low setting differential satisfaction of phase A
3.1.2 Abrupt change current differential protection

As for Abrupt change current differential protection, only fault current
(abrupt change of current) is calculated. Not affected by the load current,
this protection function has high sensitivity, especially for high-resistance
fault of heavy-load line. The Abrupt change current will disappear soon,
but the abrupt change current differential protection also needs the
detection of global fault.
The Abrupt change current differential protection has dual-percentage
differential protection characteristics, shown as follow:
ΔIDiff
Trip zone
K2
ΔI_2Diff
K1
ΔI_1Diff
ΔI_1Res ΔI_2Res ΔIRes
Figure 18 Abrupt change current differential protection characteristics

Where:
∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 : Abrupt change differential current
38
∆𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 : Abrupt change braking current

K1=0.6
K2=0.8
ΔI_1Diff=1I_Set
ΔI_2Diff=3I_Set
ΔI_1Res=5/3I_Set
ΔI_2Res=5I_Set
I_Set:“SplitPhDiffHighSet”
∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 and ∆𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 are obtained by calculating the current change of each
phase on both ends of the line in accordance with the following formula:
∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 = �∆𝑰𝑰̇𝑴 + ∆𝑰𝑰̇𝑰𝑰 �
∆𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 = �∆𝑰𝑰̇𝑴 − ∆𝑰𝑰̇𝑰𝑰 �
∆𝐈𝐈̇𝐌𝐌 : Current change on M end of the protected line
∆𝐈𝐈̇𝐍𝐍 : Current change on N end of the protected line
∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑰𝑰_𝒔𝒔𝒔𝒔𝒔𝒔
� ∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑲𝑲𝑲𝑲 × ∆𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 , 𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰 𝟎𝟎 < ∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 < 𝟑𝟑𝑰𝑰_𝒔𝒔𝒔𝒔𝒔𝒔
∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑲𝑲𝑲𝑲 × ∆𝑰𝑰𝑹𝑹𝒆𝒆𝒔𝒔 − 𝑰𝑰𝒔𝒔𝒆𝒆𝒂𝒂 , 𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰 ∆𝑰𝑰𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 ≥ 𝟑𝟑𝑰𝑰_𝒔𝒔𝒔𝒔𝒔𝒔
PhAAbruptChgDiffCurr＞I_set
& &
PhAAbruptChgDiffCurr＞0.6×PhAAbruptRestrCurr Phase A meets abrupt
changing differential
0＜PhAAbruptChgDiffCurr＜3×I_set ≥1
PhAAbruptChgDiffCurr≥3×I_set &
PhAAbruptChgDiffCurr＞0.8×PhAAbruptRestrCurr- I_set
I_set:“SplitPhDiffHighSet”
Figure 19 Logic diagram of abrupt changing differential satisfaction of phase A
3.1.3 Zero sequence current differential protection

As the complement to the phase-segregated differential protection, the
zero sequence current differential protection is more sensitive to the failure
of grounding with transition resistor. This protection has an inertial delay
when isolating the fault. The single percentage differential protection
characteristics are shown in the following picture.
39
I0Diff
Trip zone
I_0Diff
I0Res
Figure 20 Zero sequence current differential protection characteristics

Where:
𝑰𝑰𝟎𝟎𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 : zero sequence differential current
𝑰𝑰𝟎𝟎𝑹𝑹𝒆𝒆𝒔𝒔 : Zero sequence braking current
K=0.75
𝑰𝑰𝟎𝟎𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 :“REFSet”
The zero sequence differential current 𝑰𝑰𝟎𝟎𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 and the zero sequence
braking current 𝑰𝑰𝟎𝟎𝑹𝑹𝒆𝒆𝒔𝒔 are calculated from the current measured on both
sides of the line according to the following formula:
𝑰𝑰𝟎𝟎𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫
= ��𝑰𝑰̇𝑴𝑻𝑻 − 𝑰𝑰̇𝑴𝑻𝑻𝑪𝑪 � + �𝑰𝑰̇𝑴𝑩 − 𝑰𝑰̇𝑴𝑩𝑪𝑪 � + �𝑰𝑰̇𝑴𝑪𝑪 − 𝑰𝑰̇𝑴𝑪𝑪𝑪𝑪 ��
+ [�𝑰𝑰̇𝑰𝑰𝑻𝑻 − 𝑰𝑰̇𝑰𝑰𝑻𝑻𝑪𝑪 � + �𝑰𝑰̇𝑰𝑰𝑩 − 𝑰𝑰̇𝑰𝑰𝑩𝑪𝑪 � + �𝑰𝑰̇𝑰𝑰𝑪𝑪 − 𝑰𝑰̇𝑰𝑰𝑪𝑪𝑪𝑪 �]�
𝑰𝑰𝟎𝟎𝑹𝑹𝒆𝒆𝒔𝒔
= ��𝑰𝑰̇𝑴𝑻𝑻 − 𝑰𝑰̇𝑴𝑻𝑻𝑪𝑪 � + �𝑰𝑰̇𝑴𝑩 − 𝑰𝑰̇𝑴𝑩𝑪𝑪 � + �𝑰𝑰̇𝑴𝑪𝑪 − 𝑰𝑰̇𝑴𝑪𝑪𝑪𝑪 ��
− [�𝑰𝑰̇𝑰𝑰𝑻𝑻 − 𝑰𝑰̇𝑰𝑰𝑻𝑻𝑪𝑪 � + �𝑰𝑰̇𝑰𝑰𝑩 − 𝑰𝑰̇𝑰𝑰𝑩𝑪𝑪 � + �𝑰𝑰̇𝑰𝑰𝑪𝑪 − 𝑰𝑰̇𝑰𝑰𝑪𝑪𝑪𝑪 �]�
Where:
𝑰𝑰̇𝑴𝑿𝑿 and 𝑰𝑰̇𝑰𝑰𝑿𝑿 : Actual current of each phase flowing through the M side and
N side of the line
𝑰𝑰̇𝑴𝑿𝑿𝑪𝑪 and 𝑰𝑰̇𝑰𝑰𝑿𝑿𝑪𝑪 : Capacitive current of each phase on the M side and N side
of the Line
x: Phase A, B or C.
𝑰𝑰𝟎𝟎𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑰𝑰_𝒔𝒔𝒔𝒔𝒔𝒔
�
𝑰𝑰𝟎𝟎𝑫𝑫𝒊𝒊𝑫𝑫𝑫𝑫 > 𝑲𝑲 × 𝑰𝑰𝟎𝟎𝑹𝑹𝒆𝒆𝒔𝒔
REFDiffCurr＞“REFSet” &
REF conditions meet
REFDiffCurr＞0.75×REFRestrCurr
Figure 21 Logic diagram of zero sequence differential satisfaction
40
3.1.4 Other principles

3.1.4.1 Capacitive current compensation
During normal operation (before startup), �𝑰𝑰̇𝑴 + 𝑰𝑰̇𝑰𝑰 � = 𝑰𝑰𝑪𝑪 is calculated as
measured capacitive current.
After the protection device is started, 𝑰𝑰𝑪𝑪 is taken as the floating threshold.
The capacitive current is precisely compensated with the voltage
measured on both sides of the line after the fault. This is the
semi-compensation scheme, meaning that each side of the line is
compensated with half of capacitive current.
Figure 22 Line positive sequence π type equivalent circuit

The positive-sequence, negative sequence and zero sequence π-type
equivalent circuits of line are shown above. The calculation formula of
capacitive current is listed as follow.
With Phase A as the reference, the capacitive current of each sequence on
M end is calculated as follows:
𝑼𝑼̇𝑴𝟏𝟏
𝑰𝑰̇𝑴𝑪𝑪𝟏𝟏 =
−𝒋𝒋𝒋𝒋𝑿𝑿𝑪𝑪𝟏𝟏
𝑼𝑼̇𝑴𝟐𝟐
𝑰𝑰̇𝑴𝑪𝑪𝟐𝟐 =
−𝒋𝒋𝒋𝒋𝑿𝑿𝑪𝑪𝟐𝟐
41
𝑼𝑼̇𝑴𝟎𝟎
𝑰𝑰̇𝑴𝑪𝑪𝟎𝟎 =
−𝒋𝒋𝒋𝒋𝑿𝑿𝑪𝑪𝟎𝟎
If 𝑿𝑿𝑪𝑪𝟏𝟏 = 𝑿𝑿𝑪𝑪𝟐𝟐 , each phase capacitance current of M end is:
𝑼𝑼̇𝑴𝟏𝟏 + 𝑼𝑼̇𝑴𝟐𝟐 + 𝑼𝑼̇𝑴𝟎𝟎 − 𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝟎𝟎
𝑰𝑰̇𝑴𝑻𝑻𝑪𝑪 = 𝑰𝑰̇𝑴𝑪𝑪𝟏𝟏 + 𝑰𝑰̇𝑴𝑪𝑪𝟐𝟐 + 𝑰𝑰̇𝑴𝑪𝑪𝟎𝟎 = +
−𝒋𝒋𝒋𝒋𝑿𝑿𝑪𝑪𝟏𝟏 −𝒋𝒋𝒋𝒋𝑿𝑿𝑪𝑪𝟎𝟎
𝑼𝑼̇𝑴𝑻𝑻 −𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝟎𝟎
= +
−𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟏𝟏 −𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟎𝟎
𝑰𝑰̇𝑴𝑩𝑪𝑪 = 𝜶𝜶𝟐𝟐 𝑰𝑰̇𝑴𝑪𝑪𝟏𝟏 + 𝜶𝜶𝑰𝑰̇𝑴𝑪𝑪𝟐𝟐 + 𝑰𝑰̇𝑴𝑪𝑪𝟎𝟎

𝜶𝜶𝟐𝟐̇ 𝑼𝑼𝑴𝟏𝟏 +𝜶𝜶𝑼𝑼̇𝑴𝟐𝟐 +𝑼𝑼̇𝑴𝟎𝟎 −𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝑩 −𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝟎𝟎
= + = +
−𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟏𝟏 −𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟎𝟎 −𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟏𝟏 −𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟎𝟎
𝑰𝑰̇𝑴𝑪𝑪𝑪𝑪 = 𝜶𝜶𝑰𝑰̇𝑴𝑪𝑪𝟏𝟏 + 𝜶𝜶𝟐𝟐 𝑰𝑰̇𝑴𝑪𝑪𝟐𝟐 + 𝑰𝑰̇𝑴𝑪𝑪𝟎𝟎

𝜶𝜶𝑼𝑼̇𝑴𝟏𝟏 +𝜶𝜶𝟐𝟐 𝑼𝑼̇𝑴𝟐𝟐 +𝑼𝑼̇𝑴𝟎𝟎 −𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝑪𝑪 −𝑼𝑼̇𝑴𝟎𝟎 𝑼𝑼̇𝑴𝟎𝟎
= + = +
−𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟏𝟏 −𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟎𝟎 −𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟏𝟏 −𝒋𝒋𝟐𝟐𝑿𝑿𝑪𝑪𝟎𝟎
Similarly, the N end of each phase capacitance current:

𝑼𝑼̇𝑰𝑰𝑻𝑻 − 𝑼𝑼̇𝑰𝑰𝟎𝟎 𝑼𝑼̇𝑰𝑰𝟎𝟎
𝑰𝑰̇𝑰𝑰𝑻𝑻𝑪𝑪 = +
𝑼𝑼̇𝑰𝑰𝑩 − 𝑼𝑼̇𝑰𝑰𝟎𝟎 𝑼𝑼̇𝑰𝑰𝟎𝟎
𝑰𝑰̇𝑰𝑰𝑩𝑪𝑪 = +
𝑼𝑼̇𝑰𝑰𝑪𝑪 − 𝑼𝑼̇𝑰𝑰𝟎𝟎 𝑼𝑼̇𝑰𝑰𝟎𝟎
𝑰𝑰̇𝑰𝑰𝑪𝑪𝑪𝑪 = +
3.1.4.2 Differential protection CT failure check
If "CTFailTime" value of self-produced 𝟑𝟑𝟑𝟑𝟎𝟎 value in failure side is greater
than the current of zero sequence auxiliary startup component while the
failure phase-to-phase current is less than 0.06In (In is the secondary
rated current); or the calculated differential current of the normal side is
greater than 0.15In in12s continuously while the failure phase-to-phase
current is less than 0.06In, sent "LocalCTFailure" alarm. Send
"OppEndCTFail" alarm if the opposite CT failure.
Local end:Diff BI Blk
(BLK_Diff) &
Local end:DiffProtOn
Local end:“DiffOn”
Opposite end: DiffBI Blk
(BLK_Diff) & &
&
Opposite end:DiffProtOn Tset &
Opposite end:“DiffOn” Local end:CTFailPhA
&
“CTFailDetectOn”
Blocking_BI.BLK_CT_Fail
&
3I0 > Zero sequence current startup component Local end:CTFailPhB
Ia < 0.06In
Ib < 0.06In
&
Local end:CTFailPhC
Ic < 0.06In
Tset：“CTFailTime”
Figure 25 Differential local end CT failure logic(1)
42

(BLK_Diff) &
(BLK_Diff) & &
Opposite end:DiffProtOn
Opposite end:“DiffOn”
&
Blocking_BI.BLK_CT_Fail &
12S &
Idiff_A > 0.15In Local end:CTFailPhA
Ia < 0.06In
&
12S &
Idiff_B > 0.15In Local end:CTFailPhB
Ib < 0.06In
&
12S &
Idiff_C > 0.15In Local end:CTFailPhC
Ic < 0.06In
Figure 26 Differential local end CT failure logic(2)

In 3/2 connection mode and double CT Mode . the differential protection
can distinguish CT failure separately. The logic is shown in the following
figure:
43

(BLK_Diff) &
(BLK_Diff) & &
&
&
Blocking_BI.BLK_CT_Fail Tset
&
3I0 > Zero sequence current startup component ≥1
Local end:CTFailPhA
3I01 > Zero sequence current startup component
Ia1 < 0.06In &

≥1
Ib1 < 0.06In Local end:CTFailPhB
&
Ic1 < 0.06In

≥1
&
Tset & Local end:CTFailPhC
3I02 > Zero sequence current startup component
Ia2 < 0.06In

&
Ib2 < 0.06In
&
Ic2 < 0.06In
Ia1,Ib1,Ic1,3I01:the first CT current
Ia2,Ib2,Ic2,3I02:the second CT current
Figure 27 Differential local end CT failure logic using two groups CT(1)
44

(BLK_Diff) &
(BLK_Diff) & &
&
&
Blocking_BI.BLK_CT_Fail 12S
&
Idiff_A > 0.15In ≥1
Local end:CTFailPhA
Ia1 < 0.06In
&
Ia2 < 0.06In

&
12S &
≥1
Idiff_B > 0.15In
Local end:CTFailPhB
Ib1 < 0.06In
&
Ib2 < 0.06In

&
12S
&
≥1
Idiff_C > 0.15In
Local end:CTFailPhC
Ic1 < 0.06In
&
Ic2 < 0.06In
Ia1,Ib1,Ic1,3I01:the first CT current

Ia2,Ib2,Ic2,3I02:the second CT current
Figure 28 Differential local end CT failure logic using two groups CT(2)
3.1.4.3 Alarm check of long-term differential current
When the calculated differential current on both sides is greater than max
current for 12s (0.2 times the rated current and 0.15 times the braking
current), a “LongTermDiffCurr” alarm is issued.
3.1.4.4 CT saturation criteria
Detect CT saturation by adopting fuzzy identification.
Detect the CT by adopting the current wave and symmetry, if not saturated,
Ct is the smooth standard sine wave, if saturated, the current wave will be
distorted and unsmooth with dissymmetry positive and negative half-cycle.
Under this condition, new differential current and braking current
characteristics shown as follow will be merged into protection
characteristics to ensure the protection safety.
45
IDiff
Trip zone
I_LDiffCT
IRes
Figure 29 Phase-segregated differential protection characteristics under CT saturation

condition
Where:
I_LDiffCT=Max ("SplitPhDiffHighSet", "SplitPhDiffLowSet", 0.5 x
secondary current rating)
Secondary current rating: secondary rated current of CT
K=0.9
3.1.4.5 Remote transmission command
The protection device has eight binary input terminals of remote
transmission command: <Remote transmission command 1>, <Remote
transmission command 2>, <Remote transmission command 3>, <Remote
transmission command 6>, <Remote transmission command 7> and
<Remote transmission command 8>. The device sends the command to
the opposite side with the logic switch in each data frame through digital
channel. When the IED on the opposite side receives the remote
command signal, remote command 1 is driven to be output. By using this
sending signal, users are able to construct the logic. Take Remote
transmission command 1 as an example.
Remote command 1 input &

(BI_Tele_Trans1) Send: teletransfer 1
signal
Normal channel
&
Remote transmission 1 output
(BO_Tele_Trans1)
Receive: teletransfer 1 signal
Figure 30 Logic diagram of Remote transmission command
46
3.1.4.6 Direct transmit trip

In order to make sure that the opposite protection trips timely when fault
occurs between the circuit breaker and the current inductor or there is a
breaker failure, one <remote trip>input are set to send the dead zone
protection or circuit breaker failure trip signal, so as to trip the opposite
circuit breaker. When the input time of <remote trip> is greater than 20S,
the alarm "DTT BIErr" is issued. The remote trip operates according to
"DTTTime".
Local end: IEDStartup
Normal channel
&
Receive: DTT trip signal
“DTTCtrlledByStartup”
“DTTCtrlledByZ2” & ≥1 T_DTT

Remote trip (BO_DTT)
In distance zone 2
&
“DTTCtrlledByZ3”
In distance zone 3
≥1 &
&
Remote trip signal input Send: DTT trip signal

(BI_DTT)
T_DTT：“DTTTime”
Figure 31 Remote trip logic diagram

3.1.4.7 Time synchronization
For protection on both ends of the line, the differential current and braking
current are calculated from local-end current and Offend current and
whether it is an internal or external fault is detected from the calculation
result. For this purpose, the protection devices on both ends need to
transmit the current data in two directions through communication
channels. The data transmitted are used for calculating the line-end
protection current After time synchronization of differential protection IED
in both sides, differential protection can receive the correct data
transferred by the opposite side.
1) Channel mode
a) Special fiber channel with transmission rate of 2Mbps;
b) The 2Mbps (E1) interface of the PDH or SDH system is
multiplexed at the speed of 2Mbps;
c) The PCM co-directional interface is multiplexed at the rate of
64kbps;
d) PDH or SDH can be accessed through C37.94 port.
2) Synchronization mode of communication clock
a) Setting of communication clock mode and communication rate;
 The communication rate of the device can be set to "2Mbps"
47
or "64kbps" by setting the differential control bit (G.703

protocol).
 C37.94 fixed adopts a communication rate of 12*64 kbps.
 The clock mode of the device can be set by the differential
control bit: "internal clock" or "external clock".
 CSC-103 has double channels. The clock mode and
communication rate of channel A and B can be set separately.
b) Description of communication clock.
The description of communication clock, see Table 15 . For clock
description of pilot differential protection, see Figure 32 .
Table 15 Description of communication clock
Clock Mode
for PCM’s C37.94
Communication Communication
Description Protection Clock interface
mode Rate
on Both Mode module
Sides
The setting of devices on
Special optical “Internal –
2Mbps both ends shall be set to / /
fiber channel Internal”
"Internal Clock".
For 2Mbps (E1) interface,
the setting of the devices “Internal –
2Mbps / /
on both ends shall be set Internal”
to "Internal Clock".
Multiplex For 64kbps PCM
PDH/SDH digital codirectional interface,
communication the settings of the
system devices on both sides “External– “Internal–
64kbps /
shall be set to External External” External”
Clock, which is taken
from system
synchronization clock.
Multiplex SDH Fixed value N=12,
digital the setting of device
“External– “Internal–
communication N*64kbps at the both ends /
External” External”
system C37.94 should be set to "
interface External Clock ".
Note:
(1) For multiplexing the 64kbps interface, the clocks of the
base-group equipment on both sides must be set as required by
the list, otherwise regular slip codes will be generated. The whole
system can have only one internal clock;
(2) The setting of C37.94 interface module must ensure that there is
only one internal clock in the whole system.
48
If it is connected directly or through 2Mbps (E1) interface, the devices on both sides are
set to Internal Clock. The data transmitter clock is the internal clock of the device and the
receiver clock is extracted from the received data code flow.
Internal clock
Internal clock
Forwarding clock Forwarding

clock
～～
Fiber Collecting clock Fiber longitudinal

longitudinal Collecting clock Differential
Differential protection
protection ～
～
If it is connected through 64kbpsPCM same direction interface, the devices on both

sides are set as "External Clock". Both data transmitter and receiver clocks are
extracted from the received data code flow.
Internal clock Internal
clock
PCM device PCM device
Forwarding Forwarding Forwarding Forwarding

clock 64Kb/s 64Kb/s clock
～～～～
Fiber Fiber
longitudinal longitudinal
Differential Collecting Differential
Collecting (Master (Slave side)
protection clock protection
clock Collecting side) Collecting
64Kb/s 64Kb/s
～～～～
Figure 32 Description of internal and external clock for longitudinal differential

protection
3.1.4.8 Synchronous sampling
The current differential protection can also achieve the purpose of
protecting the sampling synchronization by setting the control bit to "1"
(MasterMode) or "0" (SlaveMode).
After the sampling synchronization is realized, the differential protection
devices on both sides can use the sampling data collected from the same
moment to calculate the differential current and braking current.
For current differential protection devices on both sides, one protection
device shall be slave if the other is master. This setting is irrelevant to
channel mode. Principle of sampling synchronization is shown in the
following figure.
49
M Synchronized end Reference end N

RELAY RELAY
tm1
Data sent by end m
tn1
tp1
tm2 tn2
tn*
td
tm3
tn3
tn3*
tp2
tm4
tn4
tm* Data sent by end n
tm5
tn5
Figure 33 Sampling synchronization principle

1) Each device can be preset to Host mode (reference end) or Slave
mode (synchronization end);
2) For sampling synchronization, sending and receiving routes shall be
same, in other words, 𝐭𝐭 𝐩𝐩𝐩𝐩 and 𝐭𝐭 𝐩𝐩𝐩𝐩 shown above shall be equal.
Given that 𝐭𝐭 𝐝𝐝 , 𝐭𝐭 𝐦𝐦∗ and are known, the differential protection device
on the slave side can calculate 𝐭𝐭 𝐩𝐩𝐩𝐩 (𝐭𝐭 𝐩𝐩𝐩𝐩 ). Adjustment can be made
by the differential protection device on the slave side for the purpose
of sampling synchronization;
(𝒕𝒕𝒎𝒎∗ − 𝒕𝒕𝒎𝒎𝟏𝟏 ) − 𝒕𝒕𝑰𝑰
𝒕𝒕𝒂𝒂𝟏𝟏 �𝒕𝒕𝒂𝒂𝟐𝟐 � =
𝟐𝟐
3) To ensure the sampling synchronization of the protection devices on
both sides, the slave will send a synchronous request command
(including sampling mark). After receiving the command from the
slave, the master returns a data frame including the sampling mark
of the master and the time (td) corresponding 𝒕𝒕𝑰𝑰 to this sampling.
𝒕𝒕𝒎𝒎𝟑𝟑 Given that tm3 is known, after the slave receives the data report
from the master, the communication transmission delay and the
difference between sampling time on both sides are calculated∆𝒕𝒕.
∆𝒕𝒕 = 𝒕𝒕𝒎𝒎∗ − 𝒕𝒕𝒎𝒎𝟑𝟑 − 𝒕𝒕𝒂𝒂𝟐𝟐
The slave determines the adjustment times from the deviation of sampling
time. The protection device slightly adjusts the sampling time several times
until∆𝒕𝒕 = 𝟎𝟎. Then, the sampling of the devices on both sides will be
completely synchronized.
The advantage of this synchronization method is that: If the synchronous
sampling of the devices of two ends is realized, the correctness of
differential protection algorithm can be ensured by only aligning the
sampling marks of the devices on both ends instead of calculating the
50
additional compensation to the communication delay. This is not only

simple, but more important; the calculation process of differential
protection algorithm has no relationship with communication transmission
delay. This means that the differential protection device that realizes the
sampling synchronization by this method is adaptive to the communication
system whose communication route changes. This protection device is
adaptable to the transmission delay of up to 18ms due to the change of
communication route. The synchronization error is not more than 1°.
3.1.4.9 Redundant communication channel
The differential protection device can receive the data from the redundant
communication channel at the same time. If one channel is interrupted, it
can change to the other channel without delay.
3.1.4.10 Protection functions of post manual closing and post auto-reclosing
During automatic reclosing or manual closing, if the protection device is
closed on the line with permanent fault, quick trip is allowed.
3.1.4.11 Current differential protection channel error monitor and alarm
function
1) In normal running time (before startup):
a) Channel state and frame-lost (error code) number of channel A
and B are displayed in real-time, and frame-lost (error code)
number in each channel in the last six days should be stored in
different periods and the total number of frame-lost (error code) in
each channel should be stored, which can be viewed through
sub-menu "ChanInfo";
b) When the error is not serious, in 2s report (600 frames at 50 Hz
and 720 frames at 60 Hz), the number of frame lost by error code
(hereinafter referred to as frame-lost number) is greater than 20
frames of report, and the drive channel will alarm relay and
unblock the protection;
c) As the error is serious, drive channel will alarm relay and send
alarm report: "ChanABCommErr", blocking protection (as for
double channel, it only blocks relevant channel); when the error
code disappears, report "ChanABCommRst", and the protection is
automatically enabled.
2) After the start of protection, in addition to all the features before the
start, the following functions are also be added: When the protection
starts, the sampling synchronization state is recorded in the form of a
report;
3) Be equipped with the function of identifying work state automatically:
a) When a loop appears on the channel, it can be automatically
identified by the protection device, the differential protection is
blocked (when there is dual-channel, only the corresponding
channel is blocked), and the alarm signal and alarm report are
given;
b) When the "MasterMode" and "SlaveMode" of devices of two ends
are not correct, the protection device can automatically identify
and lock the differential protection;
51
c) If the identification code in the received message is not equal to

the "OppEndIDCode" but equal to the "LocalIDCode", device will
alarm and report "ChanA(B)LoopErr"; If the identification code in
the received message is not equal to the "OppEndIDCode" and
the "LocalIDCode", the device will alarm and report
"ChanA(B)AddrErr ×", where × stands for protection received side
address; as the side of the received address error, but the other
side is correct, the normal side will alarm and report
"OppEndCommErr";
d) As using double channel, If the side channel A and the
contralateral channel B is in communication, and the side channel
B and the opposite side channel A is in communication, the
protection device can automatically identify and lock the
differential protection, and give the alarm signal and alarm
message "ChanABErrorConnection".
3.1.4.12 Current differential protection channel check BI description
1) Differential protection equipment double channel
a) As channel A(or channel B) checks and meets abnormality, it is
suggested to enable corresponding "ChanA/BMaint"BI, at this
point the channel exits to run and is displayed as an exit, but the
channel is still monitored.
b) As channel A,B both check and meet abnormality, it is necessary
to turn "DifferentialProtectionOn" to logic switch "0". If
"ChanAMaint" and "ChanBMaint" BI both enable and turn to
"DiffOn" logic switch "1", alarm signal and report will be send off.
2) Differential protection equipment single channel:
As in differential protection equipment single channel, and channel B,
A are fault, the differential lock protection, and give corresponding
channel alarm signal.
3.1.4.13 Ways to realize single and double channel
Send the corresponding channel alarm (only the fault channels are
blocked and the differential protection is unblocked) when the logic switch
of the double-channel is set to "1" and either of the channel A/B is fault.
Differential protection is blocked when the logic switch is set to "0" and
both of the channel A/B is fault.
In general, as suing the use of dual channel, the position is "1"; in the use
of a single channel, the position is "0".
The device uses the back channel A to repair BI terminal and the channel
B to repair BI terminal switch to realize the operation mode of single
channel or double channel.
3.1.5 Logic diagram
The following figures are the logic of spit-phase differential protection and
restricted earth fault protection respectively, taking phase A differential
protection as an example.
In the diagram, the spit-phase differential low value delay 40ms trip, the
restricted earth fault protection according to the "REFTime.
As VT is circuit failure, differential protection will not blocked.
52
As CT is circuit failure, restricted earth fault protection will be blocked. As

for split-phase differential protection, if logic switch "CTFailBlkDiff" logic
switch is enabled and logic switch "CTFailBlk3Ph" is also enabled, any CT
failure will lead to blocking each phase differential protection; if
"CTFailBlk3Ph" is disabled, any CT failure only blocks the corresponding
phase differential protection; if logic switch "CTFailBlkDiff" is disabled,
phase differential protection of CT failure phase will use
"CTFailSplitPhDiffSet" and the phase without CT failure will still use the
settings of "SplitPhDiffHighSet" and"SplitPhDiffLowSet". Any side meets
CT failure, it will block both side separation differential protection.
Take phase A as an example.
(BLK_Diff) &
(BLK_Diff) &
&
≥1
Opposite end:Trip position
Opposite end:IEDStartup
Local end:IEDStartup
Normal channel
PhA meets split phase
differential high setting
≥1
PhA meets abrupt & Split phase differential
&
changing differential trip (phase A)
“AbruptChgDiffOn”
PhA meets split phase 40ms

differential low setting
&
&
CTFailPhA
“CTFailDetectOn” &
Split phase differential
trip (CTFail)
CTFailPhB or CTFailPhC &
“CTFailBlkDiff” &
“CTFailBlk3Ph”
&
PhADiffCurr＞I_set
&
PhADiffCurr＞0.6×PhARestrCurr
0＜PhADiffCurr＜3×I_set
&
I_set:“CTFailSplitPhDiffSet”
Figure 34 Logic diagram of differential protection
53
&
CTFailPhA
REF meets condition
&
Local end: DiffBI Blk

&
T0_Diff
Local end:“DiffOn” REF Trip
Opposite end: DiffProtOn

&
Opposite end: DiffBI Blk &
Opposite end: Trip position ≥1
Opposite end: IEDStartup
Normal channel
T0_Diff：“REFTime”
Figure 35 Logic diagram of restricted earth fault trip

Differential switch-on-to-fault trip logic diagram is shown as follow:
Split phase differential trip

&
DiffSOTFTrip (Split trip)
SOTF: Switch-onto-fault
permission is allowed
&
REF Trip (SOTF)
REF Trip
Figure 36 Differential switch-on-to-fault trip logic diagram

The below figure is distance protection trip logic diagram, and part in the
dotted frame is only the logic of configuration auto-reclosing trip protection.
As CT is disconnection, differential protection will be permanently trip. As
manual switch-on-to, separation phase differential protection and
restricted earth fault protection will permanently trip.
Take phase A as an example for single phase fault and take phase AB as
an example for interphase fault.
54
PhSel: Phase A
“1PhARModeOn” ≥1
&
“1/3PhARModeOn”
≥1
Split phase differential trip
“REFInitAR” &
REF Trip
&
Input: Enforced3PhTrip
(AR_Lockout)
≥1 &
Trip A
“3PhTripMode”
Output:Enforced3PhTrip
(AR_Lockout)
CTFail
&
DiffDevelopmentTrip
≥1
PhSel: Phase AB &

& ≥1
“PPFaultInitAR” ≥1
Trip ABC
&
&
≥1
“3PhFaultInitAR”
&
≥1
PhSel: Phase ABC
Trip3Ph/BlkAR
&
&
REF Trip
“REFInitAR”
DiffSOTFTrip
REFTrip (SOTF)
DTT Trip
Figure 37 Tripping logic of differential protection
ChanALostFrameErrCode Channel A alarm.

&
≥1
“DualChan”=1 &
≥1
ChanBLostFrameErrCode Channel B alarm.
ChanALostFrameErrCode
&
ChanBLostFrameErrCode
“DualChan”=0
≥1
Normal Channel
Figure 38 Logic diagram of channel interruption and alarm
55
3.2 Configurable nodes by the user

Table 16 Configuration node
Type Configurable nodes in IO Matrix configuration Description
Blocking_DI.BLK_Diff Differential binary input blocking

Remote transmission command1
DI_OpticalFiberChanl.BI_Tele_Trans1
input
input
input
input
Input input
input
input
input
DI_OpticalFiberChanl.BI_DTT Remote trip signal input
DI_OpticalFiberChanl.BI_Chan_A_Test Channel A maintenance
DI_OpticalFiberChanl.BI_Chan_B_Test Channel B maintenance
Tripcom.Relay_StartUp IED startup
Tripcom.Relay_Trip IED trip
Tripcom.Relay_Trip_A TripA
Tripcom.Relay_Trip_B TripB
Tripcom.Relay_Trip_C TripC
Tripcom.Trip_3ph TripABC
Trip three phases and block
Tripcom.Relay_Block_AR
auto-reclosing
Split phase differential trip,
Diff_Trip.Curr_Diff_Trip
restricted earth fault trip
Outp
ut Diff_Trip.Diff_DTT Trip of direct transmit trip
DO_OpticalFiberChanl.BO_Tele_Trans1 Remote transmission 1 output
56
Type Configurable nodes in IO Matrix configuration Description

DO_OpticalFiberChanl.Channel_A_Alarm
communication of channel A)
DO_OpticalFiberChanl.Channel_B_Alarm
communication of channel B)
Diff_Trip.Diffcur_valid Valid sign of differential protection
Channel A alarm (associate single
ChannelAlarm.ChannelACommuInterruption
Channel B alarm (associate single
ChannelAlarm.ChannelBCommuInterruption
Tripcom.SOTF_Trip Manual close trip
3.3 Setting list

3.3.1 Setting list
Table 17 Line differential protection setting
Default
Range
No. Setting name value Step Unit Remark
(In:5A/1A)
(In:5A/1A)
1. SplitPhDiffHighSet 0.05In~20In 20 0.01 A
2. SplitPhDiffLowSet 0.05In~20In 20 0.01 A
3. CTFailSplitPhDiffSet 0.1In~20In 20 0.01 A
4. REFSet 0.05In~20In 20 0.01 A
5. REFTime 0～10 0.1 0.01 s
6. CTRatioCompCoef 0.2～1 1 0.01
7. LinePositiveSeqXcSet 40/ In~9000/In 1800 0.01 Ω
8. LineZeroSeqXcSet 40/ In~9000/In 1800 0.01 Ω
9. ShuntReactorPositiveSeqX 90/ In~9000/In 1800 0.01 Ω
10. ShuntReactorZeroSeqX 90/ In~9000/In 1800 0.01 Ω
Table 18 Setting of optical fiber channel

Default
Range
(In:5A/1A)
(In:5A/1A)
1. LocalIDCode 0～65535 00000 1
2. OppEndIDCode 0～65535 00000 1
3. DTTTime 0～10 0.1 0.01 s
57
Table 19 Line differential protection logic switch
Setting Default
No. Logic switch description Remark
Mode value
1. DiffOn 1/0 1 0: Disable, 1:Enable
2. AbruptChgDiffOn 1/0 1 0: Disable, 1:Enable
3. MasterMode 1/0 1 0: Disable, 1:Enable
4. ChanLoopTestOn 1/0 0 0: Disable, 1:Enable
5. CompByCapacitiveCurr 1/0 0 0: Disable, 1:Enable
6. CTFailBlkDiff 1/0 1 0: Disable, 1:Enable
7. CTFailBlk3Ph 1/0 0 0: Disable, 1:Enable
8. REFInitAR 1/0 1 0: Disable, 1:Enable
9. CTFailDetectOn 1/0 1 CT failure function setting
Table 20 Logic switch of optical fiber channel
Setting Default
No. Logic switch description Remark
Mode value
1. DualChan 1/0 1 0: Disable, 1:Enable
2. SelExtrClockForChanA 1/0 0 0: Disable, 1:Enable

0: Disable, 1:Enable
3. Sel64KRateForChanA 1/0 0 Valid under the G.703
protocol mode
4. SelExtrClockForChanB 1/0 0 0: Disable, 1:Enable
5. Sel64KRateForChanB 1/0 0 Valid under the G.703
protocol mode
6. DTTCtrlledByStartup 1/0 1 0: Disable, 1:Enable
7. DTTCtrlledByZ2 1/0 0 0: Disable, 1:Enable
3.3.2 Setting description

1) "SplitPhDiffHighSet": if capacitance current compensation function is
enabled, it should set as bigger than2 times of capacitance current; if
not, please set as bigger as than 4 times of capacitance current; the
high value of phase segregated differential is determined by the
600A～1000A one time; the device on both sides of the line shall be
converted to the two setting according to the same primary current;
2) "SplitPhDiffLowSet": it should set as bigger than 1.5 times of
capacitance current; if not, please set as bigger as than 2 times of
capacitance current; the high value of phase segregated differential is
determined by the 450A ~ 800A one time; the device on both sides of
the line shall be converted to the two setting according to the same
primary current;
3) “CTFailSplitPhDiffSet”: calculated in accordance with the maximum
58
load current of normal operation. The device on both sides of the line
shall be converted to the two setting according to the same primary
current. Note: when the logic switch "CTFailBlkDiff" is set to "1" and
external fault occurs after CT failure, the differential protection of high
setting and low setting will be blocked. the split phase differential
protection is enabled after the CT failure. That is, when the differential
current of disconnection phase is greater than the "CTFailSptPhDifSt",
the differential protection trip will trip three phases and block
auto-reclosing (block auto-reclosing);
4) If logic switch "CTFailBlkDiff" is "1", the setting will not functioning;
5) "REFSet": it should be calculated in accordance with the maximum
zero sequence imbalance current of three phases of an external fault,
but for internal high resistance earth fault, it should have enough
sensitivity; the setting of restricted earth fault should be greater than a
240A, generally it is set in the range of 300A ~ 600A; These settings of
the devices on both sides of the line are converted secondary values
in accordance with the same primary current value;
6) "REFTime": zero sequence differential delay trip setting;
7) "DTTTime": remote trip time setting trip time;
8) "CTRatioCompCoef" means that if the CTs for some devices have
large primary rated current, the compensation factor shall be set to 1;
for other devices, the compensation factor shall be set to the primary
rated current of CT on the local side, divided by the maximum value of
primary rated current. For example, the transformation ratio of CT on
M end is 1200/1, the transformation ratio of CT on N end is 800/5, and
the transformation ratio of CT on T end is 600/5. The M-end
compensation factor is set to 1, the N-end compensation factor is set
to 800/1200=0.6667, and the T-end compensation factor is set to
600/1200=0.5;
9) "LinePositiveSeqXcSet" and "LineZeroSeqXcSet" shall be set on the
basis of the secondary values of the whole line;
𝑵𝑵𝑻𝑻𝑻𝑻 𝟏𝟏
𝑿𝑿𝑪𝑪𝟏𝟏 = ×
𝑵𝑵𝑻𝑻𝟖𝟖 𝟐𝟐𝟐𝟐𝟐𝟐𝑪𝑪𝟏𝟏
𝑵𝑵𝑻𝑻𝑻𝑻 𝟏𝟏
𝑿𝑿𝑪𝑪𝟎𝟎 = ×
𝑵𝑵𝑻𝑻𝟖𝟖 𝟐𝟐𝝅𝝅𝝅𝝅𝑪𝑪𝟎𝟎
a) When the converted high differential setting is greater than 4 times

capacitive current and the low differential setting is greater than 2 times
of capacitive current, the logic switch "CompByCapacitiveCurr" can be
set to "0", and line positive and zero sequence capacitive reactance is
set as 9000;
b) As high differential setting is less than 4 times capacitive current or low
differential setting is less than 2 times of capacitive current, the logic
switch "CompByCapacitiveCurr" should be set "1", the line capacitive
reactance should be based on practical measurement. The following
table provides for every hundred kilometers the voltage level of
overhead line capacitive reactance and capacitive reactance current of
a reference value.
59
Table 21 Primary value of capacitive reactance and capacitive reactance current overhead
line of per hundred miles
Voltage Level Positive sequence capacitive Zero sequence Capacitive Capacitive
(KV) reactance (Ω) Reactance (Ω) Current (A)
220 3736 5260 34
330 2860 4170 66
500 2590 3790 111
750 2242 3322 193
Calculation of secondary value:

𝟏𝟏𝟏𝟏𝟏𝟏 𝑻𝑻𝑻𝑻𝒂𝒂𝒂𝒂𝒂𝒂𝒊𝒊𝑰𝑰
𝑿𝑿𝑪𝑪 × ×
𝒍𝒍 𝑻𝑻𝑻𝑻𝒂𝒂𝒂𝒂𝒂𝒂𝒊𝒊𝑰𝑰
𝒍𝒍:Line length
𝑿𝑿𝑪𝑪 : Capacitive reactance at intervals of 100km
For example, the length of the line with the Voltage Level of 220kV is
130km, the transformation ratio of CT (TA ratio) is 1200/1=1200, and
the transformation ratio of TV (TV ratio) is 220/0.1=2200, and then:
"LinePositiveSeqXcSet": 3736*(100/130)*1200/2200=1567Ω
"LineZeroSeqXcSet": 5260*(100/130)*1200/2200=2206Ω
10) "ShuntReactorPositiveSeqX", "ShuntReactorZeroSeqX": The capacity
of shunt reactor installed on the side line is converted to secondary
value:
𝑵𝑵𝑻𝑻𝑻𝑻 𝑼𝑼𝟐𝟐
𝑿𝑿𝟏𝟏 _𝑹𝑹𝒆𝒆𝒂𝒂𝑰𝑰𝒂𝒂𝑰𝑰𝒂𝒂 = ×
𝑵𝑵𝑻𝑻𝟖𝟖 𝑺𝑺
𝑵𝑵𝑻𝑻𝑻𝑻 𝑼𝑼𝟐𝟐
𝑿𝑿𝟎𝟎 _𝑹𝑹𝒆𝒆𝒂𝒂𝑰𝑰𝒂𝒂𝑰𝑰𝒂𝒂 = × ( + 𝟑𝟑𝟑𝟑𝑰𝑰 )
𝑵𝑵𝑻𝑻𝟖𝟖 𝑺𝑺
Where, 𝑿𝑿𝑰𝑰 is the phase-to-earth reactance of shunt reactor neutral

point.
For example: Shunt reactor rated voltage U=800kV, rated capacity
S=3×100Mvar, grounding reactance of shunt reactor neutral point is
500Ω, CT change ratio 𝑵𝑵𝑻𝑻𝑻𝑻 ＝2000/1, VT change ratio 𝑵𝑵𝑻𝑻𝟖𝟖 ＝750/0.1,
thereafter:
𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟐𝟐
𝑿𝑿𝟏𝟏 _𝑹𝑹𝒆𝒆𝒂𝒂𝑰𝑰𝒂𝒂𝑰𝑰𝒂𝒂 = × = 𝟓𝟓𝟓𝟓𝟓𝟓. 𝟖𝟖𝛀𝛀
𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕 𝟑𝟑 × 𝟏𝟏𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏
𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟖𝟐𝟐
𝑿𝑿𝟎𝟎 _𝑹𝑹𝒆𝒆𝒂𝒂𝑰𝑰𝒂𝒂𝑰𝑰𝒂𝒂 = ×( + 𝟑𝟑 × 𝟓𝟓𝟓𝟓𝟓𝟓) = 𝟗𝟗𝟗𝟗𝟗𝟗. 𝟖𝟖𝛀𝛀
𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕 𝟑𝟑 × 𝟏𝟏𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏
If there is no shunt reactor installation beside line, the device will be
set as upper limit(secondary value):
𝑿𝑿𝟏𝟏 _𝑹𝑹𝒆𝒆𝒂𝒂𝑰𝑰𝒂𝒂𝑰𝑰𝒂𝒂 = 𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝛀𝛀
𝑿𝑿𝟎𝟎 _𝑹𝑹𝒆𝒆𝒂𝒂𝑰𝑰𝒂𝒂𝑰𝑰𝒂𝒂 = 𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝛀𝛀
In addition: if the neutral point is connected to earth directly and XN is
0, 𝐗𝐗 𝟎𝟎 _𝐑𝐑 𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞 and 𝐗𝐗 𝟏𝟏 _𝐑𝐑 𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞 are equal in value; and if the neutral
point is not connected to earth, 𝐗𝐗 𝟎𝟎 _𝐑𝐑 𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞𝐞 = 𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝛀𝛀.;
60
11) "LocalIDCode": each longitudinal differential protection device has a

unique address identifier in the whole network;
12) "OppEndIDCode": refers to the opposite end device address
identification code of pilot differential protection used with local end;
13) “DiffOn” logic switch: as using differential protection, logic switch is set
"1"; as not using differential protection, logic switch is "0";
14) “AbruptChgDiffOn” logic switch: as using differential protection, logic
switch is set "1"; as not using differential protection, logic switch is "0";
15) Send the corresponding channel alarm (only the fault channels are
blocked and the differential protection is unblocked) when the logic
switch of the "DualChan" is set to "1" and either of the channel A/B is
fault. Send the channel alarm when the logic switch is set to "0" and
both of the channel A/B are fault. In general, as suing the use of dual
channel, the position is "1"; in the use of a single channel, the position
is "0";
16) "MasterMode" logic switch: "1" is for host machine mode and "0" for
slave mode. Device of both side must be set as one with host machine
mode and the other with slave machine mode;
17) “CompByCapacitiveCurr” logic switch: when the line height difference
is less than 4 times the capacitance current, or the low differential
value is less than 2 times the capacitance current, it is recommended
to compensate the capacitive current (set "1") When the height
difference value is greater than 4 times the capacitance current, and
the low difference value is greater than 2 times the capacitance
current, the capacitor current can be compensated, and the
longitudinal difference logic switch can be set to the
non-compensation capacitive current (set as "0");
18) "CTFailBlkDiff" logic switch, "CTFailBlk3Ph" logic switch, as
"CTFailBlkDiff" logic switch is set “1”, CT failure blocks differential
protection. Given this, it can use logic switch "CTFailBlk3Ph" to further
select CT failure to block three-phase differential protection ("1") or CT
failure only to block failure phase differential protection ("0"). If CT
disconnection only blocks disconnection phase differential protection,
and non-disconnection meets failure, non-disconnection will detect
according to separation phase differential high setting and low setting.
When the logic switch "CTFailBlkDiff" is set to "0", the CT failure does
not block the differential protection and the "CTFailBlk3Ph" does not
work. The CT disconnection phase is enabled with differential
protection after the CT failure. That is, when the differential current of
disconnection phase is greater than the "CTFailSplitPhDiffSet", the
differential protection trip will trip three phases and block
auto-reclosing;
19) "REFInitAR" logic switch: "1" is zero sequence deferential protection
trip startup auto-reclosing; "0" is zero sequence deferential protection
trip blocking auto-reclosing;
20) "SelExtrClockForChanA" logic switch: "1" is channel A external clock
and "0" is Channel B internal clock. When using special channel, set
to "0"; set to "1" when using multiplexing 64kbps channel; and set to
"0" when using multiplexing 2Mbps channel;
61
21) "Sel64KRateForChanA": it is valid under the G.703 protocol. When it

is set as "0", the rate chose by channel A is 2Mbps; when it is set as
"1", the rate chose by channel B is 64kbps. As using restricted channel,
it is suggested to set "0";
22) "SelExtClockForChanB" logic switch: "1" is channel B external clock
and "0" is Channel B internal clock. When using special channel, set
to "0"; set to "1" when using multiplexing 64kbps channel; and set to
"0" when using multiplexing 2Mbps channel;
23) "Sel64KRateForChanB": it is valid under the G.703 protocol. When it
is set as "0", the rate chose by channel B is 2Mbps; when it is set as
"1", the rate is 64kbps. As using restricted channel, it is suggested to
set "0". Note: If logic switch is set to single mode,
"Sel64KRateForChanB" logic switch should be set the same with
"Sel64KRateForChanA;
24) "ChanLoopTestOn" logic switch: as testing channel self-loop or
channel remote loop, it will display "1"; as normally running, it will
display "0";
25) "DDTCtrlledByStartup" logic switch: when set as "1", local side startup
component trips and receives the remote trip signal from the opposite
side, permanent trip; when set as "0", the remote trip is not controlled
by startup component, and the local side receives the remote trip
signal from the opposite side, permanent trip. If direct transmit trip
function is not used, it is also recommended to set this as "1";
26) "DDTCtrlledByZ2" logic switch is "1", permanent trip can start only do
remote trip is under protection startup, any phase separation
impedance is in zone 2 stage and receive remote trip signal. When
using zone 2 phase blocking, it is necessary to consider whether the
sensitivity meets the requirements; if it is "0", the remote tripping is not
controlled by zone 2. If direct transmit trip function is not used, it is
also recommended to set this as "1";
27) "DDTCtrlledByZ3" logic switch is "1", permanent trip can start only do
remote trip is under protection startup, any phase separation
impedance is in zone 3 and receive remote trip signal. When using
zone 3 blocking, it is necessary to consider whether the sensitivity
meets the requirements; if it is "0", the remote tripping is not controlled
by zone 3. If direct transmit trip function is not used, it is also
recommended to set this as "1".
3.4 Report list

Table 22 Report list
No. Report name Remark
Trip report:
1. SplitPhDiffTrip /
2. REFTrip /
3. DiffDevelopmentTrip /
4. DTTTrip /
62
5. TeleTransferCmd1BO /
13. TeleTransferCmd1Rst /
21. DiffWeakInfeedStartup /
22. DiffRmtCallStartup /
23. 3PhDiffCurr /
24. 3PhRestrCurr /
25. DTT BI /
26. TeleTransferCmd1BI /
63
34. OppEndDiffTrip /
35. SampleAsynchronization /
36. SampleSynchronized /
37. DataSrcChanA /
38. DataSrcChanB /
39. DiffSOTFTrip /
40. SplitPhDiffPhATrip /
41. SplitPhDiffPhBTrip /
42. SplitPhDiffPhCTrip /
Alarm report:
1. ChanACommInterrupt
2. ChanBCommInterrupt
3. DTT BIErr
4. ChanAAddrErr Alarm report of optical fiber channel
5. ChanBAddrErr
6. ChanABErrorConnection
7. OppEndCommErr
8. LocalCTFail /
9. OppEndCTFail /
10. LongTermDiffCurr /
11. SyncModeSetErr /
12. ChanALoopErr /
13. ChanBLoopErr /
14. NoSampleRptInChanA /
64
15. NoSampleRptInChanB /
16. LongTermChanLoopOn /
17. DiffLSInconsist /
18. ChanMaintDiffOff /
Operation report:
1. ChanACommRst
2. ChanBCommRst
Operation report of optical fiber channel
3. OppEndIEDRst
4. OppEndIEDOff
5. DiffFcnOn /
6. DiffFcnOff /
7. RmtLoopbackOfChanA /
8. ChanALoopbackEnd /
9. RmtLoopbackOfChanB /
10. ChanBLoopbackEnd /
65
3.5 Technical parameter

Table 23 Line differential protection technical parameter
Items Range and value Error
Differential current 0.1In to 20.00In ≤ ±3% or 0.02In

 Split-phase differential
protection
 Abrupt change
differential protection
Differential current of 0.05In to 20.00In ≤ ±5% or 0.02In

restricted earth fault
protection
0 to10.00s When the setting is greater

Trip time of restricted
than 100ms, it satisfies
≤±1% or +30ms
Trip time Typical trip time 25ms, when

200% setting, and
 Split-phase differential
IDifferential>2IRestraint
protection
 Abrupt change
differential protection
Note: In: CT secondary rated current, 1A or 5A.
66
Chapter 5 Line distance protection (21/21N)
Chapter 5 Line Distance Protection

(21/ 21N)
About this chapter

This Chapter describes the principle of line distance
protection, input and output signal, setting parameters, report
and technical parameters.
67
1 Introduction
Transmission line distance protection covers five distance trip zones and
one extension distance trip zone, to remove phase-to-phase and
single-phase grounding faults and it is also equipped with fast distance
protection. The IED employees separated measuring component for three
single-phase fault loops and three phase to phase fault loops for each
individual zones.
Each distance protection is enabled/disabled in accordance with
corresponding logic switch. Fast distance protection is enabled/disabled
by logic switch "FastDistZ1Prot" and "DistZ1On".
Individual settable zones in resistance and reactance component give the
flexibility for using on overhead lines and cables of different types and
lengths.
The independent measurement of impedance for each fault loop together
with a sensitive and reliable built in phase selection makes the function
suitable in applications with single phase auto-reclosing.
Each zone of the distance protection can be set as MHO or polygon
characteristic by setting the logic switch. Take distance zone 1 as an
example, when the logic switch "PEZ1MhoCharac" is set to 1, the MHO
characteristic of phase-to-earth zone 1 is enabled, when it is set to 0, the
polygon characteristic of phase-to-earth zone 1 is enabled; when the logic
switch "PPZ1MhoCharac" is set to 1, the MHO characteristic of
phase-to-phase zone 1 is enabled, when it is set to 0, the polygon
characteristic of phase-to-phase zone 1 is enabled. The following figures
illustrate the different available zone characteristics.
Line
X
Zone 5
Zone 4
Zone 3
Zone 2
Zone Ext.
Zone 1
Zone 3 Reverse
(optional)
Zone 4 Reverse
(optional)
Zone 5 Reverse
(optional)
Figure 39 Distance polygonal protection and trip zone characteristics
68
X
Zone 5
Zone 4
Zone 3
Zone 2
Zone Ext.
Zone 1
Zone 3 Reverse
(optional)
Zone 4 Reverse
(optional)
Zone 5 Reverse
(optional)
Figure 40 Distance protection MHO trip zone characteristics

Input and output signals of the distance protection function are shown as
follow:
Line Distance protection
1 1
BLK_Dis Relay_StartUp
2 2
BLK_Zone1 Relay_Trip
3 3
BLK_Zone2 Relay_Trip_A
4 4
BLK_Zone3 Relay_Trip_B
5 5
BLK_Zone4 Relay_Trip_C
6 6
BLK_Zone5 Trip_3ph
7 7
BLK_Zone1Ext Relay_Block_AR
8 8
PSBSB Zone1_Trip
9 9
BLK_Seriescap Zone2_Trip
10
Zone3_Trip
11
Zone4_Trip
12
Zone5_Trip
13
Zone1ExtTrip
14
DIST_PSB_Trip
15
DIST_PSB_Alarm
16
SOTF_Trip
Figure 41 Input and output signal diagram of the distance protection function
right.
69
Function Logo Description
Input:
BLK_Dis 1: Distance protection binary input blocking
BLK_Zone1 1:Distance zone 1 binary input blocking

Blocking_BI
BLK_Zone1Ext 1:Distance zone 1 binary input blocking

1: swing blocking identification binary input
PSBSB
blocking
BLK_Seriescap 1: Series compensation binary input blocking
Output:
Relay_Trip IED trip
Relay_Trip_A TripA
Relay_Trip_B TripB
Relay_Trip_C TripC
Trip_3ph TripABC
Relay_Block_AR Trip three phases and block auto-reclosing
Tripcom Zone1_Trip Trip of distance zone 1
Zone2_Trip Trip of distance zone 2
Zone1ExtTrip Extension zone 1 impedance trip
DIST_PSB_Trip Distance trip in power swing
DIST_PSB_Alarm Blocking output of power swing
70
The execution of the different fault loops are of full scheme type, which
means that each fault loop for phase to earth faults and phase to phase
faults for forward and reverse faults are executed in parallel.
The table as follow presents an outline of the different measuring
components for the basic five zones, impedance-measuring zones and
zone extension.
Table 25 Different impedance measurement component of single phase earth faults and
phase-phase faults
Distance
Distance measurement components
zone
Impedance Impedance Impedance Impedance of Impedance of Impedance of
Zone 1 of phase A to of phase B to of phase C to phase A to phase B to phase C to
earth earth earth phase B phase C phase A
Extended
of phase A to of phase B to of phase C to phase A to phase B to phase C to
zone 1
Each zone is an independent distance protection with six distance

measurement components.
3.1.1 Distance protection polygonal characteristics
3.1.1.1 Distance protection polygonal characteristics
Distance protection polygonal characteristics as shown as follow.
X
Line
X_Zset
Φ_Ztop
Φ_Zleft
Φ_Zright
R_Zset R
Φ_Zbottom
Figure 42 Distance protection polygonal characteristics
71
Where:
R_Zset: "ResistanceSetOfPEZ1", "ResistanceSetOfPEZ2",
"ResistanceSetOfPEZ3", "ResistanceSetOfPEZ4”,
"ResistanceSetOfPEZ5", "RSetOfPEExtZ1" or "ResistanceSetOfPPZ1",
"ResistanceSetOfPPZ2", "ResistanceSetOfPPZ3",
"ResistanceSetOfPPZ4", "ResistanceSetOfPPZ5", “RSetOfPPExtZ1".
X_Zset:"ReactanceSetOfPEZ1", "ReactanceSetOfPEZ2",
"ReactanceSetOfPEZ3", "ReactanceSetOfPEZ4", "ReactanceSetOfPEZ5",
"ReactanceSetOfPEExtZ1" or "ReactanceSetOfPPZ1",
"ReactanceSetOfPPZ2", "ReactanceSetOfPPZ3", "ReactanceSetOfPPZ4",
"ReactanceSetOfPPZ5", "ReactanceSetOfPPExtZ1".
Particular attention: When R_Zset is set in accordance with the normal
overload impedance, the setting range is usually large, so the setting value
of resistance used in distance protection is appropriately reduced on the
basis of setting value. The setting value of resistance is automatically
calculated by the following formula within the device:
𝐗𝐗 𝐙𝐙𝐙𝐙𝐙𝐙𝐙𝐙 𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑 𝟏𝟏 𝟏𝟏
𝐑𝐑_𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢 = 𝐦𝐦𝐦𝐦𝐦𝐦{𝐑𝐑 𝐙𝐙𝐙𝐙𝐙𝐙𝐙𝐙 , 𝐦𝐦𝐦𝐦𝐦𝐦 � , + 𝑹𝑹𝟏𝟏� , ( + ) × 𝐗𝐗_𝐙𝐙𝐙𝐙𝐙𝐙𝐙𝐙}
𝟐𝟐 𝑳𝑳𝒁𝒁 𝐒𝐒𝐒𝐒𝐰𝐰 𝛂𝛂 𝐒𝐒𝐒𝐒𝐰𝐰 𝛂𝛂𝐥𝐥𝐥𝐥𝐥𝐥𝐥𝐥
Where:
R_innerset: actually used resistance value;
LZ: The conversion coefficient of impedance, i. e. the ratio of "PTRatio
divided by "CTRatio";
R1: positive sequence impedance resistance component of the whole line;
𝟏𝟏 𝟏𝟏
( + ) × 𝐗𝐗_𝐙𝐙𝐙𝐙𝐙𝐙𝐙𝐙: In complex plane impedance characteristics, the
𝐒𝐒𝐒𝐒𝐰𝐰 𝛂𝛂 𝐒𝐒𝐒𝐒𝐰𝐰 𝛂𝛂𝐥𝐥𝐥𝐥𝐥𝐥𝐥𝐥
intersection of the lower slant of the first quadrant and the R axis.
𝛂𝛂
angle:“DistZ1PEInclinedAngle”,“DistZ1PPInclinedAngle”“OtherZonePEIncl
inedAngle”,“OtherZonePPInclinedAngle”.
𝛂𝛂𝐥𝐥𝐥𝐥𝐥𝐥𝐥𝐥 angle: LineImpedanceAngle.
Φ_Ztop: The upper boundary angle of the polygonal characteristic in the
first quadrant is designed to avoid distance protection overreaching when
a close-in fault happens on the adjacent line.
Φ_Zbottom: The bottom boundary angle of the polygonal characteristic in
the fourth quadrant improves the reliability of the IED to operate reliably for
close-in faults with arc resistance.
Φ_Zright: The right boundary angle of polygonal characteristic in the first
quadrant is used to deal with load encroachment problems.
Φ_Zleft: The left boundary angle of the polygonal characteristic in the
second quadrant considers the line impedance angle which generally is
not larger than 90°. Thus this angle guarantees the correct operation of the
IED.
The Φ_Ztop angle can be adjusted: When a single-phase fault occurs, the
distance zone 1 and the extension distance zone 1 can set
“DistZ1PEInclinedAngle” in accordance with the actual situation, and other
zones can set “OtherZonePEInclinedAngle” in accordance with the actual
situation, and the angle range is 0~45°; When phase-to-phase fault occurs,
the distance zone 1 and the extension distance zone 1 can set
72
“DistZ1PPInclinedAngle” in accordance with the actual situation, and other

zones can set "OtherZonePPInclinedAngle" in accordance with the actual
situation, and the angle range is 0~45°.
Φ_Zright angle can adjust “ResistanceLineAngle” in accordance with the
actual situation. For the distance protection in each zone, the adjusting
range is 45°~90°.
Φ_Zleft angle can be set as "2ndQuadrantAngle" in accordance with the
actual situation. For the distance protection in each zone, the adjusting
range is 0°~45°.
Φ_Zbottom angle can be set as "4thQuadrantAngle" in accordance with
the actual situation. For the distance protection in each zone, the adjusting
range is 0°~15°.
The device is equipped with load encroachment clear functions, shown in
figure as follow.
Logic switch: Use "PEDistLoadEncroachment" and
"PPDistLoadEncroachment" to control the single phase faults and
phase-to-phase faults whether the distance load encroachment zones are
cleared.
Scope of the encroachment zones can be adjusted according to the setting
value:
Φ_Load: "PELoadEncroachmentAngle", "PPLoadEncroachmentAngle";
Φ_Load: "PEDistLoadEncroachR", "PPDistLoadEncroachR";
The cleared load zone is shown in the dash area of the figure.
Φ_Load
R_Load
Figure 43 Characteristics of polygonal distance protection zone after the clear of the
load zone
3.1.1.2 Extension polygonal distance protection characteristics
If the faults are located at the protection assembly, the voltage at the faults
point is zero. Except of VT failure, measured impedance does not reflect
the true fault impedance. For example, in the following two cases, incorrect
actions may happen.
73
1) The fault is near the bus and in the forward direction but measured
impedance is not within the forward quadrilateral characteristic.
2) The fault is near the bus and in the reverse direction but measured
impedance is not within the reverse quadrilateral characteristic.
Using fault phase current and voltage only, resistance value cannot
accurately determine whether fault occurs in the reverse direction or the
forward direction. To solve the problem, IED considers the small rectangle
near to origin to extend protection zones. Therefore, to increase relay
reliable operation in addition to the tripping characteristic mentioned above,
an extended zone area with a little rectangular characteristic is involved. In
this case, final direction is determined based on both extended zone
characteristic and the criteria mentioned in Figure 42 , including memory
voltage direction component, the zero sequence directional component,
and the negative sequence direction component. In other words, relay
generates trip if both direction and extended zone impedance confirm
each other.
This rectangular area, which is called impedance-offset characteristic, has
been shown in Figure 44 which is added to the characteristic shown in
(Figure 42 ).
X_Zset
Φ_Ztop
Φ_Zleft
Φ_Load R_Load Φ_Zright
XOffset
R
ROffset
R_Zset
Φ_Zbottom
Figure 44 Extension polygonal distance protection characteristics

The rectangular offset characteristic (shown in the figure above) is
calculated automatically according to the related distance zones settings.
Where:
X Offset: Minimum value {XSet/ 2, 0.5ΩΩ (when In=5A) / 2.5ΩΩ (when
In=1A)}
R Offset: Minimum value {Maximum value {Minimum value {8×XOffset,
RSet/ 4}, 2×XOffset}, RSet}
R_Zset: "ResistanceSetOfPEZ1", "ResistanceSetOfPEZ2",
"ResistanceSetOfPEZ3", "ResistanceSetOfPEZ4”,
"ResistanceSetOfPEZ5", "RSetOfPEExtZ1" or "ResistanceSetOfPPZ1",
"ResistanceSetOfPPZ2", "ResistanceSetOfPPZ3",
"ResistanceSetOfPPZ4", "ResistanceSetOfPPZ5", “RSetOfPPExtZ1".
R_Zset:"ReactanceSetOfPEZ1", "ReactanceSetOfPEZ2",
74
"ReactanceSetOfPEZ3", "ReactanceSetOfPEZ4", "ReactanceSetOfPEZ5",

"ReactanceSetOfPEExtZ1" or "ReactanceSetOfPPZ1",
"ReactanceSetOfPPZ2", "ReactanceSetOfPPZ3", "ReactanceSetOfPPZ4",
"ReactanceSetOfPPZ5", "ReactanceSetOfPPExtZ1".
3.1.2 Distance protection MHO characteristics
3.1.2.1 Steady state MHO characteristics of distance protection
The steady-state MHO characteristics is the circle passing through the
coordinate origin , as shown in the figure below:
jX
ZZD
φline
R
Figure 45 Steady state MHO characteristics of distance protection

Where:
ZZD ：MHO characteristics impedance setting of each section,
“MHOImpedSetOfPEZ1”, “MHOImpedSetOfPEZ2”,
“MHOImpedSetOfPEZ5”, “MHOImpedSetOfPEExtZ1”,
“MHOImpedSetOfPPZ1”, “MHOImpedSetOfPPZ2”,
“MHOImpedSetOfPPZ5”, “MHOImpedSetOfPPExtZ1”.
Φline：Line impedance angle, obtained by calculating the setting
“WholeLinePositiveSeqX” and “WholeLinePositiveSeqR”, should not be
less than 45 degrees.
75
3.1.2.2 Polarization MHO characteristics of distance protection

The polarization MHO characteristics of distance protection passes
through the coordinate origin, as shown in the following figure:
jX
Z ZD j =0 j = 30
j
R
ZS
Figure 46 Polarization MHO characteristics of distance protection

Where:
ZS ：Source impadance
φ：Adjustable impedance offset angle of each section，to improve the
ability with transition resistance, and the setting range is 0 ~ 30 °.
“PEZ1ShiftAngle”, “PEZ2ShiftAngle”, “PEZ3ShiftAngle”, “PEZ4ShiftAngle”,
“PEZ5ShiftAngle”, “PEExtZ1ShiftAngle”, “PPZ1ShiftAngle”,
“PPZ2ShiftAngle”, “PPZ3ShiftAngle”, “PPZ4ShiftAngle”, “PPZ5ShiftAngle”,
“PPExtZ1ShiftAngle”.
3.1.2.3 Distance protection MHO relay
When the trip zone is a positive trip zone, i.e. distance zone 1, extended
distnace zone 1, distance zone 2, and distance zone 3 when "
DistZ3RvsDir " is 0 , distance zone 4 when " DistZ4RvsDir " is 0 , and
distance zone 5 when " DistZ5RvsDir” is 0:
The trip characteristics of positive directional fault is shown as the
following figure (1), and action characteristics of reverse directional fault is
shown as the following figure (2):
76
jX
jX
Z 'S
Z ZD
Z ZD
j
R R
ZS Z
（1）Positive directional fault dynamic characteristic diagram （2）Reserve directional

fault dynamic characteristic diagram
Figure 47 Polarization MHO characteristics of distance protection
The positive directional trip equation is:
U̇1
270 − φ > Arg > 90 − φWhere:
U̇−ZZD ×İ

ZS ：Total impedance from local system to protection installation;
Z′S ：Total impedance from protection installation to remote system;
Z：Measuring impedance;
U̇ 1 ：Polarization voltage, which is positive sequence voltage;
U̇ − ZZD × İ：Working voltage, which is U̇ ∅ − ZZD × �İ∅ + K × 3İ0 � for
single-phase voltage and U̇ ∅∅ − ZZD × İ∅∅ for phase-to-phase voltage, K is
the zero sequence compensation coefficient of the line.
φ：Adjustable impedance offset angle，to improve the ability with transition
resistance.“PEZ1ShiftAngle”, “PEZ2ShiftAngle”, “PEZ3ShiftAngle”,
“PEZ4ShiftAngle”, “PEZ5ShiftAngle”, “PEExtZ1ShiftAngle”,
“PPZ1ShiftAngle”, “PPZ2ShiftAngle”, “PPZ3ShiftAngle”, “PPZ4ShiftAngle”,
“PPZ5ShiftAngle”, “PPExtZ1ShiftAngle”.
The dynamic working characteristics are shown in (1) above, and ZZD and
-ZS are the diameter (offset the angle of φ), so the origin is within the
impedance circle. In case of reverse fault, its dynamic characteristics are
shown in figure (2), that is, the distance protection has clear directionality
and there is no dead zone in the memory process.
When the three-phase short circuit occurs near the outlet of the protection
installation, the positive sequence voltage will be lower than 15% Un, then
the memory positive sequence voltage is used as the polarization voltage
to eliminate the dead zone of the three-phase near zone fault distance
protection.
77
In addition, the trip zone is reverse trip zone, that is, when distance zone 3
in " DistZ3RvsDir"=1, distance zone 4 in " DistZ4RvsDir"=1, and distance
zone 5 in" DistZ5RvsDir"=1 :
The trip characteristics of fault in the zone are shown in the following
figure:
jX
'
ZS
j R
Z ZD
Figure 48 The dynamic characteristics of distance protection polarization circular

The reverse directional trip equation is:
U̇ 1
270 − φ > Arg > 90 − φ
U̇ + ZZD × İ
Where:
U̇ 1 ：Polarization voltage, which is positive sequence voltage;
U̇ + ZZD × İ：Working voltage, which is U̇ ∅ + ZZD × �İ∅ + K × 3İ0 � for
single-phase voltage and U̇ ∅∅ + ZZD × İ∅∅ for phase-to-phase voltage, K is
the zero sequence compensation coefficient of the line.
φ：Adjustable impedance offset angle of each section，to improve the
ability with transition resistance.“PEZ1ShiftAngle”, “PEZ2ShiftAngle”,
“PEZ3ShiftAngle”, “PEZ4ShiftAngle”, “PEZ5ShiftAngle”,
“PEExtZ1ShiftAngle”, “PPZ1ShiftAngle”, “PPZ2ShiftAngle”,
“PPZ3ShiftAngle”, “PPZ4ShiftAngle”, “PPZ5ShiftAngle”,
“PPExtZ1ShiftAngle”.
3.1.2.4 Distance reactance relay
At the same time, the zero sequence reactance relay is used by ground
distance protection to prevent exceeding, which avoids the transient
overshoot caused by the remote feed in power supply, and improves the
anti fault ability of the short line distance protection.
Zero sequence reactance characteristics, as shown in line A in the figure
below.
78
jX
Z ZD
θ
A
Figure 49 Distance protection zero sequence reactance characteristics

Reactance relay is adopted for phase to phase distance protection to
prevent exceeding.
3.1.2.5 Distance protection MHO characteristics load encroachment
The device is equipped with load encroachment clear functions, shown in
figure as follow.
Logic switch: Use "PEDistLoadEncroachment" and
phase-to-phase faults whether the distance load encroachment zones are
cleared.
Scope of the encroachment zones can be adjusted according to the setting
value:
R_Load: "PEDistLoadEncroachR", "PPDistLoadEncroachR".
The cleared load zone is shown in the dash area of the figure.
jX
Φ_Load
R_Load
R
Load Area R
Figure 50 Characteristics of distance protection circle which is clear of loaded zone
3.1.3 Minimum operating current

The operation of the distance measuring zone is blocked if the magnitudes
of input currents fall below certain thresholds.
When the root mean square of current is less than 0.1In, the calculations
of phase-to-phase impedance and earth impedance are locked.
3.1.4 Distance measurement components
A separate measuring system has been provided for each of the six
possible impedance loops A-E, B-E, C-E, A-B, B-C, C-A. The impedance
calculation will be continued whether a fault has been detected.
79
Based on the following differential equations, measuring elements

calculates relevant loop impedances with real-time voltages and currents.
Measuring of the single phase impedance for a single phase fault is as
follows:
𝐝𝐝(𝐈𝐈∅ + 𝐊𝐊 𝐱𝐱 × 𝟑𝟑𝐈𝐈𝟎𝟎 )
𝐔𝐔∅ = 𝐋𝐋∅ × + 𝐑𝐑 ∅ × (𝐈𝐈∅ + 𝐊𝐊 𝐫𝐫 × 𝟑𝟑𝐈𝐈𝟎𝟎 )
𝐝𝐝𝐝𝐝
∅：𝐀𝐀, 𝐁𝐁, 𝐂𝐂
Measuring of the phase-phase impedance for multi-phase faults is as
follows:
𝐝𝐝𝐈𝐈∅∅
𝐔𝐔∅∅ = 𝐋𝐋∅∅ × + 𝐑𝐑 ∅∅ × 𝐈𝐈∅∅
𝐝𝐝𝐝𝐝
∅∅：𝐀𝐀𝐀𝐀, 𝐁𝐁𝐁𝐁, 𝐂𝐂𝐂𝐂
Where, 𝐊𝐊 𝐱𝐱 and 𝐊𝐊 𝐫𝐫 are residual compensation factors. Matching of the
earth to line impedance is an essential prerequisite for the accurate
measurement of the fault impedance (impedance protection, fault locater)
during earth faults. This compensation will be done by residual
compensation settings value:
𝐗𝐗 𝟎𝟎 − 𝐗𝐗 𝟏𝟏
𝐊𝐊 𝐱𝐱 =
𝟑𝟑𝐗𝐗 𝟏𝟏
𝐑𝐑 𝟎𝟎 − 𝐑𝐑 𝟏𝟏
𝐊𝐊 𝐫𝐫 =
𝟑𝟑𝐑𝐑 𝟏𝟏
Measuring resistance R and reactance X (ωL=2πfL) at IED location can be
obtained by solving above differential equations.
For example, solving above equations leads to the following relation for
phase-phase (A-B) short circuit which can be used to calculate the
phase-to-phase loop impedance.
Figure 51 Phase-to-phase (A-B) short circuit

𝑰𝑰𝑳𝑳𝟏𝟏 × 𝒁𝒁𝑳𝑳 − 𝑰𝑰𝑳𝑳𝟐𝟐 × 𝒁𝒁𝑳𝑳 = 𝑼𝑼𝑳𝑳𝟏𝟏𝑬𝑬 -𝑼𝑼𝑳𝑳𝟐𝟐𝑬𝑬
Where:
U, I: measuring voltage and measuring current
Z=R+jX: measured impedance
Line impedance can be calculated as follow:
𝑼𝑼𝑳𝑳𝟏𝟏𝑬𝑬 − 𝑼𝑼𝑳𝑳𝟐𝟐𝑬𝑬
𝒁𝒁𝑳𝑳 =
𝑰𝑰𝑳𝑳𝟏𝟏 − 𝑰𝑰𝑳𝑳𝟐𝟐
In addition, solving differential equation for single-phase (e.g. A-E) results:
80
Figure 52 Single phase earth (A-E) short circuit

𝑹𝑹𝑬𝑬 𝑿𝑿𝑬𝑬
𝑼𝑼𝑳𝑳𝟏𝟏𝑬𝑬 = 𝑰𝑰𝑨𝑨 × (𝑹𝑹𝑳𝑳 + 𝒋𝒋𝑿𝑿𝑳𝑳 ) − 𝑰𝑰𝑬𝑬 × � 𝑹𝑹𝑳𝑳 + 𝒋𝒋 𝑿𝑿 �
𝑹𝑹𝑳𝑳 𝑿𝑿𝑳𝑳 𝑳𝑳
= 𝑰𝑰𝑨𝑨 × (𝑹𝑹𝑳𝑳 + 𝒋𝒋𝑿𝑿𝑳𝑳 ) − 𝑰𝑰𝑬𝑬 × (𝐊𝐊 𝐫𝐫 𝑹𝑹𝑳𝑳 + 𝒋𝒋𝐊𝐊 𝐱𝐱 𝑿𝑿𝑳𝑳 )
This can be used for resistance and reactance calculation by separating it
to real and imaginary parts.
The impedances of the unfaulted phases are also influenced by the
short-circuit currents and voltages in the short-circuited phases. For
example, during an A-E fault, phase-to-phase impedance calculation of.
A-B and C-A is affected by I1 and the phase-to-earth impedance
calculation of phase B and C is affected by IE. In addition to the load
currents which may flow, the unfaulted phases will be affected by faulted
loop current which have nothing to do with the actual fault distance/
impedance.
Effect in the unfaulted phases is usually greater than the short-circuit
impedance of the faulted loop, because the unfaulted phase only carries a
part of the fault current and always has a larger voltage than the faulted
loop. As mentioned earlier, all impedance calculations start independently
when the impedance calculation is triggered by any of the starting
components. First, the symmetric component phase selector chooses the
fault phase, and then the IED compare the impedance of these phases to
remove the unfaulted phases.
3.1.5 Distance polygonal direction component
Considering the VT and other failures, the polarity of the measured
impedance may not reflect the true distance from the fault. So, the IED
judges the fault direction through using integrated directional components.
The memory voltage method, which is based on the pre-fault memory
voltage and the current ratio of the fault, can effectively judge the direction
of the distance protection. Under normal circumstances, using memory
voltage to judge the direction of the fault has merit, since the transient
process has not been affected. But the memory voltage cannot be a long
effective quantity. Therefore, IED needs to rely on forward and reverse
direction to expand the logic.
For solid earthed system, characteristics of zero sequence directional
components only have relations with the zero sequence impedance angle
of the back ground, no relations with the magnitude of the load current and
the earth resistance. For zero sequence directional components, free from
the problems of memory voltage storage, direction of the distance
protection can be determined. See details in earth fault protection for zero
sequence directional components.
Negative- sequence directional components, in any asymmetric faults,
81
have the clear directivity. Characteristics of negative sequence directional

components only have relations with the negative sequence angle of the
back system, no relations with the magnitude of the load current and the
earth resistance. Like the zero sequence directional components, for
negative sequence directional components, free from the problems of
memory voltage storage, direction of the distance protection can be
determined. See details in the Chapter 7 earth fault protection for negative-
sequence directional components.
In summary, the distance protection has two essential conditions to
operate: corresponding direction detection component is satisfied and
calculated impedance is entered into the impedance characteristics zone.
The usage of direction components is different for five zone
characteristics:
1) Distance zone 1 trip area: it is used as fast zone commonly. Since high
speed and required selectivity are quite essential, requirements for the
direction component must be forward direction;
2) The extension zone 1 trip area: it is different from the other five zones.
the extended distnace zone 1 works under the invalid main protecion
condition and it is a backup of main protecion;
3) Distance zone 2 trip area: it is used as time delay zone commonly.
Considering enough reliability, its direction criterion is not reverse
direction;
4) Distance zone 3 trip area: it can be selected to trip for reverse
direction or forward direction through "DistZ3RvsDir". When
"DistZ3RvsDir" is set to 0, generally, as the last forward direction zone,
the delay time of the last forward zone is much longer, so it is mostly
used for non-reverse trip zone and the direction criterion principle is
non-reverse; when "DistZ3RvsDir" is set to 1, its direction criterion
principle is non-forward direction.
"DistZ4RvsDir" is set to 0, so it is mostly used for non-reverse trip
zone and the direction criterion principle is non-reverse; when
"DistZ4RvsDir" is set to 1, it is generally used as non-forward trip zone,
so its direction criterion principle is non-forward direction.
"DistZ5RvsDir" is set to 0, it is mostly used for non-reverse trip zone,
so the direction criterion principle is non-reverse; when "DistZ5RvsDir"
is set to 1, it is generally used as non-forward trip zone, so its direction
criterion principle is non-forward direction.
For three phase faults, direction checking is only determined by memory
voltage. In this case, IED considers impedance characteristics as well as
memory voltage determination.
If there is neither a current measured voltage nor a memorized voltage
available which is sufficient for measuring the direction, the IED selects the
forward direction. In practice this can only occur when the circuit breaker
closes onto a de-energized line, and there is a fault on this line.
82
3.1.6 Instruction of extension zone 1

The extension zone 1 is the backup protection for the main protections,
when the main protections are disabled or invalid, the extension zone 1
can be enabled to protect the whole length of the line. The extension zone
1 can be enabled as the following figure:
“DistExtZ1On”=1
Pilot distance of optical fiber:
optical fiber channel fault
Node type BI:
BI_Carr_Recv_Dist
≥1
PUTTModeValid &
POTTModeValid
Pilot distance blocking mode
Pilot earth fault of optical fiber:
optical fiber channel fault
Node type BI:
BI_Carr_Recv_DEF ≥1
Permissive pilot earth fault mode &
&
Enable distance
Pilot earth fault blocking mode extension zone 1
“DiffOn”=0 ≥1
&
“DiffOn”=1
Optical fiber channel fualt
“AROn”=0 ≥1
&
“AROn”=1
BI:AR_OFF
BI:AR_BLOCK
AR stop
Figure 53 Logic diagram of enabling the extension zone 1
3.1.7 Power swing blocking

3.1.7.1 Introduction
Power system swing refers to the swing of the power flow. Power grid is a
dynamic network connected to the generator and load via electric
transmission line. Some disturbances such as sudden change in the load
but no changes in the generator output, or system fault, or stability
disruption caused by the tripping of the large units will cause the angle
swing between the rotors of the generators to adjust the generator to a
new operation conditions. Due to the rotating inertia of the generators, a
new operation conditions will not be adjusted rapidly. Swing frequency is
determined by the system inertia and impedance between different
generators.
3.1.7.2 Work principle
Power swings are variations in power flow that occur when the internal
voltages of generators at different locations of the power system slip
relative to each other. In this way, voltage and current waveforms will have
an underfrequency swing over the power system nominal frequency.
Therefore impedance trajectory seen by a distance IED may enter the fault
detection zones and cause unwanted IED operation. A simple double
power supply system example is illustrated in the following diagram.
83
Figure 54 Two machine system to simulate power swing behavior

3.1.7.3 Impedance trajectory
The current passing through the feeder (IL) will be calculated in any time
by:
𝑬𝑬𝑺𝑺 − 𝑬𝑬𝑹𝑹
𝑰𝑰𝑳𝑳 =
𝒁𝒁𝑺𝑺 + 𝒁𝒁𝑳𝑳 + 𝒁𝒁𝑹𝑹
The direction of current flow will remain the same during the power swing
event. Only the voltage displacement will change.
The impedance measured at an IED at bus A would then be:
𝑽𝑽𝑨𝑨 𝑬𝑬𝑺𝑺 − 𝑰𝑰𝑳𝑳 × 𝒁𝒁𝑺𝑺 𝑬𝑬𝑺𝑺 𝑬𝑬𝑺𝑺 × (𝒁𝒁𝑺𝑺 + 𝒁𝒁𝑳𝑳 + 𝒁𝒁𝑹𝑹 )
𝒁𝒁 = = = − 𝒁𝒁𝑺𝑺 = − 𝒁𝒁𝑺𝑺
𝑰𝑰𝑳𝑳 𝑰𝑰𝑳𝑳 𝑰𝑰𝑳𝑳 𝑬𝑬𝑺𝑺 − 𝑬𝑬𝑹𝑹
It is assumed that 𝑬𝑬𝑺𝑺 advance𝑬𝑬𝑹𝑹 is δ, and that the ratio of the two source
voltage magnitudes𝑬𝑬𝑺𝑺 /𝑬𝑬𝑹𝑹 is 𝒌𝒌. then:
𝑬𝑬𝑺𝑺 𝒌𝒌(𝐜𝐜𝐜𝐜𝐜𝐜 𝜹𝜹 + 𝒋𝒋 𝐬𝐬𝐬𝐬𝐬𝐬 𝜹𝜹) 𝒌𝒌[(𝒌𝒌 − 𝐜𝐜𝐜𝐜𝐜𝐜 𝜹𝜹) − 𝒋𝒋𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬]
= =
𝑬𝑬𝑺𝑺 − 𝑬𝑬𝑹𝑹 𝒌𝒌(𝐜𝐜𝐜𝐜𝐜𝐜 𝜹𝜹 + 𝒋𝒋 𝐬𝐬𝐬𝐬𝐬𝐬 𝜹𝜹) − 𝟏𝟏 (𝒌𝒌 − 𝐜𝐜𝐜𝐜𝐜𝐜 𝜹𝜹)𝟐𝟐 + 𝐬𝐬𝐬𝐬𝐬𝐬𝟐𝟐 𝜹𝜹
When the two power supply amplitudes equal, k=1, formula above can be:
𝑬𝑬𝑺𝑺 𝟏𝟏 𝜹𝜹
= �𝟏𝟏 − 𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋 �
𝑬𝑬𝑺𝑺 − 𝑬𝑬𝑹𝑹 𝟐𝟐 𝟐𝟐
Finally, the measured impedance in the device is:
𝑽𝑽𝑨𝑨 (𝒁𝒁𝑺𝑺 + 𝒁𝒁𝑳𝑳 + 𝒁𝒁𝑹𝑹 ) 𝜹𝜹
𝒁𝒁 = = (𝟏𝟏 − 𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋 ) − 𝒁𝒁𝑺𝑺
𝑰𝑰𝑳𝑳 𝟐𝟐 𝟐𝟐
Therefore, in the process of system swing, if the voltage angle between
two power supplies changes, the measured impedance of the device
changes. When the voltage amplitudes of two power supply are not equal,
the swing trajectory is shown in the figure as follow.
Figure 55 Impedance trajectories for k values
84
The figure as follow shows the practical possible impedance trajectory

which may happen in the power system. Cases 1 and 2 indicate a stable
power swing which entered the distance protection tripping zone. Case 3 is
unstable power swing which enters and exits the trip zones. Curve 4 also
shows the impedance trajectory in the case of short circuit occurrence in
the power system.
X 2
3
Figure 56 Impedance trajectories for different power swing conditions

3.1.7.4 Unblocking component of power swing
To ensure the correct operation of the protection logic and avoiding IED
maloperation in power swings conditions, power swing blocking function
has been integrated in IED. The main purpose of the PSB function is to
differentiate between faults and power swings and block distance.
However, faults that occur during a power swing must be detected and
cleared with a high degree of selectivity and dependability. Power swing
blocking happens if one of the following conditions remains for 30ms.
1) A, B, C phase currents are greater than
"SteadyLossStabilityCurrSet"and the sudden-change current startup
component hasn't operated;
2) AB, BC, CA phase- phase impedances and measured impedances
are in the scope of impedances III and the sudden-change current
startup component hasn't operated.
As mentioned, if any of the above conditions has been valid for 30ms,
power swing startup will operate and protection program is switched to
power swing blocking routine. At the same time, “SteadyLossStabilityStart”
(for the first condition) or “ImpedComponentStartup” (for the second
condition) and “IEDStartup” signals are reported. It should be note that
"SteadyLossStabilityCurrSet” should be set greater than maximum load
current in the protected feeder.
Operation of sudden-change current indicates a fault occurred in the
power system network. In short circuit conditions, the measured
impedance jumps instantaneously from load impedance area to the fault
detection zones. On the other hand, power swings have a slow behavior.
So, lack of operation of current sudden-change component beside high
measured current and/ or low calculated impedance indicates that power
swing happened in the system. Therefore above condition has been used
85
to initiate power swing startup component.

In addition, experimental results of power swing show that it is not possible
for impedance vector to come into the distance zone 1 in 150ms after
current sudden-change startup operation. Therefore, power swing blocking
logic has been designed such that in 150ms after current sudden-change
startup, power swing blocking will not happen and distance protection can
trip in this duration if required conditions fulfill.
Time starts from the startup of power swing blocking and after
"PowerSwingUnblkTime", the distance protection is unblocked and the
swing blocking is off.
System power swings are normally three-phase symmetrical processes.
Therefore, in general, a certain degree of measured value symmetry may
be assumed. Accordingly, beside current sudden-change startup, zero
sequence current startup will be used to remove or prevent power swing
blocking. In addition fault detection during a power swing removes power
swing blocking in the tripping logic.
SteadyLossStabilityStart
ImpedComponentStartup
≥1
ZeroSeqAuxStartup
& EnterSwingBlk
AbruptChgCurrStartup |150ms 0|
BIBlk SwingBlkDetect
(PSBSB)
Time<“PowerSwingUnblkTime”
Figure 57 Enter the swing blocking logic

This unblocking logic of the zones which have already blocked with power
swing blocking has been shown in following Figure. "Dist *
BlkByPowerSwing" is the logic switch, "Distance1(stage 2, 3, 4, 5,
extension 1 )ExtBlockByPS" indicates corresponding setting for blocking of
the zones in power swing condition.
AbruptChgCurrStartup |150ms 0|
&
≥1
EnterSwingBlk UnblkSwingBlk
&
&
SwingBlk
UnblkComponent
“DistZ*BlkByPowerSwing”
BI Blk SwingBlkDetect
(PSBSB)
Time>“PowerSwingUnblkTime”
Figure 58 Swing unblocking logic

The amount of kinetic energy gained by the generators during a fault is
directly proportional to fault duration and the positive sequence voltage at
the point of fault. Therefore, application of high-speed relaying systems
and high-speed circuit breakers is essential in locations where fast fault
clearing is important. So, the faults that occur during a power swing must
be detected and cleared with a high degree of selectivity and dependability.
For this purpose, IED considers different fault detector components during
power swing occurrence for symmetric and asymmetric faults. It also
86
provides six logic switches which can be set to block individually each
protection zones (“Dist x BlkByPowerSwing” where x, 1, 1Ext, 2, 3, 4,5,
indicates zone number).
In the duration of power swing, there is a special program module to detect
whether power swing has been finished or not. So, after continuous set
"IEDRstTime", the device will be reset when the sis impedances of zero
sequence auxiliary startup component, static failure check component and
the distance 3 do not trip.
EnterSwingBlk
&
UnblkSwingBlk PowerSwingBlkoutput
NoDistTrip
InDistZone3
Figure 59 Blocking output of power swing

For asymmetric faults and three-phase short circuit, swing unblocking
components are different.
1) Asymmetric faults detection component
Power swing is generally a three phase system and some degree of
symmetric behavior is considered in this condition. Therefore, zero and
negative sequence current can distinguish fault from power swing. The
criterion is described as following:
|𝑰𝑰𝟎𝟎 | > 𝒎𝒎𝒎𝒎 × |𝑰𝑰𝟏𝟏 |or|𝑰𝑰𝟐𝟐 | > 𝒎𝒎𝒎𝒎 × |𝑰𝑰𝟏𝟏 |
Factors 𝒎𝒎𝒎𝒎 and 𝒎𝒎𝒎𝒎 ensure that power swing can be reliability
differentiated from internal asymmetric faults. When only power swing
occurs in the network, zero and negative sequences will be close to zero
and it is not possible for the above equations to be fulfilled. When both
power swing and external asymmetric fault occur, the zero and negative
sequences, which will be seen by IED, are not so considerable to satisfy
above equations. But in the case of power swing and internal asymmetric
fault happening at the same time, zero and negative sequence of the
measured current will be large enough to detect the fault in the power
swing durations.
Therefore, maloperation of the protection IED will be prevented by
checking above criteria.
2) Unblocking component of three-phase fault
As mentioned, the amount of kinetic energy in the generator rotors is
proportional to duration of faults which may be dangerous for system
stability, particularly in three phase faults. Therefore, a three phase fault in
power swing duration should be cleared as soon as possible. IED
guarantees fast tripping of the three phase faults in power swing duration
by considering following states.
Impedance and resistance trajectory in the power swing
When swing occurs, measuring resistance and impedance at the
protection location can vary over time and the change rate is affected by
the system inertia and impedance of different system. In addition, the
87
change rate is also determined by the swing period and power angle δ.
The typical trajectories of the power system swing measuring impedance
are shown as follow. Rf is the component of the normal load resistance
and Tz is the system swing period. In the system swing, whether the
trajectory of measuring resistance in R-X plane is the straight line or the
arc is determined by the amount of the equivalent electromotive force at
the two sides of the power supply.
(a) Resistance (Rm) trajectory in normal and power swing condition

(b) Impedance trajectory on R-X plane in power swing condition
Figure 60 Trajectory of the measuring impedance during power swing
Resistance trajectory in three phase faults
When a three phase fault occurs on the protected line, resistance
component of measuring impedance maybe changes due to short circuit
arc. Analysis shows that arc resistance rating in three phase fault is far
less than that of resistance changing corresponding to the possibly largest
swing period. Following Figure illustrates measured resistance trajectory in
normal and three phase fault conditions. In this figure RK indicates
resistance in three phase short circuit. Unlike power swing conditions,
resistance variation after three phase fault is negligible.
Figure 61 Measuring resistance trajectory in normal and three phase faults

Therefore, power system is determined to be in power swing condition if its
88
measuring resistance is continuously changing in a monotony manner.

Conversely, three phase short circuit will be determined if resistance
variations seem to be a small constant.
When the varying of measured resistance exceeds one threshold, then it
can be considered that the system is in swing condition, consider the
condition of minimal resistance varying, the angle difference between the
two generators is 180° (equivalent to two-power-source systems) and
power system has maximum power swing period Tzmax. This condition
has been shown in following figure.
Figure 62 In the condition of δ=180°and Tzmaxmeasure the resistance trajectory

Therefore, for a specific time T, a minimum value of the resistance change
ΔRmin shall be calculated (180°, Tzmax, T). In this way, in any swing
period and any time:
ΔR≥ΔRmin(180°, Tzmax, T)
In consideration of calculation error and margin, the formula above will
change into:
ΔR≥K×ΔRmin(180°, Tzmax, T)
Where K<1.
Through the analysis above, methods of distinguishing short circuit and
swing can be acquired:
1) Within time T, if condition ΔR<K× ΔRmin (180°, Tzmax, T) is met, then
system is determined as short circuit.
2) Within time T, if condition ΔR≥K× ΔRmin (180°, Tzmax, T) is met, then
system is determined as swing.
Fault detection using impedance jumping
In conditions when three phase fault suddenly occurs on the protected line
outside the power swing center point or the generator difference angle (δ)
is not approximately 180°, the magnitude and angle of measured
impedance will jump and exceed rated changes. Based on this behavior,
distance component can be unblocked quickly when three-phase fault
happen with above conditions of not serious swing or after 150ms of
protection activation.
89
PhSel：Phase ABC
&
|I0|>m1|I1| or I2>m2|I1|
≥1 SwingBlk
UnblkComponent
PhSel: Phase ABC
&
ΔR<K×ΔRmin(180°,Tzmax,T)
Measure impedance R－X
plane trajectory ≥1
Abrupt changing of impedance

size and angle
Figure 63 Unblocking component of power swing
3.1.8 Phase-to-earth fault determination

For phase-to-earth fault logic, zero sequence current or zero sequence
voltage should also be considered. For solid earthed system, only if the
measured zero sequence current is 𝟑𝟑𝟑𝟑𝟎𝟎 no less than the setting
“PEDist3U0” could phase-to-earth fault be determined; For isolated neutral
system, only if the measured zero sequence current is 𝟑𝟑𝟑𝟑𝟎𝟎 no less than the
setting “PEDist3U0”, and the measured zero sequence voltage is 𝟑𝟑𝟑𝟑𝟎𝟎 no
less than the setting “PEDist3U0”, could phase-to-earth fault be
determined.
3.1.9 Logic of series compensation capacity
At present, logic of series compensation capacitor is only suitable for the
polygon characteristics of distance protection, not for the MHO
characteristics of distance protection.
As shown in the figure as follow, if the line is set with series compensation
capacity or the adjacent line is set with series compensation capacity,
directions shall be determined via memory voltage. In addition, distance
zone 1 and distance extension zone 1 shall be handled to prevent
protection from overreaching.
Zl I1
C F1
I2
(a) c1 c2
Zl I1
C c3
F2
F3
I2
(b)
Zl I1
C F1
(c)
C Zl I1
F1
(d)
90
xc
MOV
P
K
(e)
P: protection gap; MOV: metallic oxide voltage- sensitive valve block; K: by- pass switch (e)
Figure 64 Schematic diagram of impedance Z1

As shown in the Figure (a) above, if faults happen at F1 point after
capacitance, protect the measuring impedance 𝒁𝒁𝒎𝒎 = 𝒁𝒁𝒍𝒍 − 𝒋𝒋𝑿𝑿𝑪𝑪 (𝟏𝟏 + 𝑰𝑰𝟐𝟐 /𝑰𝑰𝟏𝟏 )
(equation deducing process omitted). From the formula, if the impedance
Z1 is adjusted as 𝒌𝒌𝒁𝒁𝒍𝒍 (k= 0.8~0.85), then faults points shown in the figure
above, due to the augmentation outside the zone, overreaching may
happen. Especially when the short circuit current is relatively low, when
MOV of metal oxide pressure sensitive valve piece does not move or gap
does not break down, overreaching may happen, shown in Figure 64
Figure 60 (e).
In the line with series compensation capacity, for transient component
produced in the MOV circuit of series compensation capacity during faults
and electrical distance shortening during faults, if no special treatment to
the protection is handled, overreaching of distance zone 1 may happen.
The protection, according to the features of series compensation capacity
models, utilizes setting value of "positive- sequence MOV breakdown
voltage" and the measuring current to automatically adjust the scope of
distance zone 1. To this end, setting value adjustment in Z1 is the same
with that in the conventional lines. As per the line impedance multiplies the
confidence coefficient (excluding the capacitance) 𝒌𝒌𝒁𝒁𝒍𝒍 , k can take
80%~85%.
If faults happen at the outlet of the capacitance and the capacitance is not
broken down shown in Figure 64 (d), distance zone 1 may not be operated.
To this end, impedance in the fourth quadrant shall be adopted for the
scope of distance protection.
Impedance direction is of memory calculation direction. It is shown in the
theoretical analysis that if the line has series compensation capacity,
adoption of memory calculation direction is correct.
3.1.10 Logic diagram
3.1.10.1 Distance protection tripping logic
As mentioned above, when the faults happen, one or multiple startup
components, including sudden- change start-up components, zero
sequence current start-up components and low-voltage start-up
components will be operated when the faults are detected. 6 measured
impedance (A, B, C, A-B, B-C and C-A) will be calculated simultaneously,
and the phase selector selects the fault phase. Compare the impedance of
the selected fault phase with the setting value to detect whether faults exist
in the zone.
91
By checking and fulfilling the fault detection criteria, IED distance

protection will trip according to the following logics for different faults and
zones:
1) No power swing
One of the main criteria in tripping logic of different zones is that IED
doesn’t detect power swing. Power swing blocking component can be
enabled or disabled by setting different logic switches ("Dist n
BlkByPowerSwing", n is 1~5). In IED, power swing will be detected by
steady state losing stability component startup (for detail information refers
under heading “Power swing blocking/ unblocking”).
2) Z1 fault
Logic of distance zone 1 fault check is shown in the figure as follow.
Measure impedance
in distance Z1
Forward direction & DistZ1Startup
≥1
“DistZ1BlkBy
PowerSwing” &
UnblkedDistZ1
“DistZ1On”
&
DistProtFcnOn
DistProtBI Blk (BLK_Dis)
DistZ1BI Blk (BLK_Zone1)
Figure 65 Distance zone 1 fault check logic

A fault is considered in distance zone 1 if the calculated impedance lies
within distance zone 1 characteristic zone and direction checking criteria
confirms that the fault is forward direction. In addition, power swing
unblocking should be released. As mentioned before, power swing
blocking for distance zone 1 can be selected individually by logic switch
“DistZ1BlkByPowerSwing”. If the “DistZ1BlkByPowerSwing” is set to “0”,
power swing blocking is disabled. If the setting “Z1_PS blocking” is set to
“1”, power swing blocking will be enabled.
3) Z2 fault
Measure impedance
in distance Z2
Non-reverse direction & DistZ2Startup
≥1
“DistZ2BlkByPowerSwing”
&
UnblkedDistZ2
“DistZ2On”
&
DistProtFcnOn
92
Figure 66 Z2 fault check logic

Logic of Z2 fault check is shown in the figure below. A fault is considered in
Z2 if the calculated impedance lies within distance zone 2 characteristic
and direction checking criteria confirms that the fault is not reverse. In
addition, power swing unblocking should be released. As mentioned above,
power swing blocking for Z2 can be selected individually by logic switch
“DistZ2BlkByPowerSwing”. If “DistZ2BlkByPowerSwing” is set to “0”,
power swing blocking is disabled. If “DistZ2BlkByPowerSwing” is set to “1”,
power swing blocking will be enabled.
4) Z3 fault
Asymmetric fault
Measure impedance
in distance Z3 &
≥1 DistZ3Startup
Non-reverse direction
≥1
&
UnblkedDistZ3
“DistZ3RvsDir”
&
Asymmetric fault
Measure impedance
in distance Z3
Non-forward direction
≥1
&
UnblkedDistZ3
symmetric fault
Measure impedance
in distance Z3 &
≥1
&
UnblkedDistZ3
“DistZ3On” &
DistProtFcnOn
Figure 67 Z3 fault check logic

Z3 fault check logics are shown in the figure above. Logic switch can be in
the forward direction or the reverse direction. If "non-reverse direction" is
considered as the trip criterion, the logic switch is of the forward direction;
if "non-reverse direction" is considered as the trip criterion, the logic switch
if of reverse direction. Generally, Z3 is used in the "non-reserve direction"
93
zone. The main check criterion is to measure if the measured impedance

is in the scope of Z3. In addition, symmetry fault and asymmetry fault
judgment has different logics. For asymmetry fault, the direction is
determined as non-reverse direction; for symmetry fault, direction criterion
shall not be considered. Z3 swing blocking components can be activated
by setting the logic switch "DistZ3BlkByPowerSwing". If
“DistZ3BlkByPowerSwing” is set to “0”, power swing blocking is disabled. If
“DistZ3BlkByPowerSwing” is set to “1”, power swing blocking will be
enabled.
5) Distance stage 4 and 5 failure
Logic of Z4 and Z5 fault check is shown in the figure as follow. Same with
Z3, vector quantity of the measured impedance is the main logic criterion.
As the logic switches can be in the forward direction or reverse direction,
direction judgment is different from that in Z2. If the "non-reverse direction"
is considered as the trip criterion, the logic switches are in forward
direction; if the "non-forward direction" is considered as the trip criterion,
the logic switches are in reverse direction. Z4 swing blocking components
can be activated by setting the logic switch "DistZ4BlkByPowerSwing". Z5
swing blocking components can be activated by setting the logic switch
"DistZ5BlkByPowerSwing".
Measure impedance
in distance Z4 &
Non-reverse direction ≥1 DistZ4Startup
≥1
“DistZ4BlcByPowerSwing”
&
UnblkedDistZ4
“DistZ4On” &
DistProtFcnOn
“DistZ4ProtRvsDir”
Measure impedance
&
in distance Z4
≥1
“DistZ4BlcByPowerSwing”
&
UnblkedDistZ4
94
Measurement impedance felt in &

to distance zone 5 ≥1
Startup of distance 5
Non-reverse direction
≥1
&
Distance zone 5
is unblocked
&
“DistZ5On”
Enable the distance
protection function
Distance protection binary
input blocking
Distance zone 5
binary input blocking
“DistZ5RvsDir”
&
Measurement impedance
felt in to distance zone 5
≥1
&
Distance zone 5 is unblocked
Figure 68 Logics of Z4 and Z5 faults check tripping logic

6) Distance extension zone 1 faults
Logic of distance extension zone 1 fault check logic is shown in the figure
as follow.
Measure impedance
in distance Z1
& DistExtZ1Startup
Forward direction
≥1
“DistExtZ1BlkByPowerSwing”
&
UnblkedDistExtZ1
“DistExtZ1On”
DistProtFcnOn &

DistExtZ1BI Blk
(BLK_Zone1Ext)
DisablePilotProt
&
ARFullCharge
NoARTrip
Figure 69 Distance extension zone 1 fault check logic

3.1.10.2 Trip logic
Distance protection tripping will be blocked in the case of VT failure (for
more detail, refer to under heading “VT failure”). In addition in the case of
switch-onto-fault condition, the delay timers of distance zone 1, 2, 3, 4and
5 will be bypassed and short circuit will be immediately removed.
Auto-reclosing can be activated by the logic switch "PPFaultInitAR" and
"3PhFaultInitAR" under three-phase, phase-to-phase faults.
Notes: "PPFaultInitAR" needs to cooperate with "3PhFaultInitAR".
95
initiate auto-reclosing, when phase-to-phase or three-phase fault occurs.

If both “PPFaultInitAR” and “3PhFaultInitAR” are set to 1, IED can initiate
auto-reclosing, when phase-to-phase or three-phase fault occurs.
If logic switch “PPFaultInitAR” is set to 1, and “3PhFaultInitAR” is set to 0,
IED can initiate auto-reclosing, when phase-to-phase occurs.
If logic switch “PPFaultInitAR” is set to 0, and “3PhFaultInitAR” is set to 1,
IED cannot initiate auto-reclosing, when phase-to-phase or three-phase
fault occurs.
Device provides logic switch "DistZ2InitAR"," DistZ3InitAR","DistZ4InitAR"
and "DistZ5InitAR" to set whether Z2, Z3, Z4 and Z5 can initiate the
auto-reclosing. Special attention: when Z3, Z4 and Z5 sections are put into
reverse action area, only permanent tripping fault is considered in Z3 to Z5,
without the function of initiating the auto-reclosure.
Distance speedup stage after auto-reclosing can select whether it will be
block by inrush. When the "AccelZBlkByHarm" is set to "1" and the
measuring current is greater than " OCHarmUnblkCurr", accelerate the
input Z2 and Z3 and unblock the inrush current. Acceleration in Z2 and Z3
is the instantaneous tripping.
When the logic switch "SOTFFaultChk2ndH" is set to "1", SOTF distance
function will be blocked by inrush. As measurement current is greater than
" OCHarmUnblkCurr", inrush current will be unblocked. If measurement
impedance felt into distance zone 1, 2, 3, 4 or 5, and the maximum phase
current is greater than "DistSOTFCurrSet", switch-on-to distance will trip
instantaneously.
Manual closing function enable/disable through the logic switch
"DistZ3SOTFOn", "DistZ4SOTFOn" and "DistZ5SOTFOn".
96
T1
DistZ1Startup
&
DistZ1Trip
T1Ext
DistExtZ1Startup &
DistZ1ExtTrip
& DistZ2Trip
T2
DistZ2Startup
VTFailBlk
& DistZ3Trip
T3
DistZ3Startup
& DistZ4Trip
T4
DistZ4Startup
T5
DistZ5Startup & DistZ5Trip
& DistZ2AccelTrip
“DistZ2AccelOn”
&
DistZ3AccelTrip
“DistZ3AccelOn”
ARFault
T1：“PEZ1Time”or“PPZ1Time”
T1Ext：“PEZ1ExtTime”or“PPZ1ExtTime”
Figure 70 Distance protection tripping logic

Logic diagram of distance manual close is shown as follow:
SOTF: Switch-onto-fault
permission
max(Ia,Ib,Ic)>“DistSOTFCurrSet”
DistZ1Startup ≥1
DistZ2Startup
& DistSOTFAccelTrip
DistZ3Startup
&
“DistZ3SOTFOn”
DistZ4Startup
&
“DistZ4SOTFOn”
DistZ4Startup
&
“DistZ5SOTFOn”
DIcom.V3P_MCB
Figure 71 Distance manual close trip logic

The below figure is distance protection trip logic diagram, and part in the
dotted frame is only the logic of configuration auto-reclosing trip protection.
Take phase A as an example for single phase fault and take phase AB as
an example for phase-to-phase fault.
97
PhSel: Phase A
≥1 &
“1PhARModeOn”
“1&3PhARModeOn”
DistZ1Trip
≥1
DistZ1ExtTrip
& &
DistZ2Trip
“DistZ2InitAR” &
DistZ3Trip Trip A
&
“DistZ3InitAR”
“DistZ3RvsDir”=0
DistZ4Trip &
“DistZ4InitAR”
DistZ5Trip &
“DistZ5InitAR”
Input: Enforced3PhTrip(AR Lockout)

≥1
“3PhTripMode”
Output:Enforced3PhTRip &
(AR Lockout)
≥1
& ≥1
Trip ABC
&
PhSel: Phase AB
“PPFaultInitAR” ≥1
&
&
PhSel: Phase ABC ≥1
& Trip3Ph/BlkAR
DistSOTFAccelTrip
DistZ2AccelTrip
DistZ3AccelTrip
≥1
DistZ1DevelopmentTrip
DistZ2DevelopmentTrip
“DistZ2InitAR” &
DistZ2Trip
&
DistZ3Trip ≥1
≥1
“DistZ3InitAR”
&
&
DistZ4Trip
≥1
“DistZ4InitAR”
&
&
DistZ5Trip
≥1
“DistZ5InitAR”
&
Figure 72 Distance protection tripping logic
98

Configurable nodes in IO Matrix
Type Description
configuration
Blocking_DI.BLK_Dis Distance protection binary input blocking
Blocking_DI.BLK_Zone1 Distance zone 1 binary input blocking
Input Blocking_DI.BLK_Zone4 Distance zone 4 binary input blocking
Blocking_DI.BLK_Zone1Ext Distance zone 1 binary input blocking

Swing blocking identification binary input
Blocking_DI.PSBSB
blocking
Blocking_DI.BLK_Seriescap Series compensation binary input blocking
Tripcom.Relay_StartUp IED startup
Tripcom.Relay_Trip IED trip
Tripcom.Relay_Trip_A TripA
Tripcom.Relay_Trip_B TripB
Tripcom.Relay_Trip_C TripC
Tripcom.Trip_3ph TripABC
Tripcom.Relay_Block_AR Trip three phases and block auto-reclosing
Tripcom.Zone1_Trip Trip of distance zone 1
Output Tripcom.Zone4_Trip Trip of distance zone 4
Tripcom.Zone1ExtTrip Extension zone 1 impedance trip
Tripcom.DIST_PSB_Trip Distance trip in power swing
Tripcom.DIST_PSB_Alarm Blocking output of power swing
ZONEStartup.DistanceZ1Startup Startup of distance zone 1
ZONEStartup.PEDistanceZ2Startup Startup of Phase-to-earth distance zone 2
ZONEStartup.PPDistanceZ2Startup Phase-to-phase distance zone 2 startup
ZONEStartup.PEDistanceZ3Startup Startup of Phase-to-earth distance zone 3
ZONEStartup.PPDistanceZ3Startup Phase-to-phase distance zone 3 startup
99

Type Description
configuration
3.3 Setting list

Table 27 Distance setting
Default
Range
(In:5A/1A)
(In:5A/1A)
Compensation
coefficient of
distance zone
1 zero
1. DistZ1ZeroSeqXCompCoef -0.33～10 8 0.001 sequence
reactance, for
zone 1 and
extension zone
1
Compensation
coefficient of
distance zone
1 zero
2. DistZ1ZeroSeqRCompCoef -0.33～10 8 0.001 sequence
resistance, for
zone 1 and
extension zone
1
Compensation
coefficient of
OtherZoneZeroSeqXComp
3. -0.33～10 8 0.001 other zones
Coef
zero sequence
reactance
Compensation
coefficient of
OtherZoneZeroSeqRComp
4. -0.33～10 8 0.001 other zones
Coef
zero sequence
resistance
Zero sequence
AdjacLineZeroSeqCompCo compensation
5. -0.33～10 0 0.001
ef factor in the
adjacent line
Positive
sequence
6. WholeLinePositiveSeqX 0.05/ In~600/In 120 0.01 Ω
reactance in
the whole line
Positive
sequence
7. WholeLinePositiveSeqR 0.05/ In~600/In 120 0.01 Ω
resistance in
the whole line
8. LineLengthSet 0.1～999 999 0.01 km Line length
Setting of
9. SteadyLossStabilityCurrSet 0.1In~20In 20 0.01 A static instability
current
Current setting
10. DistSOTFCurrSet 0.08In~2In 1 0.01 A
of distance
100
Default
Range
(In:5A/1A)
(In:5A/1A)
switch-on-to-fa
ult
Threshold of
earth distance
11. PEDist3I0 0.05In~2In 0.1 0.01 A
zero sequence
current
Threshold of
zero sequence
12. PEDist3U0 0.5～60 1 0.01 V voltage of
phase-to-earth
distance
For
single-phase
fault, adjusted
downward
inclination
13. DistZ1PEInclinedAngle 0.00～45.00 7 0.01 °
angle of
distance zone
1 and
extension zone
1
For
phase-phase
fault, adjusted
downward
inclination
14. DistZ1PPInclinedAngle 0.00～45.00 7 0.01 °
angle of
distance zone
1 and
extension zone
1
For
single-phase
fault, adjusted
downward
15. OtherZonePEInclinedAngle 0.00～45.00 7 0.01 °
inclination
angle of
distance zone
2,3,4 and 5
For
phase-phase
fault, adjusted
downward
16. OtherZonePPInclinedAngle 0.00～45.00 7 0.01 °
inclination
angle of
distance zone
2,3,4 and 5
Adjusted
17. ResistanceLineAngle 45.00～90.00 60 0.01 ° resistance wire
angle
Adjustable
angle of the
18. 2ndQuadrantAngle 0.00～45.00 14 0.01 °
second
quadrant
101
Default
Range
(In:5A/1A)
(In:5A/1A)
Adjustable
angle of the
19. 4thQuadrantAngle 0.00～15.00 14 0.01 °
fourth
quadrant
Load
encroachment
PELoadEncroachmentAngl
20. 0.00~60.00 0 0.01 ° angle of
e
phase-to-earth
distance
Load
encroachment
21. PEDistLoadEncroachR 0.1/In~600.0/In 0.1 0.01 Ω resistance of
phase-to-earth
distance
Phase-to-phas
PPLoadEncroachmentAngl e distance load
22. 0.00~60.00 0 0.01 °
e encroachment
angle
Phase-to-phas
e distance load
23. PPDistLoadEncroachR 0.1/In~600.0/In 0.1 0.01 Ω
encroachment
resistance
Swing
24. PowerSwingUnblkTime 0.5～3600.0 3600 0.01 s unblocking
time
25. ResistanceSetOfPEZ1 0.05/ In~600/In 0.05 0.01 Ω The setting of
polygonal
26. ReactanceSetOfPEZ1 0.05/ In~600/In 0.05 0.01 Ω characteristics
Time of
27. PEZ1Time 0～60 10 0.01 s phase-to-earth
zone 1
28. ResistanceSetOfPPZ1 0.05/ In~600/In 0.05 0.01 Ω The setting of
polygonal
29. ReactanceSetOfPPZ1 0.05/ In~600/In 0.05 0.01 Ω characteristics
Time of
30. PPZ1Time 0～60 10 0.01 s phase-to-phas
e zone 1
31. PEZ1ShiftAngle 0~30 0 0.01 °
32. MHOImpedSetOfPEZ1 0.05/In~600/In 0.05 0.01 Ω The setting of

MHO
33. PPZ1ShiftAngle 0~30 0 0.01 ° characteristics
34. MHOImpedSetOfPPZ1 0.05/In~600/In 0.05 0.01 Ω

polygonal
Time of
zone 2
The setting of
38. ResistanceSetOfPPZ2 0.05/ In~600/In 0.05 0.01 Ω
polygonal
102
Default
Range
(In:5A/1A)
(In:5A/1A)
characteristics
39. ReactanceSetOfPPZ2 0.05/ In~600/In 0.05 0.01 Ω
Time of
e zone 2

MHO

polygonal
Time of
zone 3
polygonal
Time of
e zone 3

MHO

polygonal
Time of
zone 4
polygonal
Time of
e zone 4
61. PEZ4ShiftAngle 0~30 0 0.01 ° The setting of
MHO
62. MHOImpedSetOfPEZ4 0.05/In~600/In 0.05 0.01 Ω characteristics
103
Default
Range
(In:5A/1A)
(In:5A/1A)
63. PPZ4ShiftAngle 0~30 0 0.01 °

polygonal
Time of
zone 5
polygonal
Time of
e zone 5

MHO
75. ResistanceSetOfPEExtZ1 0.05/ In~600/In 0.05 0.01 Ω The setting of

polygonal
76. ReactanceSetOfPEExtZ1 0.05/ In~600/In 0.05 0.01 Ω characteristics
Time of
phase-to-earth
77. PEExtZ1Time 0～60 10 0.01 s
extension zone
1
78. ResistanceSetOfPPExtZ1 0.05/ In~600/In 0.05 0.01 Ω The setting of
polygonal
79. ReactanceSetOfPPExtZ1 0.05/ In~600/In 0.05 0.01 Ω characteristics
Time of
phase-to-phas
80. PPExtZ1Time 0～60 10 0.01 s
e extension
zone 1
81. PEExtZ1ShiftAngle 0~30 0 0.01 °
82. MHOImpedSetOfPEExtZ1 0.05/In~600/In 0.05 0.01 Ω The setting of

MHO
83. PPExtZ1ShiftAngle 0~30 0 0.01 ° characteristics
84. MHOImpedSetOfPPExtZ1 0.05/In~600/In 0.05 0.01 Ω

Series
85. FwdMOVBreakdownVoltSet 0～200 80 0.01 V
compensation
Series
86. SeriesCompXcSet (0～200)／In 0 0.01 Ω
compensation
104
Default
Range
(In:5A/1A)
(In:5A/1A)
87. OCHarmUnblkCurr 0.05In~40In 40 0.01 A
Common
setting
88. OC2ndHI2/I1Ratio 0.07～0.50 0.07 0.01
Table 28 Distance protection logic switch

Default
No. Logic switch description Setting Remark
value
1. DistZ1On 1/0 0 1-Enabled; 0-Disabled;
1-Enable MHO characteristic of
phase-to-earth zone 1; 0-
2. PEZ1MhoCharac 1/0 0
Enable polygon characteristic of
phase-to-earth zone 1
phase-to-phase zone 1; 0-
3. PPZ1MhoCharac 1/0 0
phase-to-phase zone 1
4. DistZ1BlkByPowerSwing 1/0 0 1-Enabled; 0-Disabled;

9. DistZ2AccelOn 1/0 0 1-Enabled; 0-Disabled;
10. DistZ2InitAR 1/0 0 1-Enabled; 0-Disabled;

14. DistZ3RvsDir 1/0 0 1-Enabled; 0-Disabled;
16. DistZ3AccelOn 1/0 0 1-Enabled; 0-Disabled;
17. DistZ3SOTFOn 1/0 0 1-Enabled; 0-Disabled;
105
Default
value

23. DistZ4BlcByPowerSwing 1/0 0 1-Enabled; 0-Disabled;

33. DistExtZ1On 1/0 0 1-Enabled; 0-Disabled;

phase-to-earth extension zone
34. PEExtZ1MhoCharac 1/0 0 1; 0- Enable polygon
characteristic of phase-to-earth
extension zone 1
phase-to-phase extension zone
35. PPExtZ1MhoCharac 1/0 0 1; 0- Enable polygon
characteristic of phase-to-phase
extension zone 1
36. DistExtZ1BlkByPowerSwing 1/0 0 1-Enabled; 0-Disabled;
37. AccelZBlkByHarm 1/0 0 1-Enabled; 0-Disabled;
38. PEDistLoadEncroachment 1/0 0 1-Enabled; 0-Disabled;
106
Default
value
39. PPDistLoadEncroachment 1/0 0 1-Enabled; 0-Disabled;
40. FastDistZ1Prot 1/0 0 1-Enabled; 0-Disabled;
41. SeriesCompLS 1/0 0 1-Enabled; 0-Disabled;
42. VTAtSeriesCompLineSide 1/0 0 1-Enabled; 0-Disabled;

1-Enabled; 0-Disabled;
43. TestSmallRectangleZCharac 1/0 0
For polygonal characteristic.
1-Enabled; 0-Disabled;
44. TestZCharac 1/0 0
For polygonal characteristic.
45. SOTFFaultChk2ndH 1/0 0 1-Enabled; 0-Disabled;
0: non-direct grounding system;
46. EarthSystem 1/0 1
1: grounding system
Note: The two settings, “TestSmallRectangleZCharac” and

“TestZCharac”, should set to 1 only for polygonal characteristic testing.
These two binary settings are based on the “SystemSet” in the menu.
In calculating setting menu, you can also see small rectangular offset
characteristics related to the reactance and resistance values according to
the paragraphs from the zone of trip value calculated automatically.
3.3.1 Setting instruction
1) "DistZ1ZeroSeqXCompCoef": Reactance compensation factor, it
should be calculated based on the actual line parameters. Finally, the
setting should be less than or close to calculation value. (for distance
zone 1 and extension zone 1)
𝐗𝐗 𝟎𝟎 − 𝐗𝐗 𝟏𝟏
𝐊𝐊𝐦𝐦_𝐳𝐒𝐒𝐰𝐰𝐒𝐒𝟏𝟏 =
𝟑𝟑𝐗𝐗 𝟏𝟏
2) "DistZ1ZeroSeqRCompCoef": Resistance compensation factor, it
zone 1 and extension zone 1)
𝐑𝐑 𝟎𝟎 − 𝐑𝐑 𝟏𝟏
𝐊𝐊𝐒𝐒_𝐳𝐒𝐒𝐰𝐰𝐒𝐒𝟏𝟏 =
𝟑𝟑𝐑𝐑 𝟏𝟏
3) "OtherZoneZeroSeqXCompCoef": Reactance compensation factor, it
zone 1, 2, 3, 4 and 5)
𝐗𝐗 𝟎𝟎 − 𝐗𝐗 𝟏𝟏
𝐊𝐊 𝐦𝐦 =
𝟑𝟑𝐗𝐗 𝟏𝟏
4) "OtherZoneZeroSeqRCompCoef": Resistance compensation factor, it
zone 1, 2, 3, 4 and 5)
107
𝐑𝐑 𝟎𝟎 − 𝐑𝐑 𝟏𝟏
𝐊𝐊 𝐒𝐒 =
𝟑𝟑𝐑𝐑 𝟏𝟏
5) "AdjacLineZeroSeqCompCoef": it should be calculated based on the
actual line parameters. The setting should be less than or close to
calculation value. X0m is the zero sequence mutual reactance in the
parallel lines. X1 is the positive sequence reactance of the line where
IED is located.
𝐗𝐗 𝟎𝟎𝐦𝐦
𝐊𝐊 𝐦𝐦 =
𝟑𝟑𝐗𝐗 𝟏𝟏
6) "WholeLinePositiveSeqX" and "WholeLinePositiveSeqR": Line
positive reactance and resistance: It is set according to secondary
values of actual line parameters.
7) "StaticLossStabilityCurrSet": should be greater than maximum load
current.
8) Distance zone 1, distance zone 2, distance zone 3, distance zone 4
and distance zone 5 can be set by “DistZ1On”, “DistExtZ1On”
“DistZ2On”, “DistZ3On”, “DistZ4On”, and “DistZ5On”individually.
9) "DistZ3RvsDir": Z3 of the distance can be selected to trip for reverse
direction or forward direction.
12) Manual closing function enable/disable through the logic switch
"DistZ3SOTFOn", "DistZ4SOTFOn" and "DistZ5SOTFOn".
13) PowerSwing: the operation of distance zone 1, extension distance
zone 1,distance zone 2, distance zone 3, distance zone 4 and
distance zone 5 can be separately selected to be block or unblock
during power swing. When the bit is set to “1”, distance protection
zones are disabled by power swing blocking components. If the bit is
set to “0”, for any distance protection zone, the relay can send trip
command even in power swing condition.
14) “DistZ2AccelOn” and “DistZ3AccelOn”: Instant permanent trip function
of distance protection after auto-enclosure distance protection
speedup operating mode. Distance protection speedup operating
mode can be active in Z2 or Z3.
15) “AccelZBlkByHarm”: when it is set to “1”, magnetizing inrush current
will occur after inrush current, and the measuring current will be
greater than the “OCHarmUnblkCur”, then, the “Z2 Speedup” or “Z3
Speedup” can be active. When it is set to “0”, there is no inrush
blocking.
16) “DistSOTFCurrSet”: only the maximum phase current is greater than
the setting, the manual close protection can be active.
17) “PEDist3U0” and “PEDist3U0”: minimum zero sequence current and
minimum zero sequence voltage for phase-to-earth protection
operation.
18) “DistZ1PEInclinedAngle”: When single phase fault occurs, it can be
108
set based on actual condition according to downward inclination angle

of distance zone 1 and extension zone 1. It is recommended to set to
7°~12°.
19) “DistZ1PPInclinedAngle”: When phase to phase occurs, it can be set
based on actual condition according to downward inclination angle of
distance zone 1 and extension zone 1. It is recommended to set to
7°~12°.
20) “OtherZonePEInclinedAngle”: When single phase fault occurs, it can
be set based on actual condition according to downward inclination
angle of distance zone 2, 3, 4 and 5. It is recommended to set to
7°~12°.
21) “OtherZonePPInclinedAngle”: When phase to phase occurs, it can be
set based on actual condition according to downward inclination angle
of distance zone 2, 3, 4 and 5. It is recommended to set to 7°~12°.
22) "ResistanceLineAngle": it can be set based on actual condition
according to every zone. It is recommended to set to 63.4°.
23) "2ndQuadrantAngle": it can be set based on actual condition
according to every zone. It is recommended to set to 14°.
24) "4thQuadrantAngle": it can be set based on actual condition according
to every zone. It is recommended to set to 14°.
25) "PELoadEncroachmentAngle" and "PEDistLoadEncroachR": targeted
at the single phase fault
26) "PPLoadEncroachmentAngle" and "PPDistLoadEncroachR": targeted
at interphase fault.
27) Logic switch: Use "PEDistLoadEncroachment" and
phase- phase faults whether the distance load encroachment zones
are cleared.
28) The MHO or polygon characteristic of distance zone 1, zone 2, zone 3,
zone 4, zone 5 and extension zone 1 can be set independently by
setting the logic switch "PEZ1MhoCharac", "PPZ1MhoCharac",
"PEZ2MhoCharac", "PPZ2MhoCharac", "PEZ3MhoCharac",
"PPZ3MhoCharac", "PEZ4MhoCharac", "PPZ4MhoCharac",
"PEZ5MhoCharac", "PPZ5MhoCharac", "PEExtZ1MhoCharac" and
"PPExtZ1MhoCharac".
29) In order to expand the ability of measuring transition resistance, the
MHO characteristic of single phase distance zone 1, zone 2, zone 3,
zone 4, zone 5 and extension zone 1 can be shifted to the first
quadrant. The offset angle can be adjusted by setting
"PEZ1ShiftAngle", "PEZ2ShiftAngle", "PEZ3ShiftAngle",
"PEZ4ShiftAngle", "PEZ5ShiftAngle", "PEExtZ1ShiftAngle". It is
suggested to take 0°when the line length is ≥ 40km, 15°when it is ≥
10km and 30° when it is less than 10km.
30) In order to expand the ability of measuring transition resistance, the
MHO characteristic of phase to phase distance zone 1, zone 2, zone 3,
zone 4, zone 5 and extension zone 1 can be shifted to the first
quadrant. The offset angle can be adjusted by setting "
PPZ1ShiftAngle ", " PPZ2ShiftAngle ", " PPZ3ShiftAngle ", "
109
PPZ4ShiftAngle ", " PPZ5ShiftAngle ", " PPExtZ1ShiftAngle ". It is

suggested to take 0°when the line length is ≥ 10km, 15°when it is ≥
2km and 30° when it is less than 2km.
31) "MHOImpedSetOfPEZ1","MHOImpedSetOfPEZ2","MHOImpedSetOf
PEZ3","MHOImpedSetOfPEZ4","MHOImpedSetOfPEZ5","MHOImped
SetOfPEExtZ1","MHOImpedSetOfPPZ1","MHOImpedSetOfPPZ2","M
HOImpedSetOfPPZ3","MHOImpedSetOfPPZ4","MHOImpedSetOfPP
Z5","MHOImpedSetOfPPExtZ1" are MHO characteristics setting.
32) "PowerSwingUnblkTime": shown in 3.2.4.
33) Refer to 3.2.5 for description of relevant setting and control bit of
series capacitance compensation.
34) "FastDistZ1Prot": line length is shorter than 20 KM, please set this
position as "0".
3.3.2 Distance setting
The solid grounded 400kV overhead Line A-B of neutral point grounded
system is shown in following picture. It is assumed that the line does not
support pilot protection.
Figure 73 400kV overhead line (A-B) protected by distance protection

Line 1 (line AB):
S1(length): 127km
Current Transformer: 2000A/ 5A
Voltage transformer: 400kV/ 0.1kV
Frequency: 50Hz
Rated power of the line: 300MVA
Current of the line: 433A
Line 1 positive sequence reactance = 0.030Ω/km
Line 1 zero sequence resistance = 0.302Ω/km
Line1 zero sequence reactance=0.900Ω/km
Line2
S2(length)=139km
Line 2 zero sequence resistance = 0.311Ω/km
110
Line 2 zero sequence reactance = 0.898Ω/km

So, the impedance angle of Line 1 can be derived from the line parameters
as 85.1°:
Φ=arctan(X+/R+)
The resistance ratio RE/ RL and the reactance ratio XE/ XL should be
applied for zero sequence compensation calculations. They are calculated
separately, and do not correspond to the real and imaginary components
of ZE/ ZL.
𝑹𝑹𝑹𝑹 (𝑹𝑹𝟎𝟎 − 𝑹𝑹𝟏𝟏 )
= = 𝟑𝟑. 𝟎𝟎𝟎𝟎
𝑹𝑹𝑹𝑹 𝟑𝟑𝑹𝑹𝟏𝟏
𝑿𝑿𝑿𝑿 (𝑿𝑿𝟎𝟎 − 𝑿𝑿𝟏𝟏 )
= = 𝟎𝟎. 𝟓𝟓𝟓𝟓
𝑿𝑿𝑿𝑿 𝟑𝟑𝑿𝑿𝟏𝟏
x' = 0.04 Ω/ km in secondary side
Time delay:
T1-p-e or p-p time delay 0.0sec
T5 off
3.3.2.1 Impedance setting of distance zone 1 trip
The resistance setting of the individual zone has to cover the fault
resistance at the fault location. For the distance zone 1 setting only arc
faults will be considered. The length of the arc is greater than the spacing
between the conductors (p-p), because the arc is blown into a curve due to
thermal and magnetic forces. For estimation purposes it is assumed that
arc length is twice the conductor spacing. To obtain the largest 𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 , which
is required for the setting, the smallest value of fault current must be used.
To obtain the largest value of Rarc, which is required for the setting, the
smallest value of fault current must be used.
𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 × 𝟐𝟐 × 𝒍𝒍𝒂𝒂𝒉−𝒂𝒂𝒉 𝒔𝒔𝒂𝒂𝒂𝒂𝑰𝑰𝒊𝒊𝑺𝑺𝒈
𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 =
𝑰𝑰𝟑𝟑𝑷𝑷𝒉𝒎𝒎𝒊𝒊𝑺𝑺
According to the concept that arc approximately has the characteristic with
2500V/ m, the arc resistance will be calculated with the following equation:
Min 3ph short circuit current in the local end, Isc: 10kA
Short circuit capacity=SCC=√𝟑𝟑×VL×Isc: 6920MVA
Base capacityS_base: 1000MVA
Short circuit capacity per unit SCC_pu: 6.92pu
Z_source_pu≈1/Scc_pu: 0 . 1 4 p u
Z_source_ohm: 23.12Ω
L_source: 0.073598H
Positive sequence impedance (per unit length): 0.03024+j0.35276/k
111
Line Length: 127.0km

Positive sequence impedance, Z_Line: 3.840+j44.8Ω=0.024+j0.280pu
I3Phmin=1pu/[Z_source+Z_Line]: 2.350pu=3.396kA
On secondary I3Phmin: 8.489A
So, by considering the 3 m phase-to-phase spacing:
𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 × 𝟐𝟐 × 𝟑𝟑
𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 = = 𝟒𝟒. 𝟒𝟒𝟒𝟒𝟒𝟒Ω
𝟑𝟑. 𝟑𝟑𝟑𝟑𝟑𝟑 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏
By addition of a 20% safety margin and conversion to secondary
impedance the following minimum setting is calculated (division by 2 is
because of this fact that 𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 appears in p-p loop measurement while the
setting is done as phase impedance or positive sequence impedance):
𝟏𝟏. 𝟐𝟐 × 𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 × 𝑪𝑪𝑪𝑪𝑪𝑪/𝑷𝑷𝑷𝑷𝑷𝑷
𝑹𝑹(𝒁𝒁𝒁𝒁) =
𝟐𝟐
Therefore, R (Z1) min=0.265Ω in secondary side𝑹𝑹(𝒁𝒁𝒁𝒁)
This calculation value is the minimum value that considers the arc
resistance value that covers all faults. Depending on the X (Z1) reach
calculated, this setting may be increased to obtain the desired distance
zone 1 polygon symmetry.
1) For phase to phase fault
X1+=0.353Ω/km
CT ratio=2000/5A
CT ratio/PT ratio=0.100
PT ratio=400/0.1kV
Line length=127km
Xline1+=4.48Ω in secondary side
Rline+=0.384Ω in secondary side
Since there is no any pilot protection, to get fast tripping on the end of line,
phase-phase distance zone 1 setting will be set to 85% from 80% of all the
line.
X(Z1)=0.85×X+Line1-Secondary
Therefore, R (Z1) min=3.81Ω in secondary side 𝑿𝑿(𝒁𝒁𝒁𝒁) , that is
𝑿𝑿(𝒁𝒁𝒁𝒁)𝒔𝒔𝒔𝒔𝒔𝒔=3.81Ω in secondary side
2) For phase to earth fault
Considering some error in the parameter calculation of RE/ RL and XE/ XL,
the reactance reach is considered as 80% of line A-B.
𝐗𝐗𝐄𝐄(𝐙𝐙𝟏𝟏)=0.8×X+Line1-Secondary
Therefore, XE (Z1) min=3.58Ω in secondary side 𝑿𝑿𝑿𝑿(𝒁𝒁𝒁𝒁) ,
𝑿𝑿𝑿𝑿(𝒁𝒁𝟏𝟏)𝒔𝒔𝒔𝒔𝒔𝒔=3.58Ω in secondary side.
3) For phase to phase fault
Considering minimum setting of 𝑹𝑹(𝒁𝒁𝒁𝒁) calculated before, for overhead
line protection applications, the following rule of thumb may be used for the
𝑹𝑹(𝒁𝒁𝒁𝒁) setting to get the best symmetry on polygon characteristic:
112
𝟎𝟎. 𝟖𝟖 × 𝑿𝑿(𝒁𝒁𝒁𝒁) ≤ 𝑹𝑹(𝒁𝒁𝒁𝒁) ≤ 𝟐𝟐. 𝟓𝟓 × 𝑿𝑿(𝒁𝒁𝒁𝒁)

So, 𝟑𝟑. 𝟎𝟎𝟕𝟕 ≤ 𝑹𝑹(𝒁𝒁𝒁𝒁) ≤ 𝟗𝟗. 𝟓𝟓𝟓𝟓 in this case, setting for 𝑹𝑹(𝒁𝒁𝒁𝒁) is considered
as:
𝑹𝑹(𝒁𝒁𝒁𝒁)=3.10Ω in secondary side
4) For phase to earth fault
The phase to earth fault resistance reach is calculated along the same way
as p-p faults. For the earth fault however, not only the arc voltage but also
the tower footing resistance must be considered.
𝑰𝑰𝟐𝟐
𝑹𝑹𝑻𝑻𝑭 = �𝟏𝟏 + � × 𝐒𝐒𝐒𝐒𝐰𝐰𝐒𝐒𝐒𝐒 𝐎𝐎𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐰𝐰𝐎𝐎 𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐰𝐰𝐞𝐞𝐒𝐒
𝑰𝑰𝟏𝟏
It is assumed that each tower resistance equals to: 15Ω
Considering the parallel connection of multiple towers, Effective tower
resistance ≈2Ω
In the above equation,I2/ I1 is the ratio between earth fault currents at the
opposite end to the local one. Where no information is available on the
current ratio, a value of approx. 3 is assumed for a conservative approach.
Assume that I2/ I1=3
Therefore, 𝑹𝑹𝑻𝑻𝑭 =8Ω
For the calculation of 𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 using the formula introduced above, without
detail information about the tower configuration, p-to-tower spacing is
assumed to be 3m in the worst case (conservative solution).
Assume that p-tower spacing: 3m.
𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 × 𝟐𝟐 × 𝒍𝒍𝒂𝒂𝒉−𝑻𝑻𝑰𝑰𝒘𝒆𝒆𝒂𝒂 𝒔𝒔𝒂𝒂𝒂𝒂𝑰𝑰𝒊𝒊𝑺𝑺𝒈
𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 =
𝑰𝑰𝟏𝟏𝑷𝑷𝒉𝒎𝒎𝒊𝒊𝑺𝑺
Min 1ph short circuit current in the local end, Isc: 5kA. 5kA
S_base: 1000MVA
I_base: 1.445kA
Isc pu: 3.46pu
Zs=2Z+source+Z0source_pu≈1/(Isc pu/3): 0.87pu
Positive sequence impedance: 0.0302+j0.353Ω/km
Zero sequence impedance: 0.302+j0.900Ω/km
Line Length: 127.0km
Positive sequence impedance, Z1_Line: 3.840+j44.8Ω=0.024+j0.28pu
Zero sequence impedance, Z0_Line: 38.354+114.3Ω=0.240+j0.714pu
𝑰𝑰𝟏𝟏𝑷𝑷𝒉𝒎𝒎𝒊𝒊𝑺𝑺 =3×1pu/[Zs+2Z1_Line+Z0_Line]: 1.374pu=1.986kA
Therefore, I3ph-min=4.965Ω in secondary side
So, arc resistance will be: 𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 =7.55Ω
𝟏𝟏. 𝟐𝟐 × (𝑹𝑹𝒂𝒂𝒂𝒂𝑰𝑰 + 𝑹𝑹𝑻𝑻𝑭 ) × 𝑪𝑪𝑪𝑪𝑪𝑪/𝑷𝑷𝑷𝑷𝑷𝑷
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) =
𝑹𝑹
(𝟏𝟏 + 𝑬𝑬 )
𝑹𝑹𝑳𝑳
113
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁)=0.5Ω in secondary side

This calculated value corresponds to the smallest setting required to
obtain the desired resistance coverage. Depending on the X (Z1) reach
calculated above, this setting may be increased to obtain desired distance
zone 1 polygon symmetry.
𝑿𝑿𝑬𝑬
𝟏𝟏 +
𝑿𝑿𝑳𝑳
𝟎𝟎. 𝟖𝟖 × 𝑿𝑿(𝒁𝒁𝒁𝒁) ≤ 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) ≤ × 𝟐𝟐. 𝟓𝟓 × 𝑿𝑿(𝒁𝒁𝒁𝒁)
𝑹𝑹𝑬𝑬
𝟏𝟏 +
𝑹𝑹𝑳𝑳
Therefore, 𝟑𝟑. 𝟎𝟎𝟎𝟎 ≤ 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) ≤ 𝟑𝟑. 𝟔𝟔𝟔𝟔
at this point, in secondary side𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) = 𝟑𝟑. 𝟏𝟏𝟏𝟏Ω
Z1 trip mode forward direction
𝑹𝑹(𝒁𝒁𝒁𝒁) Resistance setting of phase-to-phase faults 3.10Ω
𝑿𝑿(𝒁𝒁𝒁𝒁) Reactance setting of phase-to-phase faults 3.81Ω
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁),Resistance setting of single phase faults 3.10Ω
𝑿𝑿𝑿𝑿(𝒁𝒁𝒁𝒁), Setting of reactance of single phase faults 3.58Ω
Tele protection scheme inactive
Power swing blocking zones All zones
3.3.2.2 Impedance setting of distance zone 2 and zone 3 trip
According to the grading requirement:
X ( Z 2) = 0.8 × ( X ( Line1) + 0.8 × X ( Line2 shortest ) ) ×

CTR
PTR
X+Line1=44.8Ω in primary side
X+Line2=48.928Ω
CT ratio=2000/5A
CT ratio/PT ratio=0.100
PT ratio=400/0.1kV
Therefore, R (Z1) min=6.72Ω in secondary side𝑿𝑿(𝒁𝒁𝒁𝒁), 𝑿𝑿(𝒁𝒁𝒁𝒁)𝒔𝒔𝒔𝒔𝒔𝒔=6.72Ω
in secondary side.
Resistance coverage for all arc faults up to the set reach must be applied.
To prevent surpass in distance trip and considering a certain margin of
safety, the minimum value of 𝑹𝑹(𝒁𝒁𝒁𝒁) is obtained based on setting of
𝑿𝑿(𝒁𝒁𝒁𝒁) and internal fault arc resistance value 𝑹𝑹(𝒁𝒁𝒁𝒁).
X ( Z 2)
=
R ( Z 2) Min × R ( Z1)
X ( Line1 sec ondary )
So, 𝑹𝑹(𝒁𝒁𝒁𝒁)Min=4.65Ω in secondary side
According to the above minimum value, the setting is considered as:
𝑹𝑹(𝒁𝒁𝒁𝒁)=4.70Ω in secondary side
It is similar to the setting of 𝑹𝑹(𝒁𝒁𝒁𝒁), the setting of 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) is based on
RE(Z1).𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁)
Similar to the 𝑹𝑹(𝒁𝒁𝒁𝒁) setting, the minimum required reach for 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁)
114
setting is based on the 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) setting and 𝑿𝑿(𝒁𝒁𝒁𝒁) setting, where

𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) covers all internal fault resistance and the 𝑿𝑿(𝒁𝒁𝒁𝒁) setting
determines the amount of surpassing. Or, 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) can also be obtained
from the following formula:
X ( Z 2)
=
RE ( Z 2) × 1.2 × RE ( Z1)
X ( Line1secondary )
So, 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁)Min=5.58Ω in secondary side
Here the maximum value of 𝑹𝑹(𝒁𝒁𝒁𝒁) and 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) min is selected:
It is obtained that𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) =5.58Ω in secondary side
In addition, the resistance reaches setting for Z2 and Z3 are set according
to the maximum load current and minimum load voltage. The values are
set somewhat (approx. 10 %) less than the minimum expected load
impedance.
Maximum transmission power=250MVA
Imax=401A at Vmin=0.9*Vn
Zload_Prim=(0.9×400kV)/(401×√𝟑𝟑)=518.334Ω
Zload_Sec=52Ω
Given 10% margin, the setting is:
Zload_Sec=47Ω
Assuming a minimum power factor of CosΦmin at full load condition = 0.85
Then, Rload_Sec =40Ω
The spread angle of the load trapezoid Φ load (Ø-E) and Φload (Ø-Ø)
must be greater (approx. 5°) than the maximum arising load angle
(corresponding to the minimum power factor cosΦ).
Φload=ArcCos(0.85)+5≈37°
Therefore, according to the protection zones characteristic and maximum
calculated load impedance and angle, we will have:
X (ohm)
30.1
26.6°
37° 63.4°
R (ohm)
Rload=40
15.1
Figure 74 Impedance characteristic diagram

Therefore the maximum setting of R-Z3 should be as: 40-15.1=24.91Ω
115
The calculated resistance for Z2 is far from the above maximum value.
Finally, the Z2 and Z3 setting should as follow:
Z2 operation mode forward
direction
𝑹𝑹(𝒁𝒁𝒁𝒁), Setting of resistance of p-p-faults 4.70Ω
𝑿𝑿(𝒁𝒁𝒁𝒁), Setting of reactance of p-p-faults 6.72Ω
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁),Resistance setting of single phase faults 5.58Ω
𝑿𝑿𝑿𝑿(𝒁𝒁𝒁𝒁)Resistance setting of single phase faults 6.72Ω
Since there is no information about line3, Z3 is set 1.5 times larger than Z2,
as follow:
Z3 trip mode forward direction
𝑹𝑹(𝒁𝒁𝒁𝒁), Setting of resistance of p-p-faults 7.05Ω
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁), Setting of resistance of single phase faults 8.37Ω
𝑿𝑿𝑿𝑿(𝒁𝒁𝒁𝒁)Resistance setting of single phase faults 10.05Ω
3.3.2.3 Distance zone 4 trip
Distance zone 4 is considered to protect 30% of the distance zone 1 in
reverse direction.
So,
𝑿𝑿(𝒁𝒁𝒁𝒁) = 𝟎𝟎. 𝟑𝟑 × 𝑿𝑿(𝒁𝒁𝒁𝒁)=1.14Ω in secondary side
𝑿𝑿𝑿𝑿(𝒁𝒁𝒁𝒁) = 𝟎𝟎. 𝟑𝟑 × 𝑿𝑿𝑿𝑿(𝒁𝒁𝒁𝒁)=1.08Ω in secondary side
𝑹𝑹(𝒁𝒁𝒁𝒁) = 𝟎𝟎. 𝟑𝟑 × 𝑹𝑹(𝒁𝒁𝒁𝒁)=0.93Ω in secondary side
Similar to the 𝑹𝑹(𝒁𝒁𝒁𝒁) setting, the upper and lower limits of 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) are
defined by minimum and polygonal symmetry. In this case, the setting of
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) is the same as 𝑹𝑹(𝒁𝒁𝒁𝒁).
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁) = 𝟎𝟎. 𝟑𝟑 × 𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁)=0.93Ω in secondary side
Z4 trip mode Reverse direction
𝑹𝑹(𝑍𝑍𝟒𝟒), Setting of resistance of p-p-faults 0.93Ω
𝑹𝑹𝑹𝑹(𝒁𝒁𝒁𝒁), Setting of resistance of single phase faults 0.93Ω
𝑿𝑿𝑿𝑿(𝒁𝒁𝒁𝒁), Setting of reactance of single phase faults 1.08Ω
3.3.2.4 Distance zone 4 trip
Exit
3.3.3 Load encroachment cleared area
Within heavy-duty long transmission line, load impedance may easily
invade into the distance protection trip area. In order to eliminate the
distance protection maloperation risk under heavy duty, a cleared load
zone shall be added into the large resistance range to avoid device fault
misjudgment caused by overload. In the following figure, polygonal is
taken as example.
116
Φ_Load
R_Load
Figure 75 Setting parameters

Table 29 Setting parameter
1/0 "PEDistLoadEncroachment"
1/0 "PPDistLoadEncroachment"
0-- 60 ° "PELoadEncroachmentAngle"
0.02--600Ω “PEDistLoadEncroachR”
0-- 60 ° "PPLoadEncroachmentAngle"
0.02-600Ω “PPDistLoadEncroachR”

Φ_Load: "PEDistLoadEncroachR", "PPDistLoadEncroachR";
Their settings are about 10% less than the minimum load impedance.
When the maximum load current and minimum operation voltage are
chosen, the minimum load impedance will be obtained.
As for single-phase trip, the load characteristic setting of earth fault phase
must take the load current of phase-to-earth loop into consideration. It is
significant for parallel line (there is strong coupling between the parallel
lines on the same tower). As for zero sequence mutual inductance, when
open one phase of the parallel line, almost load current will flow toward
“ZeroSeq” passage.
R setting of phase-to-earth loop (or load encroachment setting) must take
the earth current condition after one-phase trip between parallel lines into
consideration.
Calculation case 1:
100kv overhead line, 3-pase trip, the principle line parameters are as
follow:
Maximum transmission power: Pmax=100MVA
Maximum line current corresponding to the maximum transmission power:
Imax = 577.3A
117
Minimum operating voltage: Umin = 0.9 Un

CT Ratio: 500A/5A
VT Ratio: 100kV/0.1kV
Minimum load impedance:
RLprim=0.9×Umin/(√𝟑𝟑×Imax)=0.9×100kV/(√𝟑𝟑×577.3A)=90Ω
Correspond to secondary side impedance
RLsec=RLprim×CT ration/VT ratio= (90×500/5)/(100/0.1)=9Ω
In consideration of 10% margin:
"PPLoadEncroachmentR"=0.9×90 prim=0.9×9 sec=8.1Ω
"PEDistanceLoadEncroachR"=0.9×90 prim=0.9×9 sec=8.1Ω
Distribution angle of load trapezoidal characteristic:
Phase-to-earth load angle and phase-to-phase must be greater than
(about 5°) the maximum load angle (corresponding to minimum power
factor Cosϕ)
Minimum power factor (for example)
cosΦmin = 0.63
ϕmax=51°
The phase-to-phase load angle is set as:
"PPLoadEncroachmentAngle"=ϕmax+5°=56°.
Calculation case 2:
As for the application of parallel line (zero sequence cross coupling) and
single-phase trip:
The parameters of 500kv double tower overhead line (200km) are as
follow:
Maximum load and current of single-phase circuit breaker:
Pmax=1500MVA corresponding to Imax=1732A
Minimum operating voltage: Umin = 0.9 Un
CT 2500A/5A
VT 500kV/0.1kV
Setting is set as: RE/RL 1.54
Minimum load impedance value is:
RLprim=0.9×Un/(√𝟑𝟑×Imax)=0.9×500kV/(√𝟑𝟑×1732A)=150Ω
This value is applicable to p-p measurement, when one phase of the
parallel overhead line is opened, the setting of single phase-to-earth loop
must consider this condition. Under this condition, the load current of the
same phase of fault-free line shall increase correspondingly.
To determine the minimum load current of phase-to-earth loop, the load
current must be set at first.
The maximum load current shall be calculated according to the existing
ratio.
118
The ratio between single-phase ground and the maximum in-phase current
of parallel line is:
IEpole_open/Imax = 0.4
This ratio is dependent on the line length and source and line impedance.
If the value cannot be obtained through power system simulation, then the
value can be set to from 0.4 to 0.6, where, the long transmission line
(200km) is 0.4 and the short transmission line is 0.6 (25km).
So, the minimum p-e load impedance generated by primary side is:
RL prim_Ph-E=RLprim/(1+0.4(1+RE/RL))=74.4Ω
RL prim_P-E=RLprim/ (1+0.4 (1+RE/ RL) )=74.4Ω
RLsec=RLprim×CT ratio/VT ratio=15Ω
RL sec_Ph-E=RLprim_Ph-E×CT ratio/VT ratio=7.44Ω
In consideration of 10% margin:
"PPDistLoadEncroachR"=0.9×15sec=13.5Ω
"PEDistLoadEncroachR"=0.9×7.44 sec=6.69Ω
The parallel line distribution angle of load trapezoidal characteristic shall
be calculated based on the minimum power factor, with the same
treatment method.
3.3.4 Swing unblocking characteristic
Power swing blocking will not happen in 150ms after current
sudden-change startup, therefore, the distance protection will be enabled
in 150ms after sudden-change startup is on. Time starts from the startup of
power swing blocking and after "PowerSwingUnblkTime", the distance
protection is unblocked and the swing blocking is off. In 150ms after
current sudden-change startup or overcurrent startup, the protection
enters into swing blocking status to avoid maloperation during distance
protection swing process.
The fault characteristic of swing blocking is different from unsymmetrical
fault and symmetrical fault.
3.3.5 Description of relevant setting and control bit of series
capacitance compensation
The mainly installation methods of series capacitance compensation are
shown in the figure as follow.
xc1
5
L3
xc
1 2 3 4
L1 L2
Figure 76 Installation diagram of series compensation

Figure 1~5 refer to the installation locations of protection; XC and XC1
119
refer to the installed series capacitance compensation value.

1) As for installation without Line L3, there is only the setting of Line L1
and L2:
a) Protection 1: the setting of distance zone 1 in Protection 1 is set
based on ×ZL, if Line L1 is short transmission line and the line
impedance is less than series capacitive reactance compensation
XC, the “SeriesCompXcSet” have to be set based on {XC-ZL1}; if
the reactance of Line L1 is greater than the series capacitive
reactance compensation XC, "SeriesCompXcSet" is set to “0”;
“FwdMOVBreakdownVoltSet” is set based on the peak value of
secondary value of MOV breakdown voltage of series capacitive
reactance compensation XC, and the protection will adjust the
distance zone 1 setting automatically to avoid distance zone 1
overreaching. “SeriesCompLS” is set to “1” and the
“VTAtSeriesCompLineSide” is set to “0”;
b) Protection 2: As the capacitive reactance at back side will not be
compensated over the Line L2 impedance, the
“SeriesCompXcSet” is set to 0. There is not forward series
capacitance compensation, so the “FwdMOVBreakdownVoltSet”
is set to 0. “SeriesCompLS” is set to “1”. And
“VTAtSeriesCompLineSide” logic switch is set to “0”;
c) Protection 3: The “SeriesCompXcSet” is set based on the line
actual value. If it is line PT and the PT is at the series capacitance
compensation line side, “VTAtSeriesCompLineSide” is set to “1”
and “FwdMOVBreakdownVoltSet” is set to 0; as for any other
condition, “VTAtSeriesCompLineSide” is set to “0” and
“FwdMOVBreakdownVoltSet” is set based on actual value.
“SeriesCompLS” should be set to “1”.
d) Protection 4: “SeriesCompXcSet” is set to 0.
“FwdMOVBreakdownVoltSet” is set based on actual value.
“SeriesCompLS” should be set to “1”. And
“VTAtSeriesCompLineSide” logic switch is set to “0”.
2) As for the setting of installation with adjacent line (L3) :
a) Protection1: If Line L1 is short transmission line and the line
impedance is less than the series capacitive reactance
compensation of max{XC, XC1}, the “SeriesCompXcSet” shall be
set based on{max{XC, XC1}-ZL1}; if the line impedance is greater
than the series capacitive reactance compensation max{XC, XC1},
the “SeriesCompXcSet” shall be set to 0.
“FwdMOVBreakdownVoltSet” shall be set based on the maximum
value of the two series capacitance compensation breakdown
voltage. “SeriesCompLS” should be set to “1”. And
b) Protection 2: The setting principles of Protection 2 are the same
as those principles of Protection 2 without L3;
c) Protection 3: The setting principles of Protection 3 are the same
as those principles of Protection 2 without L3;
d) Protection 4: If {XC+XC1} is less than the impedance of Line L2
total length, the “SeriesCompXcSet” shall be set to 0. Otherwise,
the “SeriesCompXcSet” shall be set based on {XC+XC1}-ZL2.
120
“FwdMOVBreakdownVoltSet” shall be the sum of XC and XC1

breakdown voltage. “SeriesCompLS” should be set to “1”. And
e) Protection 5: similar to Protection 4.
3.4 Report list


Trip report:
1. IEDStartup IED startup
2. ImpedComponentStartup Startup of impedance component
3. ZeroSeqAuxStartup Auxiliary startup of zero sequence
4. SteadyLossStabilityStart Startup of steady loss stability
5. DistZ1Trip distance zone 1 trip
10. DistExtZ1Trip Extension zone1 impedance trip
Distance switch-onto-fault protection acceleration trip
11. DistSOTFAccelTrip
(SOTF)
12. PowerSwingBlkState Blocking output of power swing

13. DistZ2AccelTrip Z2 instantaneous trip when auto-reclosing is fault
14. DistZ3AccelTrip Z3 instantaneous trip when auto-reclosing is fault
Trip three phases and block auto-reclosing after
15. 3PhTripFailTrip3Ph/BlkAR
three-phase trip failure
16. Intertrip3Ph Intertrip three-phase

17. 3PhTripAfter1PhTripFail Three-phase trip after 1 phase trip failure time delay
Impedance zone 1 development failure trip. for
example, A phase to earth fault happened, and then
18. DistZ1DevelopmentTrip
B phase to earth fault followed, the latter is
considered as an development trip
When the logic switch of “ZDistanceZ2Init&Reclose”

is enabled, impedance zone 2 development failure
19. DistZ2DevelopmentTrip trip. for example, A phase to earth fault happened,
and then B phase to earth fault followed, the latter is
considered as an development trip
20. FaultLocation Fault locater

21. FaultLocationImped Impedance at fault point
121

22. PEZTrip Earth phase B fault trip report
23. PPZTrip Phase-to-phase fault trip report
24. PEZDistPhATrip Earth phase A fault trip report
25. PEZDistPhBTrip Earth phase B fault trip report
26. PEZDistPhCTrip Earth phase C fault trip report
Alarm report:
1. VTFailDistOff /
Operation report:
1. DistFcnOn /
2. DistFcnOff /
3. FcnPowerSwingOn /
4. FcnPowerSwingOff /

Table 31 Distance protection technical data
Set zones Five zones and one extension zone
Distance zone Polygonal and MHO characteristics

characteristics
Range of 0.01Ω～120Ω, when In=5A ≤±5.0%

resistance setting
0.05Ω～600Ω, when In=1A Conditions of the static accuracy
are:
Reactance 0.01Ω～120Ω, when In=5A Voltage range: 0.01Ur to 1.2Ur
setting range
0.05Ω～600Ω, when In=1A Current range: 0.12In to 20In
Distance zone 0.00~60.00s ≤±1% or +20ms,

delay
at 70% operating setting and
setting time>60ms
Trip time Typical trip value 22ms

at 70% setting of distance zone 1
Distance zone 1 ≤±5%,

transient
0.5< system impedance ratio <30
overreaching
Note: In: CT secondary rated current, 1A or 5A
122
Chapter 6 Pilot distance protection (85-21/21N)
Chapter 6 Pilot distance protection

(85-21/21N)
About this chapter

The Chapter describes the principle of pilot distance
protection, input & output signals, setting parameters, report
123
1 Introduction
Pilot distance protection is an important function in the IED to get fast
tripping of the short circuit in the area near to remote end.
1) It uses a carrier transceiver mechanism to achieve different pilot
protection configurations through a power carrier line (PLC).
2) It uses optical fiber channel to achieve different pilot protection
configurations through optical fiber.
Pilot distance protection is an important function in the IED to get fast tripping
of the short circuit in the area near to remote end. The function employs carrier
sending and receiving feature to implement different pilot protection
configuration.

Input and output signals of the distance protection function are shown as
follow:
Pilot Distance(Carrier mode)

1 1
BI_Carr_Recv_Dist Relay_StartUp
2 2
BI_Carr_Fail_Dist Relay_Trip
3 3
BI_DTT_Send Relay_Trip_A
4 4
BI_DTT_Recv Relay_Trip_B
5 5
BLK_PilotDis Relay_Trip_C
6 6
BI_Carr_Recv_DistA Trip_3ph
7 7
BI_Carr_Recv_DistB Relay_Block_AR
8 8
BI_Carr_Recv_DistC Carr_Send_Dist
9
Carr_Fail_Dist
10
Pilot_Dist_Trip
11
Weak_End_Infeed
12
BO_DTT_Send
13
BO_DTT_Recv
14
Carr_Send_DistA
15
Carr_Send_DistB
16
Carr_Send_DistC
17
SOTF_Trip
Figure 77 Input & output signal diagram of the pilot distance protection
function(Carrier mode)
The input and output signals of pilot distance protection function in optical
fiber mode are shown as follows:
124
Pilot Distance(Optical fiber mode)

1 1
BI_Tele_Trans1 Relay_StartUp
2 2
BI_Tele_Trans2 Relay_Trip
3 3
BI_Tele_Trans3 Relay_Trip_A
4 4
BI_Tele_Trans4 Relay_Trip_B
5 5
BI_Tele_Trans5 Relay_Trip_C
6 6
BI_Tele_Trans6 Trip_3ph
7 7
BI_Tele_Trans7 Relay_Block_AR
8 8
BI_Tele_Trans8 Pilot_Dist_Trip
9 9
BI_DTT SOTF_Trip
10 10
BI_Chan_A_Test BO_DTT
11 11
BI_Chan_B_Test BO_Tele_Trans1
12
BO_Tele_Trans2
13
BO_Tele_Trans3
14
BO_Tele_Trans4
15
BO_Tele_Trans5
16
BO_Tele_Trans6
17
BO_Tele_Trans7
18
BO_Tele_Trans8
19
Channel_A_Alarm
20
Channel_B_Alarm
21
22
Figure 78 Input & output signal diagram of the pilot distance protection function
right.

Input:
Carrier receives message: pilot

BI_Carr_Recv_Dist distance receiving message (Carrier
mode)
Pilot distance channel error (Carrier

BI_Carr_Fail_Dist
mode)
Sending message of direct transfer trip

BI_DTT_Send
(Carrier mode)
BI_Telepilot Receiving message of direct transfer
BI_DTT_Recv
trip (Carrier mode)
Phase A receiving message of pilot

distance (if the
BI_Carr_Recv_DistA
"ParallelLinePhSendMsg" is enabled,
the binary input exists) (Carrier mode)
Phase B receiving message of pilot

distance (if the
BI_Carr_Recv_DistB
125
Phase C receiving message of pilot

distance (if the
BI_Carr_Recv_DistC
Input:
BI_Tele_Trans1
Remote transmission command 1
binary input (Optical fiber mode)
BI_Tele_Trans2
BI_Tele_Trans3
BI_Tele_Trans4
BI_Tele_Trans5
DI_OpticalFiberChanl BI_Tele_Trans6
BI_Tele_Trans7
BI_Tele_Trans8
BI_DTT
Remote trip signal binary input
(Optical fiber mode)
BI_Chan_A_Test
Channel A maintain (Optical fiber
mode)
BI_Chan_B_Test
Channel B maintain (Optical fiber
mode)
Input:
Blocking_BI
BLK_PilotDis 1: Pilot distance blocking binary input
Output:
Relay_Trip IED trip
Tripcom Relay_Trip_A TripA
Relay_Trip_B TripB
Relay_Trip_C TripC
Trip_3ph Trip 3 phases
126

Relay_Block_AR Trip three phases and block
Output:
Carrier sends message: pilot distance
Carr_Send_Dist
sending message(Carrier mode)
Weak_End_Infeed Pilot weak-infeed(Carrier mode)

Phase A sending message of pilot
distance (if the
Carr_Send_DistA
Telepilot_Trip2 the binary output exists) (Carrier mode)
Phase B sending message of pilot

distance (if the
Carr_Send_DistB
the binary output exists) (Carrier mode)
Phase C sending message of pilot

distance (if the
Carr_Send_DistC
Output:
Carr_Fail_Dist Pilot distance channel alarming(Carrier
Pilot_Dist_Trip Pilot distance trip(Carrier mode)
Telepilot_Trip1
BO_DTT_Send Direct transfer trip sending message
(Carrier mode)
Direct transfer trip receiving

BO_DTT_Recv
message(Carrier mode)
DO_OpticalFiberChanl Output:
BO_DTT
Trip of direct transfer trip (Optical fiber
mode)
BO_Tele_Trans1
Remote transmission 1 binary output
BO_Tele_Trans2
BO_Tele_Trans3
BO_Tele_Trans4
BO_Tele_Trans5
127

BO_Tele_Trans6
BO_Tele_Trans7
BO_Tele_Trans8
Channel_A_Alarm
communication of channel A) (Optical
fiber mode)
Channel_B_Alarm
communication of channel B) (Optical
fiber mode)
ChannelACommuInterrupti Output:
on
ChannelACommuInt
Alarm of channel A（Assocaite single
erruption
channel and double channels）
ChannelBCommuInt
Alarm of channel B（Assocaite single
erruption
channel and double channels）
Principle description and logic diagram of the carrier mode to send and
receive messages are described. If the transmission is carried out by
optical fiber, the carrier receiving and carrier sending in the logic diagram
are optical fiber receiving and optical fiber sending.
3.1.1 Permissive underreach transfer trip (PUTT)
The logic diagram of PUTT is shown as follow:
PilotProtFcnOn
Blk_PilotDist
&
“PUTTModeOn” PUTTModeValid
“DistZ1On”
“DistZ2On”
Figure 79 Pilot logic for permissive under reach transfer trip

By setting the binary “PUTTModeOn” to 1, pilot protection logic works in
permissive under reach mode. The permissive under reach transfer trip is
shown in the following figure. The scheme is based on receiving and
sending signals. IED sends distance carrier signal if its startup elements
128
operate and a fault occurs in the first protection distance zone 1. To get
reliable operation in remote line end, the carrier send signal is prolong for
200ms after resetting of the trip signal.
According to this scheme, IED will generate a trip command if a fault has
been detected in second protection zone (Z2) and a carrier signal has
been received for at least 5ms. According to the selected mode (single
phase operation, three phase protection and also auto-reclosure mode),
pilot protection can generate single or three phase tripping. For more detail
about tripping mode refer under heading auto-reclosure.
In the following, different conditions are considered to show the operation
of the IED in the permissive under reach transfer trip mode.
IEDStartup
AllProtReset &
&
0 200ms ≥1 CarrierSendMsg
VTFailBlk
DistZ1Startup
PUTTModeValid &
≥1 PilotDistTrip
DistZ2Startup
5ms
CarrierRcvMsg
“WeakInfeedOn” & ≥1
WeakInfeed
ConditionMet
&
3PhTripPosn
IEDStartup ≥1
3PhTrip&NoCurr
Figure 80 Pilot logic for permissive under reach transfer trip

Internal fault-faults within protected line
Startup element operates when an internal fault occurs. If the fault has
been detected in distance zone 1, IED trips local circuit breaker and sends
signal to the remote end. If fault occurs in the protected line outside
distance zone 1 setting, local circuit breaker will be tripped instantaneously
by detection of fault in distance zone 2 and receiving of the carrier signal
from remote end for at least 5ms. If fault occurs in the protected line
outside distance zone 1 setting, local circuit breaker will be tripped
instantaneously by detection of fault in distance zone 2 and receiving of
the carrier signal from remote end for at least 5ms.
External fault of the protected line
For external faults in reverse direction, protection IED doesn’t send a
distance carrier signal. Therefore, remote end distance relay doesn’t
generate an instantaneous trip command by only check of a fault in its Z2
characteristic. Conversely, for external faults in forward direction, local IED
may detect the fault in Z2 but it doesn’t generate trip command because
lack of any receiving carrier signal from remote end. Therefore both local
and remote end distance protection will be stable for the external faults
without any tripping.
129
3.1.2 Permissive overreach transfer trip (POTT) scheme

The logic diagram of POTT is shown as follow:
PilotProtFcnOn
Blk_PilotDist
&
“POTTModeOn”
POTTModeValid
“DistZ2On”
Figure 81 Pilot logic for permissive over reach transfer trip

This mode of operation can also be useful for distance zone 1 of extremely
short lines. Where a typical setting of 85% of line length for distance zone
1 is not possible and selective non-delayed tripping could not be achieved.
In this case zone Z1 must be delayed by a time, to avoid non- selective
tripping of distance protection by Z1.
Where the "POTTModeOn" is set to 1, the POTT mode is enabled, and the
logic diagram is shown as follows. The impedance is in the distance zone
2 and issues trip command after receiving load wave signal for
5ms.According to this scheme, IED will generate a trip command if a fault
has been detected in second protection zone (Z2) and a carrier signal has
IEDStartup
&
AllProtReset &
0 200ms ≥1 CarrierSendMsg
VTFailBlk
DistZ2Startup
&
POTTModeValid ≥1 PilotDistTrip
5ms
CarrierRcvMsg
& ≥1
“WeakInfeedOn”
WeakInfeed
ConditionMet
&
3PhTripPosn
IEDStartup
≥1
3PhTrip&NoCurr
Figure 82 Pilot logic for permissive over reach transfer trip

IED sends distance carrier signal if startup elements operate and a fault
occurs in the Z2 protection zone. To get reliable operation in remote line
end, the carrier send signal is prolong for 200ms after resetting of the trip
signal. Additionally, to support permissive over reach scheme in the case
of weak infeed sources, special echo logic is considered in IED.
According to this scheme, IED will generate a trip command if a fault has
130
been detected in second protection zone (Z2) and a carrier signal has
3.1.3 Blocking mode
Special attention: (1) Fiber optic mode does not support blocking logic; (2)
The parallel mode does not support blocking logic.
The logic diagram of pilot blocking mode is shown as follow:
PilotProtFcnOn
Blk_PilotDist
“BlkModeLogicOn”
& PilotDistBlkValid
“DistZ4On”
“DistZ4ProtRvsDir”
“DistZ2On”
Figure 83 Blocking logic

In this scheme of operation, the transferring signal is utilized to block the
IED during external faults. The carrier signal should only be transmitted
when the fault is outside the protected zone in reverse direction.
The significant advantage of the blocking procedure is that no signal needs
to be transferred during faults on the protected feeder. Pilot blocking will be
applied in if the logic switch “BlkModeLogicOn” is set to “1-on”. Related
logic is shown in Figure as follow:
IEDStartup
AllProtReset & &

CarrierSendMsg
VTFailBlk
DistZ2Startup ≥1 CarrierStopMsg
PilotDistBlkValid & 25ms

PilotDistTrip
0 200ms
DistZ2Startup
25ms
NoCarrierRcvMsgBI
&
3PhTripPosn
3PhTrip&NoCurr
Figure 84 Blocking logic

IED sends blocking signal if startup components operate and a fault has
been detected in reverse direction, e.g. Z4 considered as reverse. In this
scheme, IED generates a trip command if a fault has been detected in Z2
131
of the protection zones and no blocking message received for at least

25ms. According to the selected mode (single phase operation, three
phase protection and also auto-reclosure mode), pilot protection can
generate single or three phase tripping. For more detail about tripping
mode refer under heading auto-reclosure.
In the following, different conditions will be considered to show operation of
the protected IED in the blocking mode.
Internal faults - faults within protected line
If an internal fault occurs, startup element operates and IED trips local
circuit breaker instantaneously if it is within distance zone 1. Since the fault
is not reverse, no blocking signal will be sent and remote end will generate
trip command by detection the fault in its Z2 zone. If fault occurs in the
protected line but outside of the Z1 setting, local circuit breaker tripping
happen instantaneously by detection of fault in Z2 and no receiving
blocking signal from remote end for at least 25ms.
External faults - faults outside of protected line
For external faults in the reverse direction, IED sends a distance carrier
blocking signal. Therefore, remote end distance relay doesn’t generate an
instantaneous trip command by only detection of a fault in its Z2
characteristic zone. Conversely, in the case of external fault in forward
direction, local IED may detect the fault in Z2 but it doesn’t generate trip
command because of the receiving blocking signal from remote end.
Therefore both local and remote end distance IED will not trip for this
external fault.
3.1.4 Additional pilot logics
3.1.4.1 Direction reversing for external fault
For double-circuit lines, in the case of external fault occurring, the problem
of direction reversing may occur. Where no measures are taken, trip errors
will occur in the protection. For example, as shown in the following figure,
both sides of the double-circuit lines are configured with distance
protection. In addition, the line is configured with POTT pilot logic. In the
figure, fault occurs near to the D side of CD line. In case that Device A
identifies that a fault occurs in Z2 and no pilot signal from B side is
received, so there is no tripping. In case that Circuit Breaker D is tripped
prior to Circuit Breaker C, fault current in Line AB will be in the reverse
direction, pilot of B side will send a pilot signal and if B side receive pilot
single, trip errors will occur in protection. Certain cooperative time is taken
in account to ensure that selective tripping may reliably occur in each side
during transient process. in this case, when the fault direction has been
identified from reverse direction to forward direction by the device, through
"RvsPowerTime", the forward direction is identified on both waiting sides.
In addition, when another fault occurs, both sides can receive the carrier
signal, delayed by 15ms, and reliably and selectively trip.
Note：Permissive underreach transfer trip (PUTT) takes no account of
power reverse direction.
132
Figure 85 Power directions for external fault of the double-circuit

3.1.4.2 Weak infeed function
Failure occurring in weak power and trip acting promptly is a special
application in permissive. Weak infeed is usually in pilot distance
permissive. In this case an additional echo-circuit with tripping supplement
must be provided at this end.
During a fault behind the weak infeed end, short circuit current flows
through the protected feeder to the fault location. The IED at the weak
infeed end will start with this current and recognize the fault in the reverse
direction. The permissive over reach transfer trip protection is stable.
During an internal fault near the strong source side the IED at the weak
infeed end will not pickup, as insufficient current flows from this side into
the feeder. The signal received by the weak infeed end is returned as an
echo and allows the tripping at the strong infeed.
Simultaneously with the echo, the circuit breaker at the weak infeed end
may be tripped by the IED.
Therefore, when the weakly fed undervoltage is started and there is 5ms
delay of receiving pilot signal, distance carrier signal will be sent and
prolonged for 200ms to ensure the IED at the remote end (strong power
side) trips quickly and reliably. In this case local weak feeder generates trip
command, too.
In addition, when receiving pilot signal and then circuit breaker is in the
open position, signal sending will be prolonged for 200ms to ensure the
IED at the remote end trips quickly and reliably.
CurrStartupComponent
&
5ms
CarrierRcvMsg 0 200ms
5ms
& PilotWeakInfeedTrip
UVCondMet &
&
“WeakInfeedOn”
FwdDirComponentTrip
≥1
CarrierSendMsg
RvsDirComponentTrip
VTFailBlk
Figure 86 Pilot weak infeed function logic diagram
133
3.1.4.3 Pilot distance open position sending message logic

Permissive pilot sending message logic, as shown in the figure as follow,
similar to the logic principle of blocking type of pilot open position stop
sending message.
PUTTModeValid
≥1
POTTModeValid
5ms
CarrierRcvMsg
& 0 200ms CarrierSendMsg

3PhTripPosn (PilotOpenPosnSendMsg)
IEDStartup
≥1
3PhTrip&NoCurr
Figure 87 Permissive pilot open position sending message logic

3.1.4.4 Pilot distance trip sending message logic
Permissive pilot sending message logic, as shown in the figure as follow,
similar to the logic principle of blocking type of pilot open position stop
sending message.
≥1
PUTTModeValid
POTTModeValid
&
0 200ms Carrier sends message
DistZ1Trip (PilotTripSendMsg)
≥1
DistSOTFAccelTrip
PilotProtTrip
ZeroSeqOCTrip
Figure 88 Permissive pilot trip sending message logic

3.1.4.5 DTT Direct transfer trip logic
When the pilot distance protection function is enabled, and the
"DTTSendMsg" binary input is in protection of this side, output the
"DTTSendMsg" signal; the signal will be transferred to the other side by
carrier, to connect to the "DTTRcvMsg" binary input in protection of the
other side, and it will output the "DTTRcvMsg" signal.
3.1.4.6 Double-circuit parallel transmission lines
The protection device can be applied in the double-circuit parallel lines.
The relevant logic switches are "ParallelLineMode" and
"ParallelLinePhSendMsg".
1) At least one of the "PUTTModeOn" and "POTTModeOn" should be
enabled, if the protection device is used for the double-circuit parallel
lines, permissive mode must be used, if "BlkModeLogicOn" is enabled,
"PilotLSErr" is reported.
2) When the logic switch "ParallelLineMode"=1 and
"ParallelLinePhSendMsg"=0, phase selection will take various of
cross-line faults in to account, and the parallel lines function exists, but
the device does not support split-phase sending message and it is
134
applied in non-split-phase transmission mode. At this time, the binary

input does not receive message in splitting phase and binary output
does not send message in splitting phase. There are only
"PilotDistSendMsg" binary output and "PilotDistRcvMsg" binary input.
"ParallelLinePhSendMsg"=1, the parallel lines function exists and the
device supports split-phase sending permissive message. At this time,
the binary input receives message in splitting phase and binary output
sends message in splitting phase. There are only the binary outputs of
"PilotDistPhASendMsg", "PilotDistPhBSendMsg" and
"PilotDistPhCSendMsg" and binary inputs of "Pilot3I0PhARcvMsg",
"Pilot3I0PhBRcvMsg" and "Pilot3I0PhCRcvMsg".
4) Directional pilot distance protection of optical fiber mode adopts the
sending message mode of same tower split phase by default. In
optical fiber mode, if "BlkModeLogicOn" is enabled, "PilotLSErr" is
reported.
For Double-circuit parallel transmission lines, it is suggested to enable
"ParallelLineMode" and "ParallelLinePhSendMsg".
3.1.5 Remote transmission and direct transfer trip logic of using
optical fiber channel
3.1.5.1 Remote transmission command
The protection device has eight binary input terminals of remote
transmission command: <Remote transmission command 1>, <Remote
transmission command 6>, <Remote transmission command 7> and
<Remote transmission command 8>. The device sends the command to
the opposite side with the logic switch in each frame of data through digital
channel. When the IED on the opposite side receives the remote
command signal, remote command 1 is driven to be output. By using this
sending signal, users are able to construct the logic. Take Remote
transmission command 1 as an example.
Remote command 1 input &

(BI_Tele_Trans1) Send: teletransfer 1
signal
Normal channel
&
Remote transmission 1 output
(BO_Tele_Trans1)
Receive: teletransfer 1 signal
Figure 89 Logic diagram of Remote transmission command

3.1.5.2 Logic diagram of Remote transmission command
In order to make sure that the opposite protection trips timely when fault
occurs between the circuit breaker and the current inductor or there is a
breaker failure, one <remote trip>input are set to send the dead zone
protection or circuit breaker failure trip signal, so as to trip the opposite
circuit breaker. When the input time of <remote trip> is greater than 20S,
135
the alarm "DTT BIErr" is issued. The remote trip operates according to
"DTTTime".
Normal channel
&
Receive: DTT trip signal
“DTTCtrlledByStartup”
“DTTCtrlledByZ2” & ≥1 T_DTT

Remote trip (BO_DTT)
In distance zone 2
&
“DTTCtrlledByZ3”
In distance zone 3
≥1 &
&
Remote trip signal input Send: DTT trip signal

(BI_DTT)
T_DTT：“DTTTime”
Figure 90 Remote trip logic diagram
3.2 Pilot protection tripping logic

The following figure is pilot protection tripping logic diagram, including the
state of pilot distance and directional pilot earth fault protection trips. The
part in the dotted frame is only the logic to protect configuration
auto-reclosing. Take phase A as an example for single phase fault and
take phase AB as an example for phase-to-phase fault.
136
PhSel: PhA
“1PhARModeOn”
≥1 &
“1&3PhARModeOn”
PilotDistTrip
≥1
Pilot3I0Trip
&
“Pilot3I0InitAR” &
BI:Enforced3PhTrip
(AR_Lockout) &
TripA
≥1
“3PhTripMode”
BO: Enforced3PhTrip
(AR_Lockout) ≥1
PilotDistDevelopmentTrip
& ≥1
≥1 TripABC
&
PhSel: PhAB
& &
“PPFaultInitAR”
≥1
≥1 Trip3Ph&BlkAR
PhSel: PhABC &
&
Pilot3I0Trip
&
“Pilot3I0InitAR”
Figure 91 Pilot protection tripping logic

Type Description
configuration
Blocking_DI.BLK_PilotDis Pilot distance blocking binary input
Carrier receives message: pilot distance receiving
DI_Telepilot.BI_Carr_Recv_Dist
message (Carrier mode)
DI_Telepilot.BI_Carr_Fail_Dist Pilot distance channel error (Carrier mode)
Sending message of direct transfer trip (Carrier
DI_Telepilot.BI_DTT_Send
mode)
Input Receiving message of direct transfer trip (Carrier
DI_Telepilot.BI_DTT_Recv
mode)
Phase A receiving message of pilot distance (if the
DI_Telepilot.BI_Carr_Recv_DistA "ParallelLinePhSendMsg" is enabled, the binary
input exists) (Carrier mode)
Phase B receiving message of pilot distance (if the
DI_Telepilot.BI_Carr_Recv_DistB "ParallelLinePhSendMsg" is enabled, the binary
137

Type Description
configuration
Phase C receiving message of pilot distance (if the
DI_Telepilot.BI_Carr_Recv_DistC "ParallelLinePhSendMsg" is enabled, the binary
Remote transmission command 1 input (Optical
fiber mode)
fiber mode)
fiber mode)
fiber mode)
fiber mode)
fiber mode)
fiber mode)
fiber mode)
DI_OpticalFiberChanl.BI_DTT Remote trip signal input (Optical fiber mode)
DI_OpticalFiberChanl.BI_Chan_A_Test Channel A maintain (Optical fiber mode)
DI_OpticalFiberChanl.BI_Chan_B_Test Channel A maintain (Optical fiber mode)
Telepilot_Trip2.Weak_End_Infeed Pilot weak-infeed (Carrier mode)
Telepilot_Trip1.Carr_Fail_Dist Pilot distance channel alarming (Carrier mode)
Telepilot_Trip1.Pilot_Dist_Trip Pilot distance trip (Carrier mode)
Telepilot_Trip1.BO_DTT_Send Direct transfer trip sending message (Carrier mode)

Direct transfer trip receiving message (Carrier
Telepilot_Trip1.BO_DTT_Recv
mode)
Phase A sending message of pilot (if the
Telepilot_Trip2.Carr_Send_DistA "ParallelLinePhSendMsg" is enabled, the binary
output exists) (Carrier mode)
Phase B sending message of pilot distance (if the
Telepilot_Trip2.Carr_Send_DistB "ParallelLinePhSendMsg" is enabled, the binary
Outpu Phase C sending message of pilot distance (if the
t Telepilot_Trip2.Carr_Send_DistC "ParallelLinePhSendMsg" is enabled, the binary
DO_OpticalFiberChanl.BO_Tele_Trans1 Remote transmission 1 output (Optical fiber mode)
138

Type Description
configuration
Interruption of channel A (detect the communication
DO_OpticalFiberChanl.Channel_A_Alarm
of channel A) (Optical fiber mode)
Interruption of channel A (detect the communication
DO_OpticalFiberChanl.Channel_B_Alarm
of channel A) (Optical fiber mode)
ChannelAlarm.ChannelACommuInterruptio Channel A alarm (assocaite single channel and
n double channels) (Optical fiber mode)
ChannelAlarm.ChannelBCommuInterruptio Channel B alarm (assocaite single channel and
n double channels) (Optical fiber mode)
3.4 Setting list

3.4.1 Setting list
Table 34 Protection setting of pilot distance
Range Default value Step
No. Setting name Unit Remark
(In:5A/1A) (In:5A/1A)
Power reversing
1. RvsPowerTime 0.0～0.1 0.04 0.001 s
delay setting
Default Step
Range
No. Setting name value Unit Remark
(In:5A/1A)
(In:5A/1A)
1. LocalEndIDCode 0~65535 00000 1
2. OppEndIDCode 0~65535 00000 1
3. DTTTime 0~10 0.1 0.01 s
Table 36 Logic switch of pilot distance protection

Default
value
1. WeakInfeedOn 1/0 0 0: Disable, 1:Enable
2. BlkModeLogicOn 1/0 0 0: Disable, 1:Enable
3. PUTTModeOn 1/0 0 0: Disable, 1:Enable
4. POTTModeOn 1/0 0 0: Disable, 1:Enable

Instantaneous permanent trip
5. PilotDistAccelOn 1/0 0 function of pilot distance
protection after enabling
auto-reclosing
6. DistZ1On 1/0 0 0: Disable, 1:Enable
7. DistZ2On 1/0 0 0: Disable, 1:Enable
139
Default
value
8. ParallelLineMode 1/0 0 0: Disable, 1:Enable
When
9. ParallelLinePhSendMsg 1/0 0 "ParallelLinePhSendMsg"=1,
the "ParallelLineMode" =1 in
default.
No. Logic switch description Setting Default value Remark
1. DualChan 1/0 1
2. SelExtrClockForChanA 1/0 0
3. Sel64KRateForChanA 1/0 0 Effective under G.703
protocol
5. Sel64KRateForChanB 1/0 0 Effective under G.703
protocol
6. DTTCtrlledByStartup 1/0 1
7. DTTCtrlledByZ2 1/0 0
3.4.2 Setting description

1) "WeakInfeedOn": If only one side of the protected line is weak infeed,
the protection can be done selectively when the IED in weak side
operates in Week Infeed mode;
2) "POTTModeOn": If "POTTModeOn" is set to 1 then the
“BlkModeLogicOn” and “PUTTModeOn” must be set to 0. If distance
Z2 module sends permissive message, close the contact of
“PilotDistSendMsg”. If Z2 module stops sending permissive message,
open the contact of "PilotDistSendMsg"l. Now, "DistZ2On" shall be set
to 1;
3) "PUTTModeOn": If "PUTTModeOn" is set to 1, “BlkModeLogicOn” and
“POTTModeOn” must be set to 0. If distance Z1 module sends
permissive message, close the contact of “PilotDistSendMsg”. If
Z1 module stops sending permissive message, open the contact of
"PilotDistSendMsg"l. At the same time, both of “DistZ1On” and
“DistZ2On” should be set to 1;
4) "BlkModeLogicOn": if "BlkModeLogicOn" is set to 1, both of
"PUTTModeOn" and "POTTModeOn" shall be set to 0. At this time,
"DistZ4On", "DistZ2On" and "DistZ4RvsDir" shall be set to 1;
5) Description of "ParallelLineMode" is shown in Section 3.1.4.4;
140
6) "ParallelLinePhSendMsg": if "ParallelLinePhSendMsg" is set to 1, the

protection device adopts the mode of split-phase sending message
and split-phase receiving message. When
"ParallelLinePhSendMsg"=1, the "ParallelLineMode" =1 in default.
Please refer to the Section 3.1.4.6 for details.
7) "WeakinfeedFunctionOn": If only one side of the protected line is weak
infeed, the protection can be done selectively when the IED in weak
side operates in Week Infeed mode;
8) “PermissiveOverrangeOn”: If "POTTModeOn" is set to 1 then the
“BlkModeLogicOn” and “PUTTModeOn” must be set to 0. If distance
Z2 module sends permissive message, close the contact of
“PilotDistSendMsg”. If Z2 module stops sending permissive message,
open the contact of "PilotDistSendMsg"l. Now, "DistZ2On" shall be set
to 1.
9) “PUTTMode”: If "PUTTModeOn" is set to 1, “BlkModeLogicOn” and
“POTTModeOn” must be set to 0. If distance Z2 module sends
permissive message, close the contact of “PilotDistSendMsg”. If Z2
module stops sending permissive message, open the contact of
"PilotDistSendMsg"l. At the same time, both of “DistZ1On” and
“DistZ2On” should be set to 1.
10) Blocking logic: if "BlkModeLogicOn" is set to 1, both of
"PUTTModeOn" and "POTTModeOn" shall be set to 0. At this time,
"DistZ4On", "DistZ2On" and "DistZ4RvsDir" shall be set to 1.
11) Description of "ParallelLineMode" is shown in Section 3.1.4.4.
12) "ParallelLinePhSendMsg": if "ParallelLinePhSendMsg" is set to 1, the
protection device adopts the mode of split-phase sending message
and split-phase receiving message. When
"ParallelLinePhSendMsg"=1, the "ParallelLineMode" =1 in default.
Please refer to the Section 3.1.4.6 for details.
3.5 Report list

Trip report:
1. PilotDistTrip Pilot distance tripping trip
2. PilotDistDevelopmentTrip Pilot distance development fault trip
Signal stopping of pilot distance is only valid in

3. PilotDistStopMsg
blocking mode
Signal stopping in tripping position is only valid in

4. PilotOpenPosnStopMsg
blocking mode
5. PilotDistSendMsg
6. PilotOpenPosnSendMsg Trip position sending message
141
7. PilotWeakInfeedSendMsg Carrier signal sending of week infeed end
8. DTTSendMsg DTT Direct transfer trip logic
9. DTTRcvMsg DTT Direct transfer trip logic
Trip stops sending message is only valid in

10. PilotTripStopMsg
blocking mode
11. PilotTripSendMsg
12. PilotWeakInfeedTrip Pilot protection at weak feeder side
13. TeleTransferCmd1BI
21. TeleTransferCmd1BO
23. TeleTransferCmd3BO Reports of optical fiber channel
29. TeleTransferCmd1Rst
142
37. DTT BI
38. DTTTrip
Alarm report:
Alarm report of carrier channel: Alarm report when

1. PilotDistChanFault
"BI_Carr_Fail_Dist" occurs
2. PilotLSErr /
5. DTT BIErr
7. ChanBAddrErr
9. OppEndCommErr
Operation report:
1. PilotDistFcnOn /
2. PilotDistFcnOff /
3. ChanACommRst
4. ChanBCommRst
5. OppEndIEDRst
6. OppEndIEDOff
143

Table 39 Technical parameters of pilot distance technology
Trip time Allowable logic, the distance setting of 70%, typical

trip time of 25ms
144
Chapter 7 Directional pilot earth fault protection
(85-67N)
Chapter 7 Directional pilot earth fault

protection (85–67N)
About this chapter

This Chapter describes the principle of directional pilot earth
fault protection, input and output signal, setting parameters,
report and technical parameters.
145
(85-67N)
1 Introduction
Directional pilot earth fault protection t is an important feature in the
transmission line protection. Similar to pilot distance protection:
1) It uses a carrier transceiver mechanism to achieve different pilot
protection configurations through a power carrier line (PLC).
2) It uses optical fiber channel to achieve different pilot protection
configurations through optical fiber

Input and output signals of the directional pilot earth fault protection
function are shown as follow:
Directional Pilot Earth Fault Protection

1 1
BI_Carr_Recv_DEF Relay_StartUp
2 2
BI_Carr_Fail_DEF Relay_Trip
3 3
BI_DTT_Send Relay_Trip_A
4 4
BI_DTT_Recv Relay_Trip_B
5 5
BLK_PilotDEF Relay_Trip_C
6 6
BI_Carr_Recv_DEFA Trip_3ph
7 7
BI_Carr_Recv_DEFB Relay_Block_AR
8 8
BI_Carr_Recv_DEFC Carr_Send_DEF
9
Carr_Fail_DEF
10
Pilot_DEF_Trip
11
Weak_End_Infeed
12
BO_DTT_Send
13
BO_DTT_Recv
14
SOTF_Trip
15
Carr_Send_DEFA
16
Carr_Send_DEFB
17
Carr_Send_DEFC
Figure 92 Input and output signal diagram of the directional pilot earth fault protection
function(Carrier mode)
146
(85-67N)
The input and output signals of directional pilot earth fault protection
function in optical fiber mode are shown as follows:
Pilot Earth Fault Protection

1 1
BI_Tele_Trans1 Relay_StartUp
2 2
BI_Tele_Trans2 Relay_Trip
3 3
BI_Tele_Trans3 Relay_Trip_A
4 4
BI_Tele_Trans4 Relay_Trip_B
5 5
BI_Tele_Trans5 Relay_Trip_C
6 6
BI_Tele_Trans6 Trip_3ph
7 7
BI_Tele_Trans7 Relay_Block_AR
8 8
BI_Tele_Trans8 Pilot_DEF_Trip
9 9
BI_DTT SOTF_Trip
10 10
BI_Chan_A_Test BO_DTT
11 11
BI_Chan_B_Test BO_Tele_Trans1
12
BO_Tele_Trans2
13
BO_Tele_Trans3
14
BO_Tele_Trans4
15
BO_Tele_Trans5
16
BO_Tele_Trans6
17
BO_Tele_Trans7
18
BO_Tele_Trans8
19
Channel_A_Alarm
20
Channel_B_Alarm
21
22
Figure 93 Input and output signal diagram of the directional pilot earth fault protection
function (Optical fiber mode)
right.

Input:
BI_Carr_Recv_D Carrier receives message: pilot earth fault

EF receiving message(Carrier mode)
BI_Carr_Fail_DE
Pilot earth fault channel error(Carrier mode)
F
BI_DTT_Send Sending message of direct transfer
trip(Carrier mode)
BI_Telepilot Receiving message of direct transfer
BI_DTT_Recv
trip(Carrier mode)
Phase A receiving message of pilot earth fault

BI_Carr_Recv_D
(if the "ParallelLinePhSendMsg" is enabled,
EFA
Phase B receiving message of pilot earth fault

BI_Carr_Recv_D
EFB
147
(85-67N)
Phase C receiving message of pilot earth

BI_Carr_Recv_D fault (if the "ParallelLinePhSendMsg" is
EFC enabled, the binary input exists) (Carrier
mode)
Input:
BI_Tele_Trans1
Remote transmission command 1 binary
input (Optical fiber mode)
BI_Tele_Trans2
BI_Tele_Trans3
BI_Tele_Trans4
BI_Tele_Trans5
DI_OpticalFiberChanl input (Optical fiber mode)
BI_Tele_Trans6
BI_Tele_Trans7
BI_Tele_Trans8
BI_DTT
Remote trip signal binary input (Optical fiber
mode)
BI_Chan_A_Test
Channel A maintain (Optical fiber mode)
BI_Chan_B_Test
Channel B maintain (Optical fiber mode)
Input:
Blocking_BI
BLK_PilotDEF 1: Pilot earth fault blocking binary input
Output:
Relay_Trip IED trip
Relay_Trip_A TripA
Tripcom Relay_Trip_B TripB
Relay_Trip_C TripC
Trip_3ph Trip 3 phases
Relay_Block_AR Trip three phases and block auto-reclosing
148
(85-67N)
Output:
Carrier sends message: pilot earth fault
Carr_Send_DEF
sending message (Carrier mode)
Weak_End_Infee
Pilot weak-infeed (Carrier mode)
d
Phase A sending message of pilot earth fault
Carr_Send_DEFA (if the "ParallelLinePhSendMsg" is enabled,
Telepilot_Trip2 the binary output exists) (Carrier mode)
Phase B sending message of pilot earth fault

Carr_Send_DEF
B
Phase C sending message of pilot earth fault

Carr_Send_DEF
C
Output:
Carr_Fail_DEF Pilot earth fault channel alarm(Carrier mode)
Pilot_DEF_Trip Pilot earth fault trip
Telepilot_Trip1
BO_DTT_Send Direct transfer trip sending message(Carrier
mode)
Direct transfer trip receiving message(Carrier

BO_DTT_Recv
mode)
Output:
BO_DTT BO_DTT
BO_Tele_Trans1 BO_Tele_Trans1
DO_OpticalFiberChanl
149
(85-67N)
Output:
ChannelACommu Alarm of channel A（Assocaite single channel

ChannelACommuInterru
Interruption and double channels）(Optical fiber mode)
ption
ChannelBCommu Alarm of channel B（Assocaite single channel
Interruption and double channels）(Optical fiber mode)
Principle description and logic diagram of the carrier mode to send and
receive messages are described. If the transmission is carried out by optical
fiber, the carrier receiving and carrier sending in the logic diagram are optical
fiber receiving and optical fiber sending.
3.1.1 Permissive
The logic diagram of permissive pilot earth fault is shown as follow:
PilotProtFcnOn
Blk_PilotDEF
“PUTTModeOn” ≥1 &
Pilot3I0Valid
“POTTModeOn”
“Pilot3I0On”
Figure 94 The logic diagram of permissive pilot earth fault

To detect fault reliably and selectively for the device, the permissive pilot
earth fault logic is shown in the following figure, and the tripping logic is
shown in former pilot protection tripping logic diagram.
150
(85-67N)
IEDStartup
AllProtReset
&
VTFailBlk &
0 200ms ≥1 CarriersSendMsg
CTFail
3I0>“Pilot3I0Set”
3I0FwdDir
3PhInrushCurrBlk
&
“Pilot3I0BlkByHarm”
Blk_PilotDEF &
&
T0
“Pilot3I0On” ≥1 Pilot3I0Trip
“PUTTModeOn” ≥1
“POTTModeOn”
5ms
CarrierRcvMsg
& ≥1
“WeakInfeedOn”
WeakInfeedCondMet
&
3PhTripPosn
T0：“Pilot3I0Time”
Figure 95 The logic diagram of permissive mode of directional pilot earth fault
When the logic switch "Pilot3I0On" is set to 1, "POTTModeOn" or
"PUTTModeOn" is set to 1; if internal fault occurs, startup component
starts, the measuring zero sequence current is more than "Pilot3I0Set" and
the fault is in forward direction, through delay "Pilot3I0Set" send the pilot
earth fault signal. In addition, when "Pilot3I0BlkByHarm" is set to 1, in case
of inrush current exists and less than the setting of “OCHarmUnblkCurr”,
meanwhile, the detected value of second harmonic divided by fundamental
wave is greater than "OC2ndHI2/I1Ratio", then the sending message of
directional pilot earth fault will be blocked.
Note: The "Pilot3I0BlkByHarm" logic switch is recommended to exit
without special circumstances.
When an external fault occurs, fault direction in one end will be reverse.
Therefore, in this end, no tripping command will be generated by
directional earth fault carrier receiving.
In addition, carrier sending will prolong for 200ms for reliable operation of
remote end. The prolongation of the send signal only comes into effect
when the protection has already issued a trip command. This ensures that
the permissive message releases the opposite line ends even if the earth
fault is very rapidly cleared by a different independent protection.
151
(85-67N)
3.1.2 Blocking mode
Special attention: (1) Fiber optic mode does not support blocking logic; (2)
The parallel mode does not support blocking logic.
The logic diagram of pilot earth fault blocking mode is shown as follow:
PilotProtFcnOn
Blk_PilotDEF
&
“BlkModeLogicOn” Pilot3I0BlkValid
“Pilot3I0On”
Figure 96 The logic diagram of pilot earth fault blocking method

In this scheme of operation, the transferring signal is utilized to block the
IED during external faults. The carrier signal should only be transmitted
when the fault is outside the protected zone in reverse direction.
The significant advantage of the blocking procedure is that no signal needs
to be transferred during faults on the protected feeder. When the logic
switch “BlkModeLogicOn” is set to 1, the blocking logic is enabled. The trip
logic is shown in the logic diagram of pilot protection trip
3.1.3 Direction reversing for external fault
For double-circuit lines, in the case of external fault occurring, the problem
of direction reversing may occur. Where no measures are taken, trip errors
will occur in the protection. For example, as shown in the following figure,
both sides of the double-circuit lines are configured with distance
protection. In addition, the line is configured with POTT pilot logic. In the
figure, fault occurs near to the D side of CD line. In case that Device A
identifies that a fault occurs in Z2 and no pilot signal from B side is
received, so there is no tripping. In case that Circuit Breaker D is tripped
prior to Circuit Breaker C, fault current in Line AB will be in the reverse
direction, pilot of B side will send a pilot signal and if B side receive pilot
single, trip errors will occur in protection. Certain cooperative time is taken
in account to ensure that selective tripping may reliably occur in each side
during transient process. in this case, when the fault direction has been
identified from reverse direction to forward direction by the device, through
"RvsPowerTime", the forward direction is identified on both waiting sides.
In addition, when another fault occurs, both sides can receive the carrier
signal, delayed by 15ms, and reliably and selectively trip.
Figure 97 Power directions for external fault of the double-circuit
3.1.4 Pilot zero sequence open position sending message logic
152
(85-67N)
Diagram of pilot open position sending message logic is shown as below.
Pilot3I0Valid
5ms
CarrierRcvMsg
& 0 200ms CarrierSendMsg

3PhTripPosn (PilotOpenPosnSendMsg)
IEDStartup
≥1
3PhTrip&NoCurr
Figure 98 Diagram of pilot open position sending message logic
3.1.5 Pilot zero sequence trip sending message logic

Diagram of pilot trip sending message logic is shown as below.
Pilot3I0Valid
&
0 200ms Carrier sends message
DistZ1Trip （PilotTripSendMsg)
≥1
DistSOTFAccelTrip
PilotProtTrip
ZeroSeqOCTrip
Figure 99 Diagram of pilot zero sequence trip sending message logic
3.1.6 Weak infeed function

Failure occurring in weak power and trip acting promptly is a special
application in permissive. Weak infeed is usually in pilot distance
permissive. Pilot earth fault does not use weak infeed function usually.
3.1.7 DTT Direct transfer trip logic
When the directional pilot earth fault protection is enabled and the
"DTTSendMsg" binary input is in protection of this side, output the
"DTTSendMsg" signal; the signal will be transferred to the other side by
carrier, to connect to the "DTTRcvMsg" binary input in protection of the
other side, and it will output the "DTTRcvMsg" signal.
3.1.8 Double-circuit parallel transmission lines
The protection device can be applied in the double-circuit parallel lines.
The relevant logic switches are "ParallelLineMode" and
"ParallelLinePhSendMsg".
1) At least one of the "PUTTModeOn" and "POTTModeOn" should be
enabled, if the protection device is used for the double-circuit parallel
lines, permissive mode must be used, if "BlkModeLogicOn" is enabled,
"PilotLSErr" is reported.
"ParallelLinePhSendMsg"=0, phase selection will take various of
cross-line faults in to account, and the parallel lines function exists, but
the device does not support split-phase sending message and it is
applied in non-split-phase transmission mode. At this time, the binary
153
(85-67N)
input does not receive message in splitting phase and binary output
does not send message in splitting phase. There are only
"Pilot3I0SendMsg" binary output and "Pilot3I0RcvMsg" binary input.
"ParallelLinePhSendMsg"=1, the parallel lines function exists and the
device supports split-phase sending permissive message. At this time,
the binary input receives message in splitting phase and binary output
sends message in splitting phase. There are only the binary outputs of
"Pilot3I0PhASendMsg", "Pilot3I0PhBSendMsg" and
"Pilot3I0PhCSendMsg" and binary inputs of "Pilot3I0PhARcvMsg",
"Pilot3I0PhBRcvMsg" and "Pilot3I0PhCRcvMsg".
4) Directional pilot earth fault protection of optical fiber mode adopts the
sending message mode of same tower split phase by default. In
optical fiber mode, if "BlkModeLogicOn" is enabled, "PilotLSErr" is
reported.
3.1.9 Remote transmission and direct transfer trip logic of using
optical fiber channel
Ibid. Chapter 6, Section 3.1.5 "Remote transmission and trip logic when
using optical fiber channel".

Type Description
configuration
Blocking_DI.BLK_PilotDEF Pilot earth fault blocking binary input
Carrier receives message: pilot earth fault
DI_Telepilot.BI_Carr_Recv_DEF
receiving message (Carrier mode)
Pilot earth fault channel error (Carrier
DI_Telepilot.BI_Carr_Fail_DEF
mode)
Sending message of direct transfer trip
DI_Telepilot.BI_DTT_Send
(Carrier mode)
Receiving message of direct transfer trip
DI_Telepilot.BI_DTT_Recv
(Carrier mode)
Phase A receiving message of pilot earth
fault (if the "ParallelLinePhSendMsg" is
DI_Telepilot.BI_Carr_Recv_DEFA
enabled, the binary input exists) (Carrier
mode)
Input Phase B receiving message of pilot earth
DI_Telepilot.BI_Carr_Recv_DEFB
mode)
Phase C receiving message of pilot earth
DI_Telepilot.BI_Carr_Recv_DEFC
mode)
DI_OpticalFiberChanl.BI_Tele_Tra Remote transmission command 1 input
ns1 (Optical fiber mode)
154
(85-67N)
Type Description
configuration
Remote trip signal input (Optical fiber
DI_OpticalFiberChanl.BI_DTT
mode)
Telepilot_Trip2.Weak_End_Infeed Pilot weak-infeed (Carrier mode)
Pilot earth fault channel alarm (Carrier
Telepilot_Trip1.Carr_Fail_DEF
mode)
Telepilot_Trip1.Pilot_DEF_Trip Pilot earth fault trip
Direct transfer trip sending message
Telepilot_Trip1.BO_DTT_Send
(Carrier mode)
Direct transfer trip receiving message
Telepilot_Trip1.BO_DTT_Recv
(Carrier mode)
Phase A sending message of pilot earth
Telepilot_Trip2.Carr_Send_DEFA
enabled, the binary output exists) (Carrier
mode)
Phase B sending message of pilot earth
Telepilot_Trip2.Carr_Send_DEFB
mode)
Phase C sending message of pilot earth
Telepilot_Trip2.Carr_Send_DEFC
Output mode)
Tripcom.SOTF_Trip Manual close trip(Carrier mode)
DO_OpticalFiberChanl.BO_Tele_T Remote transmission command 1 output
rans1 (Optical fiber mode)
DO_OpticalFiberChanl.Channel_A
communication of channel A) (Optical fiber
_Alarm
mode)
155
(85-67N)
Type Description
configuration
DO_OpticalFiberChanl.Channel_B
communication of channel B) (Optical fiber
_Alarm
mode)
ChannelAlarm.ChannelACommuIn Channel A alarm (assocaite single channel
terruption and double channels) (Optical fiber mode)
ChannelAlarm.ChannelBCommuIn Channel B alarm (assocaite single channel
terruption and double channels) (Optical fiber mode)
3.3 Setting list

Table 42 Setting of zero sequence protection of pilot direction
Default
Range
(In:5A/1A)
(In:5A/1A)
Power reversing
1. RvsPowerTime 0.0～100 0.04 0.001 s
delay setting
Pilot earth fault

2. Pilot3I0Set 0.08In~20In 20 0.01 A
setting
3. Pilot3I0Time 0.01～10 0.15 0.01 s Pilot earth fault time

Common setting
5. OC2ndHI2/I1Ratio 0.07～0.50 0.07 0.01

Default
Range
(In:5A/1A)
(In:5A/1A)
1. LocalEndIDCode 0~65535 00000 1
2. OppEndIDCode 0~65535 00000 1
3. DTTTime 0~10 0.1 0.01 s
Table 44 Logic switch of directional pilot earth fault protection
Default
value
1. WeakInfeedOn 1/0 0 0: Disable, 1:Enable
2. BlkModeLogicOn 1/0 0 0: Disable, 1:Enable
3. PUTTModeOn 1/0 0 0: Disable, 1:Enable
4. POTTModeOn 1/0 0 0: Disable, 1:Enable
5. Pilot3I0On 1/0 0 0: Disable, 1:Enable
6. Pilot3I0BlkByHarm 1/0 0 0: Disable, 1:Enable
156
(85-67N)
Default
value
7. Pilot3I0InitAR 1/0 1 0: Disable, 1:Enable
8. ParallelLineMode 1/0 0 0: Disable, 1:Enable

When
9. ParallelLinePhSendMsg 1/0 0
"ParallelLinePhSendMsg"=1, the
"ParallelLineMode" =1 in default.
1. DualChan 1/0 1
2. SelExtrClockForChanA 1/0 0
3. Sel64KRateForChanA 1/0 0 Effective under G.703
protocol
5. Sel64KRateForChanB 1/0 0 Effective under G.703
protocol
6. DTTCtrlledByStartup 1/0 1
7. DTTCtrlledByZ2 1/0 0
Note 1: the logic switch "Pilot3I0On" is set to 1, and one of

"POTTModeOn" or "PUTTModeOn" is set to 1.
Note 2: when the logic switch "Pilot3I0InitAR" is set to 0, the trip of pilot
earth fault is tripping and blocking auto-reclosing;
Note 3: If "ParallelLinePhSendMsg" is set to 1, the protection device
adopts the mode of split-phase sending message and split-phase
receiving message. Please refer to the Section 3.1.6 for details.
157
(85-67N)
3.4 Report list
Trip report:
1. Pilot3I0SendMsg /
2. Pilot3I0Trip /
3. Pilot3I0StopMsg /
14. TeleTransferCmd3BO Reports of optical fiber channel
158
(85-67N)
28. DTT BI
29. DTTTrip
Alarm report:
Alarm report of carrier channel: Alarm

1. Pilot3I0ChanFault
report when "BI_Carr_Fail_DEF" occurs
2. PilotLSErr /
5. DTT BIErr
7. ChanBAddrErr
9. OppEndCommErr
Operation report:
1. Pilot3I0FcnOn /
2. Pilot3I0FcnOff /
3. ChanACommRst
4. ChanBCommRst
5. OppEndIEDRst
6. OppEndIEDOff
159
Chapter 8 Overcurrent protection (50, 51, 67)
Chapter 8 Overcurrent Protection

(50,51,67)
About this chapter

This chapter describes the overcurrent principle, the input
and output signals, setting value parameters, messages and
technical parameters.
161
1 Introduction
When the power system fault occurs, the current of the system increases,
and the overcurrent protection can avoid the damage of the fault current to
the equipment. The device provides 4 stages of overcurrent protection,
each stage provides options of overcurrent definite time protection or
inverse time protection. Each stage of overcurrent protection has the same
logic criterion, and each stage can be enabled or disabled independently.
Each stage of the overcurrent protection can be selectively enabled
harmonic blocking component and directional component, and overcurrent
can trip based on the phase measurement of the current. In addition, each
stage of the definite-time overcurrent protection can be selectively input
the composited voltage blocking component.
Main characteristics of overcurrent protection:
1) The device provides 4 stages of overcurrent protection, each stage
adopts definite time-lag or 12 IEC and ANSI standard curve of inverse
time characteristic, and it adopts user-defined characteristic curve as
well;
2) The flow direction sensitive angle can be adjusted to meet different
application occasions;
3) Each section of the overcurrent protection can be respectively set
whether it enables direction component, whether the trip area is
"forward" or "reverse" trip is set by the logic switch;
4) Each section of the overcurrent protection can be respectively set
whether it’s through harmonic locking;
5) Harmonic blocking can lock across;
6) Each stage of the overcurrent protection can be respectively set
whether it’s blocked by composited voltage;
7) The protection of the input direction component needs to detect
whether the VT secondary circuit disconnects. If VT is disconnected,
the protection of the input direction component can be set as VT
failure existing protection or VT failure protection not existing
protection.

The input and output signals of overcurrent protection function diagram are
shown as follow:
162
Directional / Non-directional Overcurrent Protection

1 1
BIBlk Start
2
Operation
3
PhaseA
4
PhaseB
5
PhaseC
6
TripA
7
TripB
8
TripC
9
Trip3P
Figure 100 The input and output signals of overcurrent protection function diagram
Input:
OC*
BIBlk BI blocking function
Output:
Start IED startup
Operation IED trip

OCStage* Phase A meets overcurrent trip, phase A trip
PhaseA
signal
Phase B meets overcurrent trip, phase B trip
PhaseB
signal
Phase C meets overcurrent trip, phase C trip
PhaseC
signal
Output:
TripA Overcurrent protection trip phase A
FB_OC*Trip TripB Overcurrent protection trip phase B
TripC Overcurrent protection trip phase C
Trip3P Overcurrent protection trip three phase
Note: “*” in the table is the stage number of overcurrent protection.
IED is equipped with 4 stages overcurrent protection, please refer to the
setting list for details. The overvoltage protection stage 1 will be taken as
an example below and the principle will be introduced.
163

3.1.1 Inrush blocking components
Logic of inrush blocking recognition is shown as follow:
PhAI2/I1Ratio>“OC2ndHI2/I1Ratio”
≥1
PhBI2/I1Ratio>“OC2ndHI2/I1Ratio”
&
3PhInrushCurrBlk
PhCI2/I1Ratio>“OC2ndHI2/I1Ratio”
Time<“HarmCrossBlkTime”
Figure 101 Inrush blocking logic diagram

Note: three phase inrush blocking output can be used as input for other
protection functions with harmonic blocking.
When "OC1BlkBy2ndH"=1, inrush will be detected, the inrush criterion is
shown as below:
𝐈𝐈∅𝟐𝟐
> “𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎/𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈”, (∅ = 𝒂𝒂, 𝒃𝒃, 𝒄𝒄)
𝐈𝐈∅
When it is detected that the ratio of second harmonic and fundamental
wave is greater than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase.
When it is detected that there is inrush condition, within the
"HarmCrossBlkTime", one phase inrush protection fails and three phase
protection; after the "HarmCrossBlkTime", one phase inrush protection
fails and one phase protection; when the inrush criterion returns, release
each blocking.
When the maximum fundamental wave current of the three phases is
greater than " OCHarmUnblkCurr", release each blocking
The output blocking state of each phase is caused by inrush blocking of
overcurrent stage 1 phase A, phase B and phase C. Schematic diagram is
shown as follow.
164
3PhInrushCurrBlk
&
3PhInrushCurrBlkOfOC1
“OC1BlkBy2ndH”=1
& &
PhAInrushCurrBlkOfOC1
Time>“HarmCrossBlkTime”
“OC1stHI2/I1Ratio”=1
&
& PhBInrushCurrBlkOfOC1
&
& PhCInrushCurrBlkOfOC1
Figure 102 Logic diagram of overcurrent stage 1 inrush blocking
3.1.2 Composited voltage blocking unit

When “OCStage1BlkByVolt” =1, check the voltage. The voltage blocking
component is composited voltage component, including undervoltage and
negative sequence voltage components, composited voltage criterion:
𝐦𝐦𝐦𝐦𝐦𝐦(𝐔𝐔𝐔𝐔𝐔𝐔, 𝐔𝐔𝐔𝐔𝐔𝐔, 𝐔𝐔𝐔𝐔𝐔𝐔) < “𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏”𝐨𝐨𝐨𝐨𝐔𝐔𝟐𝟐 > “𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔”
When the "3PhVoltConnect" is 1, the low voltage or negative sequence
voltage is detected; when the "3PhVoltConnect" is 0, the negative
sequence voltage component exits.
min(Uab,Ubc,Uca)<“PPVoltBlkSet”
&
“3PhVoltConnect”=1
& ≥1
U2>“U2BlkSet” &
≥1 MultiVoltComponentMet
&
max(Uab,Ubc,Uca)<“PPVoltBlkSet”
“OCStage1BlkByVolt”=1
“OCStage1BlkByVolt”=0
Figure 103 The logic diagram of the characteristics of the composited voltage
component
3.1.3 Directional component

When "DirOCStage1"=1, direction check. Directional components are
165
connected with a 90° angle, the fault phase direction is determined by the
fault phase current and the phase-to-phase voltage of the sound phase.
When the "3PhVoltConnect" =0, the directional component is disabled, and
operates under the pure overcurrent mode.
Table 48 Fault phase direction detection
Phase Current Voltage

A Ia U bc
B Ib U ca
C Ic U ab
When the three-phase fault occurs, there is no sound phase voltage, which
is not enough to detect the fault current direction, so memory voltage is
adopted. Diagram forward and reverse direction characteristics of phase A
current:
90° IA
FWD 90° IA
Bisector
Bisector
RVD
Φ Φ
0° 0°
U BC_Ref U BC_Ref
5°
-IA -IA 5°
Figure 104 Forward or reverse direction interval
Overcurrent direction sensitive angle Φ =Angle: Adjustable;

Overcurrent directional range: 85;
Taking phase A as an example, direction detection logic diagram is shown
as follow.
VTFailBlk
&
“VTFailProtOff”=0
“3PhVoltConnect”=0 ≥1 PhADirComponentMet
PhAInTripZone &
OfCorrectDir
PhADirComponentMet
&
≥1
DirComponentMet
“DirOCStage1”=1
“DirOCStage1”=0
166
Figure 105 Direction detection logic diagram

In the process of direction detection and voltage detection, the VT failure
may lead actions or alarms that are not consistent with the flow direction
detection or the voltage detection along overcurrent protection stages.
When VT fails, the trip mode is decided according to "VTFailProtOff"; if
“VTFailProtOff” is set to 1, earth fault protection with voltage or directional
component is blocked; if “VTFailProtOff” is set to 0, voltage blocking
component and directional component exit and act in a pure overcurrent
mode.
3.1.4 Definite time
When "OCStage1Curve"=0, overcurrent is the definite time characteristic,
inverse time function is disabled.
𝐈𝐈∅ > “𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎”, (∅ = 𝒂𝒂, 𝒃𝒃, 𝒄𝒄)
When the phase-to-earth current is greater than"OCStage1CurrSet",
timing component starts and until "OCStage1Time“, overcurrent protection
trips, when the phase-to-earth current𝐈𝐈∅ < 𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃 × “𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎”,
Dropout is dropoff coefficient, timing component returns, overcurrent
protection resets.
3.1.5 Inverse time
When "OCStage1Curve"=1~13, overcurrent is the inverse time
characteristic, definite time function is disabled.
 
 
 A
=t + B ⋅T
  IΦ  P 
  −1 
  Iset  
Where:
A: "OCStage1InvTimeCoefA"
P: "InvTimeOCStage1IndexP"
B: "InvTimeOCStage1TimeB"
T: "InvTimeOCStage1ConstT"
Iφ: Phase current value in the system
Iset: "OCStage1CurrSet"
If the phase-to-earth current is greater than "OCStage1CurrSet", the timing
component starts, inverse time characteristic curve is selected by
"OCStage1Curve", A, P, B are determined when the value is from 1 to 12,
see the following table; when the value is 13, it is user defined
characteristics, calculate the trip delay according to the setting of the A, P,
B, T. While timing, overcurrent protection trips. When the delay is less than
the "OC1InvTimeMinTime", the component trips according to the
"OV1InvTimeMinTime"
167
Table 49 Curve definition
Curve Curve Characteristic A P B

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
3 IEC EXTERMELY INV. 80.0 2.0 0
4 IEC SHORT TIME INV. 0.05 0.04 0
5 IEC LONG TIME INV. 120.0 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
9 ANSI MODERATELY INV. 0.0103 0.02 0.0228
10 ANSI VERY INV. 3.922 2.0 0.0982
11 ANSI EXTERMELY INV. 5.64 2.0 0.02434
12 ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13 USER DEFINE
3.1.6 Trip characteristic

Overcurrent stage 1 is taken as an example: When overcurrent protection
function is enabled (En=1) and no BI blocking, if the "OCStage1On"=1, the
overcurrent stage 1 protection is enabled.
If the trip conditions are met, time component starts until "OCStage1Trip".
When IED trips, at the same time, each phase trip states will be displayed.
LED, IED output and others can be configured by AESP.
When "OC1BlkBy2ndH"=1, the harmonic locking component is put into
operation, when the trip timer is time out, the inrush current is checked,
and if the current is not locked, unblock overcurrent protection, otherwise it
will output “InrushBlk” report.
When "OCStage1BlkByVolt"=1, the composited voltage locking
component is put into the device. When the protection is started, the
device checks the composited voltage locking condition, unblock
overcurrent protection if the it meets the conditions, otherwise the
protection is locked.
When “DirOCStage1"=1, overcurrent protection is with the directional
component, and choose the forward or reverse direction characteristic
according to "OCStage1FwdDir", when the directional component is not
satisfied, overcurrent protection is blocked.
When the overcurrent component trips, at the same time, three-phase
current value of Ia, Ib and Ic will also be displayed.
3.1.7 Logic diagram
Stage1 of the overcurrent definite time logic diagram
168
Ia>“OC1CurrSet”
VTFailBlk
&
≥1 &
“VTFailProtOff”=1 OC1PhAStartup
DirComponentMet
MultiVoltComponentMet
OCProtFcnOn
OC1PhAStartup
& T1
&
BI Blk
& OC1ProtTrip
3PhInrushCurrBlkOfOC1
“OC1StageOn”=1
T1：“OCStage1Time”
Figure 106 Stage1 of the overcurrent definite time logic diagram

Configurable nodes in
Type IO Matrix Description Remark
configuration
Input OC*.BIBLK BI blocking function
OCStage*.Start IED startup
OCStage*.Operation IED trip

Phase A meets overcurrent trip, Configurable
OCStage*.PhaseA
phase A trip signal initiate
Phase B meets overcurrent trip, reclosing
OCStage*.PhaseB
phase B trip signal node
Output Phase C meets overcurrent trip,
OCStage*.PhaseC
phase C trip signal
FB_OC*Trip.TripA Overcurrent protection trip phase A
FB_OC*Trip.TripB Overcurrent protection trip phase B
FB_OC*Trip.TripC Overcurrent protection trip phase C

Overcurrent protection trip three
FB_OC*Trip.Trip3P
phase
169
3.3 Setting list

Table 51 Overcurrent protection setting
Default
No. Setting name Range Step Unit Remark
value
1. OCStage1CurrSet 0.05In~40In 40 0.01 A
2. OCStage1Time 0.00~100.00 100 0.01 s
3. OCStage1Curve 0~13 0 1
4. InvTimeOCStage1CoefA 0.001~1000 10 0.001 s
5. InvTimeOCStage1IndexP 0.01~10.00 10 0.01
6. InvTimeOCStage1TimeB 0.000~100.00 100 0.01 s
7. InvTimeOCStage1ConstT 0.025~1.5 0.025 0.001
8. InvTimeOCStage1MinTime 0.00~100.00 0.1 0.01 s
10. OCStage2Time 0.00~100.00 100 0.01 s
18. OCStage3Time 0.00~100.00 100 0.01 s
26. OCStage4Time 0.00~100.00 100 0.01 s
170
Default
value
33. DirOCSensitiveAngle 0.00~90.00 30 0.01 °
34. PPVoltBlkSet 1.00~120.0 30 0.01 V
35. U2BlkSet 0.05~100.0 3 0.01 V
36. HarmCrossBlkTime 0.000~100.00 100 0.01 s
37. OCHarmUnblkCurr 0.05In~40In 40 0.01 A Common

38. OC2ndHI2/I1Ratio 0.07~0.50 0.07 0.01 setting
Table 52 Overcurrent protection logic switch

1-Enable stage 1 of
1. OCStage1On 1/0 0 overcurrent, 0-Disable
stage 1 of overcurrent;
1-overcurrent stage 1 Dir
2. DirOCStage1 1/0 0 on, 0-Overcurrent stage 1
Dir off
1-overcurrent stage 1
forward direction,
3. OCStage1FwdDir 1/0 0
reverse direction
4. OCStage1BlkByVolt 1/0 0 voltage on, 0-Overcurrent
stage 1 voltage off
secondary harmonic on,
5. OC1BlkBy2ndH 1/0 0
0-Overcurrent stage 1
secondary harmonic off
1-Enable stage 2 of
Dir off
forward direction,
reverse direction
stage 2 voltage off
1-Enable stage 3 of
Dir off
171

forward direction,
reverse direction
stage 3 voltage off
1-Enable stage 4 of
Dir off
forward direction,
reverse direction
stage 4 voltage off
connection;
21. 3PhVoltConnect 1/0 1 0-single-phase voltage
connection
Common logic switch
1-VT failure protection
off, 0-VT failure
protection on
Common logic switch
3.4 Report list

Trip report:
1. OCStage1Trip /
2. OCStage2Trip /
3. OCStage3Trip /
4. OCStage4Trip /
5. OCStage1PhATrip /
6. OCStage1PhBTrip /
172
7. OCStage1PhCTrip /
Inrush conditions meet the requirements of
17. InrushBlk
blocking overcurrent protection
18. OCAuxStartup /

Table 54 Overcurrent protection technical data
Definite time characteristic
Current 0.05In~40.00In ≤ ±2.5% setting or ±0.02In

≤ ±1% setting or +40 ms,
Time delay 0.00~100.00s
At 2 times of trip current
Minimum trip time About equal to 10ms
Dropoff coefficient About 0.95, when I/In>0.4
Reset time About equal to 10ms

Inverse time characteristic

Normal inverse time
Very inverse time IEC60255-151
IEC standard ≤ ±5% setting or +40 ms,
Extreme inverse time
When 2<I/ISETTING<20
Long inverse time
Inverse time
Short inverse time
ANSI/IEEE C37.112,
Long inverse time
ANSI ≤ ±5% setting or +40 ms,
Medium inverse time
When 2<I/ISETTING<20
Very inverse time
173

Definite inverse time
 
  IEC60255-151
 A
User defined characteristic
=t + B ⋅T ≤ ±5% setting or +40 ms,
curve   IΦ  P  When 2<I/ISETTING<20
  − 1 
  Iset  
Time coefficient of inverse
0.001~1000s
time, A
Time delay of inverse time,
0.000s~100.00s
B
Inverse time index, P 0.01～10.00
Inverse time constant: T 0.025～1.5

Directional component
Trip angle range 170° ≤ ±3°,

when phase-to-phase
Sensitive Angle 0°~90° voltage >2V
Inrush blocking
Content Range and value Error

Harmonic unblocking phase
0.05In~40.00In ≤ ±2.5% setting or ±0.02In
current of overcurrent
Overcurrent secondary
0.07～0.5
harmonic I2/I1 ratio
Harmonic cross blocking
0.00s~100.00s ≤ ±1% setting or +40ms
time
174
Chapter 9 Earth fault protection (50N, 51N, 67N)
Chapter 9 Earth fault protection(50N,

51N, 67N)
About this chapter

This chapter describes the earth fault protection principle, the
input and output signals, setting parameters, messages and
175
1 Introduction
Under the condition of high resistance grounding fault in the neutral point
grounding system, the calculated impedance located out of the distance
impedance zone and the IED maloperate. Therefore, other protection trips
are needed to isolate the fault, earth fault protection can reliably identify
high resistance grounding fault. For example, in the double circuit lines,
the directional earth fault protection simultaneously distinguishes the size
and direction of fault current and cooperates with other protection devices
in the system.
The characteristics of earth fault protection are listed as follow:
1) Definite-time of 4 stage, inverse-time limit (including all IEC/ANSI
standard inverse-time characteristic);
2) The direction feature of each stage is Independently selectable;
3) Negative sequence directional component (optional);
4) The inrush blocking feature of each stage is independently
(selectable);
5) Inrush locking is distinguished by secondary harmonic currents;
6) The maximum current of open magnetizing inrush current can be
adjusted;
7) VT failure blocking directional earth fault protection;
8) Single phase trip or three-phase trip can be selected by the logic
switch for the four definite time stages. Note, when the protection IED
is used for the voltage level of single phase trip, it is suggested to
enable the stage 1 or stage 2 of earth fault protection, the high
impedance earth fault can be fast and reliably isolated;
9) The earth fault protection is blocked during the open-phase period.

The input and output signals of earth fault protection function are shown as
follow:
Directional / Non-directional Zero
Overcurrent Protection
1 1
BIBlk Start
2
Operation
1Directional/Non-directional Zero Overcurrent

Protection_SeltTrip
1 1
BIBlk Start
2
Operation
3
TripA
4
TripB
5
TripC
6
Trip3P
Figure 107 The input and output signals diagram of earth fault protection function
176
right.
Input:
EF*
BIBlk BI blocking
Output:
EFStage* Start IED startup
Operation IED trip
The input and output of single phase trip module of earth fault protection
Input:
EF*SeltTrip
BIBlk BI blocking
Output:
Start IED startup
Operation IED trip
EFStage*SeltTrip TripA Trip phase A of earth fault protection
TripB Trip phase B of earth fault protection
TripC Trip phase C of earth fault protection
Trip3P Trip three phases of earth fault protection
Note: “*” in the table is the stage number of earth fault protection.
IED is equipped with 4 stages earth fault protection, please refer to the
setting list for details. Take zero sequence stage 1 protection as an
example to explain the principle.

When "3I0Stage1BlkBy2ndH"=1, inrush will be detected. There are two
inrush criteria:
Check phase current harmonics and external zero sequence current
harmonic.
1) Only when "3I0HarmonChkExtrI02/I01"=1, and "Extr3I0"=1, zero
sequence current harmonic is detected.
wave is greater than "3I02ndHI02/I01" and there is zero sequence current,
then the zero sequence inrush condition is satisfied.
When the maximum fundamental wave of zero sequence current is greater
than "3I0HarmUnblkCurr", release each blocking.
177
2) In addition to the first case, detect the phase current harmonic.

When the maximum fundamental wave of phase current is greater than "
OCHarmUnblkCurr", release each blocking.
Output locking statue when any of the above second harmonic check
method is satisfied, the secondary harmonic current is high.
3I0>“3I0UnblkHarmBlkCurr”
&
&
3I02/3I0>“3I02ndHI02/I01Ratio”
“Extr3I0”=1
& ≥1
2ndH HighCurr
“3I0HarmonChkExtrI02/I01”=1
Imax>“HarmUnblkPhCurr” &
Ia2/Ia1>“OC2ndHI02/I01Ratio”
≥1
Ib2/Ib1>“OC2ndHI02/I1Ratio”
Ic2/Ic1>“OC2ndHI02/I1Ratio” 3I02/3I0:3I02ndH/3I0FundWave
Ia2/Ia1：
PhACurr2ndH/PhACurrFundWave
Ib2/Ib1：
PhBCurr2ndH/PhBCurrFundWave
Ic2/Ic1：
PhCCurr2ndH/PhCCurrFundWave
Figure 108 Logic diagram of the secondary harmonic blocking of earth fault protection
3.1.2 Directional component

1) Zero sequence direction component
In order to meet the different operating conditions of power system, the
reference voltage can be clockwise rotate 0 to 90°according to the
"3I0DirectSensitiveAngle". this setting influences direction characteristics
of each stage. The reference voltage vector after rotation is closer to the
𝟑𝟑𝟑𝟑𝟎𝟎 angle Φd −𝟑𝟑𝟑𝟑𝟎𝟎 , which makes the direction distinguishing more
sensitive. Rotate reference voltage vector to define the forward direction
and reverse direction trip zone. The direction range of the forward direction
is rotating voltage reference vector for the vertical bisector between -80
degrees and +80 degrees. If −𝟑𝟑𝟑𝟑𝟎𝟎 vector is in this zone, the device is
considered to be in forward direction.
An example is given to illustrate the direction detection of A phase faults. In
the figure,𝟑𝟑𝟑𝟑𝟎𝟎 leads 𝟑𝟑𝟑𝟑𝟎𝟎 , so−𝟑𝟑𝟑𝟑𝟎𝟎 lags 𝟑𝟑𝟑𝟑𝟎𝟎 , the reference voltage 𝟑𝟑𝟑𝟑𝟎𝟎
vector rotates "3I0DirectSensitiveAngle", in order to be closer to vector
−𝟑𝟑𝟑𝟑𝟎𝟎 . In addition, the yellow area in the diagram is a forward direction.
178
3I 0 90°
3I 0 90°
Reverse
10° 10°
0° 0°
3 U 0_Ref 3U 0_Ref
Φ0 Φ0
Forward Bisector Bisector
-3 I 0 -3 I 0
Figure 109 Zero sequence directional element diagram

Where:
Ф0:"3I0DirectSensitiveAngle" is settable;
Zero sequence current directional range: 80;
2) Negative sequence direction component
When "3I0ChkU2I2DirOn"=1, and the zero sequence current is small, then
input the negative sequence directional component. For example, zero
sequence current mutual coupling or uncertain zero sequence directional
impedance happen in the double circuit line. Here, it is necessary to input
the negative sequence directional component to detect the fault current
direction, the logic switch “3I0ChkU2I2DirOn” is set to 1. Here, it is still the
default enabling zero sequence direction detection. However, when 𝟑𝟑𝟑𝟑𝟎𝟎
is less than 1V and 𝟑𝟑𝟑𝟑𝟐𝟐 is greater than 2V, it is converted into negative
sequence direction detection, and the negative sequence component is
used to detect the direction.
Negative sequence directional characteristics diagram:
3I 2 90°
3I 2 90°
Reverse
10° 10°
0° 0°
3 U 2-Ref 3U 2-Ref
Φ2 Φ2
Forward Bisector Bisector
-3 I 2 -3 I 2
Figure 110 Negative sequence directional characteristic diagram

Where:
179
Negative sequence current directional range: 80;

In the process of direction detection, the VT failure may lead actions or
alarms that are not consistent with the flow direction detection or the
voltage detection along overcurrent protection stages. When VT fails, the
trip mode is decided according to "VTFailProtOff"; if “VTFailProtOff” is set
to 1, earth fault protection with voltage or directional component is blocked;
if “VTFailProtOff” is set to 0, voltage blocking component and directional
component exit and act in a pure overcurrent mode.
When the "3PhVoltConnect" =0, the directional component is disabled, and
operates under the pure overcurrent mode.
VTFailBlk
&
3I0FwdDirZone
&
≥1 FwdDir
3U0>1V
“3I0ChkU2I2DirOn”=1 &
U2FwdDirZone
3U2>2V
3I0FwdDirZone: to calculate in accordance with 90°connection mode, and 3I0 is in direction
zone.
U2FwdDirZone: to calculate in accordance with 90°connection mode, and U2 is in direction
zone.
Figure 111 Directional zero sequence current sensitive angle logic diagram
3.1.3 Definite time

When "3I0Stage1Curve"=0, earth fault protection is the definite time
characteristic, inverse time function is disabled.
𝟑𝟑𝐈𝐈𝟎𝟎 > “𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑”
When zero sequence current is greater than "3I0Stage1CurrSet", timing
component starts and until "3I0Stage1Time“, earth fault protection trips,
when 𝟑𝟑𝐈𝐈𝟎𝟎 < 𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃 × “𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑” , Dropout is dropoff
coefficient, timing component returns, earth fault protection returns.
3.1.4 Inverse time
When "3I0Stage1Curve"=1~13, earth fault protection is the inverse time
 
 
 A 
=t  P
+ B  ⋅T
  3 I  
0
−1
  3I 0set  
Where:
A: "InvTime3I0Stage1CoefA"
P: "InvTime3I0Stage1IndexP"
B: "InvTime3I0Stage1TimeB"
180
T: "InvTime3I0Stage1ConstT"
3I0: Zero sequence current setting
3I0set: "3I0Stage1CurrSet"
If the current is greater than "3I0Stage1CurrSet", the timing component
starts, inverse time characteristic curve is selected by "3I0Stage1Curve", A,
P, B are determined when the value is from 1 to 12, see the following table;
when the value is 13, it is user defined characteristics, calculate the trip
delay according to the setting of the A, P, B, T. While timing, earth fault
protection trips. When the calculated delay is less than the
"EF1InvTimeMinTime", the component trips according to the
"EF1InvTimeMinTime".

0 Definite time
1 IEC INV. 0.14 0.02 0

2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE
Note: The selecting trip module of earth fault only supports definite time
mode, not inverse time mode.
Take earth fault protection stage 1 as an example. When earth fault
protection is enabled and there is no binary input blocking, if
"3I0Stage1On"=1, then earth fault protection stage 1 is enabled.
If the trip conditions are met, time component starts until "3I0Stage1Trip".
When IED trips, at the same time, each phase trip states will be displayed.
LED, IED output and others can be configured by AESP.
When "3I0Stage1BlkBy2ndH"=1, the harmonic locking component is put
into operation, when the trip timer is time out, the inrush current is checked,
and if the current is not locked, unblock earth fault protection, otherwise it
will output “InrushBlocking” report.
181
When "ZSOCStage1DirOn"=1, protection is with the directional component,

and choose the forward or reverse direction characteristic according to
"ZSOCStage1PositiveDir", when the directional component is not satisfied,
earth fault protection is blocked.
When "CTFailDetectOn"=1, enable “CTFailBlk3I0” logic switch, then the
CT failure blocking earth fault protection, otherwise unblocking earth fault
protection.
component trip triggers action, meanwhile output analog quantity of trip
time, when the component is based on the self-produce zero sequence
current judgment, self-produce zero sequence current is output; when it is
based on the external zero sequence current, external zero sequence
current is output.
Take earth fault protection stage 1 as an example. When the trip conditions
of stage 1 of earth fault protection is met, and the
"DefTime3I0Stage1SelTripOn"=1, according to the phase selection result,
the stage 1 of earth fault protection can trip the corresponding phase. The
trip logic diagram is shown in Figure 113 .
3.1.7 Logic diagram
Logic diagram with the definite time overcurrent Stage 1 as example
&
VTFailBlk
3I0>“3I0Stage1CurrSet”
&
≥1 T1
BI Blk
& &
CTFailBlk
3I0Stage1Trip
“CTFailBlk3I0”=1
&
FwdDir ≥1
“3I0Stage1FowardDir”=1
“Dir3I0Stage1”=1
2H HighCurr &
“3I0Stage1BlkBy2ndH”=1
“3I0Stage1On”=1
Open-phase operation
3I0Stage1ProtFcnOn
T1:“3I0Satge1Time”
Figure 112 Logic diagram of earth fault protection function

The figure below is the trip logic diagram of earth fault protection, the part
in the dotted frame is the logic with auto-reclosing function. Take phase A
as an example for single phase fault and take phase AB as an example for
phase-to-phase fault.
182
“DefTime3I0Stage1SelTripOn”
Phase selection: PhA
≥1 &
“1PhARModeOn”
“1/3PhARModeOn”
EF stage 1 trip &
BI:Enforced3PhTrip &
≥1
Trip PhA
“3PhTripMode”
BO:Enforced3PhTrip
& ≥1
Phase selection: PhAB ≥1 Trip PhABC
Phase selection: PhABC
EF stage 1 trip (inverse time)
Figure 113 Trip logic diagram of earth fault protection

Configurable nodes in IO
Type Description Remark
Matrix configuration
Input EF*.BIBLK BI blocking function
EFStage*.Start IED startup

Output Configurable
EFStage*.Operation IED trip initiate
reclosing node
The selecting trip module of earth fault protection
Input EF*SeltTrip.BIBLK BI blocking function
EFStage*SeltTrip.Start IED startup

EFStage*SeltTrip.Operati
IED trip
on
Trip phase A of earth fault Configurable
EFStage*SeltTrip.TripA
protection initiate
Output Trip phase B of earth fault reclosing node
EFStage*SeltTrip.TripB
protection
Trip phase C of earth fault
EFStage*SeltTrip.TripC
protection
Trip three phases of earth fault
EFStage*SeltTrip.Trip3P
protection
Note: “*” in the table is the stage number of earth fault protection.
183
3.3 Setting list

Table 58 Earth fault protection setting
Default
value
Three times of
1. 3I0Stage1CurrSet 0.05In~40In 40 0.01 A zero sequence
current
2. 3I0Stage1Time 0.00～100.00 100 0.01 s
0: Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7:ANSI
SHORT INV.
3. 3I0Stage1Curve 0～13 0 1
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
4. InvTime3I0Stage1CoefA 0.001～1000 10 0.001 s
5. InvTime3I0Stage1IndexP 0.01～10.00 10 0.01

0.000～
6. InvTime3I0Stage1TimeB 100 0.01 s
100.00
7. InvTime3I0Stage1ConstT 0.025～1.5 0.025 0.001
8. InvTime3I0Stage1MinTime 0.00～100.00 0.1 0.01 s

Three times of
current
10. 3I0Stage2Time 0.00～100.00 100 0.01 s
184
Default
value
0.000～
100.00

Three times of
current
18. 3I0Stage3Time 0.00～100.00 100 0.01 s

0.000～
100.00

Three times of
current
26. 3I0Stage4Time 0.00～100.00 100 0.01 s

0.000～
30. InvTime3I0Stage4IndexB 100 0.01 s
100.00
31. InvTime3I0Stage4IndexT 0.025～1.5 0.025 0.001
33. 3I0DirectSensitiveAngle 0.00～90.00 70 0.01 °
34. NSDSensitiveAngle 0.00～90.00 70 0.01 °

Common
setting
36. 3I0HarmUnblkCurr 0.05In~40In 40 0.01 A
37. OC2ndHI2/I1Ratio 0.07～0.50 0.07 0.01
38. 3I02ndHI02/I01 0.07～0.50 0.07 0.01
185
Table 59 Earth fault protection logic switch

Default
value
1-Enable stage 1 of earth fault
1. 3I0Stage1On 1/0 0 protection:, 0-Disable stage 1 of
earth fault protection:
1-Phase selection trip of stage
1 of earth fault protection stage
2. DefTime3I0Stage1SelTripOn 1/0 1
1; 0-Three-phase trip of stage 1
of earth fault protection
1-earth fault protection stage 1
3. Dir3I0Stage1 1/0 0 Dir on, 0-earth fault protection
stage 1 Dir off
forward direction, 0-earth fault
4. 3I0Stage1FwdDir 1/0 0
protection stage 1 reverse
direction
secondary harmonic blocking
5. 3I0Stage1BlkBy2ndH 1/0 0 on, 0-earth fault protection
stage 2 secondary harmonic
blocking off
stage 2 Dir off
direction
blocked by secondary
10. 3I0Stage2BlkBy2ndH 1/0 0 harmonic; 0-earth fault
protection stage 2 is not
blocked by secondary harmonic
stage 3 Dir off
direction
15. 3I0Stage3BlkBy2ndH 1/0 0
on, 0-earth fault protection
186
Default
value
blocking off

stage 4 Dir off
direction
20. 3I0Stage4BlkBy2ndH 1/0 0 on, 0-earth fault protection
blocking off
1: check negative sequence
21. 3I0ChkU2I2DirOn 1/0 0 direction; 0: don't check
negative sequence direction
1-Zero sequence current
harmonics checking external
22. 3I0HarmonChkExtrI02/I01 1/0 0 connection I02/I01; 0-Zero
sequence current harmonics
checking phase current I2/I1
23. CTFailBlk3I0 1/0 1 0-open; 1-lock.
current; 0-self-produced zero
24. Extr3I0 1/0 0
sequence current
Common setting
0-open; 1-lock.
Common setting
connection; 0-single-phase
voltage connection
Common setting
187
3.4 Report list

Trip report:
1. 3I0Stage1Trip /
2. 3I0Stage2Trip /
3. 3I0Stage3Trip /
4. 3I0Stage4Trip /
If inrush conditions meet the requirements, block
5. InrushBlk
When the “DefTime3I0Stage1SelTripOn” is
6. 3I0Stage1TripFail3PhTrip
enable, the report issues

Table 61 Earth fault protection technical data



Normal inverse time
IEC standard ≤ ±5% setting or +40 ms,
When 2<3I0/3I0set<20
Long inverse time
Inverse time
Short inverse time
Long inverse time ANSI/IEEE C37.112,
ANSI Medium inverse time ≤ ±5% setting or +40 ms,
Very inverse time When 2<3I0/3I0set<20
188
User defined characteristic IEC60255-151

curve
0.001~1000.0s
time, A
Time delay of inverse time, B 0.000~100.00s
Directional component
Zero sequence direction
160°
component trip angle range
≤ ±3°, when 3U0≥1V
Sensitive angle of directional
0°~90°
zero sequence
Negative sequence direction
160°
component trip angle range
≤ ±3°, when 3U2≥2V
Sensitive angle of directional
0°~90°
negative sequence
189
Chapter 10 Emergency overcurrent protection（50,51）
Chapter 10 Emergency overcurrent

protection（50,51）
About this chapter

This chapter describes the emergency overcurrent
principlethe input and output signals, setting value
parameters, messages and technical parameters.
191
1 Introduction
In case of VT failure, the distance protection and voltage related protection
are locked. At this time, the emergency overcurrent protection put into
operation.
Emergency overcurrent protection is backup overcurrent protection without
direction.
Main characteristics of emergency overcurrent protection:
1) The device provides 2 stages of emergency overcurrent protection,
each stage adopts definite time-lag or 12 IEC and ANSI standard
curve of inverse time characteristic, and it adopts user-defined
characteristic curve as well;
2) Under VT failure condition，emergency overcurrent protection is
enabled；
3) Each section of the emergency overcurrent protection can be
respectively set whether it’s through harmonic locking;
4) Harmonic blocking can lock across;
5) The maximum current of open harmonic blocking can be adjusted.

Input and output signals of the emergency overcurrent protectionfunction
are shown as follow:
Emergency Overcurrent Proteciton

1 1
BIBlk Start
2
Operation
3
PhaseA
4
PhaseB
5
PhaseC
6
TripA
7
TripB
8
TripC
9
Trip3P
Figure 114 The input and output signals of emergency overcurrent protection function
diagram
192
Input：
EMOC*
BIBlk BI blocking function
Output：
Start IED startup
Operation IED trip

EMOCStage* Phase A meets emergency
PhaseA
overcurrent trip, phase A trip signal
Phase B meets emergency
PhaseB
overcurrent trip, phase B trip signal
Phase C meets emergency
PhaseC
overcurrent trip, phase C trip signal
Output：
emergency overcurrent protection trip
TripA
phase A
FB_EMOC*Trip TripB
phase B
TripC
phase C
Trip3P
three phase
Note: “*” in the table is the stage number of emergency overcurrent
protection.
IED is equipped with 2 stages emergency overcurrent protection , please
refer to the setting list for details. Take emergency overcurrent stage 1
protection as an example to explain the principle.

Logic of inrush blocking recognition is shown as follow：
≥1
&
3PhInrushCurrBlk
Time<“EmOCHarmCrossBlkTime”
Figure 115 Inrush blocking logic diagram

Note: three phase inrush blocking output can be used as input for other
protection functions with harmonic blocking.
When " EmOCStage1BlkBy2ndH "=1, inrush will be detected, the inrush
criterion is shown as below:
193
𝐈𝐈∅𝟐𝟐
> “𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎/𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈”, (∅ = 𝒂𝒂, 𝒃𝒃, 𝒄𝒄)
𝐈𝐈∅
When it is detected that there is inrush condition, within the
"EmOCHarmCrossBlkTime", one phase inrush protection fails and three
phase protection; after the "EmOCHarmCrossBlkTime", one phase inrush
protection fails and one phase protection; when the inrush criterion returns,
release each blocking.
When the maximum fundamental wave current of the three phases is
greater than " OCHarmUnblkCurr", release each blocking
The output blocking state of each phase is caused by inrush blocking of
emergency overcurrent stage 1 phase A, phase B and phase C.
Schematic diagram is shown as follow.
3PhInrushCurrBlk
& 3PhInrushCurrBlkOfEmOC1
“EmOCStage1BlkBy2ndH”=1
& &
PhAInrushCurrBlkOfEmOC1
Time>“EmOCHarmCrossBlkTime”
“EmOC1stHI2/I1Ratio”=1
&
& PhBInrushCurrBlkOfEmOC1
&
& PhCInrushCurrBlkOfEmOC1
Figure 116 Logic diagram of emergency overcurrent stage 1 inrush blocking
3.1.2 Definite time

When "EmOCStage1Curve"=0, emergency overcurrent is the definite
time characteristic, inverse time function is disabled.
𝐈𝐈∅ > “𝐄𝐄𝐦𝐦𝐎𝐎𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐎𝐎𝐒𝐒𝟏𝟏𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒”, (∅ = 𝒂𝒂, 𝒃𝒃, 𝒄𝒄)
When the phase-to-earth current is greater than"EmOCStage1CurrSet",
timing component starts and until "EmOCSatge1Time“, emergency
overcurrent protection trips, when the phase-to-earth current 𝐈𝐈∅ <
𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃 × “𝐄𝐄𝐦𝐦𝐎𝐎𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐎𝐎𝐒𝐒𝟏𝟏𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒”, Dropout is dropoff coefficient, timing
component returns, emergency overcurrent protection resets.
194
3.1.3 Inverse time

When "EmOCStage1Curve"=1~13, emergency overcurrent is the inverse
time characteristic, definite time function is disabled.
 
 
A
=t  + B  ⋅T
  IΦ  P 
  − 1 
  Iset  
Where:
A：“InvTimeEmOCStage1CoefA”
P：“InvTimeEmOCStage1IndexP”
B：“InvTimeEmOCStage1TimeB”
T：“InvTimeEmOCStage1ConstT”
Iφ：Phase current value in the system
Iset：“EmOCStage1CurrSet”
If the phase-to-earth current is greater than "EmOCStage1CurrSet", the
timing component starts, inverse time characteristic curve is selected by
"EmOCStage1Curve", A, P, B are determined when the value is from 1 to
12, see the following table; when the value is 13, it is user defined
B, T. While timing, emergency overcurrent protection trips. When the delay
is less than the "InvTimeEmOCStage1MinTime", the component trips
according to the "InvTimeEmOCStage1MinTime".

0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE
195

Emergency overcurrent satge 1 is taken as an example: When VT failure
and no BI blocking, if the "EmOCStage1On"=1, the emergency overcurrent
stage 1 protection is enabled.
If the trip conditions are met, time component starts until
"EmOCStage1Trip". When IED trips, at the same time, each phase trip
states will be displayed. LED, IED output and others can be configured by
AESP.
When " EmOCStage1BlkBy2ndH"=1, the harmonic locking component is
put into operation, when the trip timer is time out, the inrush current is
checked, and if the current is not locked, unblock emergency overcurrent
protection trip.
When the emergency overcurrent component trips, at the same time,
three-phase current value of Ia, Ib and Ic will also be displayed.
3.1.5 Logic diagram
Stage1 of the emergency overcurrent definite time logic diagram.
Ia>“EmOCStage1CurrSet”
&
VTFailBlk EmOCStage1PhAStartup
“EmOCStage1On”=1
EmOCStage1PhAStartup &
T1 &
EmOCStage1Trip
BI Blk
3PhInrushCurrBlkOfEmOC1
T1：“EmOCSatge1Time”
Figure 117 Stage1 of the emergency overcurrent definite time logic diagram

Configurable node in
Type IO Matrix Description
configuration
Input EMOC*.BIBLK BI blocking function
EMOCStage*.Start IED startup

EMOCStage*.Operati
IED trip
on
Phase A meets emergency Configurable
EMOCStage*.PhaseA initiate
overcurrent trip，A trip singal
Output Phase B meetsemergency reclosing
EMOCStage*.PhaseB node
overcurrent trip，B trip singal
Phase C meets emergency
EMOCStage*.PhaseC
overcurrent trip，C trip singal
Emergency overcurrent protection trip
FB_EMOC*Trip.TripA
phase A
196
Emergency overcurrent protection trip

FB_EMOC*Trip.TripB
phase B
FB_EMOC*Trip.Trip Emergency overcurrent protection trip
C phase C
FB_EMOC*Trip.Trip3 Emergency overcurrent protection trip
P three phase
Note: “*” in the table is the stage number of emergency overcurrent
protection.
3.3 Setting list

Table 65 Overcurrent protection setting
Default
value
1. EmOCStage1CurrSet 0.05In~40In 40 0.01 A
2. EmOCSatge1Time 0.00~100.00 100 0.01 s
3. EmOCStage1Curve 0~13 0 1
4. InvTimeEmOCStage1CoefA 0.001~1000 10 0.001 s
5. InvTimeEmOCStage1IndexP 0.01~10.00 10 0.01
6. InvTimeEmOCStage1TimeB 0.000~100.00 100 0.01 s
7. InvTimeEmOCStage1ConstT 0.025~1.5 0.025 0.001
8. InvTimeEmOCStage1MinTime 0.00~100.00 0.1 0.01 s
9. EmOCStage2CurrSet 0.05In~40In 40 0.01 A
10. EmOCSatge2Time 0.00~100.00 100 0.01 s
11. EmOCStage2Curve 0~13 0 1
12. InvTimeEmOCStage2CoefA 0.001~1000 10 0.001 s
13. InvTimeEmOCStage2IndexP 0.01~10.00 10 0.01
14. InvTimeEmOCStage2TimeB 0.000~100.00 100 0.01 s
15. InvTimeEmOCStage2ConstT 0.025~1.5 0.025 0.001
16. InvTimeEmOCStage2MinTime 0.00~100.00 0.1 0.01 s
17. EmOCHarmCrossBlkTime 0.000~100.00 100 0.01 s
18. OCHarmUnblkCurr 0.05In~40In 40 0.01 A Common

Table 66 Overcurrent protection logic switch

Default
value
1-Enable stage 1 of
emergency overcurrent ；
1. EmOCStage1On 1/0 0
0-Disable stage 1 of
emergency overcurrent
1- emergency overcurrent
2. EmOCStage1BlkBy2ndH 1/0 0
197
Default
value
on；
off
1- Enable stage 2 of
emergency overcurrent ；
3. EmOCStage2On 1/0 0
0- Disable stage 2 of
emergency overcurrent
4. EmOCStage2BlkBy2ndH 1/0 0 on；
stage2 secondary harmonic off
1-Three phase voltage
connection；0-single-phase
voltage connection
Common logic switch
3.4 Report list

Trip report：
1. EmOCStage1Trip /
2. EmOCStage2Trip /

Table 68 Emergency overcurrent protection technical data
Current 0.05In~40.00In ≤±2.5% setting or ±0.02In

≤±1%±1% setting or +40 ms,
Dropoff coeffficient About 0.95, when I/In>0.4
Current 0.05In~40.00In ≤±2.5% setting or ±0.02In

Normal inverse time
IEC standard ≤±5% setting or +40 ms,
When 2<I/Iset<20
Long inverse time
Inverse time
ANSI/IEEE C37.112，
Short inverse time
ANSI ≤±5% setting or +40ms，
Long inverse time
Medium inverse time When 2<I/Iset<20
198

Very inverse time
IEC60255-151
≤±5% setting or +40ms，
curve
When 2<I/Iset<20
0.001~1000s
time, A
0.000s~100.00s
B
Inverse time index, P 0.01~10.00
Inverse time constant: T 0.025~1.5

About equal to 0.95, when
Dropoff coefficient
I/In>0.4
Inrush blocking
Content Range and value Error

Harmonic unblocking phase
0.05In~40.00In ≤±2.5% setting or ±0.02In
current of overcurrent
Overcurrent secondary
0.07~0.5
harmonic I2/I1 ratio
Emergency overcurrent
harmonic cross blocking 0.00s~100.00s ≤±1% setting or +40ms
time
199
Chapter 11 Emergency earth fault protection（50N,51N）
Chapter 11 Emergency earth fault

protection（50N,51N）
About this chapter

This chapter describes the emergency earth fault principle,
the input and output signals, setting parameters, messages
201
1 Introduction
In case of VT failure, the distance protection and voltage related protection
are locked. At this time, the emergency earth fault protection is on.
Emergency earth fault protection is the backup emergency earth fault
protection without direction。
The characteristics of emergency earth fault protectionare listed as follows：
1) The device provides 2 stages of emergency earth fault protection,
each stage adopts definite time-lag or 12 IEC and ANSI standard
curve of inverse time characteristic, and it adopts user-defined
characteristic curve as well;
2) In case of VT failure, emergency earth fault protection is enabled；
3) CT failure blocking emergency earth fault protection can be set；
4) Emergency earth fault protection is blocked during the open-phase
period.
5) Emergency earth fault protection of each stage can be set whether
harmonic blocking is on；
6) Inrush locking is distinguished by secondary harmonic currents;
7) Zero current open harmonic blocking maximum current can be set.

The input and output signals of emergency earth fault protection function
Emergency Zero OVercurrent
Protection
1 1
BIBlk Start
2
Operation
Figure 118 The input and output signals diagram ofemergency earth fault protection
function
right.
Input:
EMEF*
BIBlk BI blocking
Output:
EMEFStage* Start IED startup
Operation IED trip
Note: “*” in the table is the stage number of emergency earth fault
202
protection.
IED is equipped with satge 2 emergency earth fault protection, please refer
to the setting list for details. Take emergency earth fault stage 1 protection
as an example to explain the principle.
3.1 Protection Principle

When “Em3I0Stage1BlkBy2ndH” =1, inrush will be detected. There are
two inrush criteria:
Check phase current harmonics and external zero sequence current
harmonic.
1) Only when “Em3I0HarmChkExtrI02/I01”=1, and “Extr3I0”=1, zero
sequence current harmonic is detected.
wave is greater than " 3I02ndHI02/I01Ratio" and there is zero sequence
current, then the zero sequence inrush condition is satisfied.
When the maximum fundamental wave of zero sequence current is greater
than "3I0HarmUnblkCurr", release each blocking.
2) In addition to the first case, detect the phase current harmonic.
When the maximum fundamental wave of phase current is greater than "
OCHarmUnblkCurr", release each blocking.
Output locking statue when any of the above second harmonic check
method is satisfied, the secondary harmonic current is high.
3I0>“3I0HarmUnblkCurr” &
&
3I02/3I0>“3I02ndHI02/I01Ratio”
“Extr3I0”=1 & ≥1
2ndH HighCurr
Em3I0HarmChkExtrI02/I01=1
&
Imax>"OCHarmUnblkCurr"
Ia2/Ia1>"OC2ndHI2/I1Ratio"
≥1
Ib2/Ib1>"OC2ndHI2/I1Ratio"
Ic2/Ic1>"OC2ndHI2/I1Ratio"
3I02/3I0:3I02ndH/3I0FundWave
Ia2/Ia1：PhACurr2ndH/PhACurrFundWave
Ib2/Ib1：PhBCurr2ndH/PhBCurrFundWave
Ic2/Ic1：PhCCurr2ndH/PhCCurrFundWave
Figure 119 Logic diagram of the secondary harmonic blocking of emergency earth fault
203
protection
3.1.2 Definite time

When “Em3I0Stage1Curve”=0, emergency earth fault is the definite time
𝟑𝟑𝐈𝐈𝟎𝟎 > “𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄”
When zero sequence current is greater than "Em3I0Stage1CurrSet",
timing component starts and until " Em3I0Stage1Time “, emergency earth
fault protection trips, when 𝟑𝟑𝐈𝐈𝟎𝟎 < 𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃 × “𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄𝐄” ,
Dropout is dropoff coefficient, timing component returns, emergency earth
fault protection returns.
3.1.3 Inverse time
When " Em3I0Stage1Curve "=1~13, emergency earth fault is the inverse
 
 
 A 
=t  P
+ B ⋅T
  3I 0  − 1 
  3I 0set  
Where:
A：“InvTimeEm3I0Stage1CoefA”
P：“InvTimeEm3I0Stage1IndexP”
B：“InvTimeEm3I0Stage1TimeB”
T：“InvTimeEm3I0Stage1ConstT”
3I0： Zero sequence current setting
3I0set：“Em3I0Stage1CurrSet”
If the current is greater than "Em3I0Stage1CurrSet", the timing component
starts, inverse time characteristic curve is selected by "
Em3I0Stage1Curve ", A, P, B are determined when the value is from 1 to
12, see the following table; when the value is 13, it is user defined
B, T. While timing, emergency earth fault protection trips. When the
calculated delay is less than the " InvTimeEm3I0Stage1MinTime ", the
component trips according to the " InvTimeEm3I0Stage1MinTime ".
0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
204
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

Take emergency earth fault protection stage 1 as an example. When VT
failure and there is no binary input blocking, if “Em3I0Stage1On”=1, then
emergency earth fault stage 1 is enabled.
If the trip conditions are met, time component starts until "
Em3I0Stage1Trip ". When IED trips, at the same time, each phase trip
states will be displayed. LED, IED output and others can be configured by
AESP.
When " Em3I0Stage1BlkBy2ndH "=1, the harmonic locking component is
put into operation, when the trip timer is time out, the inrush current is
checked, and if the current is not locked, unblock emergency earth fault
protection.
When "CTFailDetectOn"=1, enable “CTFailBlkEm3I0” logic switch, then
the CT failure blocking emergency earth fault protection, otherwise
unblocking emergency earth fault protection.
Component trip triggers action, meanwhile output analog quantity of trip
time, when the component is based on the self-produce zero sequence
current judgment, self-produce zero sequence current is output; when it is
based on the external zero sequence current, external zero sequence
current is output.
3.1.5 Logic diagram
Logic diagram with the definite time emergency earth fault stage 1 as
example
205
VTFailBlk
3I0>“Em3I0Stage1CurrSet”
&
≥1 T1
BIBlk
& &
CTFailBlk
Em3I0Stage1Trip
“CTFailBlkEm3I0”=1
“Em3I0Stage1On”=1
2ndH HighCurr &
“Em3I0Stage1BlkBy2ndH”=1
T1：“Em3I0Stage1Time”
Figure 120 Logic diagram of emergency earth fault protection function
3.2 Configuration nodes by the user

Type Description
configuration
Input EMEF*.BIBLK BI blocking function
EMEFStage*.Start IED startup

Output IED trip (Configurable initiate
EMEFStage*.Operation
reclosing node)
Note: “*” in the table is the stage number of emergency earth fault
protection.
3.3 Setting list

Table 72 Emergency earth fault protection setting
Default
value
Three times of
1. Em3I0Stage1CurrSet 0.05In~40In 40 0.01 A zero sequence
current
2. Em3I0Stage1Time 0.00~100.00 100 0.01 s
0：Definite
time
1：IEC INV.
2：IEC VERY
INV.
3：IEC
EXTERMELY
3. Em3I0Stage1Curve 0~13 0 1 INV.
4：IEC
SHORT TIME
INV.
5：IEC LONG
TIME INV.
6：ANSI INV.
7：ANSI
206
Default
value
SHORT INV.
8：ANSI
LONG INV.
9：ANSI
MODERATELY
INV.
10：ANSI
VERY INV.
11：ANSI
EXTERMELY
INV.
12：ANSI
DEFINITE INV.
13：User
defined
4. InvTimeEm3I0Stage1CoefA 0.001~1000 10 0.001 s
5. InvTimeEm3I0Stage1IndexP 0.01~10.00 10 0.01
6. InvTimeEm3I0Stage1TimeB 0.000~100.00 100 0.01 s
7. InvTimeEm3I0Stage1ConstT 0.025~1.5 0.025 0.001
8. InvTimeEm3I0Stage1MinTime 0.00~100.00 0.1 0.01 s

Three times of
9. Em3I0Stage2CurrSet 0.05In~40In 40 0.01 A zero sequence
current
10. Em3I0Stage2Time 0.00~100.00 100 0.01 s
11. Em3I0Stage2Curve 0~13 0 1
12. EmInvTime3I0Stage2CoefA 0.001~1000 10 0.001 s
13. EmInvTime3I0Stage2IndexP 0.01~10.00 10 0.01
14. EmInvTime3I0Stage2TimeB 0.000~100.00 100 0.01 s
15. EmInvTime3I0Stage2ConstT 0.025~1.5 0.025 0.001
16. EmInvTime3I0Stage2MinTime 0.00~100.00 0.1 0.01 s
18. 3I0HarmUnblkCurr 0.05In~40In 40 0.01 A Common

20. 3I02ndHI02/I01Ratio 0.07~0.50 0.07 0.01
Table 73 Earth fault protection logic switch

Default
value
1- Enable stage 1 of emergency
earth fault ;
1. Em3I0Stage1On 1/0 0
0- Disable stage 1 of emergency
earth fault
2. Em3I0Stage1BlkBy2ndH 1/0 0 1- emergency earth fault stage 1
207
Default
value
secondary harmonic blocking on；
0- emergency earth fault stage 1
secondary harmonic blocking off
1- Enable stage 2 of emergency
earth fault ；
3. Em3I0Stage2On 1/0 0
0-Disable stage 2 of emergency
earth fault
secondary harmonic blocking on；
4. Em3I0Stage2BlkBy2ndH 1/0 0
secondary harmonic blocking off
1-Emergency zero sequence
current harmonics checking
external connection I02/I01;
5. Em3I0HarmChkExtrI02/I01 1/0 0
0-Emergency zero sequence
current harmonics checking
phase current I2/I1
6. CTFailBlkEm3I0 1/0 1 0-open；1-lock.
current; 0-self-produced zero
7. Extr3I0 1/0 0
sequence current
Common setting
voltage connection
Common setting
3.4 Report list

Trip report：
1. Em3I0Stage1Trip /
2. Em3I0Stage2Trip /
3.5 Techinical parameter

Table 75 emergency earth fault protection technical data
Current 0.05In~40.00In ≤±2.5% setting or±0.02In

Dropoff coefficient
I/In>0.4
208
Current 0.05In~40.00In ≤±2.5% setting or±0.02In

Normal inverse time
IEC60255-151
Very inverse time
IEC standard ≤±5% setting or +40ms，
Long inverse time
nverse time
Short inverse time
Long inverse time ANSI/IEEE C37.112，
ANSI Medium inverse time ≤±5% setting or +40ms，
Very inverse time When 2<3I0/3I0set<20
IEC60255-151
curve
0.001~1000.0s
time, A
Time delay of inverse time, B 0.000~100.00s
Inverse time index, P 0.01~10.00
Inverse time constant: T 0.025~1.5

Dropoff coefficient
I/In>0.4
Note: In: CT secondary rated current, 1A or 5A
209
Chapter 12 Negative sequence current protection (46)
Chapter 12 Negative sequence current

protection (46)
About this chapter

This chapter describes the negative sequence current
principle, the input and output signals, setting parameters,
messages and technical parameters.
211
1 Introduction
Negative sequence current protection can detect the unbalance of power
system load. When the generator connect unbalanced load, negative
sequence current protection is particularly useful. Because the unbalanced
load will produce a reverse magnetic field in the three-phase induction
motor, resulting in overheating of the rotor end. Secondly, the negative
sequence current protection can also be used to detect the disconnection,
short circuit and polarity of current transformer. Besides, the negative
sequence current protection can also detect the single-phase or two-phase
faults in the system, and the fault statue when the fault current is less than
the load current.
The characteristics of negative sequence current are listed as follow:
1) The main characteristics of the negative sequence current protection
is: offer 4 stages of negative sequence current protection, and definite
time or inverse time can be selected
2) CT failure blocks negative sequence current protection;
3) During the open-phase operation, the negative sequence current
protection can be enabled or disabled by setting the logic switch.

The input and output signals of negative sequence current protection
Negative Sequence Over Current
Protection
1 1
BIBlk Start
2
Operation
Figure 121 The input and output signals diagram of negative sequence current
protection function
right.
Input:
NOSC*
BIBlk BI blocking
Output:
NOSCStage* Start IED startup
Operation IED trip
Note: “*” in the table is the stage number of negative sequence current
protection.
212
IED is equipped with 4 stages negative sequence current protection,
please refer to the setting list for details. Take negative sequence current
stage 1 protection as an example to explain the principle.

3.1.1 Definite time
When "3I2Stage1Curve"=0, negative sequence current is the definite time
The negative sequence current protection trip current is calculated by the
three-phase current as follow:
𝟑𝟑𝐈𝐈̇𝟐𝟐 = 𝐈𝐈̇𝐀𝐀 + 𝐒𝐒𝟐𝟐 𝐈𝐈̇𝐁𝐁 + 𝐒𝐒𝐈𝐈̇𝐒𝐒
𝟑𝟑𝐈𝐈𝟐𝟐 > “𝟑𝟑𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈”
When the current is greater than "3I2Stage1CurrSet", timing component
starts and until "3I2Stage1Time“, negative sequence current protection
trips, when current 𝟑𝟑𝐈𝐈𝟐𝟐 < 𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃 × “𝟑𝟑𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈” , timing
component returns, negative sequence current protection resets.
Where:
3I2: Negative sequence current;
I2set: "3I2Stage1CurrSet";
Dropoff: Dropoff coefficient
3.1.2 Inverse time
When "3I2Stage1Curve"=1~13, negative sequence current is the inverse
 
 
 A 
=t  P
+ B ⋅T
 I2  
−1
  I 2set  
If the current is greater than "I2Stage1CurrSet", the timing component

starts, inverse time characteristic curve is selected by "3I2Stage1Curve", A,
P, B are determined when the value is from 1 to 12, see the following table;
delay according to the setting of the A, P, B, T. While timing, negative
sequence voltage protection trips. When the delay is less than the
"NSOC1InvTimeMinTime", the component trips according to the
"NSOC1InvTimeMinTime".
Where:
A: "InvTime3I2Stage1CoefA"
P: "InvTime3I2Stage1IndexP"
B: "InvTime3I2Stage1TimeB"
T: "InvTime3I2Stage1ConstT"
213
I2: Negative sequence current

I2set: "3I2Stage1CurrSet"
0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

Take negative sequence current protection stage 1 as an example. When
negative sequence current protection function is enabled and there is no
binary input blocking, if "I2Stage1On"=1, then the negative sequence
current protection is enabled.
Negative sequence current protection is tripped, after the starting of
protection trip, if the trip conditions are satisfied, timing component starts,
and works till the IED issues "3I2Stage1Trip". LED, IED output and others
can be configured by AESP.
When the negative sequence current protection trips, analog in the trip
time will be output.
214
3.1.4 Logic diagram

I2Stage1ProtFcnOn
&
&
“I2Stage1On”=1 T1
I2Stage1Trip
3I2>“I2Stage1CurrSet”
BI Blk
≥1
CTFailure
&
“Non3PhOperBlkI2”
T1：“I2Stage1Time”
Figure 122 Logic diagram of negative sequence current protection function

Type Description
Input NOSC*.BIBLK BI blocking function
NOSCStage*.Start IED startup

Output IED trip (Configurable initiate reclosing
NOSCStage*.Operation
node)
Note: “*” in the table is the stage number of negative sequence current
protection.
3.3 Setting list

Table 79 Negative sequence current protection setting
Default
value
Three times of
negative
1. 3I2Stage1CurrSet 0.05In~40.00In 40 0.01 A
sequence
current
Negative
sequence
2. 3I2Stage1Time 0.00～100.00 100 0.01 s
current stage 1
time
0: Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
3. 3I2Stage1Curve 0～13 0 1 4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7:ANSI SHORT
INV.
8: ANSI LONG
215
Default
value
INV.
9: ANSI
MODERATELY
INV.
10: ANSI VERY
INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User defined
InvTime3I2Stage1
4. 0.001～1000 10 0.001 s
CoefA
InvTime3I2Stage1
5. 0.01～10.00 10 0.01
IndexP
InvTime3I2Stage1
6. 0.000～100.00 100 0.01 s
TimeB
InvTime3I2Stage1
7. 0.025～1.5 0.025 0.001
ConstT
InvTime3I2Stage1
8. 0.00～100.00 0.1 0.01 s
MinTime
Three times of
negative
sequence
current
10. 3I2Stage2Time 0.00～100.00 100 0.01 s
InvTime3I2Stage2
12. 0.001～1000 10 0.001 s
CoefA
InvTime3I2Stage2
13. 0.01～10.00 10 0.01
IndexP
InvTime3I2Stage2
14. 0.000～100.00 100 0.01 s
TimeB
InvTime3I2Stage2
15. 0.025～1.5 0.025 0.001
ConstT
InvTime3I2Stage2
16. 0.00～100.00 0.1 0.01 s
MinTime
Three times of
negative
sequence
current
18. 3I2Stage3Time 0.00～100.00 100 0.01 s
216
Default
value
InvTime3I2Stage3
20. 0.001～1000 10 0.001 s
CoefA
InvTime3I2Stage3
21. 0.01～10.00 10 0.01
IndexP
InvTime3I2Stage3
22. 0.000～100.00 100 0.01 s
TimeB
InvTime3I2Stage3
23. 0.025～1.5 0.025 0.001
ConstT
InvTime3I2Stage3
24. 0.00～100.00 0.1 0.01 s
MinTime
Three times of
negative
sequence
current
26. 3I2Stage4Time 0.00～100.00 100 0.01 s
InvTime3I2Stage4
28. 0.001～1000 10 0.001 s
CoefA
InvTime3I2Stage4
29. 0.01～10.00 10 0.01
IndexP
InvTime3I2Stage4
30. 0.000～100.00 100 0.01 s
TimeB
InvTime3I2Stage4
31. 0.025～1.5 0.025 0.001
ConstT
InvTime3I2Stage4
32. 0.00～100.00 0.1 0.01 s
MinTime
Table 80 Negative sequence current protection logic switch

Default
value
1: enable, open-phase
1. Non3PhOperBlkI2 1/0 0 operation blocks negative
sequence overcurrent
2. 3I2Stage1On 1/0 0 1: On; 0: Off
3. 3I2Stage2On 1/0 0 1: On; 0: Off
4. 3I2Stage3On 1/0 0 1: On; 0: Off
5. 3I2Stage4On 1/0 0 1: On; 0: Off
217
3.4 Report list

Trip report:
1. 3I2Stage1Trip /
2. 3I2Stage2Trip /
3. 3I2Stage3Trip /
4. 3I2Stage4Trip /

Table 82 Negative sequence current protection technical data
Items Setting range Trip value error

≤ ±2.5% times of setting or
Current setting 0.05In to 40.00In
±0.02In
≤ ±1% setting or
Time setting 0.00 to 100.00s +40ms,when operation value
is 200% current setting

±0.02In
Normal inverse time; ≤±5% setting or +40ms,
Very inverse time; when 2<I2/I2set<20, it meets
IEC standard curve
Extreme inverse time; the standard of
Long inverse time; IEC60255-151
Standard inverse time;
Short inverse time
Long inverse time; ≤±5% setting or +40ms,
when 2<I2/I2set<20, it meets
ANSI standard curve Normal inverse time;
the standard of
Very inverse time;
ANSI/IEEEC37.112
Extreme inverse time;
User-defined inverse time;
 
  ≤±5% setting or +40ms,
 A  when 2<I2/I2set<20, it meets
User defined curve =t  P
+ B ⋅T
the standard of
  I2  −1 
  I 2set 
IEC60255-151

0.001to1000.0s
time, A
0.000 to100.00s
B
218
Inverse time index, P 0.01 to 10.00
Inverse time constant: T 0.025 to 1.5
219
Chapter 13 Overvoltage protection (59)
About this chapter

This chapter describes the overvoltage principle, the input
and output signals, setting parameters, reports and technical
parameters.
221
1 Introduction
Overvoltage protection is used to prevent the impact of overvoltage on
electrical equipment. The abnormal overvoltage often occurs in low load,
long transmission line, generator voltage regulation fails in the islanded
system, or the load shedding of the generator in the system. Even if the
compensating capacitor can compensate line capacitive reactance, lower
the overvoltage of the lines, when the compensating capacitor fails,
overvoltage will endanger the line insulation system, here the circuit must
be removed.
Overvoltage protection has the following characteristics:
1) Definite time and reverse time are selective on stage 4;
2) Set the alarm or trip in stage;
3) Measured voltage can be phase-to-earth voltage or phase-to-phase
voltage;
4) Dropoff coefficient is adjustable.

The input and output signals of overvoltage protection function are shown
as follow:
Overvoltage Protection
1 1
BIBlk Start
2
Operation
3
PhaseA
4
PhaseB
5
PhaseC
6
Alarm
Figure 123 The input and output signals of overvoltage protection function diagram
right.

Input:
OV*
BIBlk BI blocking
Output
Start IED startup: start the timer
Operation IED trip
OVStage* PhaseA Phase A trip signal
PhaseB Phase B trip signal
PhaseC Phase C trip signal
Alarm Alarm
222
Note: “*” in the table is the stage number of overvoltage protection.
The overvoltage protection stage 1 will be taken as an example and the
principle will be introduced. The phase-to-earth voltage or phase-to-phase
voltage of overvoltage protection is selected by enabling and disabling
logic switch “OVChkPEVolt”. Logic switch "OVChkPEVolt" is set 1, select
the phase-to-earth voltage UA-N, UB-N, UC-N; logic switch
"OVChkPEVolt" is set 0, select the phase-to-phase voltage UA-B, UB-C,
UC-A.
3.1.1 Definite time
When "OVStage1Curve"=0, overvoltage is the definite time characteristic,
inverse time function is disabled.
𝐔𝐔∅ > “𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎”, (∅ = 𝒂𝒂, 𝒃𝒃, 𝒄𝒄)
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when
"OVChkPEVolt"=0, use the phase-to-phase voltage. When the
phase-to-earth (phase-to-phase) voltage is greater than
"OVStage1VoltSet", timing component starts and until timing to the
"OVStage1Time", overvoltage protection trips, when the phase-to-earth
(phase-to-phase) voltage 𝐔𝐔∅ < 𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎 × “𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎” , timing
component returns, overvoltage protection resets.
3.1.2 Inverse time
When "OVStage1Curve"=1-13, overvoltage is the definite time
 
 
 A
=t + B ⋅T
  UΦ P 
  −1 
  Uset  
Where:
A: "OVStage1InvTimeCoefA"
P: "OVStage1InvTimeIndexP"
B: "OVStage1InvTimeB"
T: "OVStage1InvTimeConstantT"
Uφ: phase-to-earth/phase-to-phase voltage
Uset: "OVStage1VoltSet"
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when
"OVChkPEVolt"=0, use the phase-to-phase voltage. If the
phase-to-earth(phase-to-phase) voltage is greater than
"OVStage1VoltSet", the timing component starts, inverse time
characteristic curve is selected by "OVStage1Curve", A, P, B are
determined when the value is from 1 to 12, see following table; when the
value is 13, it is user defined characteristics, calculate the trip delay
223
according to the setting of the A, P, B, T. While timing, overvoltage

protection trips. When the delay is less than the "OV1InvTimeMinTime",
the component trips according to the "OV1InvTimeMinTime"
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
3. IEC EXTERMELY INV. 80.0 2.0 0
4. IEC SHORT INV 0.05 0.04 0
5. IEC LONG INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
9. ANSI MODERATELY INV. 0.0103 0.02 0.0228
10. ANSI VERY INV. 3.922 2.0 0.0982
11. ANSI EXTERMELY INV. 5.64 2.0 0.02434
12. ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13. User defined

The overvoltage protection stage 1 will be taken as an example. When
overvoltage protection function is enabled and binary input blocking is
disabled, if "OVStage1On"=1, overvoltage protection stage 1 is enabled.
Negative sequence voltage protection is tripped, after the starting of
protection trip, if the trip conditions are met, timing component starts, when
time is over, and “OVStage1Trip" is issued. LED, IED output and others
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the overvoltage protection trips, the component is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-phase
voltage; when it is based on the voltage judgment, it issues three-phase
phase-to-phase voltage.
3.1.4 Logic diagram
Overvoltage stage 1 is taken as an example in the logic diagram of
overvoltage protection and is shown in following figure.
224
max(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=1 ≥1
min(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=0
&
“OVChkPEVolt”=1
max(Uab,Ubc,Uca)>“OVStage1VoltSet” &
min(Uab,Ubc,Uca)>“OVStage1VoltSet” &
& &
T1
OVStage1Trip
“OVChkPEVolt”=0
OVStage1ProtFncOn
“OVStage1On”=1
T1：“OVStage1Time”
Figure 124 The logic diagram of overvoltage protection

Type Description
Input OV*.BIBLK BI blocking function
OVStage*.Start IED startup
OVStage*.Operation IED trip

Phase A meets overvoltage trip, phase A
OVStage*.PhaseA
trip signal
Output Phase B meets overvoltage trip, phase B
OVStage*.PhaseB
trip signal
Phase C meets overvoltage trip, phase C
OVStage*.PhaseC
trip signal
OVStage*.Alarm Overvoltage alarm
Note: “*” in the table is the stage number of overvoltage protection.
3.3 Setting list

Table 86 Overvoltage protection setting
Default Step
No. Setting name Range Unit Remark
value
0.01
1. OVStage1VoltSet 40.00～200.0 110 V
0.01
2. OVStage1Time 0.00～120.00 120 s
1 0: Definite time
3. OVStage1Curve 0～13 0
1: IEC INV.
225
Default Step
value
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7:ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
0.001 Inverse time
4. InvTimeOVStage1CoefA 0.001～1000 10 s
characteristic
0.01
5. InvTimeOVStage1IndexP 0.01～10.00 10
0.01
6. InvTimeOVStage1TimeB 0.000～100.00 100 s
0.001
7. InvTimeOVStage1ConstT 0.025～1.5 0.025
0.01
8. InvTimeOVStage1MinTime 0.00～100.00 0.1 s
0.01
0.01
10. OVStage2Time 0.00～120.00 120 s
1
0.001 Inverse time
12. InvTimeOVStage2ConstA 0.001～1000 10 s
characteristic
0.01
0.01
0.001
0.01
0.01
0.01
18. OVStage3Time 0.00～120.00 120 s
226
Default Step
value
1
0.001 Inverse time
characteristic
0.01
0.01
0.001
0.01
0.01
0.01
26. OVStage4Time 0.00～120.00 120 s
1
0.001 Inverse time
characteristic
0.01
0.01
0.001
0.01
0.01
33. OVDropoffCoef 0.95～1 1
Table 87 Overvoltage protection logic switch

Logic switch Default
No. Setting Remark
description value
Single-phase voltage;
1. OVChkPEVolt 1/0 0
0-phase-to-phase voltage
1-check phase 1; 0-check
phase 3
2. OVChk1Ph 1/0 0 When the logic switch of
"3PhVoltConnect" is 0, this
setting should be 1
3. OVStage1On 1/0 0 /
1-Overvoltage stage 1 alarm;
7. OVStage1Alarm 1/0 0
0-Overvoltage stage 1 trip
227

No. Setting Remark
description value
3.4 Report list

Trip report:
1. OVStage1Trip /
2. OVStage2Trip /
3. OVStage3Trip /
4. OVStage4Trip /
5. OVStage1Alarm /
6. OVStage2Alarm /
7. OVStage3Alarm /
8. OVStage4Alarm /

Table 89 Overvoltage protection technical data
Voltage wiring type Phase-to-phase voltage or ≤ ±2.5% setting or ±1V

phase-to-earth voltage
Phase-to-earth voltage 40 to 100 V ≤ ±2.5% setting or ±1V
Phase-to-phase voltage 80 to 200 V ≤ ±2.5% setting or ±1V
Dropoff coefficient 0.95 to 1.00 ≤ ±3% setting
Time delay setting 0.00 to 9999s ≤ ±1% setting or +60 ms

At 1.2 times of trip voltage
Reset time <40ms
Voltage setting 40V～100V ≤ ±2.5% setting or ±1V
IEC standard curve Normal inverse time; In the case of 2 <U/Uset< 20,
Very inverse time; the allowable trip time error
Extreme inverse time; is: ±5%or +60 ms;
Long inverse time;
228
ANSI standard curve Standard inverse time; In the case of 2 <U/Uset< 20,
Short inverse time the allowable trip time error
Long inverse time; is: ±5%or +60 ms;
Normal inverse time;
Very inverse time;
User defined curve   In the case of 2 <U/USET<
  20, it meets the standard of
 A
+ B ⋅T
IEC60255-151
=t
  UΦ P 
  − 1 
  Uset  
Time coefficient of inverse 0.001～10.0
time, A
Time delay of inverse time, B 0.000～100.00
Minimum trip time 100ms
Reset time About 40 ms
229
Chapter 14 Negative sequence voltage protection (47)
Chapter 14 Negative sequence voltage

protection (47)
About this chapter

This chapter describes the negative sequence voltage
231
1 Introduction
In normal operating three-phase system, the negative sequence voltage is
almost 0, and the negative sequence voltage will occur when there is
asymmetrical situation in the system. Negative sequence voltage
protection trips by checking negative sequence voltage.
The main characteristic of the negative sequence voltage protection is: it
provides 4 stages protection, and definite and inverse time can be
selected.

The input and output signals of negative sequence voltage protection
Negative Sequence Over Voltage Protection

1 1
BIBlk Start
2
Operation
Figure 125 The input and output signals diagram of negative sequence voltage
protection function
right.
Input:
NSOV*
BIBlk BI blocking
Output:
NSOVStage* Start IED startup
Operation IED trip
Note: “*” in the table is the stage number of negative sequence voltage
protection.
3.1.1 Definite time
Negative sequence voltage stage 1 is taken as an example. When
"U2Stage1Curve"=0, negative sequence voltage is the definite time
The negative sequence voltage protection trip voltage is calculated by the
three-phase voltage as follow:
𝐔𝐔̇𝟐𝟐 = 𝐔𝐔̇𝐀𝐀 + 𝐒𝐒𝟐𝟐 𝐔𝐔̇𝐁𝐁 + 𝐒𝐒𝐔𝐔̇𝐒𝐒
232
𝟑𝟑𝐔𝐔𝟐𝟐 > "𝟑𝟑𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔"

If the voltage is greater than "3U2Stage1VoltSet", timing component starts
and until timing to "3U2Stage1Time", negative sequence voltage
protection trips.
Where:
3U2: Negative sequence voltage
U2set: "3U2Stage1VoltSet"
3.1.2 Inverse time
"3U2Stage1Curve"=1~13, negative sequence voltage is the inverse time
 
 
 A 
=t  P
+ B ⋅T
  U2  −1 
 U 2set  
If the voltage is greater than "3U2Stage1VoltSet", the timing component

starts, inverse time characteristic curve is selected by "3U2Stage1Curve",
A, P, B are determined when the value is from 1 to 12, see following table;
delay according to the setting of the A, P, B, T. While timing, negative
sequence voltage protection trips. When the delay is less than the
"NSOV1InvTimeMinTime", the component trips according to the
"NSOV1InvTimeMinTime"
Where:
A: "InvTime3U2Stage1CoefA"
P: "InvTime3U2Stage1IndexP"
B: "InvTime3U2Stage1TimeB"
T: "InvTime3U2Stage1ConstT"
U2: Negative sequence voltage
U2set: "3U2Stage1VoltSet"
0 Definite time
1 IEC INV. 0.14 0.02 0
2 IEC VERY INV. 13.5 1.0 0
233
6 ANSI INV. 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
10 ANSI VERY INV. 3.922 2.0 0.0982
13 USER DEFINE

negative sequence voltage protection function is enabled and there is no
binary input blocking, if "U2Stage1On"=1, then the negative sequence
voltage protection is enabled.
After the protection trip starts, if the trip conditions are satisfied, timing
component starts, and works till the IED issues "3U2Stage1Trip" LED, IED
output and others can be configured by AESP.
Negative sequence voltage protection outputs analog quantity of trip
moment during operation, when the component judges based on the
self-produced analog quantity, it shall output self-produced analog quantity;
if based on the external analog quantity, and it shall output external analog
quantity.

Type Description
configuration
Input NSOV*.BIBLK BI blocking function
NSOVStage*.Start IED startup

Output
NSOVStage*.Operation IED trip
Note: “*” in the table is the stage number of negative sequence voltage
protection.
234
3.3 Setting list

Table 93 Negative sequence voltage protection setting
Default Step
value
0.01 3 times of
negative
1. 3U2Stage1VoltSet 40～100.00 100 V
sequence
voltage
0.01
2. 3U2Stage1Time 0.00～100.00 100 s
1 0: Definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7:ANSI
SHORT INV.
3. 3U2Stage1Curve 0～13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
0.001
4. InvTime3U2Stage1CoefA 0.001～1000 10 s
0.01
5. InvTime3U2Stage1IndexP 0.01～10.00 10
0.01
6. InvTime3U2Stage1TimeB 0.000～100.00 100 s
0.001
7. InvTime3U2Stage1ConstT 0.025～1.5 0.025
0.01
8. InvTime3U2Stage1MinTime 0.00～100.00 0.1 s
0.01 3 times of
negative
9. 3U2Stage2VoltSet 40～100.00 100 V
sequence
voltage
0.01
10. 3U2Stage2Time 0.00～100.00 100 s
1
235
Default Step
value
0.001
0.01
0.01
0.001
0.01
0.01 3 times of
negative
17. 3U2Stage3VoltSet 40～100.00 100 V
sequence
voltage
0.01
18. 3U2Stage3Time 0.00～100.00 100 s
1
0.001
0.01
0.01
0.001
0.01
0.01 3 times of
negative
25. 3U2Stage4VoltSet 40～100.00 100 V
sequence
voltage
0.01
26. 3U2Stage4Time 0.00～100.00 100 s
1
0.001
0.01
0.01
0.001
0.01
Table 94 Negative sequence voltage protection logic switch

Default
value
1. 3U2Stage1On 1/0 0 1: On; 0: Off
2. 3U2Stage2On 1/0 0 1: On; 0: Off
3. 3U2Stage3On 1/0 0 1: On; 0: Off
4. 3U2Stage4On 1/0 0 1: On; 0: Off
236
3.4 Report list

Trip report:
1. 3U2Stage1Trip /
2. 3U2Stage2Trip /
3. 3U2Stage3Trip /
4. 3U2Stage4Trip /

Table 96 Negative sequence voltage protection technical data
Trip voltage U2 (calculated) 40.0 to100V ≤ ±5% times of setting or ±1V

≤ ±1% setting or + +60 ms,
Time setting 0.00 to100.00s when trip voltage is set as
120% of setting
Dropoff coefficient About 0.95

Trip voltage 3U2
40V～100V ≤ ±5% times of setting or ±1V
(self-produce)
Normal inverse time;
In the case of 2<U2/U2set<20,
Very inverse time;
IEC standard curve the allowable trip time error
is: + 5% or +60 ms;
Long inverse time;
Standard inverse time;
Short inverse time
Long inverse time; In the case of 2<U2/U2set<20,
ANSI standard curve Normal inverse time; the allowable trip time error
Very inverse time; is: + 5% or +60 ms;
 
 
 A  In the case of 2<U2/U2set<20,
User defined curve =t  P
+ B ⋅T it meets the standard of
  U2  −1  IEC60255-151
 U 2set  
0.001～10.0
time, A
Time delay of inverse time, B 0.000～100.00
237
238
Chapter 15 Undervoltage protection (27)
Chapter 15 Undervoltage protection

(27)
About this chapter

This chapter describes the undervoltage protection principle,
the input and output signals, setting parameters, messages
239
1 Introduction
Undervoltage protection can effectively protect the power equipment from
the impact of voltage drop.
The main features of undervoltage protection are as follow:
1) It provides 4 stages of protection, definite and inverse time can be
selected;
2) Undervoltage protection voltage can be selected as phase voltage or
phase-to-phase voltage;
3) Undervoltage blocking current check;
4) State check of circuit breaker;
5) VT failure check, VT failure blocking undervoltage protection;
6) Dropoff coefficient is adjustable;
7) Existed live voltage condition had been tested, can be enabled or
disabled logic switch.

The input and output signals of undervoltage protection function diagram
are shown as follow, left side is input and right side is output:
Undervoltage Protection
1 1
BIBlk Start
2 2
CBOpen Operation
3
PhaseA
4
PhaseB
5
PhaseC
6
Alarm
Figure 126 The input and output signal diagram of undervoltage protection function

Input:
UV* BIBlk BI blocking
CBOpen Open position of circuit breaker
Output:
Operation IED trip
UVStage* PhaseA Phase A trip signal
PhaseB Phase B trip signal
PhaseC Phase C trip signal
Alarm Alarm
240
Note: “*” in the table is the stage number of undervoltage protection.
Device configuration stage 4 undervoltage protection, phase-to earth
voltage/phase-to-phase voltage is available, definite/inverse time is
available, alarm /trip is available, see details in setting list.

Under-voltage protection can provide four stages of protection, with the
changeable definite/inverse time. Take the under-voltage stage 1 as the
example, it can be enabled or disabled via the enabled/disabled connector
"UVStage1On". Under-voltage 1 stage can choose the exit alarm or exit
trip via the enabled or disabled logic switch "under-voltage stage 1 alarm".
With the enabled logic switch "UVChkPEVolt", the undervoltage protection
operation voltage setting can choose phase-to-earth voltage UA-N, UB-N,
UC-N, otherwise, it chooses phase-to-phase voltage UA-B, UB-C, UC-A.
With the limit of field condition, the voltage transformer of the circuit
breaker may be connected to the power supply side or the load side. The
installation position of VT is different, and the operation characteristics of
undervoltage protection are different. As the undervoltage protection starts
tripping and the circuit breaker is open, the voltage beside power supply
latches unchangeable but the voltage beside load drops to zero, now
undervoltage protection resets. If the voltage transformer is installed on
the power supply side, and does not want to protect the undervoltage
detection current, the setting of "UVChkCurrOn" can be set to 0. In addition,
the undervoltage protection can also be controlled by the word
"UVChkCBState" to choose whether the trip logic is to detect the circuit
breaker status. When the undervoltage protection is required to check the
circuit breaker state, the undervoltage protection sends out the trip
command only when the circuit breaker is closed. If the voltage
transformer is installed on the power supply side, and undervoltage
protection does not check circuit breaker status, the logic switch
"UVChkCBState" is set to 0.
3.1.1 Blocking condition
When "UVChkCBState"=1, circuit breaker will be checked at blocking
protection during the trip, with non-blocking protection starting and
blocking protection delaying.
When "UVChkCurrOn" =1, the blocking is protected as the maximum value
of three-phase current is less than UVCurrSet", the non-blocking
protection starts, and the blocking is delayed.
As VT Fails, the blocking is protected, the non-blocking protection start,
and the blocking is delayed.
When "UVChkExistedLiveVoltOn" logic switch is on: if the existed live
voltage condition is not satisfied, then the low-voltage protection is
blocked.
When "UVChkPEVolt"=1, and three-phase voltage is lower than
"3PhUVBlkSet", or when "UVChkPEVolt"=0 and three-phase voltage is
lower than the 1.732 times of "3PhUVBlkSet", the blocking is protected,
the blocking protection starts.
241
3.1.2 Definite time

When "UVStage1CurveSel"=0, undervoltage is the definite time
characteristic, and inverse time function is disabled.
𝐔𝐔 < "𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔”
When the voltage is lower than "UVStage1VoltSet", timing component
starts and works until the setting "UVStage1Time", and undervoltage
protection trips. When voltage> "𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔" × ”𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔",
timing component drops out, undervoltage protection drops out.
3.1.3 Inverse time
When "UVStage1CurveSel"=1~4, undervoltage is the inverse time
 
 
A
=t  + B  ⋅T
  U P 
1 −   
 Uset  
If the voltage is lower than the inverse time starting voltage
"UVStage1VoltageSetting", the timing component starts, inverse time
characteristic curve is selected by "UVStage1CurveSel", A, P, B are
determined when the value is from 1 to 3, as shown in following table;
delay according to the setting of the A, P, B, T. While timing, undervoltage
protection trips. When the delay is less than the "UV1InvTimeMinTime",
the component trips according to the "UV1InvTimeMinTime".
Where:
A: "InvTimeUVStage1CoefA"
P: "InvTimeUVStage1IndexP"
B: "InvTimeUVStage1TimeB"
T: "InvTimeUVStage1ConstT"
U: voltage
Uset: "UVStage1VoltSet"
0. Definite time
1. Curve1 1 1 0
2. Curve 2 40 2 1
3. Curve 3 5 2 2
4. User defined
242

The undervoltage protection stage 1 will be taken as an example. When
undervoltage protection function is enabled and binary input blocking is
disabled, if "UVStage1On"=1, undervoltage protection stage 1 is enabled.
𝐔𝐔 < "𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔"
When "UVChkPEVolt"=1, check phase-to-earth voltage; when
"UVChkPEVolt"=0, check phase-to-phase voltage.
While "3PhVoltConnect"is 1, three phases or "OR" logic can be selected
by logic switch "UVChk1Ph" and the protection starts while at least one
voltage is lower than the setting; it can also select "AND" logic, and the
protection starts while three voltages are all lower than the setting.
While "3PhVoltConnect"=0, that is, the single phase VT is connected, it is
fixed as the "AND" logic and need to take the maximum phase-to-earth
(phase-to-phase) voltage to judge.
Undervoltage protection is tripped, after the starting of protection trip, if the
trip conditions are met, timing component starts, and works till the IED
issues "UVProtectionStage1Trip" LED, IED output and others can be
configured by AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the undervoltage protection trips, the component is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-earth
voltage; when it is based on the phase-to-phase voltage judgment, it
issues three-phase phase-to-phase voltage.
When "UVChkExistedLiveVoltOn"=1, the existed live voltage condition
shall be checked. When the existed live voltage condition is: 𝐔𝐔 >
“𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐨𝐨𝐥𝐥𝐥𝐥𝐥𝐥𝐥𝐥𝐥𝐥” determined 40ms, and now it is
< “𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔𝐔” , then the existed live voltage condition meet. This
condition is returned when the T= “UVStage1Time”+2S.
243
3.1.5 Logic diagram

Ua<“UVStage1VoltSet”
≥1
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
“UVChk1Ph”=1 ≥1
“UVChk1Ph”=0
Ua<“UVStage1VoltSet”
& &
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
≥1
“UVChkPEVolt”=1 UVStage1Startup
“UVChkPEVolt”=0
Uab<“UVStage1VoltSet”
≥1
& &
Ubc<“UVStage1VoltSet”
Uca<“UVStage1VoltSet”
“UVChk1Ph”=1
≥1
“UVChk1Ph”=0
Uab<“UVStage1VoltSet”
&
&
Ubc<“UVStage1VoltSet”
Uca<“UVStage1VoltSet”
Figure 127 Logic diagram for undervoltage stage 1 protection startup
244
“UVStage1On”=1
UVStage1Startup
BIBlk
Existed live voltage

conditions are met &
≥1
“UVChkExistedLiveVoltOn”=1
“UVChkExistedLiveVoltOn”=0
3PhTripPosn & &

≥1 T1
UVStage1Trip
“UVChkCBState”=1
“UVChkCBState”=0
max(Ia,Ib,Ic)>“UVCurrSet” &
≥1
&
“UVChkCurrOn”=1
“UVChkCurrOn”=0
VTFailBlk
Ua<“3PhUVBlkSet”
Ub<“3PhUVBlkSet”
&
Uc<“3PhUVBlkSet”
“UVChkPEVolt”=1
≥1
“UVChkPEVolt”=0
Uab<1.732×“3PhUVBlkSet”
&
Ubc<1.732×“3PhUVBlkSet”
Uca<1.732×“3PhUVBlkSet”
T1：“UVStage1Time”
Figure 128 Logic diagram for undervoltage stage 1 protection trip

Type Description
IO Matrix configuration
Input UV*.BIBLK BI blocking function
UVStage*.Start IED startup
UVStage*.Operation IED trip
UVStage*.PhaseA Phase A meets overcurrent trip, phase A trip signal

Output
UVStage*.PhaseB Phase B meets overcurrent trip, phase B trip signal
UVStage*.PhaseC Phase C meets overcurrent trip, phase C trip signal
UVStage*.Alarm Undervoltage alarm
245
Note: “*” in the table is the stage number of undervoltage protection.
3.3 Setting list

Table 100 Settings of undervoltage protection
Default
value
1. UVStage1VoltSet 5.00～150 100 0.01 V
2. UVStage1Time 0.00～120.0 120 0.01 s

0: Definite
time
1: A-1; P-1;
B-0
2: A-40;
3. UVStage1CurveSel 0～4 0 1
P-2; B-1
3: A-5; P-2;
B-2
4: User
defined
0.00
4. InvTimeUVStage1CoefA 0.001～1000 10 s
1
5. InvTimeUVStage1Indexp 0.01～10.00 10 0.01
6. InvTimeUVStage1TimeB 0.000～100.00 100 0.01 s

0.00
7. InvTimeUVStage1ConstT 0.025～1.5 0.025
1
8. InvTimeUVStage1MinTime 0.00～100.00 0.1 0.01 s
10. UVStage2Time 0.00～120.0 120 0.01 s

0: Definite
time
1: A-1; P-1;
B-0
2: A-40;
P-2; B-1
3: A-5; P-2;
B-2
4: User
defined
0.00
1
13. InvTimeUVStage2IndexP 0.01～10.00 10 0.01

0.00
1
246
Default
value
18. UVStage3Time 0.00～120.0 120 0.01 s
0: Definite
time
1: A-1; P-1;
B-0
2: A-40;
P-2; B-1
3: A-5; P-2;
B-2
4: User
defined
0.00
1

0.00
1
26. UVStage4Time 0.00～120.0 120 0.01 s

0: Definite
time
1: A-1; P-1;
B-0
2: A-40;
P-2; B-1
3: A-5; P-2;
B-2
4: User
defined
0.00
1

0.00
1
33. UVCurrSet 0.04In~40 In 10 0.01 A
34. UVDropoffCoef 1.00～2.00 1.02 0.01

When
"UVChkExis
35. 3PhUVBlkSet 0.00～40 0 0.01 V tedLiveVolt
On" is 0, it
is
247
Default
value
recommend
ed that this
setting be
set to be
greater than
1V.
Table 101 Undervoltage protection logic switch
Default
value
1-Enable stage 1 of undervoltage;
1. UVStage1On 1/0 0
0-Disable stage 1 of undervoltage
2. UVStage2On 1/0 0
3. UVStage3On 1/0 0
4. UVStage4On 1/0 0
1-undervoltage stage 1 alarm on;
5. UVStage1Alarm 1/0 0
0-undervoltage stage 1 trip on
1-undervoltage check CB state
9. UVChkCBState 1/0 0 on; 0-undervoltage check CB
state off
1-Undervoltage check current on;
10. UVChkCurrOn 1/0 0
0-Undervoltage check current off
1-check single phase voltage;
11. UVChk1Ph 1/0 0
0-check three phase voltage
1- undervoltage check
phase-to-earth voltage; 0-
12. UVChkPEVolt 1/0 0
undervoltage check
phase-to-phase voltage
1-undervoltage check existed live
13. UVChkExistedLiveVoltOn 1/0 1 voltage on; 0-undervoltage check
existed live voltage off
voltage connection
Common setting
1-VT failure protection off, 0-VT
15. VTFailProtOff 1/0 0 failure protection on
Common setting
248
3.4 Report list

Trip report:
1. UVStage1Trip /
2. UVStage2Trip /
3. UVStage3Trip /
4. UVStage4Trip /
5. UVStage1Alarm /
6. UVStage2Alarm /
7. UVStage3Alarm /
8. UVStage4Alarm /

Table 103 Undervoltage protection technical data

Phase-to-phase voltage or
Accessed voltage ≤ ±2.5% times of setting or ±1V
phase-to-earth voltage
Phase-to-earth voltage 5 to75V ≤ ±2.5% times of setting or ±1V
Phase-to-phase voltage 10 to150V ≤ ±2.5% times of setting or ±1V
Dropoff coefficient 1.00 to 1.05 ≤±3% setting

≤ ± 1% times of setting or
Time setting on
0.00 to120.00s +60ms, when trip value is set
undervoltage
at 80% of setting
Voltage setting 5V～150V ≤ ±2.5% times of setting or ±1V

In the case of 0.05 <U/Uset<
IEC60255-127 0.5, the allowable trip time
error is: ±5%or +60 ms;
249
 
  ≤ ±5% setting or +60ms, when
 A  ⋅T
User defined curve =t + B 2<U/Uset<20, it meets the
  U P  standard of IEC60255-151
1 −   
 Uset  
0.001～10.0
time, A
Time delay of inverse
0.000～100.00
time, B
250
Chapter 16 Thermal overload protection (49)
Chapter 16 Thermal overload protection

(49)
About this chapter

This chapter describes the thermal overload protection
251
1 Introduction
Thermal overload protection protects the device against overheating
caused by overload. Overheating can affect insulation characteristics of
insulation material between transformers, lines and other electrical
equipment. In fact, if the device temperature exceeds the allowable
operating temperature, the insulation material will accelerate aging.
Therefore, special protection should be provided to prevent the protected
equipment from excessive temperature. Since the temperature is
proportional to the square of the current, the thermal overload protection is
based on the square of the measured current flowing through the
protected device. In addition, due to the cumulative effect of over
temperature, the thermal overload protection needs to consider the
historical thermal effect of the device. The device realizes the above
functions by providing a thermal model of the simulated protected device.
In this way, the thermal overload protection of the device has the ability of
memory, which can consider the historical overload and heat loss.

The input and output signals of thermal overload protection function
diagram are shown as follow:
ThermalOL
ThermalOL
1
Start
2
Act1
3
Act2
4
Act3
5
APhase
6
BPhase
7
CPhase
Figure 129 The input and output signals of thermal overload protection function
diagram
right.

Output:
When the thermal overload is accumulated to
Act1
RatioAct1, the alarm is sent.
Act2
ThermalOL RatioAct2, the alarm is sent.
Act3
100%, the trip is sent.
APhase Phase A overheating trip signal or alarm
BPhase Phase B overheating trip signal or alarm
CPhase Phase C overheating trip signal or alarm
252
The device provides 1 stage thermal overload trip stage and stage 2
thermal overload alarm stage. The alarm stage needs to adjust the
"ThermalOLAlarmCoef1" and "ThermalOLAlarmCoef2", which means that
the value of the alarm stage trip setting is the product of the setting of the
trip stage and the overload alarm coefficient. The thermal overload
protection function is realized by a temperature model equivalent to the
protected device. Temperature model (low temperature curve or high
temperature curve) is selected from IEC60255-8 standard. Temperature
model can be used to calculate the temperature rise of each phase current.
The maximum temperature rise calculated from the three-phase current is
the trip value of thermal overload protection.

The temperature rise of each phase is calculated by the following formula:
dΘ I
τ + Θ = ( )2
dt Iϑ
where, τ is "ThermalTimeConst", with s as the unit; Iθ is the maximum

allowed constant thermal overload current "ThermalOLCurrSet"; Θ refers
to each unit temperature rise at the maximum allowable thermal overload
current Iθ; and I is measurement current.
Based on the difference model, the calculation formula of overload trip
time:
 I 2  I 2 
   −  P  
  Iϑ   Iϑ  
t = τ ln  2 
  I  − 1 
   
  Iϑ  
Where IP is the stable current before the overload, the formula is the heat
curve in the IEC60255-8 specification, and the trip time is calculated
according to the cold curve is as follow:
  I 2 
   
 I 
t = τ ln   ϑ 2 
  I  − 1
  I ϑ  
 
Thermal overload protection can reflect the current fundamental frequency
component or RMS value trip, which are divided into stage 1 trip and stage
2 alarm, when𝑰𝑰 > “𝐓𝐰𝐰𝐒𝐒𝐒𝐒𝐦𝐦𝐒𝐒𝐒𝐒𝐎𝐎𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒𝐒”, over heat protection starts, when
the thermal overload percentage reaches "ThermalOLAlarmCoef1", the
report "ThermalOLStage1Alarm" is sent out; when the thermal load
percentage reaches 100%, the report "ThermalOLTrip" is sent out. LED,
IED output and others can be configured by AESP after the alarm or trip
report is issued.
While alarming or tripping, three phase current value Ia, Ib, Ic of trip
moment and state PhaseA, PhaseB, PhaseC of each phase of trip
moment are output.
253
Three phase thermal accumulative percentage is sent out timely by

TermalA, TermalB, and TermalC in the case of overheating protection.
The shutdown load current is 0, and the time coefficient of the equipment
in the process of heat dissipation is the product of
"ThermalOLCoolingCoef" and “ThermalTimeConst".

Type Description
ThermalOL.Start IED startup: start the timer
ThermalOL.Act1
ThermalOL.Act2
Output When the thermal overload is accumulated to
ThermalOL.Act3
100%, the trip is sent.
ThermalOL.APhase Phase A overheating trip signal or alarm
ThermalOL.BPhase Phase B overheating trip signal or alarm
ThermalOL.CPhase Phase C overheating trip signal or alarm
3.3 Setting list

Table 106 Thermal overload protection setting
Default
value
1. ThermalOLCurrSet 0.05In~40.00In 40 0.01 A
2. ThermalTimeConst 6～9999 60 0.01 s
3. ThermalOLCoolingCoef 0.1～10 10 0.01
4. ThermalOLAlarmCoef1 0.5～1 1 0.01
5. ThermalOLAlarmCoef2 0.5～1 1 0.01
Table 107 Thermal overload logic switch

No. Setting Remark
description value
1. ThermalOLOn 1/0 0 Enabled or disabled thermal overload
Enabled and disabled thermal overload
2. ThermalOLAlarm1On 1/0 0
alarm stage
Enabled and disabled thermal overload
3. ThermalOLAlarm2On 1/0 0
alarm stage
4. ThermalCurve 1/0 0 1: hot curve; 0: cool curve
254
3.4 Report list


Trip report:
1. ThermalOLTrip Thermal overload protection issues trip command
2. ThermalOLPhAFault /
3. ThermalOLPhBFault /
4. ThermalOLPhCFault /
5. ThermalOLStartup Thermal overload protection startup
Alarm report:
1. ThermalOLStage1Alarm Thermal overload protection sends off alarm 1 command
2. ThermalOLStage2Alarm Thermal overload protection sends off alarm 2 command

Table 109 Thermal overload protection technical data

±0.02In
Thermal overload protection
6 to 9999s
thermal time constant
Cooling coefficient of thermal
0.1～10
overload
 I eq 
2 IEC 60255–8,
IEC low temperature curve τ = τ ln  2 2 
≤ ±5% times of setting or
 I eq − I θ  +40ms,
 I eq2 − I P2  IEC 60255–8,
IEC high temperature curve τ = τ ln  2 2  ≤ ±5% times of setting or
 I eq − I θ  +40ms,
255
Chapter 17 Power protection (32D)
About this chapter

This chapter describes the power protection principle, input
and output signals, setting parameter, IED report and
technical data.
257
1 Introduction
Generally, the power direction of generator is from generator to bus bar.
However, as long as generator losses excitation or something
dysfunctional, generator is like to operate with motor, which means that the
generator will absorb from system, or inverse power. Inverse protection
plays a role in preventing blade damage caused from overheated turbine
as the steam turbine suddenly shutdowns and shifts to operate with motor.
It provides 2 stages over-power direction protection,power direction
controlled by logic switch to be forward or reverse.

Power protection function input and output signals are shown as follow:
Directional power/reverse power protection
1 1
BIBlk Start
2
Operation
Figure 130 The input and output signal diagram of power protection function
right.
Input:
OP*
BIBlk BI blocking
Output:
OPStage* Start IED startup
Operation IED trip
Note: “*” in the table is the stage number of power protection.
As the inverse power reaches setting, protection trips. Power protection
stage 1 will be taken as an example.
As the logic switch "OutgoLineRvsPowerStage1On" is 1, the incoming line
is judged to be under inverse power. As the logic switch
"OutgoLineRvsPowerStage1On" is 0, the outlet line is under inverse
power.
Over power
P > Pset
When power protection function is on and binary input blocking is off, if
258
"PowerProtStage1On"=1, then the power protection stage 1 is enabled.

In addition, if VT failure blocking or CT failure occurs, the power protection
will be blocked
After starting power protection, and BI blocking is zero, the time delay
capacitor will be on.
If the requirements of trip are met, start timing components until
"PowerProStage1Trip" is on. LED and output can be configured by AESP.
As the trip signal is output, the power value at the time of outputting is P
(absolute value).
Power protection stage 1 is taken as an example, the logic diagram is as
follow.
Power<0
&
“OutgoLineRvsPowerStage1On”=1
≥1
Absolute value of Power> &
“PowerProtStage1PowerSet” T1
PowerProtStage1Trip
&
“OutgoLineRvsPowerStage1On”=0
Power>0
BIBlk
≥1
VTFailBlk
CTFail
PowerProtFncOn
“PowerProtStage1On”=1
T1：“PowerProtStage1Time”
Figure 131 Power protection logic diagram

Type Description
Input OP*. BIBlk BI blocking function
OPStage*.Start IED startup

Output
OPStage*.Operation IED trip
Note: “*” in the table is the stage number of power protection.
259
3.3 Setting list

Table 112 Power protection setting
Default
value
1. PowerProtStage1PowerSet 0～500 500 0.01 W
2. PowerProtStage1Time 0～100 100 0.01 s
3. PowerProtStage2PowerSet 0～500 500 0.01 W
4. PowerProtStage2Time 0～100 100 0.01 s
Table 113 Power protection logic switch

Default
value
1. PowerProtStage1On 1/0 0 1: On, 0: Off
2. OutgoLineRvsPowerStage1On 1/0 0 1: On, 0: Off
3. PowerProtStage2On 1/0 0 1: On, 0: Off
4. OutgoLineRvsPowerStage2On 1/0 0 1: On, 0: Off
3.4 Report list

Trip report:
1. PowerProtStage1Trip /
2. PowerProtStage2Trip /

Table 115 Power protection technical data
1W～500W Allowable error of power trip value:

Power setting
±3% or ±0.5 Pn
Reset time Less than 55ms
Note: Pn: Power setting.
260
Chapter 18 Circuit Breaker Failure protection (50BF)
Chapter 18 Circuit Breaker Failure

protection (50BF)
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
circuit breaker failure protection function.
261
1 Introduction
Circuit breaker failure protection can detect the operation of circuit breaker
during the fault isolation. This protection can isolate the fault by tripping the
circuit breaker of corresponding bus bars as fast backup protection. Once
there is a circuit breaker failure on feeder or transformer, the connected
busbar can be isolated from the power grid by circuit breaker failure
protection. In addition, the device sends out a trip command to the
protection of other end of the feeder. In the event of a circuit breaker failure
with a busbar fault, IED sends the trip command to the opposite of the
feeder.
In order to improve the reliability of circuit breaker failure protection, the
current criterion is added. Three phase current, zero sequence current and
negative sequence current are available.
In order to avoid the other around circuit breaker trip caused by the error of
judgment, circuit breaker failure protection can be set to issue a trip
command to the local circuit breaker once again.
Circuit breaker failure protection has the characteristics as below:
1) 2 trip stages (local circuit breaker retrip and trip the busbar);
2) Transfer trip command to the remote line end in stage 2;
3) Internal/ external initiation;
4) Single phase startup failure/ Three-phase startup failure;
5) Breaker auxiliary contact check;
6) Current criteria (including phase-to-earth current, zero and negative
sequence currents).

Circuit breaker failure protection function input and output signal diagram
is shown as follow:
Circuit-Breaker Failure Protection
1 1
BIBlk CBF_Init
2 2
CBFail Trip1
3 3
CBOpenA Trip1pTr3p
4 4
CBOpenB Trip2
5 5
CBOpenC TripA
6 6
CBClose3P TripB
7 7
BIInitA_CBF TripC
8 8
BIInitB_CBF Tri3p
9
BIInitC_CBF
10
BIInit3P_CBF
11
TrInitA
12
TrInitB
13
TrInitC
14
TrInit3P
Figure 132 Circuit breaker failure protection function input and output signal diagram
262
The input signals are on the left side and the output signals are on the right.
Table 116 parameter description
Input:
CBOpenA Trip position A
CBOpenB Trip position B
CBOpenC Trip position C
DIcom CBClose3P Close position
BIInitA_CBF External phase A initiating failure signal
BIInitB_CBF External phase B initiating failure signal
BIInitC_CBF External phase C initiating failure signal

External three-phase initiating circuit
BIInit3P_CBF
breaker failure signal
Input:
BIBlk BI blocking
Internal phase A initiating circuit breaker failure
TrInitA
signal: can be configured by IO Matrix
Internal phase B initiating circuit breaker failure
CBF TrInitB
Internal phase C initiating circuit breaker failure
TrInitC
Internal three phase initiating failure signal:
TrInit3P
can be configured by IO Matrix
Circuit breaker failure Spring discharge binary
CBFail
input
Output:
Initiating failure: external initiating failure
CBF_Init
signal, internal initiating failure signal
Trip1 Trip of circuit breaker failure stage 1
Time of three-phase trip of circuit breaker
Trip1pTr3p
failure stage 1
CBFail Trip2 CBFStage2Trip
TripA Failure stage 1 protection trip phase A
TripB Failure stage 1 protection trip phase B
TripC Failure stage 1 protection trip phase C
Tri3p Failure stage 1 protection trip three phase
263
3.1 Protection function
Circuit breaker failure protection can be enabled or disabled by setting the
logic switch In the case of the protection function is enabled, the protection
function trips, the relevant protection function start failure protection, and
the timing of the counter works until to setting time delay, and the time
delay is set to“CBFTime1". If the circuit breaker is not switched off after the
setting time, the circuit breaker failure protection sends off the trip order to
trip the circuit breaker (e.g., through a second two trip coil). If the circuit
breaker has no response when the other time delay "CBFTime2", then IED
will send off trip command to trip the corresponding circuit breakers to
isolate the fault (e.g. other circuit breakers on the same busbar connected
with the failure circuit breaker). After tripping, LED, IED output and others
The internal and external protection function can both start circuit breaker
failure protection. If the external are all failed, it needs to configure 4
special starting failure BI, ranging from "Extr3PhInitCBF",
"ExtrPhAInitCBF", "ExtrPhBInitCBF", and "ExtrPhCInitCBF". If the circuit
breaker supports the split trip coil and the single-phase auto-reclosing
input enables, the phase separation is opened.
When the lasting time of external failure met "CBFBIAlarmTime", configure
"CBF BIErr" alarms.
Circuit breaker failure detection includes two criteria. The first criterion is
detecting the disappeared current after issuing the trip command. The
second criterion is detecting the auxiliary contacts of circuit breaker.
3.1.1 Current detection
When the current is disappeared, then the circuit breaker is considered to
be on the open position. So the first criterion (current criterion) is the most
effective way to detect the position of circuit breaker. The current check is
used to detect the circuit breaker position in circuit breaker failure
protection. At this time, the current measurement of each phase compares
with the setting of 'I_Circuit breaker failure'. Besides, the zero sequence
(𝟑𝟑𝐈𝐈̇𝟎𝟎 = 𝐈𝐈̇𝐀𝐀 + 𝐈𝐈̇𝐁𝐁 + 𝐈𝐈̇𝐒𝐒 )or negative sequence current (3𝐈𝐈̇𝟐𝟐 =𝐈𝐈̇𝐀𝐀 +a2𝐈𝐈̇𝐁𝐁 +a𝐈𝐈̇𝐒𝐒 ) can
also be used as current criteria by setting the logic switch. If the IED is set
to detect zero and negative sequence currents, then the zero and negative
currents should be compared with the corresponding settings respectively.
Breaker current detection logic diagram is shown as follow:
264
&
Ia > I_CBF
≥1
3I0 > 3I0_CBF &
CBFCurrCriteriaPhALiveCurr
≥1 &
3I2 > 3I2_CBF
Ib > I_CBF
Ic > I_CBF
“CBFChk3I0/3I2”
&
Ib > I_CBF
≥1
3I0 > 3I0_CBF & CBFCurrCriteriaPhBLiveCurr
≥1 &
3I2 > 3I2_CBF
Ic > I_CBF
Ia > I_CBF
“CBFChk3I0/3I2”
&
Ic > I_CBF
≥1
3I0 > 3I0_CBF &
CBFCurrCriteriaPhCLiveCurr
≥1 &
3I2 > 3I2_CBF
Ib > I_CBF
≥1
Ia > I_CBF CBFCurrCriteria3PhLiveCurr
“CBFChk3I0/3I2”
I_CBF：“CBFCurrSet”
3I0_CBF：“CBF3I0Set”
3I2_CBF：“CBF3I2Set”
Figure 133 Logic diagram of circuit breaker current detection
3.1.2 Breaker auxiliary contact detection

Circuit breaker auxiliary contact position can be used to judge whether the
circuit breaker trips or not. If set logic switch "CBFChkCBPosn" is 1,
criterion for auxiliary contact of circuit breaker will be enabled, and
"TripPosnA", "TripPosnB","TripPosnC" is needed to be BI.
The auxiliary contact monitoring criterion for circuit breaker failure
protection only works if the current monitoring is not started. In the delay of
circuit breaker failure protection, once the current criterion starts and the
identified current disappears, even if the auxiliary contact of the circuit
breaker does not identify that the circuit breaker has been disconnected,
the protection also considers that the circuit breaker is disconnected. More
reliable current criteria have higher priority to avoid signal errors caused by
auxiliary contact mechanism or circuit failures. The criterion of circuit
breaker auxiliary contact is as follow:
265
&
Trip Position A
PhACBClosePosn
&
PhAInitCBF
≥1
&
Trip Position B
PhBCBClosePosn
&
PhBInitCBF
≥1
CBFCurrCriteriaPhBLiveCurr
&
Trip Position C
PhCCBClosePosn
&
PhCInitCBF
≥1
Trip Position A
&
Trip Position B
&
Trip Position C 3PhCBClosePosn
&
3PhInitCBF
≥1
CBFCurrCriteria3PhLiveCurr
Figure 134 Breaker auxiliary contact judgment logic diagram
266
3.1.3 CBF protection trip logic

The internal and external initiating logic is shown as follow:
“CBFOn”
&
“1PhCBFOn”
BI:External phase A initiating

CBF signal
≥1
BI:External phase B initiating &
CBF signal ≥1 CBF BIErr
T_alarm
BI:External phase C initiating
CBF signal
BI:External 3-phase
initiating CBF signal
&
≥1
BI:External phase A initiating
CBF signal
PhAInitCBF
Internal phase A
Initiating CBF signal
&
≥1
BI:External phase B initiating
CBF signal PhBInitCBF
Internal phase B
&
≥1
BI:External phase C initiating PhCInitCBF
CBF signal
Internal phase C
Initiating CBF signal &
&
& ≥1
3PhInitCBF
&
BI:External 3-phase
Internal 3-phase
T_alarm：”CBF BIAlarmTime”
Figure 135 Logic diagram of internal and external initiating CBF
267
Initiating circuit breaker failure logic diagram is shown as follow:
“CBFChkCBPosn” &
PhACBClosePosn
≥1
&
PhACBFStartup
PhAInitCBF
“CBFChkCBPosn” &
PhBCBClosePosn
≥1
CBFCurrCriteriaPhBLiveCurr
&
PhBCBFStartup
PhBInitCBF
“CBFChkCBPosn”
&
PhCCBClosePosn
≥1
&
PhCCBFStartup
PhCInitCBF
“CBFChkCBPosn”
&
3PhCBClosePosn
≥1
CBFCurrCriteria3PhLiveCurr &
3PhCBFStartup
3PhInitCBF
Figure 136 Logic diagram of initiating circuit breaker failure
268
Circuit breaker failure stage 1 trip logic diagram is shown as follow:

T ≥1
PhACBFStartup
CBFStage1TripPhA
T ≥1
PhBCBFStartup
CBFStage1TripPhB
T ≥1
PhCCBFStartup
CBFStage1TripPhC
&
&
≥1
&
CBFStage1Trip3Ph
T
3PhCBFStartup
T：“CBFTime1”
Figure 137 Circuit breaker failure stage 1 trip logic diagram

Single-phase initiating CBF time delay three-phase trip logic diagram is
shown as follow:
“CBFStage1 1PhTrip3Ph”
&
≥1 T
CBFPhAStartup
& ≥1
≥1 T
CBFPhBStartup CBFStage1 1PhTrip3Ph
CBFPhCStartup &
≥1 T
CBFStage1Trip3Ph
T：“CBFStage1 1PhTrip3PhTime”
Figure 138 Single phase initiating CBF time delay three-phase trip
269
Circuit breaker failure stage 2 trip logic diagram is shown as follow:
T
PhACBFStartup
T
PhBCBFStartup
≥1
T
PhCCBFStartup CBFStage2Trip
T
3PhCBFStartup
≥1
&
BI (CBFaiI)
T：“CBFTime2”
Figure 139 Circuit breaker failure stage 2 trip logic diagram

Type Description
DIcom.BIInitA_CBF External phase A initiating failure signal
DIcom.BIInitB_CBF External phase B initiating failure signal
DIcom.BIInitC_CBF External phase C initiating failure signal
External three-phase initiating circuit breaker
DIcom.BIInit3P_CBF
failure signal
CBF.BIBlk BI blocking
Input Internal phase A initiating circuit breaker failure
CBF.TrInitA
signal
Internal phase B initiating circuit breaker failure
CBF.TrInitB
signal
Internal phase C initiating circuit breaker failure
CBF.TrInitC
signal
Internal three-phase initiating circuit breaker
CBF.TrInit3P
failure signal
Circuit breaker failure Spring discharge binary
CBF.CBFail
input
Initiating failure: external initiating failure signal,
CBFail.CBF_Init
internal initiating failure signal
CBFail.TripA Failure stage 1 protection trip phase A
Output CBFail.TripB Failure stage 1 protection trip phase B
CBFail.TripC Failure stage 1 protection trip phase C
CBFail.Tri3p Failure stage 1 protection trip three phase
270
Type Description
CBFail.Trip1 Trip of circuit breaker failure stage 1
Time of three-phase trip of circuit breaker failure
CBFail.Trip1pTr3p
stage 1
CBFail.Trip2 CBFStage2Trip
3.3 Setting list

Table 118 The setting of circuit breaker failure protection
Default
value
1. CBFCurrSet 0.05In~40.0In 10 0.01 A
Three times of
2. CBF3I0Set 0.05In ~40.0In 10 0.01 A zero sequence
current
Three times of
negative
3. CBF3I2Set 0.05In ~40.0In 10 0.01 A
sequence
current
4. CBFTime1 0.00～100.00 100 0.01 s
5. CBFTime2 0.00～100.00 100 0.01 s
CBFStage1
6. 0.00～100.00 100 0.01 s
1PhTrip3PhTime
7. CBF BIAlarmTime 0.00～100.00 100 0.01 s
Table 119 Circuit breaker failure logic switch

Default
value
Enable/disable circuit breaker
1. CBFOn 1/0 0
failure protection
When "1PhCBFOn"=1, the
single phase trip configured with
2. 1PhCBFOn 1/0 0
internal startup failure protection
can start the failure.
Enable or disable failure stage 1
3. CBFStage1 1PhTrip3Ph 1/0 0
trip three phase
Enable/ disable circuit breaker
4. CBFChk3I0/3I2 1/0 0 failure check negative sequence
current
Enable/disable circuit breaker
5. CBFChkCBPosn 1/0 0
failure check position
271
3.4 Report list


Trip report:
1. Intr3PhInitCBF /
2. Extr3PhInitCBF /
3. IntrPhAInitCBF /
4. ExtrPhAInitCBF /
5. IntrPhBInitCBF /
6. ExtrPhBInitCBF /
7. IntrPhCInitCBF /
8. ExtrPhCInitCBF /
9. CBFStage1Trip /
10. CBFStage1 1PhTrip3Ph /
11. CBFStage2Trip /
12. PhACBFTrip
13. PhBCBFTrip
14. PhCCBFTrip
15. 3PhCBFTrip
Alarm report:
1. CBF BIErr /

Table 121 Circuit breaker failure protection technical data

Current setting
Setting of negative
sequence current 0.05In to40.00In ≤ ±2.5% setting or ±0.02In
Zero sequence current
setting
Time 1 of circuit breaker
0.00s~100.00s ≤ ± 1% times of setting or +25ms,
failure
when trip current is set as 200%
Time 2 of circuit breaker
0.00s~100.00s setting
failure
Reset time less than 30ms
272
Chapter 19 Dead zone protection (50DZ)
Chapter 19 Dead zone protection

(50DZ)
About this chapter

dead zone protection.
273
1 Introduction
IED provides dead zone protection to detect dead zone fault, i.e. when
circuit breaker is in open position, a fault occurs between CT and circuit
breaker. So, when circuit breaker auxiliary contact shows that the circuit
breaker is in open position, IED can detect fault current of dead zone.
For busbar side CT, when dead zone fault occurs, IED trips all circuit
breakers on the busbar where the fault bay is located. Trip logic is shown
as follow,
Trip
Busbar
IFAULT
Line1 Line2 LineN
Legend：
Circuit breaker division position
Circuit breaker close position
Figure 140 Busbar side trip logic diagram

For line side CT, when dead zone fault occurs, IED sends remote trip
command to the other IED which located on the opposite side. Trip logic is
shown as follow,
Internal trip
Busbar
IFAULT
Line1 Line2 LineN
Trip
Device
Legend:
Circuit breaker division position

Circuit breaker close position
Figure 141 Line side trip logic diagram
274

The input and output signals of dead zone protection function diagram are
shown as follow:
Dead Zone Protection

1 1
BIBlk Start
2 2
CBOpen Operation
3 3
BI_IntDZ Alarm
4
SigIntDZ
Figure 142 The input and output signals of dead zone protection function diagram
right.
Input:
DIcom 1: Breaker trip position
CBOpen If the split phase position needs to be satisfied,
the three phase positions are all divided
Input:
BIBlk BI blocking
DZ External startup dead zone binary input (whose
BI_IntDZ configure is almost the same with that of
initiating CBF binary input)
Sign of trip starting dead zone: can be
SigIntDZ
configured by Mask-I0
Output:

DeadZone
Operation Time delay is over, IED trips
Alarm Abnormal alarm of external BI
When dead zone protection function is enabled and binary input blocking
is disabled, if "DZProtOn"=1, then the corresponding dead zone protection
is enabled.
The trip conditions are shown as follow:
1) The trip start dead zone protection sign is 1, or the external start dead
zone binary input is 1 and there is no external binary input abnormal
alarm. ;
275
2) The circuit breaker shall be in trip position;

3) Fundamental current𝐈𝐈Ф > “𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃𝐃” (Ф=A, B, C);
4) Enabled or disabled the criterion of zero current and negative
sequence current by setting the logic switch "DZChk3I0/3I2". If the
logic switch is set as 1, the zero or negative sequence current is also
necessary to be greater than the corresponding setting.
If the trip conditions are met, time component starts, when time is over,
"DZTrip" is issued. LED and output can be configured by AESP. At the
same time, the three phase fundamental current Ia, Ib, Ic, zero and
negative sequence current are output. When current or circuit breaker
position is not satisfied, timing component returns, dead zone protection
resets.
When the existing time of external BI initiating dead zone is longer than the
alarm time settings, "DZBIErrAlarm”will be issued. LED and output can be
configured by AESP.
276
&
“DZChk3I0/3I2”=0
Ia>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ic>“DZCurrSet”
3I0>“DZProt3I0Set”
&
Ib>“DZCurrSet”
Ic>“DZCurrSet”
& ≥1 ≥1
≥1 & Dead zone current
Ia>“DZCurrSet” conditions are met
“DZChk3I0/3I2”=0 &
Ic>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ia>“DZCurrSet”
DZProtFncOn
BIBlk
Dead zone current

conditions are met
&
&
3PhTripPosn T
DZTrip
≥1
SigIntDZ
&
T_BIErr
BI_IntDZ
DZ BIErrAlarm
“DZProtOn”=1
T：“DZTime”
T_BIErr：“BIErrAlarmTime”
Figure 143 Dead zone logic diagram
277

Type Description
DZ. BIBlk BI blocking function
External startup dead zone binary input (whose
Input DZ.BI_IntDZ configure is almost the same with that of
initiating CBF binary input)
Sign of trip starting dead zone: can be
DZ.SigIntDZ
configured by Mask-I0
DeadZone.Start IED startup
Output DeadZone.Operation IED trip
DeadZone.Alarm IED alarm
3.3 Setting list

Table 124 Dead zone protection setting
Default
value
1. DZCurrSet 0.05In~40In 10 0.01 A
2. DZTime 0～100 100 0.01 s

Three times of zero
3. DZProt3I0Set 0.05In~40In 40 0.01 A
sequence current
Three times of negative
4. DZProt3I2Set 0.05In~40In 40 0.01 A
sequence current
5. BIErrAlarmTime 0.00～100 100 0.01 s
Table 125 Dead zone logic switch
1. DZProtOn 1/0 0
2. DZChk3I0/3I2 1/0 0
3.4 Report list

Trip report:
1. DZTrip /
Alarm report:
1. DZ BIErrAlarm /
278

Table 127 Dead zone protection technical data

Current setting 0.05In to40.00In ≤ ±2.5% times of setting or ±0.02In
≤ ±1% setting or +40ms,when
Time setting 0.00s to100.00s operation value is 200% current
setting
279
Chapter 20 Stub protection (50STUB)
About this chapter

This chapter describes the protection principle, the input and
output signals, setting parameters, messages and technical
parameters for stub protection.
281
1 Introduction
The stub protection protects the zone between the CTs and the open
isolator. The stub protection is enabled when the open position of the
dis-connector is informed to the IED through connected binary input.
The function is equipped with stage 1 time limit settings.

Stub protection function input and output signals are shown as follow:
STUB-Bus Overcurrent Stage
1 1
DSOpen Start
2 2
BIBlk Operation
Figure 144 The input and output signals of stub protection function diagram
right.
Input:
DIcom 1: Isolator is in the open position; 0:
DSOpen
Isolator is in the close position
Input:
STUB
BIBlk BI blocking
Output:
STUB_Protection Start IED startup
Operation Stub protection trip
The stub protection is an overcurrent protection which is only in service if
the status of the line isolator indicates the open condition. Stub protection
is disabled while the isolator is at the close position. The stub protection
provides definite time stage with changeable time delay. CBF protection
can be enabled or disabled by setting the logic switch. Corresponding
current setting can be inserted in setting. When the current is more than
settings and the time is delayed to later, the protection device sends out a
trip command or alarm signal. LED and output can be configured by AESP.
282
Ia>“StubCurrSet”
≥1
Ib>“StubCurrSet”
Ic>“StubCurrSet”
&
IsoOpenPosn T
StubTrip
BIBLK
“StubOn”=1
T：“StubTime”
Figure 145 Stub protection function logic

Logic diagram of application scenarios:
Bus line A
CB1
STUB-Bus
CT1 Overcurrent fault
Line1
Switch1
CB3
CT3
Line2
Switch2
CT2
CB2
Bus line B
Figure 146 3/2 Connection mode Stub protection

Type Description
1: Isolator is in the open position; 0: Isolator is in
DIcom.DSOpen
Input the close position
STUB.BIBLK BI blocking function
STUB_Protection.Start IED startup

Output
STUB_Protection.Operation IED trip
283
3.3 Setting list

Table 130 Setting of stub protection
Default Step
value
0.01 Current setting of
1. StubCurrSet 0.05In~40In 40 A
stub protection
0.01 Time of stub
2. StubTime 0～100 100 s
protection
Table 131 ProtBinSet
Default
value
1. StubOn 0, 1 0 0: disable; 1: enable
3.4 Report list

Trip report:
1. StubTrip /

Table 133 Stub protection technical parameters
Current setting 0.05In to 40.00In ≤±2.5% times of setting or ±0.02In

Time setting 0.00s to100.00s ≤±1% setting or +40ms,when
operation value is 200% current
setting

Note: In: CT secondary rating, 1A or 5A.
284
Chapter 21 Pole discrepancy protection (62PD)
Chapter 21 Pole discrepancy protection

(62PD)
About this chapter

pole discrepancy protection.
285
1 Introduction
Under normal operating condition, all three poles of the circuit breaker
must be closed or open at the same time. The phase separated operating
circuit breakers can be in different positions (close-open) due to electrical
or mechanical failures. This can cause negative and zero sequence
currents which gives thermal stress on rotating machines and can cause
unwanted operation of zero sequence or negative sequence current
functions.
Single pole opening of the circuit breaker is permitted only in the short
period related to single pole dead times, otherwise the circuit breaker is
tripped three pole to resolve the problem. If the problem still remains, the
remote end can be intertripped via circuit breaker failure protection
function to clear the unsym-metrical load situation.
The pole discrepancy function operates based on information from
auxiliary contacts of the circuit breaker for the three phases with additional
criteria from unsymmetrical phase current.

Pole discordancy protection function input and output signals are shown
as follow:
Pole-Discrepancy Protection
1 1
BIBlk Start
2 2
CBOpenA Operation
3 3
CBOpenB Alarm
4
CBOpenC
Figure 147 Pole discrepancy protection function input and output signals diagram
right.
Input:
PD
BIBlk BI blocking
Input:
CBOpenA Trip position of phase A

DIcom
CBOpenB Trip position of phase B
CBOpenC Trip position of phase C
Output:

Pole_Discrepancy
Operation IED trip
Alarm IED alarm
286
The circuit breaker position signals are connected to IED via binary input in
order to monitor the circuit breaker state. Pole discrepancy conditions are
met, when logic switch “PDProtOn” is set to 1 and at least one pole is open
and at the same time not all three poles are closed. The auxiliary contact
of the circuit breaker is inspected by the corresponding phase current.
When the auxiliary contact signal of the circuit breaker is indicated as an
open, the current is in phase, and after the 5S, the device alarm is made of
"PDProtectTripPosnErr". LED and output can be configured by AESP.
Additionally the function can be informed via logic switch “HV PD Chk
3I0/3I2” and “MV PD Chk 3I0/3I2”for additionally zero and negative
sequence current as well as current criteria involved in CBF protection.
Pole discrepancy can be detected when current is not flowing through all
three poles. When current is flowing through all three poles, all three poles
must be closed even if the circuit breaker auxiliary contacts indicate a
different status.
After pole discrepancy protection trip, LED, IED output and others can be
configured by AESP.
3.2 Logic diagram

Pole discrepancy protection logic diagram is as below:
Trip position A &
Ia > 0.06In
≥1
Trip position B &
Ib > 0.06In
Trip position C &
Ic > 0.06In
&
5s
PDProtectTripPosnErr
“PDProtOn”=1
Trip position A
&
Trip position B
Trip position C
Trip position A &

&
T_PD
Ia < 0.06In PDTrip
≥1
Trip position B &
Ib < 0.06In
Trip position C &
Ic < 0.06In
3I2 > 3I2Set ≥1
3I0 > f3I0Set
&
≥1
“PDChk3I0/3I2”=1
“PDProtOn”=1
3I2Set：“PD3I2Set”
3I0Set：“PD3I0Set”
Figure 148 Pole discrepancy protection logic diagram
287

Type Description
configuration
Input PD. BIBlk BI blocking function
Pole_Discrepancy.Start IED startup
Output Pole_Discrepancy.Operation IED trip
Pole_Discrepancy.Alarm IED alarm
3.4 Setting list

Table 136 Pole discrepancy protection setting
Default Step
Range
No. Setting name value Unit Remark
(In:5A/1A)
(In:5A/1A)
Zero sequence
current rating of
1. PD3I0Set 0.05In~40In 40 0.01 A
pole discrepancy
protection
Negative
sequence current
2. PD3I2Set 0.05In~40In 40 0.01 A rating of pole
discrepancy
protection
Pole discrepancy
3. PDTripTime 0～100 10 0.01 s
protection time
Table 137 Pole discrepancy protection logic switch
Logic switch
No. Setting Default value Remark
description
Enable pole discrepancy protection
1. PDProtOn 1/0 0
1-Enable, 0-Disable
Pole discrepancy checks zero and
2. PDChk3I0/3I2 1/0 0 negative sequence current
1-Check, 0-Not check
3.5 Report list

Trip report:
1. PDStart /
2. PDTripPosnErr /
3. PDTrip /
288

Table 139 Pole discrepancy protection technical parameter

Current 0.05In to 40.00In ≤ ±2.5% setting or ±0.02In
≤ ±1% setting or +40 ms, when
Time delay 0.00s to 60.00s
200% setting
Note: In is CT rated secondary current, 1A or 5A.
289
Chapter 22 Broken conductor protection (46BC)
Chapter 22 Broken conductor

protection (46BC)
About this chapter

parameters for disconnection protection.
291
1 Introduction
The system will monitor the volume of load in real time.
This protection function has the following characteristics:
1) Be able to test the negative sequence current
2) Detect the ratio of negative and positive sequence current.

Input and output signals of broken conductor protection are shown as
follow:
Broken Conductor
1 1
BIBlk Start
2 2
CBOpen Operation
3
Alarm
Figure 149 The input and output signals of broken conductor protection function
diagram
right.
Input:
BC
BIBlk BI blocking
Input:
CBOpenA Trip position A

DIcom
Output:

BC_Protection
Operation Broken conductor trip
Alarm Primary failure alarm
292
The logic diagram of broken conductor protection is shown in as follow
figure.
BrokenConductorProtFcnOn
BIBLK
&
PhATripPosn
≥1
PhBTripPosn
&
PhCTripPosn ≥1
“BrokenConductorChkCBPosn”=1
&
T &
“BrokenConductorChkCBPosn”=0
BrokenConductorTrip
3I2>“BrokenConductor3I2Set” &
“BrokenConductorChk3I2”=1 ≥1
&
BrokenConductorAlarm
“BrokenConductorChk3I2”=0 &
3I2>3I1×“I1/I2Coef”
“BrokenConductorOn”=1
“BrokenConductorTripOn”=1
T：“BrokenConductorTime”
Figure 150 Broken conductor protection logic diagram

Where:
f3I1:secondary side positive sequence current value;
f3I2:secondary side negative sequence current value;
I2_Set:“BrokenConductor3I2Set”;
I2_Set: “I1/I2Coef”；
Tset: “BrokenConductorTime”.
After IED outputs "BrokenConductorTrip", LED, IED output and others can
be configured by AESP.

Type Description
Input BC.BIBLK BI blocking function
BC_Protection.Start IED startup
Output BC_Protection.Operation IED trip
BC_Protection.Alarm IED alarm
293
3.3 Setting list

Table 142 Broken conductor protection setting
Default Step
value
0.01 Three times of
1. BrokenConductor3I2Set 0.05In~40In 40 A negative sequence
current
0.01
2. I1/I2Coef 0.2～1 1
0.01
3. BrokenConductorTime 0～100 100 s
Table 143 Broken conductor protection logic switch

Default
value
1. BrokenConductorOn 1/0 0 0: disable; 1: enable
2. BrokenConductorTripOn 1/0 1 0: disable; 1: enable

1: test the negative
sequence current
3. BrokenConductorChk3I2 1/0 0
0: test positive sequence
ratio value
0: non-check circuit breaker
position
4. BrokenConductorChkCBPosn 1/0 0
1: check circuit breaker
position
3.4 Report list

Trip report:
1. BrokenConductorTrip /
2. BrokenConductorAlarm /

Table 145 Technical parameters
Current setting 0.05In to 40.00In ±2.5% setting or ±0.02In

≤±1% setting or +40ms,when operation
Time setting 0.00s to 100.00s
value is 200% current setting
Dropoff coefficient About 0.95
294
Chapter 23 Underfrequency protection (81UF)
Chapter 23 Underfrequency protection

(81UF)
About this chapter

parameters for underfrequency protection.
295
1 Introduction
Unfrequency and load shedding protection monitors the performance of
grid by testing the decreasing frequency. Underfrequency load shedding
will trip and certain load will be eliminated as the frequency is lower than
the setting of underfrequency load shedding protection or other conditions.
The main features of underfrequency load shedding protection are as
follow:
1) Undervoltage blocking;
2) Undercurrent blocking;
3) Frequency change rate(df/dt) blocking;
4) Circuit breaker position check and loaded current blocking;
5) VT secondary circuit failure blocking.
There are four stages of underfrequency load shedding protectiona and
each stage can be enabled and disabled separately.

The input and output signals of underfrequency load shedding protection
Under Frequency protection
1 1
BIBlk Start
2 2
CBOpen Operation
Figure 151 The input and output signals of underfrequency load shedding protection
diagram
right.
Input:
UF*
BIBlk BI blocking
Input:
DIcom
CBOpen Trip position
Output:
UFStage* Start IED startup
Operation IED trip
Note: “*” in the table is the stage number of underfrequency protection.
296
3.1.1 Protection function introduction
The principle of underfrequency load shedding protection is "load shedding
by bay". Specifically, the principle means that each interval will be
configured with underfrequency load shedding protection rather than the
incoming line interval will be configured with underfrequency load
shedding protection and send off tripping command through outlet line
interval. As a result, each interval can be set to the appropriate frequency
setting to make the protection start, and the appropriate time setting to
make the protection trip. Based on "the principle of shedding in the line of
intervals", the device will be offered with 4 stages underfrequency load
shedding protection. Each stage will be enabled or disabled through
corresponding plate and underfrequency load shedding protection will be
enabled and disabled by principal plate, companying with each plate to
enable and disable. Trip frequency of underfrequency load shedding
protection can be tested by input Uab voltage. By enabling and disabling
logic switch "3PhVoltConnect" to choose the input voltage mode. Take
underfrequency load shedding stage 1 as example, as the measured
frequency is lower than settings "UFLSStage1FreqSet", the timing
component will start working; however, as it delays to the definite time
"UFLSStage1Time ", the configuration will send off tripping command. LED
and output can be configured by AESP.
As the trip frequency of underfrequency load shedding protection is
calculated by measuring voltage, underfrequency load shedding protection
will be blocked with meeting the following requirement.
1) When three-phase voltage is connected, the minimum phase-to-phase
voltage is lower than "LoadShedVoltBlkSet". When single-phase
voltage is connected, the highest phase-to-phase voltage is lower than
settings, "LoadShedVoltBlkSet";
2) The device detects VT failure or the device will detect high-level from
VT failure;
3) When "UFLSChkCurrOn" logic switch is enabled, loaded current is
lower than settings, "LoadShedCurrBlkSet". As voltage transformer is
configured at the side of power supply, it is useful to detect current
setting. As the circuit is blocking, "LoadShedCurrBlkSet" refers to as
the smallest loaded current;
4) Circuit breaker is at open position. If it is in the same case, as voltage
transformer is configured at the side of power supply, it is useful to
detect current setting. Meanwhile, although the frequency is lower
than the underfrequency load shedding setting, the protection will not
send off trip command;
5) When "UFLSChkDf/dt" logic switch is enabled:
The frequency change rate (Δf/Δt) is greater than the setting
"Df/dtBlkSet".
297
3.1.2 Logic diagram

Take underfrequency stage 1 protection as example, the logic diagram is
shown as follow.
“GenlUFLSOn”=1
&
“UFStage1On”=1
Frequency<
“UFLSStage1FreqSet”
Frequency<54Hz or
&
frequency>66Hz
system frequency=60Hz ≥1
frequency<45Hz or
&
frequency>55Hz
system frequency=50Hz
VTFailBlk
≥1
3PhTripPosn
BIBlk
max(Ia,Ib,Ic)<
&
“LoadShedCurrBlkSet” &
≥1 T1
UFStage1Trip
“UFLSChkCurrOn”=1
max(Uab,Ubc,Uca)<
&
“LoadShedVoltBlkSet”
min(Uab,Ubc,Uca)<
& ≥1
“LoadShedVoltBlkSet”
Absolute value of frequency

&
changing rate>“Df/dtBlkSet”
“UFLSChkDf/dt”=1
T1：“UFLSStage1Time”
Figure 152 Underfrequency load shedding stage 1 protection logic diagram

Type Description
configuration
Input UF*. BIBlk BI blocking function
UFStage*.Start IED startup

Output
UFStage*.Operation IED trip
Note: “*” in the table is the stage number of underfrequency protection.
298
3.3 Setting list

Table 148 Settings of underfrequency load shedding protection
Default Step
value
0.01 It is applied when
"UFLSChkDf/dt" logic
switch is enabled. The
1. Df/dtBlkFreqSet 0.9Fn~1.0Fn 49.5 Hz frequency is greater
than the setting,
slippage locking
returns
0.01
2. UFLSStage1FreqSet 0.9Fn~1.0Fn 49.5 Hz
0.01
3. UFLSStage1Time 0.00～600.00 100 s
0.01
0.01
0.01
0.01
0.01
0.01
0.01
10. Df/dtBlkSet 0.30～20.00 20 Hz/s
0.01 It is also used in
10.00～
11. LoadShedVoltBlkSet 120 V overfrequency
120.00 protection
0.01
12. LoadShedCurrBlkSet 0.05In~10.0In 10 A
Table 149 Logic switch of underfrequency load shedding

No. Setting Remark
description value
Enable or disable underfrequency load
1. GenlUFLSOn 1/0 0
shedding protection
2. UFStage1On 1/0 0
shedding stage 1 protection
3. UFStage2On 1/0 0
shedding stage 2 protection
4. UFStage3On 1/0 0
shedding stage three protection function
5. UFStage4On 1/0 0
shedding stage four protection function
6. UFLSChkDf/dt 1/0 0 0: no check df/dt; 1: Check df/dt
0: Single phase access; 1: three-phase
7. 3PhVoltConnect 1/0 1 access
Common setting
8. UFLSChkCurrOn 1/0 0 0: no check I; 1: check I
299
3.4 Report list

Trip report:
1. UFStage1Trip /
2. UFStage2Trip /
3. UFStage3Trip /
4. UFStage4Trip /

Table 151 Underfrequency load shedding protection technical parameter
Underfrequency load shedding
Rated frequency Fn=50Hz or 60Hz 0.9Fn to 1.0Fn ≤±20mHz

≤ ± 1.5% times of setting
Time setting 0.10 to 100.00s
or +60ms
Blocking condition
Frequency change rate blocking
0.3 to 20Hz/s ≤±0.5Hz/s
setting Δf/Δt
Blocking setting of load shedding ≤ ±2.5% times of setting or
10 to 120V
voltage ±1V
Blocking setting of load shedding ≤ ±2.5% times of setting or
0.05In to 10In
current ±0.01In
Notice: In: CT secondary rated current, 1A or 5A; Fn: 50Hz or 60Hz.
300
Chapter 24 Overfrequency protection (81OF)
Chapter 24 Overfrequency protection

(81OF)
About this chapter

parameters for overfrequency protection.
301
1 Introduction
Overfrequency protection is used to monitor whether the network is normal
by detecting the frequency. When the frequency is higher than the
overfrequency protection setting and also meets other conditions, the
overfrequency protection trips to remove the specified load.
Main characteristics of overfrequency protection are as follow:
1) Undervoltage blocking;
2) VT secondary circuit failure blocking.
There are four stages of overfrequency protection and each stage can be
enabled or disabled separately.

The input and output signals of overfrequency protection function diagram
Over Frequency protection
1 1
BIBlk Start
2
Operation
Figure 153 The input and output signals of overfrequency protection function diagram
right.
Input:
OF*
BIBlk BI blocking
Output:
OFStage* Start IED startup
Operation IED trip
Note: “*” in the table is the stage number of overfrequency protection.
The device offers 4 stages of overfrequency protection. Each stage will be
enabled or disabled through corresponding logic switch and overfrequency
protection will be enabled and disabled by principal logic switch, and
function of each stage can be enabled or disabled through logic switch of
each stage. Trip frequency of overfrequency protection can be tested by
302
input Uab voltage. By enabling and disabling logic switch

"3PhVoltConnect" to choose the input voltage mode. Take overfrequency
stage 1 as example, if the measured frequency is high than setting,
"OFStage1FreqSet", the timing component will start timing. As time delay
reaches "OFStage1Time", the equipment will send off trip command. LED
As the trip frequency of overfrequency protection is calculated by
measuring voltage, overfrequency protection will be blocked with meeting
the following requirement.
1) When three-phase voltage is connected, the minimum phase-to-phase
voltage is lower than "LoadShedVoltBlkSet". When single-phase
voltage is connected, the highest phase-to-phase voltage is lower than
settings, "LoadShedVoltBlkSet";
2) The device detects VT failure or the device will detect high-level from
VT failure;
3) Circuit breaker is at open position.
3.1.2 Logic diagram
Take overfrequency stage 1 protection as example, the logic diagram is
shown as follow.
OFProtFncOn
&
“OFStage1On”=1
Frequency>“OFSatge1FreqSet”
Frequency<54Hz or frequency>66Hz &
System frequency=60Hz ≥1
Frequency<45Hz or frequency>55Hz &
System frequency=50Hz
VTFailBlk
&
≥1 ≥1 T1
OFStage1Trip
3PhTripPosn
BIBlk
max(Uab,Ubc,Uca)<“LoadShedVoltBlkSet” &
“3PhVoltConnect”=0 ≥1
min(Uab,Ubc,Uca)<“LoadShedVoltBlkSet” &
T1：“OFSatge1Time”
Figure 154 Logic diagram of overfrequency stage 1 protection
303

Type Description
Input OF*. BIBlk BI blocking function
OFStage*.Start IED startup

Output
OFStage*.Operation IED trip
Note: “*” in the table is the stage number of overfrequency protection.
3.3 Setting list

Table 154 Overfrequency protection setting
Default
value
1. OFStage1FreqSet 1.0Fn~1.1Fn 52 0.01 Hz
2. OFStage1Time 0.00～600.00 100 0.01 s
4. OFStage2Time 0.00～600.00 100 0.01 s
6. OFStage3Time 0.00～600.00 100 0.01 s
8. OFStage4Time 0.00～600.00 100 0.01 s

Underfrequency
9. LoadShedVoltBlkSet 10.00～120.00 10 0.01 V
protection setting
Table 155 Logic switch of overfrequency protection
No. Setting Remark
description value
Enable or disable overfrequency
1. OFStage1On 1/0 0
stage 1 protection
2. OFStage2On 1/0 0
stage 2 protection
3. OFStage3On 1/0 0
stage 3 protection
4. OFStage4On 1/0 0
stage 4 protection
0: Single phase access; 1:
5. 3PhVoltConnect 1/0 1 three-phase access
Common setting
304
3.4 Report list

Trip report:
1. OFStage1Trip /
2. OFStage2Trip /
3. OFStage3Trip /
4. OFStage4Trip /

Table 157 Overfrequency protection technical parameter
Overfrequency
Rated frequency Fn=50Hz
1.0Fn to 1.1Fn ≤±20mHz
or 60Hz
Time setting 0.10 to 100.00s ≤±1.5% times of setting or +60ms
Blocking condition
Blocking setting of load
10 to 120V ≤±2.5% times of setting or ±1V
shedding voltage
Note: Fn: 50Hz or 60Hz.
305
Chapter 25 Frequency rate protection (81DF)
Chapter 25 Frequency rate protection

(81DF)
About this chapter

This chapter describes the frequency change rate protection
principle, input and output signals, setting parameter, IED
report and technical parameter.
307
1 Introduction
Frequency change rate protection is used to monitor whether the network
is normal by detecting the frequency. Device provides 4 stages frequency
change rate protection. If frequency change rate is greater than the setting
of frequency change rate protection and meets the other conditions at the
same time, frequency change rate protection will trip.

Frequency change rate protection function input and output signal diagram
is shown as follow:
Frequency rate of change protection

1 1
BIBlk Start
2
Operation
Figure 155 Frequency change rate protection function input and output signal diagram
right.
Table 158 Input
Input:
DF*
BIBlk BI blocking
Output:
DFStage* Start IED startup: start the timer
Operation IED trip
Note: “*” in the table is the stage number of configured frequency change
rate protection.
The device offers 4 stages frequency change rate protection. Each stage
will be enabled or disabled through corresponding logic switch and
frequency change rate protection will be enabled and disabled by principal
logic switch and function of each stage will be enabled or disabled through
logic switch of each stage. The trip frequency of frequency change rate
protection can be measured by the input the Uab voltage. By enabling and
disabling logic switch "3PhVoltConnect" to choose the input voltage mode.
Take frequency change rate stage 1 as example, if the measured
frequency is high than setting, "FreqDf/dtStage1Set", the timing
component will start timing. As time delay reaches
"FreqDf/dtStage1TimeSet", the equipment will send off trip command. LED
308

As the trip frequency of frequency change rate protection is calculated by
measuring voltage, frequency change rate protection will be blocked with
meeting the following requirement.
1) When "FreqDf/dtStage1DetectVolt" is enabled: When three-phase
voltage is connected, the minimum phase-to-phase voltage is lower
than "FrequencyDf/dtVoltPickup". When single-phase voltage is
connected, the highest phase-to-phase voltage is lower than settings,
"FrequencyDf/dtVoltPickup".
2) The frequency change rate has protection range, when
"Df/dtStage1ChkFreq" is enabled and the frequency is not in the range
("Df/dtStage1LFThreshold"~Df/dtStage1HFThreshold), the IED will be
blocked;
3) The frequency change rate has protection range, and when the
frequency is not in the range ("FreqDf/dtLowThreshold"~
“FreqDf/dtHighThreshold”), the IED will be blocked;
4) If the frequency is in the valid range (±15Hz of rated frequency), the
protection will be unblocked after 2 seconds.
5) The rate of change of frequency can be set by "DirModeDf/dtStage1"
to determine whether the rates of change of frequency move forward,
reverse or not. "DirModeDf/dtStage1" = 1 indicates positive direction;
"DirModeDf/dtStage1" = 2 indicates reverse direction;
"DirModeDf/dtStage1" = 3 indicates non-detection direction.
3.1.2 Logic diagram
Take frequency change rate protection stage 1 as example, the logic
diagram is shown as follow.
309
“GenlFreqDf/dtOn”=1
“FreqDf/dtStage1On”=1
&
“DirModeDf/dtStage1”=3
Absolute value of frequency changing rate

>“FreqDf/dtStage1Set”
Frequency changing rate>0

&
“DirModeDf/dtStage1”=1 ≥1 & T1
FreqDf/dtStage1Trip
Frequency changing rate<0

&
“DirModeDf/dtStage1”=2
45Hz<Frequency<75Hz &
System frequency=60Hz ≥1
2s
35Hz<Frequency<65Hz &
System frequency=50Hz
BIBlk
≥1
Absolute value of frequency changing rate ≥1
>“FreqDf/dtHighThreshold”

<“FreqDf/dtLowThreshold”
&
“Df/dtStage1ChkFreq”=1
Frequency>“Df/dtStage1HFThreshold” ≥1
Frequency<“Df/dtStage1LFThreshold”
Max(Uab,Ubc,Uca)<“FreqDf/dtVoltThreshold” &
Min(Uab,Ubc,Uca)<“FreqDf/dtVoltThreshold” & &
“FreqDf/dtStage1DetectVolt”=1
T1：“FreqDf/dtStage1Time”
Figure 156 Logic diagram of frequency change rate protection stage 1

Type Description
Input DF*. BIBlk BI blocking function
DFStage*.Start IED startup

Output
DFStage*.Operation IED trip
Note: “*” in the table is the stage number of configured frequency change
rate protection.
310
3.3 Setting list

Table 160 Frequency change rate protection setting (81DF)
Default
value
1. FreqDf/dtStage1Set 0.1～20 20 0.01 Hz/s
2. FreqDf/dtStage1Time 0.0～100.00 100 0.01 s
3. DirModeDf/dtStage1 1～3 1 1
4. Df/dtStage1HFThreshold 0.9Fn~1.1Fn 55 0.01
5. Df/dtStage1LFThreshold 0.9Fn~1.1Fn 45 0.01
19. Df/dtStage4HFThreshold 0.9Fn~1.1Fn 1.1Fn 0.01
20. Df/dtStage4LFThreshold 0.9Fn~1.1Fn 0.9Fn 0.01

30.00～
21. FreqDf/dtVoltThreshold 50 0.01 V
120.00
22. FreqDf/dtHighThreshold 0.00～20.00 20 0.01 Hz/s
23. FreqDf/dtLowThreshold 0.00～20.00 0.1 0.01 Hz/s
311
Table 161 Frequency change rate protection logic switch

Default
value
1. GenlFreqDf/dtOn 1/0 0
2. FreqDf/dtStage1On 1/0 0
3. FreqDf/dtStage1DetectVolt 1/0 0
4. Df/dtStage1ChkFreq 1/0 0

0: Single phase access; 1:
three-phase access
3.4 Report list

Trip report:
1. FreqDf/dtStage1Trip /
312

Table 163 Technical parameter of frequency change rate protection

0.1 to 20Hz/s ≤±0.5Hz/s
setting Δf/Δt
Time setting 0.10 to 100.00s ≤±1.5% setting or +60ms
Blocking condition
Upper limit of frequency
0.0 to 50Hz/s ≤±0.5Hz/s
change rate
Lower limit of frequency
0.0 to 50Hz/s ≤±0.5Hz/s
change rate
Blocking voltage 30 to 120V ≤±2.5% times of setting or ±1V
313
Chapter 26 Out of step protection (78)
About this chapter

output signals, parameter, IED report and technical data of
out-of-step protection.
315
1 Introduction
The out-of-step protection can measure the change track of impedance,
avoid the system short circuit and steady oscillation reliably, and
distinguish the acceleration losing step and the losing step during the
out-of-step swing.

Input and output signals are shown as follow:
OutOfStep_Protection
1
Start
2
Op
3
UP_Alarm
4
DOWN_Alarm
5
OUTER_Alarm
Figure 157 The input and output signal diagram of out-of-step protection function
The left is the input and the right is the output.
Output:
Start Out-of-step protection startup
Op Out-of-step trip in internal zone

OutOfStep_Protecti
on UP_Alarm Accelerate out-of-step protection alarm
Decrease the speed of out-of-step protection
DOWN_Alarm
alarm
OUTER_Alarm Out-of-step protection alarm in external zone
3.1.1 Take generator protection as an example:
The out-of-step protection generator can measure the change track of
impedance, avoid the system short circuit and steady oscillation reliably,
and distinguish the acceleration losing step and the losing step during the
out-of-step swing. In the out-of-step protection, the linear multi shield
feature is adopted, and the impedance plane is divided into many regions
by the resistance line. where, The XA of A is the transient reactance of
generator Xd’. The XB of the B point is the system connection reactance,
including system reactance Xs and transformer reactance Xt (convert to
the generator terminal voltage).
If the reactance of the generator is less than the reactance Xt of the
transformer, the oscillation center will fall into the inner part of the
316
transformer group. Rs in the diagram is resistance, the calculation formula

1
(X A + X B )ctg(StartAngle / 2)
is Rs= 2 , Rj is fixedly set as 0.5Rs by the
procedure.
jX
Zone6 Zone 5 Zone4 Zone3 Zone2 Zone1
Xs B
Xt
DecelerationOutOfStep AccelOutOfStep
-Rs -Rj 0 Rj Rs R
δ4 δ3 δ2 δ1
Figure 158 Multi-zone characteristics of generator out-of-step protection

The 1~3 region and the 6~4 region are symmetrical to the axis jX on the
impedance plane, and in the synchronous generator mode:
1) When the system is in normal operation, the generator changes the
impedance >Rs. its change path does not enter the 2~5 area;
2) When the generator loses its speed, the measuring impedance
passes through the 2, 3, 4, 5 and 6 zones sequentially from the zone 1,
and the residence time in each zone is longer than the corresponding
time;
3) When the generator loses its speed, the measuring impedance
passes through the 5, 4, 3, 2 and 1 zones sequentially from the zone 6,
and the residence time in each zone is longer than the corresponding
time;
4) When a short circuit fault occurs, the measured impedance will fall into
the next zone when it stays in any area of the 2~5 less than the
corresponding time;
5) When a steady oscillation occurs, the impedance passes through the
section and then returns backward, instead of passing through all the
regions in the same direction.
When the device detects that the starting motor is out of step, it sends out
the signal in time. When the out-of-step oscillation center falls inside the
generator transformer group, the slip times are counted and updated, and
the trip order is issued after reaching the setting pole times Nsb. Out of
step protection applies blocking measurement internally and sends trip
317
pulse as both sides of the electromotive force phase is less than

“TripAngle”. The circuit breaker can cut off the current in no more than its
breaking capacity, so as to ensure the safety of circuit breaker. In order to
improve the reliability of out of step protection, the change of active power
is taken as an auxiliary criterion.
Logic diagram of generator out-of-step protection is shown as follow.
Ride through from the right to
“OutOfStepProtOn” the left
IntrZoneAccelOutOfStepAlarm
“IntrZoneOutOfStepOn” & slip times reached

Nsb1
IntrZoneOutOfStepTrip
Generator terminal measurement impedance
ride through each district slowly
out-of-step oscillation center falls IntrZoneDecelOutOfStepAlarm

Ride through from the left to
inside the generator transformer group the right
Nsb1：“IntrZoneOutOfStepSlipTimes”
“OutOfStepProtOn”
Ride through from the

right to the left
“ExtrZoneOutOfStepOn” &
≥1
Generator terminal measurement
impedance ride through each district
slowly Ride through from the & ExtrZoneOutOfStepAlarm
left to the right
Out-of-step oscillation center falls slip times reached
outside the generator transformer group Nsb2
Nsb2：“ExtrZoneOutOfStepSlipTimes”
Figure 159 Logic diagram of out-of-step protection

1) “DistanceDwellTime1” and “DistanceDwellTime2”
Generator power angle δ changes in constant speed in consideration of
system oscillation. The time of impedance staying at Zone2 and Zone5 is
δ 2 − δ1
T= Ts . In which, TS is the smallest oscillation period in system (it is
360°
provided by dispatching center, and its value usually is 0.5s～1.5s), δ 1 is
Rj
δ 2 = 2ctg −1 δ −δ
120°, 1 . Setting T 1 = 0.5 2 1 Ts .
∑X 360°
2
180° − δ 2
The time of impedance staying at Zone3 and Zone4 is T ′ = Ts
360°
180° − δ 2
when system is oscillating, its setting value is T2 = 0.5 Ts .
360°
2) Number of slipping times of out-of-step protection NSb:
"IntrZoneOutOfStepSlipTimes" are generally set as 2 when oscillation
center is internally located.
3.1.2 Take line protection setting as an example:
In out-of-step condition, the step should be detected and the line between
1 and 2 of the substation should be tripped.
318
XA=Positive power supply reactance
XB Xt=“WholeLinePositiveS
eqX”
IED
Figure 160 Line application of out of step protection

If the cross of the reactance and reactance line XB-XA is considered, this
is the criterion for the check of out of step conditions:0
Protective setting parameters:
“XA”: Forward power supply reactance;
“XB”: Reverse power supply reactance;
Xt: "WholeLinePositiveSeqX"
AnglePHi: The impedance phase angle is adjusted to 88 degrees as an
example.
Use the following values:
UBase:400kV;
SBase: set to 1000MVA;
There is no protective line feed into the power station 1 short circuit power:
5000MVA (assuming pure reactance);
There is no protective line feed into the power station 2 short circuit power:
5000MVA (assuming pure reactance);
Line impedance: 2+j20 Ω , or Xt=20 Ω ;
All phase pressure and phase current are available and flow into the
protection IED. It is proposed that “SelPositiveSeqImped” is 1, which is the
positive sequence parameter.
Through per-unit system of XBase to complete the reactance adjustment,
as follow:
UBase 2 400 2
XBase = = = 160Ω
SBase 1000
20
Xt=20 Ω , corresponding to per-unit value Xt = = 0.126
160
400 2
XA = Xt + Xsc(statio n2) = 20 + = 52Ω
5000
52
The corresponding per-unit value: XA = = 0.325
160
400 2
XB = Xsc(statio n1) = = 32Ω
5000
32
The corresponding per-unit value: XB = = 0.2
160
319
The critical angle (StartAngle) should be selected as no cross angle and

normal operation area. The maximum line power is assumed to be
2000MVA (assumed to be pure reactance). Corresponding apparent
impedance:
U2 400 2
X = = = 80Ω
S 2000
Simplified, this can be expressed as a triangle, see below.
jX
XA
Xload
XB
Figure 161 A simplified StartAngle graph is derived

XB XA 32 52
StartAngle ≥ arctan + arctan = arctan + arctan ≈ 55 0
Xload Xload 80 80
Under the condition of small damping oscillation impedance, the normal
operation does not want to start the protection. Therefore, set the starting
angle with a large margin.
Set StartAngle to 110 degrees.
For the TripAngle, it is recommended to set this parameter to 90 degrees
to ensure that the circuit breaker stresses are limited.
In power systems, the network is intended to be the default part when the
step is out of step. Therefore, the protection is located in the default
decomposition that will occur on the online road.
Generally, "IntrZoneOutOfStepSlipTimes" is set to 1 so that the line can
trip when the first step is lost.
If line trips under all out-of-step conditions, the parameter
"ExtrZoneOutOfStepSlipTimes" is also set to 11, and in other cases, a
slightly larger number is recommended.
320
3.2 Configurable output nodes by the user

Type Description
configuration
OutOfStep_Protection.Start Out-of-step protection startup
OutOfStep_Protection.Op Out-of-step trip in internal zone

Accelerate out-of-step protection
Output OutOfStep_Protection.UP_Alarm
alarm
Decrease the speed of out-of-step
OutOfStep_Protection.DOWN_Alarm
protection alarm
Out-of-step protection alarm in
OutOfStep_Protection.OUTER_Alarm
external zone
3.3 Setting list

Table 166 Out-of-step protection setting
Default
value
WholeLinePositiveSe 0.05/ Setting in distance
1. 120 0.01 Ω
qX In~600/In protection
2. ImpedStayTime1 0.01～0.9 0.9 0.01 s
3. ImpedStayTime2 0.01～0.9 0.9 0.01 s
IntrZoneOutOfStepSli
4. 1～30 1 1
pTimes
ExtrZoneOutOfStepS
5. 1～30 1 1
lipTimes
For generator
protection: generator
transient reactance
6. XA 0/ In~500/In 100.0 0.01 Ω Xd
For line protection:
forward power supply
reactance
For generator
protection: system
connection reactance,
including system
reactance Xs and
transformer reactance
7. XB 0/ In~500/In 100.0 0.01 Ω
Xt (convert to
generator terminal
voltage) For line
protection: reverse
power supply
reactance.
Starting angle, the
generator is generally
8. StartAngle 0～180 120 0.01 ° set to 120 degrees;
the line is deduced
according to the
321
Default
value
deduction.
The trip angle is

allowed, and the
generator is normally
9. TripAngle 0～180 90 0.01 ° adjusted to 90
degrees, and the line
is generally adjusted
to 90 degrees.
Table 167 Out-of-step protection logic switch
Default
value
1. OutOfStepProtOn 1/0 0
2. IntrZoneOutOfStepOn 1/0 0
3. ExtrZoneOutOfStepOn 1/0 0
1: Select positive sequence
4. SelPositiveSeqImped 1/0 0
impedance
5. SelPhABPPZ 1/0 0
6. SelPhBCPPZ 1/0 0
7. SelPhCAPPZ 1/0 0
3.4 Report list

Trip report:
1. IntrZoneOutOfStepTrip /
Alarm report:
1. IntrZoneAccelOutOfStepAlarm /
2. IntrZoneDecelOutOfStepAlarm
3. ExtrZoneOutOfStepAlarm
322
Chapter 27 The direction protection of zero sequence
power (32N)
Chapter 27 The direction protection of

zero sequence power (32N)
About this chapter

This chapter describe the principles, the input and output signal,
the setting parameter, the message and technical parameter of
zero sequence power protection
323
power (32N)
1 Overview
In the system of the nurture point grounding to the earth directly, in the
case of high resistance grounding fault, one should calculate the
protection refuses to operate when the impedance falls outside the
distance impedance characteristic. Therefore, other protection trip is
needed to isolate the fault, zero sequence direction power protection can
reliably identify high resistance grounding fault.
the protection features of zero sequence direction are listed as following;
1) The configuration 1 stage of zero sequence power direction protection
2) Zero sequence power direction protection is blocked by the opening
circuit breaker of any phase;
3) The VT failure blocking of zero sequence power protection
4) Block the zero sequence overcurrent protection during non-full-phase
operation.

The input and output signals of zero sequence power protection show as
following:
Zero Sequence tower
trotection
1 1
BIBlk Start_3I0
2 2
ZspTimer Block BI Start_Zsp
3
Zsp_ACT
4
Operation
Figure 162 The input and output signal diagram of zero sequence power protection
right.
Input:
ZSP BIBlk BI blocking
ZspTimerBlockBI Timer blocking enable
Output:
Output when zero-sequence
Start_3I0 current is greater than
"ZSPProtPowerSet"
Output when the zero
ZSPower sequence power calculated by
Start_Zsp zero sequence direction is
greater than
"ZSPProtPowerSet"
Output when the duration that
Zsp_ACT
the zero sequence greater
324
power (32N)
than "ZSPProt3I0Set" reaches
200ms or the duration of the
zero sequence power
calculated by zero sequence
power direction greater than
"ZSPProtPowerSet" is greater
than "ZSPProtFundTime".
The trip of zero sequence
Operation
power direction protection
3.1.1 Component of zero sequence power direction
The zero sequence power Sr of zero sequence direction protection is
calculated by zero sequence voltage and zero sequence current. The
formula is as follows:
Sr = |3𝑈𝑈0 | × |3𝐼𝐼0 | × cos(θ − 180° − Ф0 )
Where:
θ：Power Factor Angle of 3𝐼𝐼0 and 3𝑈𝑈0
3.1.2 Inverse time characteristic
The formula of time T calculated by the inverse time characteristic of zero
sequence direction is:
𝑆𝑆𝑟𝑟𝑟𝑟𝑟𝑟
t=K×
𝑆𝑆𝑟𝑟
Where:
K: "InvTZSPProtDropoffCoefK";
Sref :"InvTimeZSPProtRef";
Sr : Calculated value of zero sequence power
3.1.3 The instruction of user-defined configuration
1) Zero Sequence Power Direction Protection startup has three outputs
for user-defined configuration to trigger wave recording and protect
startup:
When the current of zero sequence is larger than the output of
"ZSPProt3I0Set", ZSP_Start_3I0 outputs;
When the zero sequence power calculated by zero sequence power
direction is greater than "ZSPProt3I0Set", there is ZSP_Start_Zsp output;
When the duration of zero sequence current greater than "ZSPProt3I0Set"
reaches 200ms, or the duration of zero sequence power calculated in zero
sequence power direction is greater than "ZSPProtPowerSet" and
325
power (32N)
"ZSPProtFundTime", Zsp_ACT output;
The user can choose ZSP_Start_3I0, ZSP_Start_Zsp, Zsp_ACT to trigger
the wave recording and protection startup. The configuration method is
connecting the setting selected output custom logic. connect to
"FAULT_POU::ExtStartup", as shown in the figure below.
2) The trip of zero sequence power direction protection output
ZSP_Operation, user defined configuration whether to enable
reclosing
The configuration method is link ZSP_Operation to
"FAULT_POU::ExtTripInitAR3P", and protect the startup of recloser as the
following figure.
Figure 163 The user-defined configuration
3.1.4 Other instructions

Consider that the zero sequence power direction protection does not
misoperate during acceleration after auto-reclosing and manual-closing,
as follows:
1) Manual closing acceleration, the minimum operating time of zero
sequence power direction protection is 40ms.
2) Accelerate after auto-reclosing and input zero sequence power
direction protection delay 100ms.
3) The trip time of zero sequence power protection is the sum of the
"ZSPProtFundTime" and the inverse time calculated by limit
characteristics.
3.1.5 Logic diagram
Logic diagram is shown as follow:
&
VTFailBlk &
0.2s 0 ≥1
Zero Sequence Power Direction
Open position of any Protection startup
phase circuit breaker (Zsp_ACT)
3I0˃“ZSPProt3I0Set” &
& t Zero Sequence Power
Ta 0 Direction Protection Trip
ZSP_Operation
Sr˃“ZSPProtPowerSet”
Timer blocking enable

(ZSP. ZspTimerBlockBI)
ZSP_Start_3I0
Ta：“ZSPProtFundTime” (ZSPower.Start_3I0)
Sr:Calculated value of zero sequence power ZSP_Start_Zsp

(ZSPower.Start_Zsp)
t：Calculated inverse time delay
Figure 164 The logical diagram of zero sequence power direction protection
326
power (32N)
Type Description
configuration
ZSP.BIBlk BI blocking function
Input
ZSP. ZspTimerBlockBI Timer blocking enable
Output when
zero-sequence current is
ZSPower.Start_3I0
greater than
"ZSPProtPowerSet"
Output when the zero
sequence power calculated
ZSPower.Start_Zsp by zero sequence direction
is greater than
"ZSPProtPowerSet"
Output when the duration
that the zero sequence
Output greater than
"ZSPProt3I0Set" reaches
200ms or the duration of the
zero sequence power
ZSPower.Zsp_ACT
calculated by zero
sequence power direction
greater than
"ZSPProtPowerSet" is
greater than
"ZSPProtFundTime".
The trip of zero sequence
ZSPower.Operation
power direction protection
ZSP_Start_3I0 、 ZSP_Start_Zsp 、 The logic and configurative
The variables
Zsp_ACT starting reclosure can be set
available
ZSP_Operation up
3.3 Setting list

Table 171 Zero power protection setting
Default
Number Setting name Range Step Unit Remark
value
Three
times of
1. ZSPProt3I0Set 0.05In~40In 0.1 0.01 A zero
sequence
current
2. ZSPProtPowerSet 0.3In~6In 0.5 0.03 W
3. InvTimeZSPProtRef 0.84In~100In 17.32In 0.01 W
4. InvTZSPProtDropoffCoefK 0.00~2.0 0 0.01
5. ZSPProtFundTime 0.00~10.0 1 0.01 s

Common
6. 3I0DirectSensitiveAngle 0.00~90.00 70 0.01 °
setting
327
power (32N)
Table 172 The logical switch of zero sequence power direction protection
Default
Number Logic switch description Setting Remark
value
Enable and disable
the function of the
1. ZSPDirProtOn 1/0 0
zero sequence power
direction protection
1: The CT failure
blocking of zero
sequence power
protection
2. CTFailBlkZSPDirProt 1/0 0
0: The CT failure
without blocking of
zero sequence power
protection
3.4 Report list

Number Report name Remark
Trip report:
1. ZSPDirProtTrip /

Table 174 The technical parameter of zero sequence power direction protection

Current setting 0.05In~40.00In’
±0.01In
328
Chapter 28 Switch-on-to-fault protection (50SOTF)
Chapter 28 Switch-on-to-fault
protection (50SOTF)
About this chapter

This chapter describes the principles of switch-onto-fault
protection, input and output signals, setting parameter,
329
1 Introduction
Switch-onto-fault protection (SOTF) is used to protect sub-protection of
overcurrent and earth fault protection. The function shares similarity in
logic trip, trip principle and trip report. Switch-onto-fault protection will not
work if circuit breaker is closed. The trip time will start function after validity.
It is mean that switch-onto-fault protection will not open in short time.

The input and output signals of switch-onto-fault protection function
Switch-Onto-Fault Protection
1 1
BIBlk Start
2 2
BI_SOTF OCOp
3 3
CBOpen EFOp
4
SOTFErr
Figure 165 The input and output signals of Switch-onto-fault protection function
diagram
right.
Input:
SOTF
BIBlk BI blocking
Input:
DIcom BI_SOTF Manual close binary input
CBOpen Open position of circuit breaker
Output:
SOTF_Protection OCOp Trip of switching on to fault overcurrent
EFOp Trip of switch-on-to-fault zero sequence current
SOTFErr Error of manual close binary input
As circuit breaker is closed for a while, switch-onto-fault protection needs
to be detected that if there is any fault in line through detecting current
value.
330
As logic switch "SOTFChkBI" is set 1, "SOTF BI" changes from 0 to 1 and

there is no any protection startup, SOFT function works. If three-phase
current is greater than "SOTFOCSet" and experience "SOTFOCTime" or
zero sequence current is greater than "SOTF3I0Set" and experiences
"SOTF3I0Time", switch onto fault protection trip. As "SOTF BI" appears
decreasing, switch-on-to function is still functioning within
"SOTFStateLatchedTime". If the time of "SOTF BI" as high voltage level is
greater than "BIErrTimeSet", the device will send an alarm and a report
"SOTF BIErrAlarm". LED and output can be configured by AESP.
As logic switch "SOTFChkPosn" is 1, and if circuit breaker stays open
position an delay time is greater than "OpenPosnConfirmTime" and if
three-phase current is greater than "SOTFOCSet", it will experience
"SOTFOCTime" or zero sequence current is greater than "SOTF3I0Set"
and experience "SOTF3I0Time", switch-onto-fault will trip. LED and output
When the position condition changes from 1 to 0, the hand hold function is
still in effect when the delay is within the latching time value of the hand
hold state.
Blocking requirement: 2nd harmonic blocking. The second harmonic check
is carried out when the logic switch "SOTFFaultChk2ndH" is set 1.
3.1.2 Logic diagram
Logic diagram is shown as follow:
“SOTFOn”=1
“SOTFChkBI/Posn”=0
&
SOTF BIErrAlarm
≥1
T1
BI_SOTF
&
≥1
BI from one to zero

&
T2
≥1
Switch-onto-fault
permission
“SOTFChkBI”=1
“SOTFChkPosn”=1
&
3PhOpenPosn &
&
T3
3PhCloasePosn
≥1
BI from one to zero
T2
“SOTFChkBI/Posn”=1
“SOTFOn”=1
T1：“BIErrTime”
T2：“SOTFStateLatchedTime”
T3：“OpenPosnConfirmTime”
Figure 166 Logic diagram of switch-onto-fault permission
331
Switch-onto-fault permission
&
T1 &
BIBlk
SOTF OCTrip
Ia（Ib，Ic）>“SOTFOCSet”
“SOTFFaultChk2ndH”=1 &
≥1
3PhInrushCurrBlk
“SOTFFaultChk2ndH”=0
Switch-onto-fault permission
&
&
T2 SOTF 3I0Trip
BIBlk
3I0>“SOTF3I0Set”
T1：“SOTFOCTime”
T2：“SOTF3I0Time”
Figure 167 SOTF function logic diagram

Type Description
configuration
SOTF.BIBLK BI blocking function
Input
DIcom.BI_SOTF Manual close binary input
SOTF_Protection.Start IED startup

Trip of switching on to fault
SOTF_Protection.OCOp
overcurrent
Output
Trip of switch-on-to-fault zero
SOTF_Protection.EFOp
sequence current
SOTF_Protection.SOTFErr Error of manual close binary input
3.8 Setting list

Table 177 Switch-onto-fault protection
Default
value
7. SOTF OCSet 0.05In~40In 40 0.01 A
Three times of
8. SOTF3I0Set 0.05In~40In 40 0.01 A zero sequence
current
9. SOTFOCTime 0.00～100.0 100 0.01 s
10. SOTF3I0Time 0.00～100.0 100 0.01 s
11. OpenPosnConfirmTime 0.00～100.0 10 0.01 s
332
Default
value
12. SOTFStateLatchedTime 0.00～100.0 0.04 0.01 s
13. BIErrTime 0.00～100.0 10 0.01 s
Table 178 Switch-onto-fault protection

Default
value
Enable or disable
3. SOTFOn 1/0 0
switch-onto-fault protection
4. SOTFChkBI/Posn 1/0 0
5. SOTFChkPosn 1/0 0
6. SOTFChkBI 1/0 0
7. SOTFFaultChk2ndH 1/0 0
3.9 Report list

Trip report:
2. SOTF OCTrip /
3. SOTF 3I0Trip /
Alarm report:
1. SOTF BIErrAlarm /

Table 180 Technical parameters of switch-onto-fault protection

±0.01In
≤ ±1% setting or +40ms,when
Time setting 0.00 to 100.00s operation value is 200% current
setting
333
Chapter 29 Overload alarm (50OL)
About this chapter

This chapter describes the principles of overload alarm, the
input and output signals, setting parameters, messages and
335
1 Introduction
Overload alarm function enabled logic switch “OLAlarmOn” enable,
overload alarm function cannot be used as trip.

The input and output signals of overload protection function diagram are
shown as follow:
Overload
1 1
En Alarm
2
BIBlk
Figure 168 The input and output signals of overload protection function diagram
right.
Input:
BIBlk BI blocking
Overload
Output:
Alarm Overload Alarm output
Logic switch "OLAlarmOn" is set to 1. When the current of any phase of
the three-phase current is greater than "OLAlarmCurrSet", and "OLAlarm"
is issued when the delay time reaches the setting of "OLAlarmTime". LED
3.1.2 Logic diagram
The logic diagram of overload function is shown in following figure. When
any phase current is greater than "OverloadAlarmCurrSet" and the delay
reaches to send "OverloadAlarm" after "OverloadAlarmTime" is set.
336
&
Iφ> “OLAlarmCurrSet” Tset
OLAlarm
“OLAlarmOn”
Tset ：“OLAlarmTime”
Figure 169 Overload logic diagram

Type Description
Input Overload.BIBLK BI blocking function
Output Overload.Alarm Alarm
3.3 Setting list

Table 183 Overload Alarm Protection Setting
Default
value
1. OLAlarmCurrSet 0.05In~40In 40 0.01 A
2. OLAlarmTime 0.0～3600 100 0.01 s
Table 184 Overload protection logic switch list

Logic switch
No. Setting Default value Remark
description
Enable or disable
1. OLAlarmOn 1/0 0
overload alarm function
3.4 Report list

Alarm report:
1. OLAlarm /

Table 186 Overload alarm protection technical parameter
Time setting 0.00 to 3600.00s ≤ ±1% or 40ms

Minimum alarm
About equal to 10ms
time
337
Chapter 30 Synchro-check and dead voltage check (25)
Chapter 30 Synchro-check and dead

voltage check (25)
About this chapter

parameters for synchronization and voltage check.
339
1 Introduction
Synchronization voltage check ensures that when line is connected with
busbar, electricity system will latch stable. If the difference between the
charging line voltage and the bus voltage, phase difference and the
frequency difference are in allowable range, the function of voltage
synchronization will be met.
Synchronization check function need to detect that the voltage beside
circuit breaker properly meet the synchronization function or at least one
side is non-electric power which can ensure the safety of closing.
When the voltage on both sides is needed to be detected, the voltage
selected for synchronization is the busbar side voltage or the line side
voltage. If the voltage transformer used by protection is connected with line
sides, the reference voltage must adopt busbar voltage.

The input and output signals of synchronization voltage check function
Synchro-Check with Live/Dead
Line/Bus Measurement
1 1
CBOpenA syn_Req(MC)
2 2
CBOpenB syn_meet(MC)
3 3
CBOpenC LowU_meet(MC)
4 4
V1P_MCB syn_time(MC)
5 5
BI_MC Override(MC)
6 6
SyncChkMode LDBL_meet(MC)
7 7
ChkDLLB LLBD_meet(MC)
8 8
ChkLLDB LDBD_meet(MC)
9 9
ChkDLDB MCOut(MC)
10 10
SyncChkMode(MC) DU_Fail(MC)
11 11
ChkDLLB(MC) DF_Fail(MC)
12 12
ChkLLDB(MC) DAng_Fail(MC)
13
ChkDLDB(MC)
Figure 170 Input and output signals of synchronization voltage check function diagram
right.
Input:
CBOpenA Trip A

DIcom
V1P_MCB Sampled voltage abnormal BI

Manual close binary input, used in manual
BI_MC
synchronization function
340
SyncChkMode Synchronization check mode input
ChkDLLB Check dead line live busbar input
ChkLLDB Check live line dead busbar input
ChkDLDB Check dead zone of both sides input
SyncChkMode(MC) Manual synchronization check mode input
ChkDLLB(MC) Manual check dead line live busbar input
ChkLLDB(MC) Manual check live line dead busbar input
ChkDLDB(MC) Manual check dead zone of both sides input
Output:
syn_Req(MC) Manual close synchronization request
syn_meet(MC) Manual close synchronization is met
LowU_meet(MC) Undervoltage condition of manual close are met
syn_time(MC) Manual close synchronization timeout
Override(MC) Manual close override mode
MCSyn LDBL_meet(MC) Switch-onto-fault dead line live busbar output
LLBD_meet(MC) Switch-onto-fault live line dead busbar output
LDBD_meet(MC) Switch-onto-fault dead line dead busbar output
MCOut(MC) Manual close condition is met
DU_Fail(MC) Synchronization voltage difference failure
DF_Fail(MC) Synchronization frequency difference failure
DAng_Fail(MC) Synchronization angle difference failure
Synchronization function is suitable for auto-reclosing function or manual
close function or both of them. Therefore, the following situation needs
synchronization check function:
1) Internal or external auto-reclosing request;
2) Switch-onto-request.
Internal or external auto-reclosing signal and manual close signal will be
connected with synchronization function signal. If the device receives the
synchronization signal, the device can be closed through different
synchronization modes.
Automatic closing and switch-onto-closing is on the choice list:
341
1) Synchronization closing mode of auto-reclosing includes

"OverrideModeOn", "CheckSyncMode", "CheckDLLBMode",
"CheckLLDBMode" and "CheckBothSidesNonVoltageMode".
2) Manual synchronization closing mode includes "MCOverrideModeOn",
"MCSyncChkMode", "MCChkDLLBOnMode", "MCChkLLDBOnMode"
and "MCChkDLDBOnMode".
Synchronization closing mode of auto-reclosing can be switched through
input “DIcom. SyncChkMode”, “DIcom. ChkDLLB”, “DIcom. ChkLLDB”,
“DIcom. ChkDLDB”or the logic switch“SyncChkModeOn”, “ChkDLLBOn”,
“ChkLLDBOn”, “ChkDLDBOn”; Synchronization closing mode can be
switched through input “DIcom. SyncChkMode(MC)”、“DIcom.
ChkDLLB(MC)”、“DIcom. ChkLLDB(MC)”、“DIcom. ChkDLDB(MC)” or the
logic switch “MCSyncChk”、“MCChkDLLBOn”、“MCChkLLDBOn” 、
“MCChkDLDBOn”
Synchronization closing mode of auto-reclosing includes
"OverrideModeOn", "SyncChkModeOn", "ChkDLLBOn", "CheckLLDB" and
"ChkDLDBOn". Manual synchronization closing mode includes
"MCOverrideModeOn", "MCSyncChk", "MCChkDLLBOn",
"MCChkLLDBOn" and "MCChkDLDBOn".
&
“BISwitchSyncChkMode”=1
DIcom. SyncChkMode
& ≥1
SyncChkMode
DIcom. ChkDLLB
&
≥1
DIcom. ChkLLDB ChkDLLBMode
&
DIcom. ChkDLDB
≥1
ChkLLDBMode
&
“BISwitchSyncChkMode”=0
“SyncChkModeOn” &
≥1
“ChkDLLBOn” ChkDLDBMode
&
“ChkLLDBOn”
&
“ChkDLDBOn”
Figure 171 Auto-reclosing check synchronization mode

Note: whether the four synchronization modes of auto-reclosing can be put into the
user-defined configuration at the same time, the configuration method is as follows:
1) By default, four synchronization modes are allowed to be put into operation at
the same time;
2) If the four synchronization modes are not allowed to be put into operation at the
342
same time, the synchronization mode that is not allowed to be put into operation
at the same time should be logically connected to "fault"_ On POU::
synmodeerrblksyn ", it can realize the blocking and reclosing when any two
synchronization modes are connected at the same time .（“FAULT_POU::
SyncChkModeOn”(SynchronizationCheck)、“FAULT_POU:: ChkDLLBOn”
（CheckDeadLineLiveBusbar）、“FAULT_POU:: ChkLLDBOn”（Check live
line dead busbar）、“FAULT_POU:: ChkDLDBOn”（Check dead zone of both
sides））
&
“BISwitchMCSyncChkMode”=1
DIcom. SyncChkMode(MC)
& ≥1
MCSyncChkMode
DIcom. ChkDLLB(MC)
&
≥1
DIcom. ChkLLDB(MC) MCChkDLLBOnMode
&
DIcom. ChkDLDB(MC)
≥1
MCChkLLDBOnMode
&
“BISwitchMCSyncChkMode”=0
“MCSyncChkMode” &
≥1
“MCChkDLLBOn” MCChkDLDBOnMode
&
“MCChkLLDBOn”
&
“MCChkDLDBOn”
Figure 172 Manual closing synchronization check mode

Different switching modes can be configured through AESP for lights and
outputs. The above synchronization closing modes can be explained as
follow:
1) Synchronization check mode: as soon as choose this kind of
synchronization closing modes, the device will receive synchronization
request singles and then continually check whether it is satisfied the
requirement of synchronization or not;
2) Override mode : when this kind of synchronization closing mode is
chosen, the device will receive synchronization request signals and
continually check whether it is satisfied the synchronization
requirement;
3) Check line non-voltage busbar voltage mode: as soon as this kind of
synchronization closing modes are chosen, the device will receive
synchronization request singles and check whether the line side has
no voltage, and busbar has voltage;
343
4) Check line voltage busbar non-voltage mode: as soon as this kind of

synchronization closing modes are chosen, the device will receive
synchronization request singles and check whether the line side has
voltage, and busbar has no voltage;
5) Check both sides non-voltage mode, check dead line and dead busbar
mode: when this kind of synchronization closing mode is chosen, the
device will receive synchronization request signals and check whether
the line side has no voltage, and busbar has no voltage.
Synchronization voltage has various choice modes. Reference voltage
U4=UX can serve as phase-to-phase voltage or phase voltage.
Synchronization setting: "VoltFromLineVT" is 0 means that voltage
transformer protection is connected with busbar side, then reference
voltage U4 is line voltage. That "VoltFromLineVT" is 1 means that voltage
transformer protection is connected with busbar side, then reference
voltage U4 is phase-to-phase of busbar.
Under the condition of check line busbar voltage and non-voltage: if dead
line live bus mode and dead line dead bus mode are both enabled at the
same time, the device is "check line non-voltage and close" mode; when
live line dead bus mode and dead line dead bus mode are enabled at the
same time, the device is "check busbar non-voltage and close".
3.1.2 Synchronization check mode:
Synchronization check function can use device to measure the voltage
amplitude difference, frequency difference and phase difference. Device
will receive synchronization request signals and continually check whether
it is satisfied the synchronization requirement. When the phase-to-phase
voltage and busbar voltage are all larger than "SyncChkMinVolt" and
meets the synchronization check requirements, the auto-reclosing will trip.
During the time of existing synchronization check, the device will receive
synchronization request signal and continually check that it is satisfied the
requirement of synchronization. However, as the arrival of"
SyncDetectTimeOff", the device stop checking synchronization
requirement. If during "SyncDetectTimeOff ", synchronization requirement
is satisfied, timing component will stop timing and start closing.
Switch-onto-fault check synchronization phase will be set by "SyncPh";
When the "3PhVoltConnect" =1, the auto-reclosing synchronization phase
is self-adaptive; When the "3PhVoltConnect" =0, auto-reclosing
synchronization phase is set by "SyncPh". If auto-reclosing
synchronization phase difference and manual close synchronization phase
difference are chosen differently, 10s alarm "SyncPhSelConflict" will turns
out.
Synchronization check should be met the following requirement.
1) Three-phase voltage should be greater than "SyncChkMinVolt";
2) Selecting voltage should be greater than "SyncChkMinVolt";
3) Voltage difference should be in the limit of "SyncVoltDiffSet";
4) Angle difference should be in the limit of "SyncAngleDiffSet";
5) Frequency difference should be in the limit of "SyncFreqDiffSet".
Note: check synchronization can detect phase-to-earth voltage and
phase-to-phase voltage. When the sampled voltage is greater than the
344
minimum phase-to-phase voltage (i.e., 1.732* "SyncChkMinVolt"), it is

considered that the sampled voltage UX is connected to the
phase-to-phase voltage. When judging synchronization voltage abnormal
and phase voltage difference is calculated for the same period, it should be
noted that UX is calculated as the phase-to-phase voltage. Manual close
synchronization is the same.
If synchronization check is applied to manual close function, the
corresponding BI should be high power level, and timing component will
start timing “MCWaitSyncTime”. During "MCWaitSyncTime", if
synchronization requirement is satisfied and the time is longer than
"CheckSyncTime", timing component will stop and "MCSyncMet" will be
issued. "MCSyncMet" signal will latch the same in the following situations:
1) Manual close synchronization check requirements are satisfied;
2) Manual close synchronization requests high power level;
3) Delay "MCWaitSyncTime" not come yet;
4) Manual close synchronization check sends off closing command, the
following requirements should be satisfied:
a) Three-phase voltage should be greater than
"MCSyncChkMinVolt";
b) Selecting voltage should be greater than "MCSyncChkMinVolt";
c) Voltage difference should be in the limit of "MCSynVoltDiffSet";
d) Angle difference should be in the limit of "MCSynAngleDiffSet";
e) Frequency difference should be in the limit of
"MCSynFreqDiffSetting".
3.1.3 Modes of dead voltage check:
Under modes of dead voltage check, check the conditions of dead voltage
after sending synchronization requirement.If line voltage is lower than
"CheckNonVoltageMaxVoltage", reclosing can be conducted.If the voltage
of the line and the bus line are larger than "ChkDeadVoltMaxVolt", it can be
selected whether to choose automatically switch to synchronous mode by
the logical switch "DeadVoltChkFailSyncChk".This change is only for
automatic reclosing mode.
Synchronization is start when time delay of auto-reclosing is reached and
constantly judge if it meets no voltage condition during
"SyncDetectTimeOff". Send reclosing order if it meets conditions during
"SyncDetectTimeOff".
Non-voltage check sends off closing command, the following requirements
should be satisfied.
1) “ChkDLLBMode”, the line voltage that is detected by check dead
voltage is lower than dead voltage setting, and busbar voltage is
higher than live voltage setting;
2) “ChkLLDBMode”, dead voltage check needs to detect that line voltage
ratio is higher than the setting and busbar voltage ratio is lower than
setting;
3) “ChkDLDBMode”, both the line voltage that is detected by check dead
345
voltage and busbar voltage are lower than dead voltage setting.
3.1.4 Override mode
During non-synchronization mode, receiving synchronization request at
any time, synchronization requirements will be satisfied.
When auto-reclosing override mode is auto-reclosing, the device will send
off "AROverrideMode" report.
When manual close override mode is auto-reclosing, the device will send
off "MCOverrideMode" alarm report.
When there is setting error of auto-reclosing mode synchronization, alarm
of "ARLSErr" will be sent by the decice. As shown in logic
diagram,figure169.
3.1.5 Logic diagram
≥1
“3PhARModeOn”
“1/3PhARModeOn”
&
≥1
“OverrideModeOn”
“ARLSErr”
Synchronization check mode

&
≥1
Check dead line live
busbar mode
Check line voltage busbar non
voltage mode
Check dead zone of

both sides mode
Figure 173 Synchronization mode setting error logic diagram
346
Ua(Ub,Uc) >“MCSyncChkMinVolt”
≥1
Ux>“MCSyncChkMinVolt” &
&
T1
Anglediff<“MCSyncAngleDiffSet” SyncChkMet/ChkDeadVoltMet
& Three-phase
Freqdiff<“MCSyncFreqDiffSet” trip
Udiff<“MCSyncVoltDiffSet” SOTF BI BI_MC
MCSyncChkMode T2 SyncChkTimeout/
VTFailBlk ChkDeadVoltFail
MCChkDLLBOnMode
Ux <“MCChkDeadVoltMaxVolt” &
&
≥1
“VoltFromLineVT”
&
Ux>“MCSyncChkMinVolt”
Ua(Ub,Uc) <“MCChkDeadVoltMaxVolt” &
MCChkLLDBOnMode
&
Ux<“MCChkDeadVoltMaxVolt” &
Ua(Ub,Uc) <“MCChkDeadVoltMaxVolt”
MCChkDLDBOnMode
&
MCChkDLLBOnMode
&
Ux>“MCSyncChkMinVolt”
Ua(Ub,Uc) <“MCChkDeadVoltMaxVolt”
&
Ux <“MCChkDeadVoltMaxVolt” &
MCChkLLDBOnMode
T1：“MCSyncChkTime”
T2：“MCWaitSyncTime”
Figure 174 Manual close synchronization check logic diagram
347
Ua(Ub,Uc) >“SyncChkMinVolt”
Ux>“SyncChkMinVolt”
Anglediff<“SyncAngleDiffSet”
&
Freqdiff<“SyncFreqDiffSet” ≥1
&
&
Udiff<“SyncVoltDiffSet” T1 SyncChkMet/
ChkDeadVoltMet
SyncChkMode
≥1
ChkDLLBMode
VTFailBlk
ChkLLDBMode
T2 SyncChkTimeout/
ChkDeadVoltFail
ChkDLDBMode
ChkDLLBMode
Ux <“ChkDeadVoltMaxVolt” & &

≥1
&
Ua(Ub,Uc) <“ChkDeadVoltMaxVolt” &
ChkLLDBMode
&
Ux<“ChkDeadVoltMaxVolt” &
Ua(Ub,Uc) <“ChkDeadVoltMaxVolt”
ChkDLDBMode
&
ChkDLLBMode
&
Ua(Ub,Uc) <“ChkDeadVoltMaxVolt”
&
&
Ux <“ChkDeadVoltMaxVolt”
ChkLLDBMode
T1：“SyncDetectTime”
T2：“SyncDetectTimeOff”
Figure 175 Synchronization check function logic diagram

Type Description
configuration
DIcom.BI_MC Manual close binary input
DIcom.SyncChkMode Synchronization check mode
DIcom.ChkDLLB Check dead line live busbar
DIcom.ChkLLDB Check live line dead busbar

Input
DIcom.ChkDLDB Check dead zone of both sides
DIcom.SyncChkMode(MC) Manual synchronization check mode
DIcom.ChkDLLB(MC) Manual check dead line live busbar
DIcom.ChkLLDB(MC) Manual check live line dead busbar
348

Type Description
configuration
DIcom.ChkDLDB(MC) Manual check dead zone of both sides
MCSync.syn_Req Manual close synchronization request
MCSync.syn_meet Manual close synchronization is met

Undervoltage condition of manual
MCSync.LowU_meet
close are met
MCSync.syn_time Manual close synchronization timeout
MCSync.Override Manual close override mode

Switch-onto-fault dead line live busbar
MCSync.LDBL_meet
output
Output Switch-onto-fault live line dead busbar
MCSync.LLBD_meet
output
Switch-onto-fault dead line dead
MCSync.LDBD_meet
busbar output
MCSync.MCOut Manual close condition is met
Manual close synchronization voltage
MCSync.DU_Fail
difference failure
Manual close synchronization
MCSync.DF_Fail
frequency difference failure
Manual close synchronization angle
MCSync.DAng_Fail
difference failure
3.3 Setting list

Table 189 Setting of synchronization check and dead voltage check
Default
value
1. SyncDetectTime 0.02～100.00 100 0.01 s
2. SyncDetectTimeOff 0.05～100.00 100 0.01 s

1: Ua
2: Ub
3: Uc
4: Uab
3. SyncPh 1-6 1 1 5: Ubc
6: Uca
Only when
"3PhVoltConnect" is
0
4. SyncAngleDiffSet 1.00～80.00 10 0.01 °
5. SyncVoltDiffSet 1.00～40.00 40 0.01 V
6. SyncFreqDiffSet 0.02～2.00 2 0.01 Hz
7. ChkDeadVoltMaxVolt 10.00～50.0 17 0.01 V
8. SyncChkMinVolt 30.00～65.00 40 0.01 V
349
Table 190 Logic switch of synchronization check and dead voltage check
Default
value
1. OverrideModeOn 1/0 0
1: Switch synchronization check
mode through input “DIcom.
SyncChkMode”, “DIcom.
ChkDLLB”, “DIcom. ChkLLDB”,
“DIcom. ChkDLDB”;
2. BISwitchSyncChkMode 1/0 0
0: Switch synchronization check
mode through logic switch
“SyncChkModeOn”,
“ChkDLLBOn”, “ChkLLDBOn”,
“ChkDLDBOn”
3. SyncChkModeOn 1/0 0
4. ChkDLLBOn 1/0 0
5. ChkLLDBOn 1/0 0
6. ChkDLDBOn 1/0 0
DeadVoltChkFailSyncC
7. 1/0 0
hk
1-voltage connection line VT
8. VoltFromLineVT 1/0 0
0-voltage connection busbar VT
Table 191 Manual close synchronization setting
Default
value
1. MCSyncChkTime 0.02～100.00 100 0.01 s
2. MCWaitSyncTime 0.05～100.00 100 0.01 s

1: Ua
2: Ub
3: Uc
3. SyncPh 1-6 1 1
4: Uab
5: Ubc
6: Uca
4. MCSyncVoltDiffSet 1.00～40.00 40 0.01 V
5. MCSyncAngleDiffSet 1.00～10.00 10 0.01 °
6. MCSyncFreqDiffSet 0.02～2.00 2 0.01 Hz
7. MCChkDeadVoltMaxVolt 10.00～50.0 17 0.01 V
8. MCSyncChkMinVolt 30.00～65.00 40 0.01 V
350
Table 192 Manual close synchronization

Default
value
1. MCSyncOn 1/0 0
2. MCOverrideModeOn 1/0 0
1: Switch manual closing
synchronization check mode
through input “DIcom.
SyncChkMode(MC)”,
“DIcom. ChkDLLB(MC)”,
“DIcom. ChkLLDB(MC)”,
“DIcom. ChkDLDB(MC)”
3. BISwitchMCSyncChkMode 1/0 0
0: Switch manual closing
synchronization check mode
through logic switch
“MCSyncChk”,
“MCChkDLLBOn”,
“MCChkLLDBOn,
“MCChkDLDBOn”
4. MCSyncChk 1/0 0
5. MCChkDLLBOn 1/0 0
6. MCChkLLDBOn 1/0 0
7. MCChkDLDBOn 1/0 0
1-Voltage connection line
8. VoltFromLineVT 1/0 0 VT;0-Voltage connection
busbar VT
3.4 Report list

Trip report:
1. SyncVoltExchg /
2. MCVoltDiffFail
3. MCFreqDiffFail
4. MCAngleDiffFail
5. MCDeadVoltChkFail Manual synchronization function
6. MCSyncRequest
7. MCSyncMet
8. MCSyncUVMet
351
9. MCSyncTimeout
10. MCOverrideMode
11. MCSyncVoltExchg
12. MCMet
13. MCChkDLLBMet
14. MCChkLLDBMet
15. MCChkDLDBMet
Alarm report:
1. SyncVoltErr No detection when VT failure occurs

Manual close synchronization function, no
2. MCSyncVoltErr
detection when VT failure occurs
Alarm of auto-reclosing synchronization phase
3. SyncPhSelConflict difference and manual close synchronization
phase difference choosing differently

Table 194 Synchronization check and dead voltage check technical parameters

Synchronization check mode
1) Check synchronization
2) Check dead voltage, if the check
dead voltage is failure, it is the
check synchronization.
3) Override
Trip mode Modes of dead voltage check:
1) Line (V4) non-voltage busbar
(V3Ph) non-voltage
2) Line (V4) non-voltage busbar
(V3Ph) voltage
3) Line 4(V4) voltage busbar (V3Ph)
non-voltage
The setting of line or
Phase voltage: 10 to 50 V (phase ≤ ± 3% times of setting
busbar dead voltage
voltage ) or 1V
setting
The live voltage setting Phase voltage: 30 to 65 V (phase ≤ ± 3% times of setting
of line or busbar voltage ) or 1V
∆V-voltage difference 1 to 40V(phase-to-earth voltage) ≤±1V
Δf-frequency difference
0.02 to 2.00Hz ≤±20mHz
(f2>f1; f2<f1)
Δα- angle difference
1° to 80° ≤±3°
(α2>α1; α2<α1)
352

Synchronization check ≤ ± 1.5% times of setting
0.02 to 100.00s
time or +60ms
Disable
synchronization check 0.05 to 100.00s ≤ ± 1% setting or +50ms
time
353
Chapter 31 Auto-reclosing (79)
About this chapter

This chapter describes the principles of auto-reclosing
function, the input and output signals, setting parameters,
reports and technical parameters.
355
1 Introduction
When transient faults occur to lines, auto-reclosing function can be reset to
operate. Statistics show that 85% of the faults are transient faults, after
auto-reclosing, these faults will disappear. Therefore, temporal short circuit
may occur in the line. After auto-reclosing function tripping, the line will be
charged again. If the fault is permanent or short circuit arc current has not
disappeared, the protection will trip circuit breaker again.
Main features of auto-reclosing function are shown as follow:
1) There are 4 times of auto-reclosing (available);
2) Each auto-reclosing delay of single phase auto-reclosing /
three-phase auto-reclosing can be set independently;
3) Externally BI start auto-reclosing/protection trip start auto-reclosing;
4) Single-phase trip initiates auto-reclosing / three-phase trip initiates
auto-reclosing;
5) Monitoring of circuit breaker position;
6) Breaker auxiliary contacts monitoring;
7) To coordinate with auto-reclosing check synchronization function;
8) Support 3/2 wiring type.

Auto-reclosing function input and output signals are shown as follow:
356
Three-Pole Auto-Reclosure
1 1
BIBlk syn_Req
2 2
FinalTrip syn_meet
3 3
PHA_CBOpen LowU_meet
4 4
PHB_CBOpen syn_time
5 5
PHC_CBOpen Ph3TripInitAR
6 6
AR_OFF Ph3CBOTripInitAR
7 7
AR_BLOCK Ph1TripInitAR
8 8
CB_FAULTY Ph1CBOTripInitAR
9 9
PHA_INIT_AR AR_IN
10 10
PHB_INIT_AR Ph3TripBlkAR
11 11
PHC_INIT_AR Ph1TripBlkAR
12 12
PH3_INIT_AR ARFail
13 13
AR_WAIT ARSucc
14 14
V1P_MCB AR_FinalTrip
15 15
SinglePhaseARMode AR_Trip
16 16
ThreePhaseARMode AR_Block
17 17
IntegratedPhaseARMode FirstARTrip
18 18
StopARMode SecondARTrip
19 19
SyncChkMode ThirdARTrip
20 20
ChkDLLB FourthARTrip
21 21
ChkLLDB AR_Lockout
22 22
ChkDLDB CBFaulty
23
ARFullCharge
24
WaitToSlave
Figure 176 Auto-reclosing function input and output signal diagram

right.
Table 195 Function description
Input:
AR
BIBlk BI blocking
Input:
When the signal of starting auto-reclosing
ARFinalTRIP protection that is configured in IO Matrix is
FinalTrip sent to this pin, and the corresponding
section is protected by blocking
auto-reclosing.
Input:
PHA_CBOpen Trip position of phase A
DIcom PHB_CBOpen Trip position of phase B
PHC_CBOpen Trip position of phase C
AR_OFF Enable or disable auto-reclosing
357
AR_BLOCK Block auto-reclosing binary input
CB_FAULTY Spring discharge binary input

Initiating auto-reclosing binary input of phase
PHA_INIT_AR
A
PHB_INIT_AR
B
PHC_INIT_AR
C
Three-phase Initiating auto-reclosing binary
PH3_INIT_AR
input
Reclosing waiting for BI
AR_WAIT Under “3/2BreakerConnectMode”, used
when “AfterCloseSide”=1
V1P_MCB Sampled voltage abnormal BI
Single-phase auto-reclosing mode enable
SinglePhaseARMode
binary input
Three-phase auto-reclosing mode enable
ThreePhaseARMode
binary input
Integrated phase auto reclosing mode enable
IntegratedPhaseARMode
binary input
Stopping auto-reclosing mode enable binary
StopARMode
input
SyncChkMode Synchronization check mode input
ChkDLLB Check dead line live busbar input
ChkLLDB Check live line dead busbar input
ChkDLDB Check dead zone of both sides input
Output:
syn_Req Auto-reclosing synchronization request
syn_meet Auto-reclosing synchronization is met
LowU_meet Undervoltage conditions are met
syn_time Synchronization timeout
Ph3TripInitAR Three-phase trip initiates auto-reclosing

Three-phase spontaneous trip initiates
Ph3CBOTripInitAR
auto-reclosing
AutoReclosure
Ph1TripInitAR Single phase trip initiates auto-reclosing
Single phase spontaneous trip initiates
Ph1CBOTripInitAR
auto-reclosing
AR_IN Auto-reclosing is in process
Ph3TripBlkAR Three-phase trip blocking auto-reclosing
Ph1TripBlkAR Single phase trip blocks auto-reclosing
ARFail Auto-reclosing unsuccessfully
ARSucc Auto-reclosing is successful
358

Auto-reclosing trip three-phase and
AR_FinalTrip
blocking auto-reclosing
AR_Trip Auto-reclosing trip
AR_Block Auto-reclosing blocking
FirstARTrip Primary auto-reclosing trip
SecondARTrip Second auto-reclosing trip
ThirdARTrip Third auto-reclosing trip
FourthARTrip Fourth auto-reclosing trip
AR_Lockout Enforced three phases trip
CBFaulty Circuit breaker unprepared
ARFullCharge Auto-reclosing is fully charged

Reclosing waiting for BO
Used under “3/2BreakerConnectMode”=1
and “AfterCloseSide”=0.
WaitToSlave
As the first closing side circuit breaker, it is to
drive the output waiting for the after closing
side circuit breaker
Auto-reclosing function can be used for split phase circuit breaker and
three-phase circuit breaker, providing up to four times of coincidence, the
number of auto-reclosing can be adjusted by "ARTimes". Because of the
difference between the single-phase fault and the arcing time of the
three-phase fault, the auto-reclosing function provides the setting of "single
phase reclosure delay setting n" and "three-phase auto-reclosing delay
setting n" (n=1, 2, 3, 4).
3.1.1 Auto-reclosing startup
Auto-reclosing could be initiated by internal protection trip or by external BI
auto-reclosing.
The back-up protections that can collocate with internal protection trip to
initiate auto-reclosing include: overcurrent stage 1, overcurrent stage 2,
overcurrent stage 3, overcurrent stage 4, earth fault current stage 1, earth
fault current stage 2, earth fault current stage 3, earth fault current stage 4,
negative sequence current stage 1, negative sequence current stage 2,
negative sequence current stage 3, negative sequence current stage 4,
emergency overcurrent stage 1, emergency overcurrent stage 2,
emergency earth fault stage 1, emergency earth fault stage 2.
359
Table 196 Configurable initiate reclosing node

Configurable initiate Configurable nodes in IO
Description
reclosing node Matrix configuration
Phase A meets overcurrent trip, phase
OCStage*.PhaseA
A trip signal
Phase B meets overcurrent trip, phase
Overcurrent protection OCStage*.PhaseB
B trip signal
Phase C meets overcurrent trip, phase
OCStage*.PhaseC
C trip signal
Earth fault protection. EFStage*.Operation Earth fault protection trip
EFStage*SeltTrip.Trip
Earth fault protection trip phase A
A
Earth fault protection trip phase B
Earth fault definite time B
select stage trip on EFStage*SeltTrip.Trip
Earth fault protection trip phase C
C
Earth fault protection trip three phase
3P
EMOCStage*.Phase Phase A meets emergency overcurrent
A trip, phase A trip signal
Emergnecy overcurrent EMOCStage*.Phase Phase B meets emergency overcurrent
protection B trip, phase B trip signal
EMOCStage*.Phase Phase C meets emergency overcurrent
C trip, phase C trip signal
Emergnecy earth fault EMEFStage*.Operati
Emergency earth fault protection trip
overcurrent protection on
Negative sequence NOSCStage*.Operati Negative sequence current protection
current protection on trip
When the signal of starting auto-reclosing protection that is configured in
IO Matrix is sent to the pin of ARFinalTRIP->FinalTrip, and the
corresponding section is protected by blocking auto-reclosing.
The auto-reclosing logic is blocked after the backup protection operation is
started for the reconfiguration of the internal protection trip.
3.1.2 Single auto-reclosing
The auto-reclosing may start by an external command, and the
auto-reclosing delay starts at the beginning of the falling edge of the
external auto-reclosing signal. As "1PhARTime" or "3PhARTime1" delays,
"SyncDetectTimeOff " will be delayed. In the auto-reclosing delay, the
same period conditions meet "SyncDetectTime", then the coincidence
pulse will occur, and "ARSuccessTime" will start clocking. If a new fault
occurs within the successful auto-reclosing time, the auto-reclosing lock is
combined with a three-phase skip command, otherwise the auto-reclosing
is reset and the next auto-reclosing is ready.
The following diagram is a typical single auto-reclosing sequence diagram,
which is described as follow:
1) The circuit breaker is switched off within a short period of the trip
order;
2) When satisfied with no flow conditions, the auto-reclosing starts;
3) Within auto-reclosing delay time ("1PhARTime1" or "3PhARTime1"), if
the auto-reclosing condition is not satisfied, such as the three phase
360
synchronization, the auto-reclosing sequence will be issued after

auto-reclosing delay;
4) Auto-reclosing pulse will sustain "ARPulse” time;
5) "ARSuccessTime" will time after auto-reclosing command. If there is
no fault in "ARSuccessTime", the auto-reclosing is successful and
"ARSuccess" will do report;
6) "ARChargingTime" will delay until " ARSuccessTime" start timing.
Within "ARChargingTime", auto-reclosing function will be blocked;
7) After "ARChargingTime" is delayed, auto-reclosing function is ready. If
there is fault again, auto-reclosing function will start again and
execute.
Fault
TripCmd
CBTripPostion
InitARBI
3PhARTime1
AR inprogress(AR_IN)
SyncChk or
Chk3PhVoltSucc
ess
ARPulseTime
ARPulseTime
ARCmd
ARSuccessTime
ARChargingTime
Figure 177 Two instantaneous three-phase faults, two shots of auto-reclosing mode.
3.1.3 Multiple auto-reclosing

The first auto-reclosing and the single auto-reclosing are the same in
principle. If it is set to multiple auto-reclosing, the skip jump command will
not be issued after the first auto-reclosing fails. At this time, the
auto-reclosing time is renewed before the auto-reclosing time of the first
auto-reclosing, and the delay time of the auto-reclosing delay is delayed.
The whole process will be set by "ARTimes”" setting. Each auto-reclosing
time delay setting can be set independently. If multiple auto-reclosing fails,
for example, the fault has always existed, a trip command is issued, and
the auto-reclosing failure is considered.
The following diagram is a typical single auto-reclosing sequence diagram,
which is described as follow:
1) The circuit breaker is switched off within a short period of the trip
361
order;
2) When satisfied with no flow conditions, the auto-reclosing starts;
3) Within auto-reclosing delay time ("1PhARTime1" or "3PhARTime1"), if
the auto-reclosing condition is not satisfied, such as the three phase
synchronization, the auto-reclosing sequence will be issued after
auto-reclosing delay;
4) Auto-reclosing pulse will sustain "ARPulse” time;
5) "ARSuccessTime" will time after auto-reclosing command;
6) If the auto-reclosing pulse disappears and the auto-reclosing time
succeeds, the auto-reclosing will start at the second time, and the
process is similar to the first auto-reclosing;
7) The number of subsequent auto-reclosing will continue to be
implemented in the manner described above;
8) If all auto-reclosing fails, that is, after the last auto-reclosing, the fault
still exists, the three-phase trip and auto-reclosing blocking command
is issued, the report "ARFail" is displayed, and the auto-reclosing
function is locked in the auto-reclosing reset time;
9) If a reclosing is successful, which means that there is no fault in
"ARSuccessTime", "ARSuccess" will report;
10) "ARChargingTime" will delay until " ARSuccessTime" start timing.
Within "ARChargingTime", auto-reclosing function will be blocked;
11) After "ARChargingTime" is delayed, auto-reclosing function is ready. If
there is fault again, auto-reclosing function will start again and
execute.
Fault
TripCmd
CBTripPostion
InitARBI
3PhARTime1
AR inprogress(AR_IN)
SyncChk or
Chk3PhVoltSuc
cess
ARPulse ARPulse
CloseCBCmd Time Time
ARSuccessTime
ARChargingTime
Figure 178 Permanent three-phase fault, two times reclosing, permanent trip
362
3.1.4 AR coordination between tie CB and side CB

Taking the side circuit breaker as the first closing side and the tie circuit
breaker as the after closing side as an example:
When the AR function for side breaker is initiated, the protection IED will
issue the signal [WaitToSlave] to block the AR function for tie breaker. If
the AR for side breaker is successful, the signal [WaitToSlave] will dropout,
and the tie breaker will be reclosed immediately. If the AR for side breaker
fails, the AR for side breaker will send the signal “ARFail” and the signal
[WaitToSlave] will be kept during the time of the “ARChargingTime”.
If the AR for tie breaker receives the signal “ARFail” or the signal
[WaitToSlave] continuously for [WaitMasterTime], the AR for tie breaker will
be blocked.
The following figure illustrates the key connection between AR for side CB
(CB 1 in figure) and tie CB (CB 3 in figure) for AR coordination.
363
Busbar A
AR1
AR1 For
For bus
bus CB
CB
1 1
BIBlk syn_Req
2 2
FinalTrip syn_meet
3 3
4 4
PHB_CBOpen syn_time
5 5
6 6
7 7
8 8
9 9
PHA_INIT_AR AR_IN
10 10
11
11 CT1-1
12 12
PH3_INIT_AR ARFail
13
AR_WAIT ARSUCC
13 CB1
14 14
15 15
SinglePhaseARMode AR_Trip CT1-2
16 16
17 17
18 18
19 19
20 20
21 21
ChkLLDB AR_Lockout
22 22
ChkDLDB CBFaulty
23
ARFullCharge
WaitToSlave
AR2
AR2 For
For tie
tie CB
CB
1 1 Feeder 1
BIBlk syn_Req
2 2
FinalTrip syn_meet
3 3
4 4
PHB_CBOpen syn_time
5 5
6 6
7 7
8 8
9 9
PHA_INIT_AR AR_IN
10 10
11 11
12 12 CT3-1
PH3_INIT_AR ARFAil
13 13
AR_WAIT ARSUCC
14
14 CB3
15 15
SinglePhaseARMode AR_Trip
16
16
CT3-2
17 17
18 18
19 19
20 20
21 21
ChkLLDB AR_Lockout
22
ChkDLDB CBFaulty
22 Feeder 2
23
ARFullCharge
WaitToSlave
CT2-1
CB2
CT2-2
Busbar B
Figure 179 Logic connection of AR for tie CB blocked by AR for side CB

The typical tripping-reclosing procedure of single shot reclosing scheme
for coordination between side CB and tie CB of 3/2 breaker arrangement,
is illustrated in following two time sequence diagrams, and are described
as following:
The first diagram shows that:
1) After trip command issued, side CB and tie CB are opened in a short
time.
2) The auto-reclosing for side CB and for tie CB are initiated when the
fault current is cleared.
364
3) At the moment of side CB initiation, the binary output, “AR_Wait to

Slave”, is transmitted to AR for tie CB as the binary input, “AR_Wait”.
As soon as the BI is received, the timer, “WaitMasterTime” of AR for
tie CB is started.
4) The AR for tie CB can wait only and cannot issue the reclosing
command, until the binary input, “AR_Wait” dropout before the timer,
“WaitMasterTime” of AR for tie CB elapses, even if the timer,
“1PhARTime1” (or “3PhARTime1”) of AR for tie CB has elapsed.
5) After the auto-reclosing delay time, “1PhARTime1” (or “3PhARTime1”)
of AR for side CB, elapses, the reclosing command is issued if all
reclosing conditions (e.g. synchro- -check for 3-pole tripping) are
satisfied without any blocking reclosing input. The side CB is reclosed.
6) At the moment that the closing signal for side CB is issued, reclaim
timer “ARSuccessTime” of AR for side CB is started.
7) By the end of the period, “ARSuccessTime”, if there is not fault
happening, auto-reclosing operation of side CB is successful. At the
end of “ARSuccessTime”, the binary output, “AR_Wait to Slave”, of AR
for side CB, is dropped out. It means that, the binary input, “AR_Wait”
of AR for tie CB is dropped out.
8) The AR for tie CB will do synchronization check or voltage check
according the setting, as soon as the BI, “AR_Wait” of AR for tie CB is
dropped out.
9) If the auto-reclosing delay time, “1PhARTime1” (or “3PhARTime1”) of
AR for side CB, has elapsed, the reclosing command is issued at once
if all reclosing conditions (e.g. synchro- -check for 3-pole tripping) are
satisfied without any blocking reclosing input. The tie CB is reclosed.
365
Fault
Trip Command
Side CB Open PosItion
AR for side CB: AR Initiate
AR for side CB:3PhARTime1
AR for side CB: Synchro-check

or voltage check OK
ARPulse
AR for side CB: Closing command
AR for side CB:ARSuccessTime
BO of AR for side CB: Wait to Slave

BI of AR for tie CB: AR Wait
Tie CB Open PosItion
AR for tie CB: 3PhARTime1
AR for tie CB:WaitMasterTime
AR for tie CB: Synchro-check

or voltage check OK
ARPulse
AR for tie CB: Closing command
AR for tie CB:ARSuccessTime
Figure 180 A transient fault, single shot scheme, coordination between AR for tie CB
and AR for side CB
The second diagram shows that:
1) After trip command issued, side CB and tie CB are opened in a short
time.
2) The auto-reclosing for side CB and for tie CB are initiated when the
fault current is cleared.
366
3) At the moment of side CB initiation, the binary output, “AR_Wait to

Slave”, is transmitted to AR for tie CB as the binary input, “AR_Wait”.
As soon as the BI is received, the timer, “WaitMasterTime” of AR for
tie CB is started.
4) The AR for tie CB can wait only and cannot issue the reclosing
command, until the binary input, “AR_Wait” dropout before the timer,
“WaitMasterTime” of AR for tie CB elapses, even if the timer,
“1PhARTime1” (or “3PhARTime1”) of AR for tie CB has elapsed.
5) After the auto-reclosing delay time, “1PhARTime1” (or “3PhARTime1”)
of AR for side CB, elapses, the reclosing command is issued if all
reclosing conditions (e.g. synchro- -check for 3-pole tripping) are
satisfied without any blocking reclosing input. The side CB is reclosed.
6) At the moment that the closing signal for side CB is issued, reclaim
timer “ARSuccessTime” of AR for side CB is started.
7) During the reclaim timer “ARSuccessTime” of AR for side CB, if the
side CB is reclosed on a permanent fault, the protection IED will trip
the CB instantaneously. At same time, the binary output, “AR Failure”
is transmitted to AR for tie CB as the binary input, “AR Block”.
8) The AR for tie CB is blocked. The tie CB will keep open.
367
Fault
Trip Command
Side CB Open PosItion
AR for side CB: AR Initiate
AR for side CB: 3PhARTime1
AR for side CB: Synchro-

check or voltage check OK
ARPulse
AR for side CB: Closing command
AR for side CB:ARSuccessTime
BO of AR for side CB: Wait To Slave

BI of AR for tie CB: AR WAIT
BO of AR for side CB: AR Failure

BI of AR for tie CB: AR Block
AR for side CB: ARChargingTime
Tie CB Open PosItion
AR for tie CB: AR Initiate
AR for tie CB:3PhARTime1
AR for tie CB: WaitMasterTime
AR for tie CB: ARChargingTime
Figure 181 A permanent fault, single shot scheme, coordination between AR for tie CB
and AR for side CB
368
3.1.5 Auto-reclosing mode

The auto-reclosing logic switch and related BI determines the
auto-reclosing mode and the auto-reclosing input and exit.
The associated logic switch are described as follow:
1) “BISwitchARMode”: When the setting is 1, switch auto-reclosing mode
through input “DIcom. SinglePhaseARMode”, “DIcom.
ThreePhaseARMode”, “DIcom. IntegratedPhaseARMode”, “DIcom.
StopARMode”; when the value is 0, the auto-reclosing mode is
switched by the “ARMode” logic switch;
2) "ARMode": This logic switch works when "BISwitchARMode" is 0;
a) When the setting is 1, "1PhARModeOn ": In the single mode, only
when the single phase trip is protected and the external
single-phase auto-reclosing is turned in, the auto-reclosing will
automatically start and coincide with the single phase. If
"3PhTripInitAR" BI is valid, auto-reclosing will be blocked;
b) When the setting is 2, "3PhARModeOn": In the three mode, only
three-phase tripping start auto-reclosing and auto-reclosing
three-phase;
c) When the setting is 3, "1/3PhARModeOn": In the mode of
integrated mode, single phase tripping starts auto-reclosing and
auto-reclosing single phase, three-phase tripping starts
auto-reclosing and auto-reclosing three-phase;
d) When the setting is 4, "StopModeOn": Auto-reclosing function is
off or out of service.
369
&
“BISwitchARMode”=1
DIcom. SinglePhaseARMode
& ≥1
&
“1PhARModeOn”
DIcom. ThreePhaseARMode
&
≥1
&
DIcom. IntegratedPhaseARMode
“3PhARModeOn”
&
DIcom. StopARMode
≥1
&
& “1/3PhARModeOn”
“BISwitchARMode”=0
ARMode=1 &
≥1
ARMode=2 &
& “StopARModeOn”
ARMode=3
&
ARMode=4
&
“AROn”=1
AR.BIBlk
Figure 182 Auto-reclosing mode

3) "3PhFaultInitAR": When the logic switch is set to "1", the single phase
fault and the three-phase fault can start the auto-reclosing. When the
logic switch is set to "0", only the single phase fault can start the
auto-reclosing (in a single mode or in an integrated manner);
4) "PPFaultInitAR" needs to cooperate with "3PhFaultInitAR".
occurs.
If both “PPFaultInitAR” and “3PhFaultInitAR” are set to 1, IED can
occurs.
to 0, IED can initiate auto-reclosing, when phase-to-phase occurs.
to 1, IED cannot initiate auto-reclosing, when phase-to-phase or
5) "ARTrip3Ph/BlkAR": When the logic switch is set to "1", and when the
auto-reclosing fails, the auto-reclosing function generates a
three-phase trip command.In "1PhARModeOn ", after single-phase
tripping in single-phase auto-reclosing time delay, auto-reclosing
function is locked and if "PDProtOn " is "1", the other two circuit
breaker tripping protection device. So the logic switch
"ARTrip3Ph/BlkAR" is mostly used for the pole discrepancy protection
which is not configured.
370
6) “BISwitchSyncChkMode”: When the setting is 1, switch

synchronization check mode through input “DIcom. SyncChkMode”,
“DIcom. ChkDLLB”, “DIcom. ChkLLDB” and “DIcom. ChkDLDB”；
When the setting is 0, switch auto-reclosing mode through logic switch
“SyncChkModeOn”, “ChkDLLBOn”, “ChkLLDBOn” and
“ChkDLDBOn”.
3.1.6 Auto-reclosing startup mode
The auto-reclosing mode of the auto-reclosing device has an internal
auto-reclosing mode and is BI with the external switch.
3.1.7 Protection device coordination
Typical wiring for auto-reclosing between protective devices.

PhATripSignal PhAInitARBI Protective
PhBTripSignal PhBInitARBI devices
IED PhCTripSignal PhCInitARBI with
3PhInitARBI
automatic
3PhTripSignal
reclosing
BlkARBOSignal MC/AutoARBlkBI function
On Off AROffBI
Figure 183 Typical wiring for auto-reclosing between protective devices.
3.1.8 Auto-reclosing logic

The key points related to auto-reclosing are described as follow:
1) When 'BlkAR' is in its rise edge, it extends 'ARChargingTime' after the
falling edge;
2) three-phase auto-reclosing synchronization check starts from the
falling edge of initiating auto-reclosing, the maximum extension is
"3PhARTime" + "SyncDetectTimeOff ". After "3PhARTime",
synchronization requirements will be checked Before
"SyncDetectTimeOff ", if synchronization requirements are met
continuously, "SyncDetectTime" will send reclosing command. After
"SyncDetectTimeOff", if synchronization requirements still do not meet
"SyncDetectTime", "ARFail" will be sent and auto-reclosing is blocked
during "ARChargingTime" The logic sequence diagram is shown as
follow:
371
Fault
TripCmd
CBTripPostion
InitARBI
3PhARTime1
t1 t2 t3 t4 t5 t6
SyncChk or
Chk3PhVoltSucce
ss
SyncDetectTim
e间
SyncDetectTimeOff
ARPulse
Time
CBCloseCmd
ARSuccessTime
ARChargingTime
SyncChkTime > t1, t2, t4, t5, t6;

SyncChkTime ≤ t3
Figure 184 In the case of permanent fault, the first reclosing is successful, and the
second reclosing is failed
3) Reclosing pulse maximum extension is "ARPulse" time. During this
period, synchronization will not be checked. Prior to the end of the
auto-reclosing pulse, the auto-reclosing command terminates if the
protection trips again;
372
Fault
TripCmd
CBTripPostion
InitARBI
3PhARTime1
SyncChk or
Chk3PhVoltSuccess
ARPulse
Time
CBCloseCmd
ARSuccessTime
ARChargingTime
Figure 185 In case of permanent fault, single reclosing is successful.

4) In the device test, in order to prevent auto-reclosing to the no voltage
line (circuit breaker division), it is necessary to latch the circuit breaker
in "ARChargingTime" to start the first auto-reclosing.
3.1.9 Auto-reclosing blocking condition
1) If "AROff" BI is valid, auto-reclosing function exit;
2) Auto-reclosing function is blocked during time delay
"ARChargingTime" since BI "BlkAR" is valid;
3) When the circuit breaker is checked abnormal, auto-reclosing function
is blocked;
373
4) When binary input of "SpringDischargeBI" is valid, for example, the

spring charging fault, indicates that the circuit breaker is unprepared in
case of reclosing occurring before switch is prepared. Therefore,
detect the state of binary input of "SpringDischargeBI" after the
synchronization condition is satisfied and the auto-reclosing delay is
reached. If it is detected that the binary input of "SpringDischargeBI" is
valid and continues to be valid during the "SpringChargingTime", the
auto-reclosing will be blocked.
5) When "3/2BreakerConnectMode" =1, the after closing side circuit
breaker or the first closing side circuit breaker can be selected through
the control word " AfterCloseSide". When it is used as the after closing
side circuit breaker, it needs to wait DIcom.AR_WAIT reclosing can
only be carried out after the input disappears.
3.1.10 Logic diagram
The automatic reclosing mode fault, the device displays the alarm
"ARLSErr".
&
“1PhARModeOn”
“3PhARModeOn”
&
“1PhARModeOn”
“1/3PhARModeOn”
& ≥1
“1PhARModeOn”
“ARLSErr”
“StopModeOn”
&
“3PhARModeOn”
“1/3PhARModeOn”
&
“3PhARModeOn”
“StopModeOn”
&
“1/3PhARModeOn”
“StopModeOn”
Figure 186 The logic diagram of automatic reclosing mode error

Auto-reclosing charging and discharging logic diagram is shown below.
374
&
“1PhARModeOn”
3PhTripPosn
BI or IED3PhTrip
ARSuccess
ARFail
≥1
IEDFaultAlarm
DIcom. AR_BLOCK
IEDTrip3Ph/BlkAR ≥1
AR Direct discharge
BOTest
“StopModeOn”
Dicom. AR_OFF
PhAInitARBI
PhBInitARBI
≥1
PhCInitARBI
&
3PhInitARBI &
ARCharging
TripPosnBI or IEDTrip
TripPosnBI T1
ARFullCharge
&
“AROn”=1
AR.BIBlk
T1 ：“ARChargingTime ”
Figure 187 Auto-reclosing charging and discharging logic diagram
375
TripAInitAR BI FallingEdge &
PhADeadCurr
TripBInitAR BI FallingEdge
&
PhBDeadCurr
≥1
TripCInitAR BI FallingEdge
& &
1PhInitAR
PhCDeadCurr
TripAInitAR BI FallingEdge
&
TripBInitAR BI FallingEdge ≥1
3PhInitAR
3PhDeadCurr
TripBInitAR BI FallingEdge
&
3PhDeadCurr
TripAInitAR BI FallingEdge &
3PhDeadCurr
3TripInitAR BI FallingEdge
&
3PhDeadCurr
Figure 188 Auto-reclosing startup logic diagram1
376
In addition, circuit breaker open position also can start auto-reclosing, and
the diagram is shown as follow.
PhA CB OpenPosn
(TripPosnA BI) &
“1PhSpontaneousTripInitAR”
PhB CB OpenPosn
（TripPosnB BI） &
PhC CB OpenPosn ≥1
（TripPosnC BI） & &
1PhInitAR
PhA CB OpenPosn
（TripPosnA BI）
PhB CB OpenPosn ≥1
&
（TripPosnB BI）
3PhInitAR
PhB CB OpenPosn
（TripPosnB BI）
PhC CB OpenPosn &
（TripPosnC BI）
PhC CB OpenPosn
（TripPosnC BI）
&
PhA CB OpenPosn
（TripPosnA BI）
Figure 189 Auto-reclosing startup logic diagram 2
“1PhCBCloseChk
T1 0
3PhLiveVolt” ≥1 Chk3PhVoltOK
&
Min{Ua, Ub, Uc}>“SyncChkMinVolt”
& T2 T3 0
Chk3PhVoltFail
T1 ：“ SyncDetectTime”
T2 ：“ 3PhARTime”
T3 ：“ SyncDetectTimeOff”
Figure 190 Check three phase voltage logic diagram
377
Chk3PhVoltOK
“1PhARModeOn” ≥1 &
≥1
& T1
“1&3PhARModeOn”
1PhTripInitAR
&
“3PhARModeOn” ARTrip
≥1
“1&3PhARModeOn”
T2 T3 0
&
3PhTripInitAR
Override
≥1
ChkDeadVoltMet
SyncChkMet
Dicom. AR_BLOCK
IEDTrip3Ph&BlkAR T5
≥1
IEDFaultAlarm
Dicom. AR_OFF
&
“StopModeOn”
ARSuccess
PhATripPosn
≥1
PhBTripPosn
&
PhCTripPosn
3PhTripPosn ≥1
T4 ARFail
Dicom. CB_FAULTY
“3PhARModeOn”
≥1
Enforced3PhTrip
IED 3PhTrip (AR_Lockout)
DevicePowerFail
T1 ：“ 1PhARTime”
T2 ：“3PhARTime”
T3 ：“SyncDetectTimeOff”
T4 ：“SpringChargingTime”
T5 ：“ARSuccessTime”
Figure 191 Auto-reclosing logic diagram

Type Description
configuration
DIcom.AR_OFF Enable or disable auto-reclosing
DIcom.AR_BLOCK Block auto-reclosing binary input
DIcom.CB_FAULTY Spring discharge binary input
Input DIcom.PHA_INIT_AR Initiating auto-reclosing binary input of phase A

DIcom.PHB_INIT_AR Initiating auto-reclosing binary input of phase B
DIcom.PHC_INIT_AR Initiating auto-reclosing binary input of phase C
Three-phase Initiating auto-reclosing binary
DIcom.PH3_INIT_AR
input
378

Type Description
configuration
Reclosing waiting for BI

DIcom.AR_WAIT Used under “3/2BreakerConnectMode”=1 and
“AfterCloseSide”=1”
DIcom.V1P_MCB Sampled voltage abnormal BI

Single-phase auto-reclosing mode enable
DIcom.SinglePhaseARMode
binary input
Three-phase auto-reclosing mode enable
DIcom.ThreePhaseARMode
binary input
Integrated phase auto reclosing mode enable
DIcom.IntegratedPhaseARMode
binary input
Stopping auto-reclosing mode enable binary
DIcom.StopARMode
input
DIcom.SyncChkMode Synchronization check mode
DIcom.ChkDLLB Check dead line live busbar
DIcom.ChkLLDB Check live line dead busbar
DIcom.ChkDLDB Check dead zone of both sides

AR.BIBlk BI blocking
When the signal of starting auto-reclosing
protection that is configured in IO Matrix is sent
ARFinalTRIP. FinalTrip
to this pin, and the corresponding section is
protected by blocking auto-reclosing.
AutoReclosure.syn_Req Auto-reclosing synchronization request
AutoReclosure.syn_meet Auto-reclosing synchronization is met
AutoReclosure.LowU_meet Undervoltage conditions are met
AutoReclosure. syn_time Synchronization timeout
AutoReclosure.Ph3TripInitAR Three-phase trip initiates auto-reclosing
Three-phase spontaneous trip initiates
AutoReclosure.Ph3CBOTripInitAR
auto-reclosing
AutoReclosure.Ph1TripInitAR Single phase trip initiates auto-reclosing
Output Single phase spontaneous trip initiates
AutoReclosure.Ph1CBOTripInitAR
auto-reclosing
AutoReclosure.AR_IN Auto-reclosing is in process
AutoReclosure.Ph3TripBlkAR Three-phase trip blocking auto-reclosing
AutoReclosure.Ph1TripBlkAR Single phase trip blocks auto-reclosing
AutoReclosure.ARFail Auto-reclosing unsuccessfully
AutoReclosure.ARSucc Auto-reclosing is successful
Auto-reclosing trip three-phase and blocking
AutoReclosure.AR_FinalTrip
auto-reclosing
AutoReclosure.AR_Trip Auto-reclosing trip
AutoReclosure.AR_Block Auto-reclosing blocking
AutoReclosure.FirstARTrip Primary auto-reclosing trip
379

Type Description
configuration
AutoReclosure.SecondARTrip Second auto-reclosing trip
AutoReclosure.ThirdARTrip Third auto-reclosing trip
AutoReclosure.FourthARTrip Fourth auto-reclosing trip
AutoReclosure. AR_Lockout Enforced three phases trip
AutoReclosure. CBFaulty Circuit breaker unprepared
AutoReclosure.ARFullCharge Auto-reclosing is fully charged
Reclosing waiting for BO

Used under “3/2BreakerConnectMode”=1 and
“AfterCloseSide”=0.
AutoReclosure.WaitToSlave
As the first closing side circuit breaker, it is to
drive the output waiting for the after closing
3.3 Setting list

Table 198 Auto-reclosing setting
Default
value
1. 1PhARTime1 0.0～600 600.00 0.01 s
2. 1PhARTime2 0.0～600 600.00 0.01 s
3. 1PhARTime3 0.0～600 600.00 0.01 s
4. 1PhARTime4 0.0～600 600.00 0.01 s
5. 3PhARTime1 0.0～600 600.00 0.01 s
6. 3PhARTime2 0.0～600 600.00 0.01 s
7. 3PhARTime3 0.0～600 600.00 0.01 s
8. 3PhARTime4 0.0～600 600.00 0.01 s
9. ARPulse 0.08～0.5 0.5 0.01 s
10. ARSuccessTime 0.1～100 100.00 0.01 s
11. SpringChargingTime 0.10～100 10.00 0.01 s
12. ARTimes 1～4 1 1
13. ARChargingTime 0.05～100 100.00 0.01 s
14. SyncDetectTime 0.02～100 100 0.01 s
15. SyncDetectTimeOff 0.05～100 100 0.01 s

When "3/2
16. WaitMasterTime 0.01~60 20 0.01 s
BreakerConnectMo
380
Default
value
de" = 1, it works
Time setting of the
locking and the
intermediate circuit
breaker reclosing
Table 199 Auto-reclosing logic switch
Default
value
1. AROn 1/0 0
1: Switch auto-reclosing mode
through input “DIcom.
SinglePhaseARMode”,
“DIcom.
ThreePhaseARMode”,
2. BISwitchARMode 1/0 0
“DIcom.
IntegratedPhaseARMode”,
“DIcom. StopARMode”
0: Switch auto-reclosing mode
through "ARMode" logic switch
This logic switch works when
"BISwitchARMode" is 0.
1: Single phase
auto-reclosing on
2: Three-phase auto reclosing
3. ARMode 1～4 4
on
3: Integrated phase auto
reclosing on
4: Enable stopping
auto-reclosing mode
4. ARTrip3Ph/BlkAR 1/0 0
5. 1PhSpontaneousTripInitAR 1/0 0
6. 3PhSpontaneousTripInitAR 1/0 0
7. 1PhARChk3PhLiveVolt 1/0 0
8. OverrideModeOn 1/0 0
1: Switch synchronization
check mode through input
“DIcom. SyncChkMode”,
“DIcom. ChkDLLB”, “DIcom.
ChkLLDB”, “DIcom.
9. BISwitchSyncChkMode 1/0 0 ChkDLDB”
0: Switch synchronization
check mode through logic
switch “SyncChkModeOn”,
“ChkDLLBOn”, “ChkLLDBOn”,
“ChkDLDBOn”
10. SyncChkModeOn 1/0 0
381
Default
value
11. ChkDLLBOn 1/0 0
12. ChkLLDBOn 1/0 0
13. ChkDLDBOn 1/0 0

1-3/2 wiring type;
14. 3/2BreakerConnectMode 1/0 0 0-single busar or double
busbar wiring type
When "3/2
BreakerConnectMode" = 1, it
works:
1-intermediate circuit breaker
15. MidBrkMode 1/0 0 mode;
0-side circuit breaker.
It is used in versions with dual
reclosing.
When "3/2
BreakerConnectMode" = 1, it
works:
16. AfterCloseSide 1/0 0 1- the after closing circuit
breaker mode;
0- the first closing circuit
breaker.
3.4 Report list

Trip report:
1. ChkARFail /
2. 3PhTripInitAR /
3. 3PhSpontaneousTripInitAR /
4. 1PhTripInitAR /
5. 1PhSpontaneousTripInitAR /
6. ARProcessing /
7. 3PhTripBlkAR /
8. 1PhTripBlkAR /
9. ARFail /
10. ARSuccess /
11. ARChkVoltDiffFail /
12. ARChkFreqDiffFail /
382
13. ARChkAngleDiffFail /
14. ARDeadVoltChkFail /
15. ARTrip3Ph/BlkAR /
16. ARSyncRequest /
17. ARSyncMet /
18. UVCondMet /
19. ARTrip /
20. BlkAR /
21. ARWaiting /
22. SyncTimeout /
23. AROverrideMode /
24. 1stARTrip /
25. 2ndARTrip /
26. 3rdARTrip /
27. 4thARTrip /
Alarm report:
1. ARLSErr /
383

Table 201 Auto-reclosingTechnical parameters
Items Reference value Error range (V)

≤4
Auto-reclosing times
From 1 to 4 can be set
Internal protection trip
initiates reclosing
Auto-reclosing startup function
External BI initiates
reclosing
Every wheel of auto-reclosing
0.05s~600.00s
time
Auto-reclosing success time 0.10s~100.00s
Auto-reclosing charging time 0.05s~100.00s ≤±1% times of setting or

+50ms
Bisection time (Equal open
0.10s~100.00s
position time)
Disable synchronization check
0.05s~100.00s
time
384
Chapter 32 Secondary circuit monitoring
Chapter 32 Secondary circuit

monitoring
About this chapter

This chapter describes VT, CT failure secondary circuit
monitoring function.
385
1 Current transformer secondary circuit

supervision
1.1 Introduction
Current transformer failure or short circuit can cause earth fault protection
and negative sequence current protection maloperation.
If there is abnormality in secondary circuit when there is no protection, it
will produce a very high voltage to cause damage to the secondary circuit.
In order to prevent the device from maloperation, the device monitors the
sudden change of the current of the secondary circuit of the current
transformer and alarms.

CT secondary circuit check function input and output signal diagram is
shown as follow:
CT-Secondary Current Supervision
1 1
BLK_CT_Fail CT_Fail
2
CT_Fail_Block
Figure 192 CT secondary circuit abnormality check function input and output signal
diagram
right.
Input:
Blocking_BI
BLK_CT_Fail 1: VT failure binary input blocking
Output:
Tripcom CT_Fail CT secondary circuit error

CT secondary circuit error, used in configuration
CT_Fail_Block
logic
1.3 Detailed description

1.3.1 Protection principle
When the measured zero sequence current is greater than "CTFail3I0Set",
it sends off the report "CTSecCircuitErr" and the earth fault protection is
blocking through the delay of "CTFailTime". LED, IED output and others
can be configured by AESP after the alarm report is issued.
386
Blocking_BI.BLK_CT_Fail
3I0 > 3I0set
& Tset
Ia <0.06In CTSecCircuitErr/CTFail
≥1
Ib <0.06In
Ic <0.06In
3U0 <1.5V
≥1
VTFail
3I0set：“CTFail3I0Set”
In：“IEDCTSecVal”
Figure 193 CT secondary circuit abnormal supervision logic diagram
1.3.2 Setting list

Table 203 CT secondary circuit abnormality check setting
Default
value
1. CTFail3I0Set 0.05In~2.0In 1 0.01 A
2. CTFailTime 0.1～15 12 0.01 s
Table 204 CT secondary circuit abnormality check logic switch
Default
value
Enabled and disabled CT failure
1. CTFailDetectOn 1/0 1
alarm function
1.3.3 Report list

Alarm report:
1. CTSecCircuitErr
2 VT failure
2.1 Introduction
When the secondary circuit of the voltage transformer is broken or short
circuit, the measured voltage is zero by the protections based on the
undervoltage criterion and this can cause the maloperation of IED. VT
failure check provides voltage monitoring for such protections. VT
monitoring is used to monitor the voltage transformer circuit, and it is
necessary to enable the VT failure function when there is the voltage
transformer circuit. VT failure monitoring includes single-phase VT failure,
two-phase VT failure and three-phase VT failure. Main characteristics are
as follow:
1) Symmetric / asymmetric VT failure;
387
2) Three-phase AC voltage miniature transformer failure monitoring.

It is used in grounding system, non-direct grounding system and
ungrounded system.

VT failure check function input and output signal diagram is shown as
follow:
VT failure supervision
1 1
BLK_PT_Fail VT_Fail
2 2
V3P_MCB VT_Fail_DeadLine
3 3
V1P_MCB VT_Fail_Delay
Figure 194 VT failure detection function input and output signal diagram
right.
Input:
Blocking_BI
BLK_PT_Fail 1: VT failure binary input blocking
Input:
DIcom V3P_MCB Three-phase VT failure BI
V1P_MCB Sampled voltage VT failure binary input
Output:
VT_Fail VT failure instantaneous blocking signs
VT failure instantaneous blocking signs,

Tripcom VT_Fail_Block
used in configuration logic
VT_Fail_DeadLine Line non-run VT failure alarm
VT_Fail_Delay VT failure delay alarm

2.3.1 Protection principle
VT failure function can be enabled or disable by setting the logic switch
"VTFailOn", when the logic switch "VTFailOn" is set as 1, VT failure
protection is enabled, it can be used to detect single-phase, two-phase
and three-phase VT failure.
There are three main criteria for detecting VT failure, which are the
detection of the three phase failure, the detection of the asymmetric failure
of the grounding system, and the detection of the asymmetry of the
non-direct grounding system. The prerequisite is that the protection device
388
starting component does not start and the zero sequence current and
negative sequence current are less than "VTFail3I0/I2"
2.3.1.1 Three-phase (symmetric) VT failure
In the logical detection of three-phase VT failure, the detection conditions
can be chosen by logic switch: "3PhVTFailCurr/PosnConfirm" and
"3PhVTFailCurrConfirm".
1) When both of the two logic switches are disabled: when the secondary
side three-phase VT failure occurs, if the stating component does not
start, then the maximum of compounded zero sequence voltage 3U0
and three-phase phase-to-earth voltage are both less than
"VTFailPEVolt" and then detect it as three-phase VT failure;
2) When "3PhVTFailCurr/PosnConfirm" is disabled and
"3PhVTFailCurrConfirm" is on: when the maximum current value of
the three phases is greater than "VTFailCurrSet " and the maximum of
compounded zero sequence voltage 3U0 and three-phase
phase-to-earth voltage are both less than "VTFailPEVolt" and then
judge it as three-phase VT failure;
3) When "3PhVTFailCurr/PosnConfirm" is enabled:
a) When VT is on the busbar, the minimum of compounded zero
sequence voltage 3U0 and three-phase phase-to-earth voltage
are both less than "VTFailPEVolt" and then judge it as
three-phase VT failure;
b) When VT is on the line, the maximum of three-phase current is
greater than "VTFailCurrSet" or the circuit breaker is on the close
position, and the maximum of compounded zero sequence
voltage 3U0 and three-phase phase-to-earth voltage are both less
than "VTFailPEVolt" and then judge it as three-phase VT failure.
2.3.1.2 Single-phase/ two-phase (asymmetric) VT failure
1) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is directly grounded and the stating component
does not start, then the maximum of compounded zero sequence
voltage 3U0 is greater than "VTFailPEVolt".
2) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is not directly grounded and the stating
component does not start, then then compounded zero sequence
voltage 3U0 is greater than "VTFailPEVolt" and the difference
between the maximum and minimum of phase-to-phase voltage is
greater than "VTFailPPVolt".
2.3.1.3 Others
In addition, when the device detect V3P_BI, three-phase phase-to-earth
voltage are all greater than "VTFailRstVolt", then it is detected as binary
input signal abnormal, send "V3p_MCB BIAlarm" through delay
"VTFailBIErrTime"; otherwise, send "V3p_MCBAlarm" through delay
"VTFailAlarmTime".
When the device detect sampled voltageV1P_BI, and the sampled voltage
is greater than "VTFailRstVolt", then it is detected as binary input signal
abnormal, send "V1p_MCB BIAlarm" through delay "VTFailBIErrTime";
389
otherwise, send "V1p_MCBAlarm" through delay "VTFailAlarmTime".

Note: "V1p_MCB BIAlarm" is detected when the auto-reclosing is enabled
and not in the non-operation state, and when any of the following logic
switches is enabled: "SyncChkModeOn", "ChkDLLBOn", "ChkLLDBOn",
and “ChkDLDBOn".
After VT failure alarm through time delay "VTFailAlarmTime", VT failure
delay alarm node output. When voltage recover, this node latch
"VTFailRstTime" delay return.
2.3.1.4 Line non-run VT failure
When the conditions of single-phase/ two-phase (asymmetric) VT failure or
three-phase(symmetric) VT failure voltage is met, and three-phase current
is less than phase current threshold, then line is considered not running,
after the time "VTFailAlarmTime", alarm "LineNonRunVTFail" is issued.
Note: this alarm is not controlled by logic switch
"3PhVTFailCurr/PosnConfirm" and "3PhVTFailCurrConfirm".
2.3.1.5 Logic diagram
If the secondary circuit failure of VT is detected, the protection based on
the standard of direction or undervoltage will be blocked and it will send off
the report "VTFailAlarm" through the delay of "VTFailAlarmTime". When
one of the following condition met within the delay of
"VTFailAlarmTime"(that is, before sending off the report "VTFailAlarm"),
VT failure blocking opens.
1) While the protection does not start, the minimum phase-to-earth
voltage is greater than "VTFailRstVolt" with 500ms delay;
2) While the protection does not start, the minimum phase-to-earth
voltage is greater than "VTFailRstVolt" and the zero sequence current
and negative current are greater than "VTFail3I0/I2".
While the protection does not start after the "VTFailAlarm" is sent off, the
minimum phase-to-phase voltage is greater than "VTFailRstVolt", VT
failure blocking opens through 1.5s delay, "VTReturnToNormal" report is
sent through "VTFailRstTime" delay.
After VT blocking and VT failure alarm are issued, LED, IED output and
others can be configured by AESP.
Diagram of VT failure logic
390
“3PhVTFailCurr/PosnConfirm” &
≥1
TripPosnA/B/C=0 &
≥1
max(Ia,Ib,Ic) > I_VT Fail
“3PhVTFailCurrConfirm” ≥1
&
“3PhVTFailCurr/PosnConfirm”
&
“3PhVTFailCurrConfirm”
&
min(Ua,Ub,Uc) < Upe_VT Fail
3U0 < Upe_VT Fail
3U0 > Upe_VT Fail &

≥1
“EarthSystem”
&
&
&
max(Uab,Ubc,Uca) - min(Uab,Ubc,Uca) > Upp_VT Fail

≥1
IEDStartup
min(3I0,3I2) > 3I02_VT Fail
DIcom.V3P_MCB
VTFailBI Blk
& VTFailBlk
“EarthSystem”
& output:VT_Fail
T_VTDX
& VTFailAlarm(output:VT_Fail_Delay)
“VTFailOn”
Upe_VT Fail：“VTFailPEVolt”
Upp_VT Fail：“VTFailPPVolt”
I_VT Fail：“VTFailCurrSet”
3I02_VT Fail：“VTFail3I0/I2”
T_VTDX：“VTFailAlarmTime”
Figure 195 VT failure blocking and VT failure alarm logic diagram
&
IEDStartup
&
1. 5S
min(Ua,Ub,Uc) > Upe_VT Normal
& ≥1
VTFailAlarm 500ms
VTFailBlkRst
&
&
min(3I0,3I2) > 3I02_VT Fail T1

VTReturnToNormal
Upe_VT Normal：“VTFailRstVolt”
3I02_VT Fail：“VTFail3I0/I2”
T1：”VTFailRstTime”
Figure 196 VT failure blocking reset and VT failure reset logic diagram
391
min(Ua,Ub,Uc) < Upe_VT Fail

&
3U0 < Upe_VT Fail

≥1
&
“EarthSystem”
& &
3U0 >Upe_VT Fail
max(Uab,Ubc,Uca) - min(Uab,Ubc,Uca) > Upp_VT Fail &

T_VTDX LineNonRunVTFail
IEDStartup (VT_Fail_DeadLine)
max(Ia,Ib,Ic) <
DeadCurrThreshold
“VTFailOn”
Upe_VT Fail：“VTFailPEVolt”
Upp_VT Fail：“VTFailPPVolt”
T_VTDX：“VTFailAlarmTime”
Figure 197 Line not-run VT failure logic diagram
2.3.2 Setting list

Table 207 VT failure setting
Default
Range
(In:5A/1A)
(In:5A/1A)
1. VTFailCurrSet 0.05In~1.0In 0.25 0.01 A
2. VTFail3I0/I2 0.05In~1.0In 0.25 0.01 A
3. VTFailPEVolt 7～20 8 0.01 V
4. VTFailPPVolt 10～30 16 0.01 V
5. VTFailRstVolt 40～65 40 0.01 V
6. VTFailAlarmTime 1.0～10.0 10 0.01 s
7. VTFailRstTime 1.5～10.0 10 0.01 s
8. VTFailBIErrTime 0.04～10.0 10 0.01 s
Table 208 VT failure detection logic switch

Default
value
1. VTFailOn 1/0 1 0: Disable, 1:Enable
2. 3PhVTFailCurr/PosnConfirm 1/0 0 0: Disable, 1:Enable
3. 3PhVTFailCurrConfirm 1/0 0 0: Disable, 1:Enable

0: non-direct grounding
4. EarthSystem 1/0 1 system;
1: grounding system
1-voltage connection line VT
5. VoltFromLineVT 1/0 0 0-voltage connection busbar
VT
392
2.3.3 Report list

Alarm report:
1. LineNonRunVTFail /
2. VTFailAlarm /
3. V3p_MCBAlarm /
4. V3p_MCB BIAlarm /
5. V1p_MCBAlarm
6. V1p_MCB BIAlarm
7. VTFailDistOff /
Operation report:
1. VTReturnToNormal /
2. VTFailFcnOn /
3. VTDXFcnOff /
2.3.4 Technical parameter

Table 210 VT failure technical parameters
Current setting of VT failure 0.05In to 1.0In ≤ ±3% setting or ±0.02In
Zero and negative sequence 0.05In to 1.0In ≤ ±5% setting or ±0.02In

current of VT failure
VT failure phase-to-earth 7.0V to 20.0V ≤ ±3% setting or ±1V
voltage
VT failure phase-to-phase 10.0V to 30.0V ≤ ±3% setting or ±1V
voltage
Reset voltage of VT failure 40.0V to 65.0V ≤ ±3% setting or ±1V
393
Chapter 33 User-defined function
About this chapter

This chapter describes BI, BO, LED configuration and user
defined logic function.
395
1 Introduction
The BI, BO, report, LED of device can be enacted secondary user defined
by engineer according to demand. According to the actual situation of the
project, the user can define the logic. This chapter mainly describes the
function of the AESPStudio tool software which may be used in
engineering application to perform the user defined function and the
matters needing attention.
2 User-defined configuration
2.1 Open project
Click the file→open, in the open file dialog box, open the file named
aespro.
2.2 Binary input configuration

The title of BI can be modified by engineering example. The property of
each binary input can be set in binary input configuration according to
demand.
Table 211 Binary input configuration introduction
Binary input configuration
Configuration item Description

Binary input time Excitation changes from 0 to 1, close position of binary input 1 is
delay 1 confirmed after binary input time 1
Binary input time Excitation changes from 0 to 1, open position of binary input 1 is
delay 2 confirmed after binary input time 2
Set of disturbance
Configure "DFR", "RisingEdgeTrigger" and "FallingEdgeTrigger"
and fault record
Configuration "SirenBit", "BellBit", "PulseQuantity", "SendSOE",
Property 1
"DualPosnBI", "ACInput" and "BCUProtocol"
Configure "NonSmartModule", "24V", "48V", "110V", "125V", "220V",
Property 2
"250V".
Property 3 Configure "OrdinaryBI", "MaintState", "Rmt/Local", "Invalid"
Bay control unit
and protection Configure "Prot", "BCU"
property
Note: when disturbance and fault record setting , if "DFR" is configured,

then the BI will be in the waveform recording. If "RisingEdgeTrigger" is
configured, when the BI changes from 0 into 1, the disturbance and fault
record will be generated. If "FallingEdgeTrigger" is configured, when the BI
changes from 1 into 0, the disturbance and fault record will be generated.
The generated disturbance and fault record file will be saved into the list of
startup disturbance and fault records.
Special attention: in order to ensure the trip speed of main protection pilot
distance protection function and directional pilot earth fault protection
396
functions, the binary input time 1 and 2 configured in the receiving binary
input in the next table should both be 0ms.
Table 212 The binary input list of configuration time 0ms
No. Configurable binary input Type Remark
Carrier receives message:

1. BI_Carr_Recv_Dist BOOL pilot distance receiving
message
Phase A receiving message

of pilot distance (if the
2. BI_Carr_Recv_DistA BOOL "ParallelLinePhSendMsg" is
enabled, the binary input
exists)
Phase B receiving message

3. BI_Carr_Recv_DistB BOOL "ParallelLinePhSendMsg" is
exists)
Phase C receiving message

4. BI_Carr_Recv_DistC BOOL "ParallelLinePhSendMsg" is
exists)
Carrier receives message:

5. BI_Carr_Recv_DEF BOOL pilot earth fault receiving
message
Phase A receiving message

of pilot earth fault (if the
6. BI_Carr_Recv_DEFA BOOL "ParallelLinePhSendMsg" is
exists)
Phase B receiving message

7. BI_Carr_Recv_DEFB BOOL "ParallelLinePhSendMsg" is
exists)
Phase C receiving message

8. BI_Carr_Recv_DEFC BOOL "ParallelLinePhSendMsg" is
exists)
The work voltage can only be configured within ranges defined by this
module unit. Hardware module contains high power voltage level and low
power voltage level, respectively marked with the work voltage of DC
"110V", "125V", "220V", "250V" and "24V", "48V".
The explanation of time sequence of "BITime1" and "BITime2" is shown as
follow.
397
Excitation
BITime1
BI
BITime2
Figure 198 Binary input time delay sequence

Configuration way of double position binary input:
Two single-position binary inputs can be used to describe the
double-position binary input, and the close position of single input
accesses to the n hardware binary input, and then the open position of
single input accesses to the n+1 hardware binary input. "DualPosnBI" can
be selected for the property 1 of binary input n; but it cannot be selected for
the property 1 of binary input n+1; and "Invalid" can be selected for the
property 3.
The logic state of a pair of binary inputs (binary input n and n+1)
configured with double-position will no longer be that of the hardware
binary input. The logic binary input n indicates the closing state, which is 1
only when (hardware binary input n and hardware binary input n+1)=(1,0);
logic binary input n+1 is the quality of double-position binary input, only
when (hardware binary input n, hardware binary input n+1) = (0, 0) or (1, 1)
is 1, which means invalid state.
The double-position hardware binary input state and logic binary input
state (including the binary input state in configuration and binary IO) are
shown as follow:
Table 213 State list for hardware binary input of double position and logic binary input
Binary input of hardware (binary
0,0 0,1 1,0 1,1
input n, binary input n+1)
Logic binary input (binary input n,
0,1 0,0 1,0 0,1
binary input n+1)
2.3 Binary output configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand.
Table 214 Binary output configuration introduction
Binary output configuration
Configuration item Description
Latched time Excitation resets and binary output also resets after latched time.
Set of disturbance and
Configure "DFR", "RisingEdgeTrigger" and "FallingEdgeTrigger"
fault record
Configure "ElectricLatched", "TripRedundancy",
Binary output property
"ReclaimRedundancy", "BlkedByStartup", "NCContact"
398
To configure "ElectricLatched" property, the electric relay will return only

after the signals reset. The movement sequence is shown as follow. When
the device is deenergized and then reenergized, the electric relay can
recover the state before power down.
Excitation
Reset
Relay
Figure 199 Electric latched relay trip sequence

Configuration is the node of electric retention, which can't
"BlkedByStartup" ; otherwise startup relay will return and so does BI.
Non "ElectricLatched" binary output can configure "LatchedTime",
excitation will return, after the set time, the relay returns.
Excitation
Relay
Figure 200 Non-electric latched relay trip sequence

Please configure in line with the hardware jumper of BO, and determine
whether BO is "BlkedByStartup" or not, and whether "NCContact" or not.
Refer to the chapter of device hardware, the instruction of binary input and
output module and binary input jumper.
Special attention: (1) Do not perform “TripRedundancy” setting for line
protection; (2) Fixed configuration of line binary output is
“ReclaimRedundancy”.
As shown in Figure 201 , one of configuration properties of BO
"BlkedByStartup" must be linked with the contact of hardware, and every
three BOs shall form a group to be configured similarly. Which means BO1,
BO2 and BO3 shall form a group; BO4, BO5 and BO6 form a group and so
on.
399
Figure 201 Diagram of binary output configuration
2.4 LED configuration

The title of LED can be modified by engineering example. On control plate,
the calibrated LED indicator light tag can be embedded into the
corresponding position of the indicator light . The property of each LED
can be set in LED configuration according to demand.
Table 215 LED configuration specification
Light configuration.
Configuration
Description
item
Latched Configure "Latched" and "Unlatched", and when the configuration is
property "Latched", reset operation should be performed to clear the LED state.
LED color The colors of LED are "yellow", "green" and "red"
The LED is flashing or constant on, n represents the flash frequency is
Flashing
n*50ms; when it is 0 or 1, the LED is always on
As the configuration is "Redundancy" property, multiple CPU will trigger light
Redundancy
at the same time and the LED will be lit.
As CPU and other redundant CPU all send out lighting commands, the
LED configured with "Redundancy" can be lit. If LED does not have
redundancy property, "Redundancy" property cannot be set.
2.5 IO Matrix configuration

The IO Matrix achieves a fast correlation between virtual and real points in
the software. Virtual point comes from the application software,
corresponding to the functional software to modify the data points, the real
point from the limited resources provided by the device.
400
2.5.1 AC IO configuration
AC IO configuration is used to specify the source of the required input
information for the application, the AC or DC excitation of the device is
configured as AC module sampling or SV data.
“X” means the valid selection.
Figure 202 AC IO configuration diagram
2.5.2 Binary IO configuration

The digital IO configuration is used to specify the protection trip of the
device. External binary input signal that each function of the device
depends on and external manifestations of trip including the binary output
and the lights, etc., are achieved through the configuration.
“H” refers to the valid high power level, “L” represents the valid low power
level.
Figure 203 Binary IO configuration diagram
2.6 Binary input switches setting group

2.6.1 Function description
IED can switch the setting group in two ways. When the setting
"BISwitchSetGrp" is set as 0, IED will response to the faceplate or SCADA
to switch the setting group; when the setting "BISwitchSetGrp" is set as 1,
401
IED will not response to the faceplate or SCADA to switch the setting
group, it will switch the setting group automatically according to the status
of binary input.
The device provides four default configurable binary inputs to switch
setting group, in BIToSetGrp, BI1, BI2, BI3, and BI4 can be set by users in
the engineering research and development version
Table 216 The specific relation between the BI and the set group
No. BISetGrp4/2/1 Setting group
1. 0000 1
2. 0001 2
3. 0010 3
4. 0011 4
5. 0100 5
6. 0101 6
7. 0110 7
8. 0111 8
9. 1000 9
10. 1001 10
11. 1010 11
12. 1011 12
13. 1100 13
14. 1101 14
15. 1110 15
16. 1111 16
If the various BI groups designate target setting group randomly, and the
user-defined logic of engineering research and development is realized,
then write the target setting group to Fault_POU::ChangeSetGrp.
InSettingZone. IED provides up to 32 setting groups.
Figure 204 Diagram of binary input switch setting group configuration
402
2.6.2 Setting list

Table 217 Logic switch of binary input switching setting group diagram
No. Setting Remark
description value
1. BISwitchSetGrp 1/0 0
2.7 Other configurations

The name of the device can be changed according to the requirements of
the project, and it can be named in accordance with the project schedule,
so as to facilitate the maintenance of the project.
The default length of waveform recording file generated by IED is 2.5
cycles before fault and 20 cycles before and after the fault together. It
supports to instantiate RS_WAVEPARAM by AESP tool and the users can
define the length of disturbance and fault records according to their needs.
The length of single disturbance and fault record cannot be greater than
200ms before fault, the total length of disturbance and fault records cannot
be greater than 20s. Single disturbance and fault record cannot be greater
than 512k.
Figure 205 Setting configuration figure
2.8 Defined logic

The AESPStudio tool provides the basic elements of the module to support
user-defined simple engineering logic. The intermediate data and the
intermediate nodes in the application software which is open to the user
can be used conveniently in the configuration interface, and the logical
application of the project is realized.
403
Chapter 34 Control function
About this chapter

This chapter describes the control functions, including the
isolator telecontrol and direct control functions. The control
function is not configured in the default software function, and
the required control functions can be added according to the
requirements of the project site.
405
1 Isolator telecontrol of circuit breaker

1.1 Introduction
The isolator telecontrol is used to control the opening and closing
operation of the circuit breaker or the isolator, and the telecontrol object
can be added according to the isolator required to be controlled at this
interval.

Input and output signals of isolator telecontrol function are shown as
follow:
CB/Isolator Control
1 1
OpenPermit OpenBO
2 2
ClosePermit CloseBO
3
BIState
Figure 206 The diagram of input and output signals of isolator telecontrol function
right.
Input:
OpenPermit Allowable opening circuit breaker
ClosePermit Allowable closing circuit breaker
CB/ISO Control BIState Binary input state of double position
Output:
OpenBO Open circuit breaker trip
CloseBO Close circuit breaker trip

Telecontrol pre-selection operation is required before executing the
isolator telecontrol command.
The telecontrol of the isolator is blocked by the remote/local state. When
the device is in the remote state, it is only remotely controllable; when the
device is in the local state, it is only locally controllable.
The opening circuit breaker permission and closing circuit breaker
permission can be connected to the interlock signal or the permission logic
of user-defined opening/closing circuit breaker.
The isolator telecontrol module can select whether to input the reverse
check. When using the reverse check function, the input state of dual
position needs to be connected to the circuit breaker position. If the
reverse check is not selected, it can achieve urgent open and close
function.
When using position check, if the input position state match with control
406
command send, IED will return success, if not return fail after 30s.
2 Direct control
2.1 Introduction
Direct control can be used for directly controlled objects, such as
intermediate relay reset or any free output command without
pre-sellection.

Input and output signals of direct control function are shown as follow:
Direct Control
1
OpenBO
2
CloseBO
Figure 207 The diagram of input and output signals of direct control function
right.
Output:
Direct Control OpenBO Open circuit breaker trip
CloseBO Close circuit breaker trip

The direct control does not require a telecontrol pre-selection operation,
and is directly exported after the telecontrol object operation.
The direct control is blocked by the remote/local state. When the device is
in the remote state, it is only remotely controllable; when the device is in
the local state, it is only locally controllable.
3 Report list
Operation report:
1. TelectrlObject /
2. TelectrlCmdSrc /
3. TelectrlResult /
4. TelectrlCmd /
5. TelectrlType /
6. FailReason /
407
Chapter 35 Substation communication
Chapter 35 Substation Communication
About this chapter

This chapter describes functions such as substation
communication and protocol, time synchronization and so on.
409
1 Introduction
Each IED provides communication port to communicate with one or more
substation system. IED supports following communication protocols:
1) Communication protocol IEC 61850-8-1;
2) 60870-5-103 communication protocol;
3) DNP 3.0;
4) MODBUS.
1.1 Communication protocol

1.1.1 IEC61850-8 communication protocol
Protocol IEC61850-8 allows two or more IED in one or more factories to
communicate and cooperate on the basis of their functions.
Standard IEC 61850-8-1 rules GOOSE (generic object of substation event).
By publishing and subscribing mechanism, GOOSE standardizes
communication state and control information between IEDs. That is to say,
if fault is detected to happen, IED shall send information to devices which
have subscribed the event by multi cast.
1.1.2 IEC60870-5-103 communication protocol
Protocol IEC 60870-5-103 belongs to master-slave mode and
communicates to control system through serial port. According to IEC rules,
main station is the master and substation is the slave. Communication is
carried out on the basis of point-to-point principle. Main station should be
equipped with the software that is able to receive IEC 60870-5-103
communication report. For a more comprehensive understanding of the
IEC60870-5-103 protocol, please refer to the fifth part of " IEC60870
standard": 103 section of "communication protocol": "Companion standard
for the informative interface of protection IED"
1.2 Communication port

1.2.1 Faceplate communication port
Faceplates of all IEDs have a RJ45 communication port respectively. By
this port, users can use PC to operate Sifang debug software to connect
IED for setting, testing, configuring and so on.
1.2.2 RS485 communication port
IED provides two electric RS485 communication ports connecting to
automatic system for substation. The port supports protocol
IEC60870-5-103, and RS485-1 port can be used for time synchronization.
1.2.3 Ethernet communication port
IED provides three Ethernet ports to connect to substation automatic
system.
410

Table 221 Faceplate communication port
Items Data
Number 1
Connection mode RJ45 port for debugging software
Communication rate 100Mbit/s
Table 222 RS485 communication port
Items Data
Number 2
By two conductors
Connection mode
Communication port of backplate
Maximum communication distance 1.0km
Test voltage 500V AC earthing
Supporting protocol IEC 60870-5-103

Parameter is set as 9600 baud,
Communication rate Minimum 1200 baud rate, maximum 19200
baud rate
Table 223 Ethernet communication port
Items Data
Ethernet communication port
Number 3
Cable or optical fibers/backplate
Connection mode
communication port
Maximum communication distance 100m
Support protocol of IEC 61850
Supporting protocol TCP103
Table 224 Time synchronization port
Items Data
Time synchronization mode Pulse or optical signal time synchronization
IRIG-B signal format IRIG-B000

Connected by two conductors or optical fibers
Connection mode
Communication port of backplate
Voltage level Differential signal
411
1.4 Typical substation communication mode

Through communication protocols supported by communication port, IED
is able to communicate with one or more substation system or device.
Server or Server or
Work Station 1 Work Station 2
Switch
Work Station 3
Net 1: IEC61850/IEC103,Ethernet Port A
Switch Net 2: IEC61850/IEC103,Ethernet Port B Switch

Switch
Gateway Switch
or
converter
Net 3: IEC103, RS485 Port A
Figure 208 Multiple network substation automatic system connection case
1.5 Typical time synchronization mode

All IEDs provide a time synchronization port (as shown below), it is able to
choose IRIG-IRIG-B or pulse time synchronization. For pulse time
synchronization, IED can automatically adapt to second pulse time
synchronization mode. Meanwhile IED could adopt SNTP mode to
synchronize.
SNTP IRIG-B Pulse
Ethernet port IRIG-B port Binary input
Figure 209 Time synchronization mode
412
Chapter 36 Remote communication
About this chapter

This chapter describes the remote communication function of
the protection device.
413
1 Binary Signal Transmission

The binary signal can be converted between two protection devices on the
overhead line or at both ends of the cable through remote communication
channel. This function is mainly used for the pilot protection of the line.
Contents of data sending are shown in the following table:
Table 225 Send data
Data Description
Ia
Ib Three-phase current
Ic
Time Used for time synchronization
Enable differential protection The logic switch of “DiffOn”
IED startup
Phase A/B/C trip position
Remote transmission signal 1~8 Remote transmission signal 1~remote transmission signal 8
Remote trip signal

Pilot earth fault permissive
Optical fiber mode pilot earth fault protection
message (Different from C/B/A)
Pilot distance permissive
Optical fiber mode directional pilot distance protection
message (Different from C/B/A)
CRC
Please refer to the Chapter 4 differential protection for functional

description of optical fiber channel.
2 Remote Communication Channel

Protection device can connect with the remote protection device by using
multiplexing device. The interface between protection and multiplexing
devices can connect with balanced/imbalanced electric signal defined by
ITU-T G.703 of non-frame format; and the optical signal connection of
frame format optical signal defined by IEEE C37.94 is also supported.
2.1 Non-frame format

In this mode, multiplexing device should be set as protection device and
the communication can be realized if any the following conditions is met:
1) Direct optical fiber communication within 100km;
2) Use the dedicated multiplexing device CSC186 and use the 64kbit/s
interface defined by the fourth part of the ITU-T G.703; or use the
2048kbit/s interface defined by the ninth part of the ITU-T G.703.
The protection device can configure the dual optical fiber communication
interface, to realize the double channel switch without delay, which is
suitable for direct and circuitous channels coexisting mode, where after the
interruption of one channel will not affect the normal operation of another
channel. It may also use only one channel.
414
Overhead Lines or Cable Lines
Single Mode FO
Length: <60kM or
60~100kM
Channel A
Device Device
Figure 210 Single-channel, optical fiber directly connected communication
Single Mode FO
Length: <60kM or
60~100kM
Channel A
Channel B
Device Device
Figure 211 Double-channel optical fiber directly connected communication

The protection device is connected with the digital communication network
through the communication interface device (CSC186). Communication
interface device is connected with the protection device by the 1310nm
optical fiber and FC connector, which can provide the electrical interface
and digital communication network connection satisfying G703-64 kbit/s or
G703-E1 2Mbit/s according to the needs.
G703.5(E1: 2048kbit/s)
G703.1(64kbit/s)
o Digital e
Communication
e Network o
The Communication The Communication
Device Interface Device Interface Device Device
Figure 212 Single channel (communicate by digital communication network)
415
G703.5(E1: 2048kbit/s)
G703.1(64kbit/s)
Channel A
Digital
o Communication e
e Network o
o e
Digital Communication
e 数字通信网络
Network o
Device Communication Communication Device
Interface Device Interface Device
Channel B
Figure 213 Dual channel (communicate via digital communication network)

Overhead Lines or Cable
Lines
Single Mode FO
Length: <60kM or
60~100kM
Channel A
o e
Digital
Communication
e Network o
Device Device
Channel B
G703.5(E1: 2048kbit/s)
G703.1(64kbit/s)
Figure 214 Double channel (one channel communicates by the digital communication
network, another channel is the directly connected by optical fiber)
2.2 Frame format

IEEE C37.94(N*64kbit/s) Multimode FO
Channel A
Channel B
Device Device
Figure 215 Connecting schematic diagram of double-channel optical fiber directly

connected communication C37.95
IEEE C37.94(N*64kbit/s)
Channel A
Digital
o Communication e
Network o
e
o Digital Communication e
e Network o
Communication Communication
Device Interface Device
Device
Interface Device Channel B
Figure 216 Dual channel (communicate via digital communication network)
416
Protection device supports “IEEE Std C37.94™-2002”, namely, the optical

fiber interface definition of remote protection device and multiplexing
device, and can directly connect with C37.94 interface of multiplex device
(e.g. SDH).
Protection device supports C37.94 interface and has the characteristic as
follow:
1) Confirm to C37.94 frame format definition;
2) For the "P", "Q", "R” and "s" defined in the "OverHead" section of the
frame format, it is fixed to use "1100", i.e. "N=12” refers to use the full
bandwidth of "PayLoad";
3) The definition of the optical signal conforms to the IEEE Std C37.94,
i.e., the light represents the logical bit '1', the logical bit '0’ represents
the light power output is less than 10% of the logic bit '1'.
3 Technical parameter
3.1 Non-frame format
Table 226 Communication interface parameter of protection device
Items Data
Interface number 1～2
Optical fiber type Single mode

Wave length and transmission 1310nm, transmission distance <60km
distance 1550nm, 60km< transmission distance <120km
Fiber acceptance sensitivity -34dBm
>-11dBm; (transmission distance <40km)
>-4dBm; (transmission distance 40～60km)
Sending optical power >-5dBm; (transmission distance 60～80km)
Fiber connector type LC
Maximum transmission distance 120km
Table 227 CSC-186 communication interface parameter
Items Data
Optical fiber Interface number 1, it is used to connect with IED
Optical fiber type Single mode, 1310nm
Fiber acceptance sensitivity -34dBm
Sending optical power >-11dBm
Fiber connector type FC
Electric Interface number 1, it is used to connect with multiplexing device
Interface standard ITU-T G.703
417
Items Data
Interface type: Balance, 120ohm
Imbalance, 75ohm
Rate 64kbit/s
2048kbit/s
Note: Optical fiber channel interface is for optical fiber pilot protection
function, that is, CSC-103 and CSC-101 with optical fiber pilot protection.
3.2 C37.94 interface specification

Table 228 C37.94 interface specification
Items Data
Quantity 1～2
Rate Channel bandwidth N=12 is supported;
Optical fiber type Single-mode Multi-mode

Wave length and transmission 1310nm, transmission distance 850nm, transmission
distance <40km distance <2km
Fiber acceptance sensitivity -34dBm -25dBm
>-11dBm (transmission distance
Sending optical power >-17dBm
<40km)
Fiber connector type LC LC
Maximum transmission
40km 2km
distance
Note: Optical fiber channel interface is for optical fiber pilot protection
function, that is, CSC-103 and CSC-101 with optical fiber pilot protection.
418
Chapter 37 Man-machine interface (MMI) and operation
Chapter 37 Man-machine interface

(MMI) and operation
About this chapter

This chapter describes the relative display of man-machine
interface and its operation.
419
1 Introduction
The MMI is composed of liquid crystal display (LCD), LED, faceplate
buttons and faceplate Ethernet port. Users can view information, set
parameters and debug through MMI.
2 Function description
2.1 Liquid crystal display (LCD)
The LCD back light of HMI is blue, 9 lines can be displayed. When
operating Sifang key or IED issuing alarm or trip report, background blue
light automatically lights up. Soon after the latest trip or alarm, background
blue light dies out after 5 minutes of time setting.
2.2 Man-machine interface (MMI)

MMI is man-machine interface. LCD screen displays the device running
information, such as measured value for current and voltage, connector
state and BI, BO and bay signal line diagram.
If there is no key operation, the MMI main cycle interface shows part of
device information in a cycle way. Users can press “ ” button to lock the
present display and press “ ” again to return to the cycle display state.
Take 19/2 inches enclosure of multi-function protection IED as an example,
the description of faceplate area is as follow: zone one is for the
user-defined indicator light area; zone two is for the key area of the control
function; zone three is for the debugging of net port; zone four is for the
key district of the basic key.
CSC-100
Figure 217 MMI module schematic diagram

The customized indicator light area consists of 24 lights, where the
position of running lights and alarm light are fixed, and the functions of
420
other 22 lamps can carry out the configuration of light color, light property
according to the needs of the user; in key areas, there is indicator light
indicating device state on each of the remote, local and blocking key
respectively.
RUN: When running lights, the green light is lightened during the normal
operation, while the running light is off if there is class 1 alarm.
ALARM: alarm indicator light, the device alarm lightens the red light.
The faceplate uses the Ethernet port to connect PC and device, which
supports setting device parameter, measuring function, downloading
programs and analyzing data. The debugging IP address of Ethernet port
is 196.178.111.1 which is unchangeable.
The key includes basic key and control functional key. Basic keys are on
the right of the screen and control functional keys are below the screen to
realize human-computer interaction. Keys for IED of CSC series contain
the same appearance and operation mode, for details in the table as
follow.
Table 229 IED MMI key
Key Function
 Move up in the menu
 Page up between screens
 Add setting
 Move down in the menu

 Page down
 Decreasing setting
Move left in the menu
Move right in the menu
 Reset LED light

 Directly back to normal circulation display interface
 Entering main menu or sub-menu

 Confirm that you want to change the settings.
 Back to up one level

 Exiting and revising setting
 Back to circulation display interface
 Locking or unlocking circulation display interface (when
locking, top right corner of LCD displays an icon of a small
key)
 Value adds 1
+ 

Page down
Logic switch shift from the present value to the opposite
421
Key Function
value; namely "1" to "0", or "0" to "1"
 Value minus 1
- 

Page up
Logic switch shift from the present value to the opposite
value; namely "1" to "0", or "0" to "1"
F1 F2  User-defined function key

 The shortcuts for menu options are able to set to relate with
menu items to execute functions of this menu.
F3 F4  as the input signal to participate in logic
 Switching to remote operation mode, and earthing control

shall be blocked.
 Switching to earthing control mode, remote operation shall
be blocked.
 It is used for locking and unlocking control key and
user-defined key so as to prevent mistakenly touching.
 Breaker closes
 Breaker opens
2.3 Menu structure

Through the MMI key, you can enter the IED menu, view information or
perform related operations. Due to the differences in the function of
various type of IED, the following lists show the maximum menu
configuration; the value of related setting information and various type of
IED is on the basis of actual display.
Table 230 Device menu
L1 menu L2 menu L3 menu L4 menu Description
Read the measure
PriVal input primary-value of
the IED
Calc
Read the measure
SecVal input second-value of
the IED
Read the measure
PriVal input primary-value of
the IED
Measure
Read the measure
SecVal input second-value of
the IED
ViewInfo IEDState
Read the analog input
Analog
of the IED
Read the power
PowerMetr
metering of the IED
Conventional Read the binary input
BI of the IED
Read the original binary
BIO GOOriginBI
input state of GOOSE
Conventional Read the binary
BO output of the IED
GOOSESubStat Read state information
GOState
e of GOOSE subscription
422

GOOSEPubStat Read state information
e of GOOSE publishing
Read state
StateMon
information of the IED
Read the optical fiber
ChanInfo
channel information
PresentErrCo
ChanInfo de
AllErrCode
LostFrame
Read the current
AlarmInfo
alarm information
ProtSet1
Read the IED setting
…
Read the calculation
CalcSet
ViewSet setting
Read the equipment
EquipParm
parameters
Read the parameter
BCUParm
of bay control unit
FunctionCo Read the function
n connector information
Read connector state
GOOSEPubSo
information of GOOSE
ConState ftCon
publishing
Read connector state
GOOSESubSo
information of GOOSE
ftCon
subscription
Read the unique code
IED IDCode
of IED
Read the version
VerInfo IEDVer
information of IED
VrtlTrmlChk Read the check code
Code of virtual terminal
Read the
SyncMode synchronization mode
of IED
IEDSet Read the Ethernet
EthernetSet
CommParm information of IED
IEDAddr Read IED address
Set function
FunctionCon
connector state
GOOSEPubSo Set state information of
ConOn/Off
ftCon GOOSE publishing
GOOSESubSo Set state information of
ftCon GOOSE subscription
Switch present
Operate SwitchSetGr
operation setting
p
group
Local control telecontrol
LocalCtrl object
Bay single line
Bay0
SLDCtrl diagram control
…
ViewRpt GenlRpt Read general report
423

Read the startup
StartupRpt
report
TripRpt Read the trip report
AlarmRpt Read the alarm report
OperationR Read the operation
pt report
BIChangeR Read the BI change
pt report
Startup disturbance
StartupDFR
and fault record
List
shown in list
Trip disturbance and
TripDFRList fault record shown in
list
ProtSet ProtSet Setting the ProtSet
Copy setting of
GrpCopy
setting group
Set substation name.
It uses Unicode
SubstationN
encoding, with a
ame
maximum input of 24
characters.
WriteSet Set the protected
EquipParm equipment name. It
ProtEquipN uses Unicode
ame encoding, with a
maximum input of 24
characters.
Set equipment
EquipParm
parameters
Set parameter of bay
BCUParm
control unit
ConventionalB
Test the BO contacts
BOTest O
GOOSE BO Test GOOSE signal
FnAlarmChk
TripRepChk
GOAlarmCh
k
BIChk
Test communication
CommChk MSTAlarmC signal
hk
ConChk
TestMenu AnalogChk
MeasureCh
k
LEDTest TestLED light
Manual triggering to
ManualRcd generate fault and
disturbance record
ViewZeroDri
ft
FactoryTest ViewScale
AdjZeroDrift
AdjScale
424

AngleCorrec
tion
ProtSet
SoftCon
Calc
SampVal
IEDState BIO
ConState
Print VerInfo Print various information
StartupRpt
TripRpt
Rpt AlarmRpt
OperationRpt
BIChangeRpt
IEDSet
SetClock Set time
Choose
SyncMode
synchronization mode
NetTimeSyncI
Set SNTP address
PSet
Set the local time
TimeSet TimeZone
zone
Set daylight-saving
Mode1 time in sequence of
year, month, day
DST
Set daylight-saving
Mode2 time in sequence of
month, week, hour
Set the Ethernet
EthernetSet
information of IED
IEDAddr Set IED address
Serial1Set
Set serial port
IEDSet SerialSet Serial2Set
parameters
Serial3Set
CommParm Set the protocol
ProtocolSet
information
PRPSet
Set IED name. It uses
Unicode encoding,
IEDName
with a maximum input
of 24 characters.
Password Set IED password
Contrast Set the contrast
Set report parameters
and the mode that
OtherSet DisplayMod
sending
e
primary-secondary
value to SCADA
PowerMetrZ Set the power
eroing metering as 0
CHN Confirm
Language Switch language
ENG Confirm
425

RUS Confirm
Click the key in the recycle main interface, the menu tree will be
shown in the MMI interface; click the key or to select menu items,
when the cursor stays in the corresponding menu item, if there is a symbol
"" behind this menu item, it can click the key or to enter the next
menu; if there is no signal "", it can click the key to enter the menu
items.
SIFANG 2017-10-01 21:30:1D
IEDState  Calc  ConventionalBI

GOOriginBI
ViewSet  Measure 
ConventionalBO
ConState  Analog
VerInfo  PowerMetr
GOOSEState
BIO 
ViewInfo  IEDSet 
StateMon
Operate  ChanInfo
ViewRpt  AlarmInfo
WriteSet 
TestMenu
IEDSet 
Language 
PresentSetGrpNo.:
Figure 218 Menu tree diagram of conventional binary output

The following diagram is an example of "ConventionalBO" menu.
BO 1/2
IEDFaultAlarm 0
RunErrAlarm 0
X9_BO3 0
X9_BO4 0
X8_BO1 0
X8_BO2 0
X8_BO3 0
X8_BO4 0
X8_BO5 0
Figure 219 Menu diagram of conventional binary output
426
Chapter 38 IED hardware
About this chapter

This chapter describes hardware for device.
427
1 Introduction
1.1 IED structure
1.1.1 4U, 19 inch device
2
Height for IED crate is 4U and width is 19 2 inches. The whole is for
embedded installation with back-wiring mode.
Figure 220 Installation size diagram (unit mm)

1) Faceplate for IED is casted by aluminum alloy and able to downward
turn. LCD, LED and setting keys are mounted on the plate. There is a
RJ45 interface on the faceplate suitable for connecting a PC;
2) Plug in or plug out the module on the backplate, module is fixed by
screw spike;
3) Module is connected through bus of backplate.
1.1.2 4U, 19 inches device
Height for IED crate is 4U and width is 19 inches. The whole is for
embedded installation with back-wiring mode.
428
482.6 465.1±0.2
465.1 +0.3
450 0
4-?
6.5
+0.3
101.6
101.6
178 0
177
447.1
426.7
263
281.4
236.5
Figure 221 Installation size diagram (unit mm)
1) Faceplate for IED is casted by aluminum alloy and able to downward
turn. LCD, LED and setting keys are mounted on the plate. There is a
RJ45 interface on the faceplate suitable for connecting a PC;
2) Plug in or plug out the module on the backplate, module is fixed by
screw spike;
3) Module is connected through bus of backplate.
1.2 Module arrangement diagram

1.2.1 4U, 19 inch device
2
Figure 222 IED backplate module layout diagram
429
1.2.2 4U, 19 inches device
Figure 223 IED backplate module layout diagram
2 Analog input module

2.1 Introduction
AC module contains voltage and current transformers. The module
converts two-side current and voltage to processable signal for IED data
acquisition system and serves as electrical isolation. IED in different type
shall be with different current and voltage transformers. The module is
optional according to different project requirements.
2.2 Analog input module introduction

The following figure shows the AC module terminal diagram of a certain
type of configuration, the module supports the access of five channels of
protective current and four channels of voltage.
The 5 channels of protection current channels Ia, Ib, Ic, I0, I4 support 1A or
rated 5A current access, and each current channel provides 3 wiring
terminals. The terminal identification without ' suffix is shared inlet positive
terminal, while that with' suffix is the outlet negative terminal. For example,
the use of rated 1A shift of Ia should access the amount of current from the
Ia terminal to the Ia_1’ terminal, with Ia_5 ' terminal suspended; the use of
rated 5A shift should access the amount of current from the Ia terminal to
Ia_5' terminal with the Ia_1' terminal suspended; the wiring principle of
other protection type of current channels is same.
I4 in the following figure is access current of adjacent current, the terminal
identification without ' suffix is shared inlet positive terminal, while that with'
suffix is the outlet negative terminal, the magnitude of current should
always be accessed from I4 terminal, and extracted from I4' terminal.
U4, Ua, Ub, Uc in the following figure are voltage channels, and the
terminal identification without ' suffix is shared inlet positive terminal, while
that with' suffix is the outlet negative terminal.
430
Figure 224 AC module terminal diagram

Note: In view of the fault characteristics of double circuit lines on the same
pole, the zero sequence current of another line needs to be introduced by
the ultra range permitted work. When the 1A CT is connected to the I4 and
I4_1’ and the 5A CT, the I4 and I4_5’ are connected.
type of configuration, the module supports the access of three channels of
measurement current.
Figure 225 Measurement AC module terminal diagram

type of configuration In 3/2 connection mode and double CT Mode, the
module supports the access of 9 channels of protective current and 4
431
channels of voltage.
The 9 channels of protection current channels IA1, IB1, IC1, I01, IA2, IB2,
IC2, I02, I4 support 1A or rated 5A current access, and each current
channel provides 3 wiring terminals. The terminal identification without '
suffix is shared inlet positive terminal, while that with ' suffix is the outlet
negative terminal. For example, the use of rated 1A shift of IA1 should
access the amount of current from the IA1 terminal to the IA1_1’ terminal,
with IA1_5 ' terminal suspended; the use of rated 5A shift should access
the amount of current from the IA1 terminal to IA1_5' terminal with the
IA1_1' terminal suspended; the wiring principle of other protection type of
current channels is same.
I4 in the following figure is access current of adjacent current, the terminal
identification without ' suffix is shared inlet positive terminal, while that with
' suffix is the outlet negative terminal, the magnitude of current should
always be accessed from I4 terminal, and extracted from I4' terminal.
UX, Ua, Ub, Uc in the following figure are voltage channels, and the
terminal identification without ' suffix is shared inlet positive terminal, while
that with ' suffix is the outlet negative terminal.
AC1 AC2
b a b a
1 IA1_1' IA1 1 I01_1' I01
2 IB1_5' IA1_5' 2 I02_5' I01_5'
3 IB1_1' IB1 3 I02_1' I02
4 IC1_1' IC1 4 I4_1' I4
5 IA2_5' IC1_5' 5 I4_5'
6 IA2_1' IA2 6 UX' UX
7 IB2_1' IB2 7
8 IC2_5' IB2_5' 8
9 IC2_1' IC2 9
10 Ua' Ua 10
11 Ub' Ub 11
12 Uc' Uc 12
Figure 226 AC module terminal diagram in 3/2 connection mode and double CT Mode
432

Table 231 Current transformer parameter
Implementation
Items Data
standards
Rated current IEC 60255-1 1A or 5A
IED CT is 0.05In to 40In
Sampling range for conventional
Measurement CT is 0.05In to
current transformer
1.2In
Sampling range for high sensitive
0.005 to 1.2A
current transformer
≤0.2VA when In=1A,
≤0.5VA when In=5A,
<0.2VA at In,<40m Ω (0~40In)
Power consumption (each phase)
In=1A;
<0.5VA at In,<10m Ω (0-40In)
In=5A.
Thermal overload capacity of IEC 60255-1 100In, overload 1s
conventional current transformer IEC 60255-27 4In, continuously
Table 232 Voltage transformer parameter
Implementation
Items Data
standards
Rated voltage Vr (phase-to-phase
IEC 60255-1 100V/110V
voltage)
Sampling range (phase-to-earth
0.4V~180V
voltage)
IEC 60255-27
Power consumption (Vr = 110V) ≤ 0.15VA, each phase
DL/T 478-2013
Thermal overload capacity (phase IEC 60255-27 400V, overload 60s
voltage) DL/T 478-2013 200V, continuous
3 BI modules
3.1 Introduction
The BI hardware part of binary input module including two types of
soldering:
1) Strong power level, self-adapting 110V,125V, 220V and 250;
2) Weak power level, self-adapting 24V and 48V.
Work rated power source of device BI is modified by configuration file
before applying.
3.2 BI Module description

There are three indicator lights on the BI faceplate to show the status of
the board, the indicator light definition is shown in the following table.
Table 233 Definition of BI module indicator light
The serial number of
Indicator light function Introduction of indicator light state
indicator light
1 Power supply light Light is on when device is energized
433
2 Running light Flash when work properly

3 Spare Off
Due to the different location of the slot, the BI module can be set at
different address of module, and the address is set through the jumper J6.
Take the side away from single board as L side, the side near single board
as H side, from bottom to top are AD0, AD1, AD2 and AD3.
Table 234 BI module address definition
Slot location Jumper Control content Jumper settings
AD3~AD1 are short connected to the L side,
BI2 J6 BI address 2
AD0 is short connected to the H side
28 binary inputs are divided into 4 groups, common terminal of all groups
are independent from each other.
BI
1 2 3 LED
c a
2 BI14 BI1
4 BI15 BI2
6 BI16 BI3
8 BI17 BI4
10 BI18 BI5
BINARY INPUT
12 BI19 BI6
14 BI20 BI7
16 BI21 BI8
18 BI22 BI9
20 BI23 BI10
22 BI24 BI11
24 BI25 BI12
26 BI26 BI13
28 COM2 COM1
30 BI28 BI27
32 COM4 COM3
Figure 227 BI module terminal diagram

Table 235 BI parameter
Implementation
Items Data
standards
110V/125V/220V/250V DC
Rated voltage IEC 60255-1
24V/48V DC
Startup voltage IEC 60255-1 70%Ur, rated DC 24V/48V, 110V/125V/220V/250V;
Return voltage IEC 60255-1 55%Ur, rated DC 24V/48V, 110V/125V/220V/250V;
286V, rated DC voltage 110V/125V/220V/250V;
The maximum BI voltage IEC 60255-1
62V, rated DC voltage 24V/48V;
Maximum 0.5W/input, 110V DC
Power consumption IEC 60255-1
Maximum 1W/input, 220V DC
434
4 BO modules
4.1 Introduction
Module provides certain of protection tripping and closing circuit breaker
control and realizes telecontrol opening or closing of isolator. Some
channels could be switched to normally open or closed contact.
4.2 BO module description

There are three indicator lights on the BO faceplate to show the status of
the board, the indicator light definition is shown in the following table.
Table 236 Definition of BO module indicator light
indicator light
Light is on when device is
1 Power supply light
energized
3 Spare Off
Due to the different location of the slot, the BO module can be set at
Table 237 BO module address definition
J7 BO2 address AD3~AD1 are short connected to the L side,
BO2
BO3 BO3 address AD3, AD2, AD0 are short connected to the L
J7
side, AD1 is short connected to the H side
BO4 BO4 address AD3 and AD2 are connected to the L side,
J7
AD1 and AD0 are connected to the H side
BO5 BO5 address AD3, AD2, AD0 are short connected to the L
J7
BO6 BO6 address AD3 and AD2 are connected to the L side,
J7
AD2 and AD0 are connected to the H side
AD3 and AD0 are short connected to the L
BO7 J7 BO7 address side, AD2 and AD1 are short connected to
the H side
BO8 BO8 address AD3 is short connected to the L side,
J7
AD2~AD0 are short connected to the H side
Each binary input and output board has 16 binary outputs. 16 binary
outputs are divided into 5 groups, each group can be set as startup
blocking or not startup blocking by changing the jumper position, there are
total four groups of jumpers J1~J5. The jumper inserting into 1, 2 pin
represents that binary output is blocked by startup relay, inserting into 2, 3
pin represents that binary output is unblocked by startup relay.
435
Table 238 BO Description for jumper of BO module

The definition of address
jumper of binary output Binary output 1 and 2 pin 2 and 3 pin
module
J1 BO1~ BO3 Startup blocking Not startup blocking
BO16 can switch to normally open or normally closed contacts. J30 is

normally open when transferred to A, and normally closed when
transferred to B.
BO
1 2 3 LED
c a
2 BO1
4 BO2
6 BO3
8 BO4
10 BO5
BINARY OUTPUT
12 BO6
14 BO7
16 BO8
18 BO9
20 BO10
22 BO11
24 BO12
26 BO13
28 BO14
30 BO15
32 BO16
Figure 228 BO module terminal diagram

Table 239 BO parameter
436
Items Implementation Data

standards
Maximum work voltage IEC60255-1 250V AC
Impact overcurrent capacity IEC60255-1 5 A continuous,
30A, 200ms ON, 15s OFF
Closing capacity IEC60255-1 1100 W( ) inductive load L/R>40 ms
1000VA (AC)
Arc breaking capacity IEC60255-1 220V , 0.15A,L/R≤40 ms
110V , 0.30A,L/R≤40 ms
Electrical life IEC60255-1 50,000,000 times (switching frequency is

3HZ)
Opening times IEC60255-1 ≥1000 times
Closing times IEC60255-1 ≥1000 times
Authentication IEC60255-1 UL/CSA, TŰV
IEC60255-23
IEC61810-1
Contact circuit resistance IEC60255-1 30mΩ
IEC60255-23
IEC61810-1
Contact insulation test (AC IEC60255-1 AC1000V 1min
dielectric strength ) IEC60255-27
Maximum temperature
IEC60255-1 55℃
operation allows
5 Binary input and output module

5.1 Introduction
Binary input and output module provides certain of protection tripping and
closing control so as to realize tele-control opening and closing of the
circuit breaker and isolator.
The BI hardware part of binary input and output module including two
types of soldering:
1) Strong power level, self-adapting 110V,125V, 220V and 250;
2) Weak power level, self-adapting 24V and 48V.
Work rated power source of device BI is modified by configuration file
before applying.
5.2 Binary input and output module introduction

There are three indicator lights on the binary input and output module, the
indicator light definition is shown in the following.
437
Table 240 Definition of binary input and output module indicator light
The serial
number of Indicator light function Introduction of indicator light state
indicator light
3 Spare Off
According to the different slot locations of the binary input and output
module, different module addresses need to be set, and address is set
through jumper J6. Take the side away from single board as L side, the
side near single board as H side, from bottom to top are AD0, AD1, AD2
and AD3.
Table 241 Definition of binary input and output module address

Binary input and
BIO1 J6 AD3~AD0 are short connected to the L side
output1 address
Binary input and AD3~AD1 are short connected to the L
BIO2 J6
output2 address side, AD0 is short connected to the H side
Binary input and AD3, AD2, AD0 are short connected to the
BIO3 J6
output3 address L side, AD1 is short connected to the H side
Binary input and AD3 and AD2 are connected to the L side,
BIO4 J6
output4 address AD1 and AD0 are connected to the H side
Each binary input and output module has 6 binary inputs and 12 binary
outputs. 6 BIs are divided into 2 groups, and each of 3 BIs shares a
common terminal.
12 binary outputs are divided into 4 groups, each group can be set
as startup blocking or not startup blocking by changing the jumper position,
there are total four groups of jumpers J11~J14. The jumper inserting into 1,
2 pin represents that binary output is blocked by startup relay, inserting into
2, 3 pin represents that binary output is unblocked by startup relay.
Table 242 Jumper introduction 1 of binary input and output module
The definition of
address jumper of
Binary output 1 and 2 pin 2 and 3 pin
binary input and
output module
J11 BO1~BO3 Startup blocking Not startup blocking
BO12 can switch normally open or normally closed contact by JP1 jumper,
when the jumper jumps to NC side, it is normally closed contact, when the
jumper jumps to NO side, it is normally open contact.
438
Table 243 Jumper introduction 2 of binary input and output module
Jumper Binary output NC NO
JP1 BO12 Normally closed contact Normally open contact
BIO
1 2 3
c a
2 BO1
4 BO2
6 BO3
BINARY OUTPUT
8 BO4
10 BO5
12 BO6
14 BO7
16 BO8
18 BO9
20 BO10
22 BO11
24 BO12
26 BI4 BI1
BINARY INPUT
28 BI5 BI2
30 BI6 BI3
32 COM2 COM1
Figure 229 Binary input and output module
439

Table 244 BI parameter
Implementatio
Items Data
n standards
110V/125V/220V/250V DC
Rated voltage IEC 60255-1
24V/48V DC
70%Ur, rated DC 24V/48V,
Startup voltage IEC 60255-1
110V/125V/220V/250V
55%Ur, rated DC 24V/48V,
Return voltage IEC 60255-1
110V/125V/220V/250V
286V,
Rated DC voltage
110V/125V/220V/250V,
62V, rated DC voltage 24V/48V;
Maximum 1W/input, 220V DC
Implementation
Items Data
standards
5A, continuous
Impact overcurrent capacity IEC60255-1
30A, 200ms On, 15s Off
1100 W(DC) inductive load L/R>40 ms
Closing capacity IEC60255-1
1000VA (AC)
220V(DC), 0.15A, L/R≤40 ms
Arc breaking capacity IEC60255-1
110V(AC), 0.30A, L/R≤40 ms
50000000 times (switching frequency is
Electrical life IEC60255-1
3HZ)
Opening times IEC60255-1 ≥1000 times
Closing times IEC60255-1 ≥1000 times

IEC60255-1
IEC61810-1
IEC60255-1
IEC61810-1
Contact insulation test (AC IEC60255-1
AC 1000V 1min
Maximum temperature
IEC60255-1 55℃
operation allows
6 CPU module
6.1 Introduction
CPU module is core of the IED and responsible for running all protection
logic, hardware self-check and device communication for external devices
such as MMI, PC, measurement, substation automatic system, working
station, RTU, printers and so on. Besides, CPU module sends telemetry,
telesignalisation, SOE, event report and recorded wave to backstage, it
440
provides time synchronization and communication port.

CPU module provides multiple configuration for user's need. Differences
lie in quantities for Ethernet port, optical/electric port, time synchronization
mode, storage capacity and so on.
6.2 CPU module introduction

The CPU module faceplate has six indicator light to indicate the operation
state of the board and the definition of indicator light is shown as follow
table.
Table 246 There are six indicator light on CPU board
The serial
number of Indicator light function Introduction of indicator light state
indicator light
Faceplate Ethernet 1 Flash when communicating normally while close
1
indicator light when communicating abnormally
2
3
CPU operation Flash when operating normally while close when
4
indicator 1 operating abnormally
5
6
CPU CPU CPU

1 2 3 1 2 3 1 2 3
4 5 6 4 5 6 4 5 6
TX TX
ETH1 ETH1 ETH1
RX RX
TX
ETH2 ETH2 ETH2
RX
ETH3 ETH3 ETH3
1
RS485-1A/PULSE- 1
RS485-1A/PULSE- 1
RS485-1A/PULSE-
2
RS485-1B/PULSE+ 2
RS485-1B/PULSE+ 2
RS485-1B/PULSE+
RS485-1GND 3 RS485-1GND 3 RS485-1GND 3

4 4 4
RS485-2A 5 RS485-2A 5 RS485-2A 5
RS485-2B 6 RS485-2B 6 RS485-2B 6
RS485-2GND 7 RS485-2GND 7 RS485-2GND 7
8 8 8
RS232-TXD 9 RS232-TXD 9 RS232-TXD 9
RS232-RXD 10 RS232-RXD 10 RS232-RXD 10
RS232-GND 11 RS232-GND 11 RS232-GND 11
Figure 230 CPU module terminal diagram

The standard CPU supports serial port 1 and time synchronization
multiplex hardware ports. The functions are switched by software. When
used as time synchronization port, the protocol of serial port 1 needs to be
set to none.
441
Table 247 Definition of CPU module in serial communication terminal
Terminals Definition Remark
01 RS485-1A/PULSE- Serial1
02 RS485-1B/PULSE+
03 RS 485-1GND
04
05 RS 485-2A Serial2
06 RS 485-2B
07 RS 485-2GND
08
09 RS232-TXD Serial3
10 RS232-RXD
11 RS232-GND
Ethernet port configuration is selectable and shown on the above figure:

Table 248 Net port configuration
Number Configuration
1 RJ45 electrical port+RJ45 electrical port+RJ45 electrical port
2 Optical port+RJ45 electrical port+RJ45 electrical port
3 Optical port+optical port+RJ45 electrical port

Items Data
Quantity 2
Extract twisted pair
Port type
On the CPU module bottom plate
Maximum transmission distance 1.0km
Voltage withstand test 500V earthing AC voltage
Used for IEC 60870-5-103 protocol

Default setting 9600bps
Transmission rate Minimum: 1200 bps
Maximum: 19200bps
Items Data
Quantity 1
Extract twisted pair

Port type
Maximum transmission distance 15m
442
Voltage withstand test 500V earthing AC voltage
Transmission rate Default setting 9600bps

Minimum: 1200 bps
Minimum: 19200 bps
Table 251 Ethernet communication port
Items Data
Ethernet port
Quantity 3
RJ45 or optical Ethernet port
Port type
Maximum transmission distance 100m
Used for protocol IEC 61850
Transmission rate 100Mbit/s
Used for IEC TCP103 protocol
Transmission rate 100Mbit/s
Table 252 Time synchronization
Items Data
Synchronization mode IRIG-B time synchronization
IRIG-B signal format IRIG-B000

Twisted-pair connection or optical fibers On
Port type
the CPU module bottom plate
Voltage level Differential signal input
7 Power supply module

7.1 Introduction
The input of the power supply module is the working voltage of the device,
and the output is the working voltage of the other modules of the device.
The input and output circuits of the power supply module are not common,
which plays the electric isolation role. In order to improve anti-interference
ability for power supply module circuit, the power supply module is
equipped with anti-interference filter inside the device. What's more, the
module is equipped with sophisticated power protection function
(undervoltage, overvoltage, overcurrent, overpower, etc.) to prevent IED
breakdown from power supply module failure. Power supply module
provides 11 channels BI and 4 channels relay BO, and provides reliable
electric isolation.
7.2 Power module introduction

There is a power indicator light on the power supply faceplate to indicate
the state of the module, it is always on when the module work properly.
443
BI10 on the power supply module is fixed defined as "IEDRst", BO1 is

fixed defined as "IEDFaultAlarm", BO2 is fixed defined as "RunErrAlarm".
Other binary inputs and binary outputs can be defined by the user,
according to different functional requirements of the users. Each channel
of binary output has two groups of contacts, respectively corresponding to
binary output common port 1 and binary output common port 2, and binary
output relays are unlatched type.
Note: BO 1 is constant-closed contact, other BOs are normally open
contacts, BO 3 and BO 4 are fixed to trip not by starting relay.
POWER
PWR
c a
2 BI7 BI1
4 BI8 BI2
BINARY INPUT
6 BI9 BI3
8 RELAY RESET BI4
10 BI11 BI5
12 BICOM BI6
14 COM2 COM1
SIGNAL CONTACT
16 FAIL 1 FAIL 2
18 ALARM 1 ALARM 2
20 BO3-1 BO3-2
22 BO4-1 BO4-2
24 IN+
POWER INPUT
26
28 IN-
30
32
Figure 231 Power supply module terminal diagram

Table 253 The definition of power supply module terminals
No. c a
2 Binary input 7 Binary input 1
8 Device reset Binary input 4
12 Common terminal of binary input Binary input 6
444
No. c a
Common terminal of binary output
14 Common terminal of binary output 2
1
16 IED fault alarm 1 IED fault alarm 2
18 Running abnormal alarm 1 Running abnormal alarm 2
20 Binary output 3-1 Binary output 3-2
22 Binary output 4-1 Binary output 4-2
24 Positive pole of power supply Positive pole of power supply
26 Undefined Undefined
28 Negative pole of power supply Negative pole of power supply
30 Undefined Undefined
32 Grounding Grounding

Table 254 Technical parameter
Implementation
Items Data
standards
Rated voltage Uaux IEC60255-1 110V to 250V
Input voltage range IEC60255-1 ±%20Uaux
Steady-state burden IEC60255-1 ≤ 50W for each power module

Maximum load power
IEC60255-1 ≤ 60W for each power module
consumption
8 TCS module
8.1 Introduction
Note that the module soldering is different from the different rated power
supply. Please confirm before use.
The built-in TCS function is applicable to the occasion when the trip
contacts in device are used for trip directly; generally, it is applied to the
occasion when installing protection device with medium voltage level in
switchgear panel. In 80% occasions, only the trip circuit is monitored, the
closing circuit does not get monitored. Therefore, the device provides a
module with TCS circuit and trip relay cooperating with each other.
8.2 Instruction of TCS module

TCS Module provides one tripping monitoring circuit, two high-capacity BI
circuits and two pairs of relays and four outlet contacts.
445
Figure 232 TCS module terminal diagram

There are three indicator lights on the TCS faceplate to show the status of
the module, the indicator light definition is shown in the following.
Table 255 Definition of indicator light of TCS module
indicator light
3 Spare Off
Due to the different location of the slot, the TCS module can be set at
Table 256 Definition of TCS module address
Control
Slot location Jumper Jumper settings
content
TCS1 J6 TCS 1 address AD3~AD0 are short connected to the L side
AD3~AD1 are short connected to the L side,
TCS2 J6 TCS 2 address
AD3, AD2, AD0 are short connected to the L
AD3 and AD2 are connected to the L side, AD1
and AD0 are connected to the H side
TCS high-capacity and general binary output circuits can be set as startup
blocking or not startup blocking by changing the jumper position, there are
total four groups of jumpers J10 and J11, the jumper inserting into 1, 2 pin
446
represents that binary output is blocked by startup relay, inserting into 2, 3

pin represents that binary output is unblocked by startup relay.
Table 257 Jumper instruction of TCS module
The definition of
address jumper Binary output 1 and 2 pin 2 and 3 pin
of TCS module
J10 PO1~PO2 Startup blocking Not startup blocking
8.2.1 TCS trip monitoring circuit

TCS module can monitor the open circuit of breaker the whole time,
including various operating conditions.
Figure 233 TCS circuit schematic diagram

Terminal a2, c4, a4 are connected with tripping circuit via auxiliary contact,
when failure occurs in circuit, K1 and K2 open simultaneously, and send
alarm signal; block can be realized through external circuit connection.
447
Figure 234 TCS circuit wiring diagram
8.2.2 Binary output circuit with high-capacity

Taking the binary output circuit with high-capacity PO1 as an example, the
schematic diagram and wiring instruction are as follows. Open PO1 to
drive trip coil or closing coil.
Figure 235 Binary output circuit with high-capacity schematic diagram

When the binary output current is greater than 6A, then the terminals of
column a and column c need to be connected in parallel.
448
8.2.3 Ordinary BO circuit
Figure 236 Ordinary BO circuit schematic diagram

Table 258 Binary output instruction
Relay BO name Terminals BO type
c26～a26 Normally open

RELAY3A BO1

RELAY4A BO2
c32～a32 Always close

Table 259 Binary output circuit with high-capacity parameters
Implementation
Items Data
standards
8A continuous,
240W (DC)
Closing capacity IEC60255-1
2000VA(AC)
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Electrical life IEC60255-1 100,000 times (resistive load)
Opening times IEC60255-1 ≥1000
Closing times IEC60255-1 ≥1000

IEC60255-1
IEC61810-1
IEC60255-1
IEC61810-1
AC1000V 1min
Maximum temperature operation
IEC60255-1 55℃
allows
449
Table 260 TCS circuit (binary input) parameter

Implementation
Items Data
standards
Rated voltage IEC 60255-1 110V, 220V DC
Startup voltage IEC 60255-1 70%Ur
Return voltage IEC 60255-1 55%Ur

143V, rated DC voltage 110V
286V, rated DC voltage 220V
Implementation
Items Data
standards
Maximum work voltage IEC60255-1 250 AC
8A continuous,
240W(DC) at inductive load
Closing capacity IEC60255-1 L/R>40 ms
2000VA(AC)
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Electrical life IEC60255-1 100,000 times (resistive load)
Opening times IEC60255-1 ≥1000
Closing times IEC60255-1 ≥1000

IEC60255-1
IEC61810-1
IEC60255-1
IEC61810-1
AC1000V 1min
Maximum temperature operation
IEC60255-1 55℃
allows
9 Wire connection terminal

Table 262 Terminal wiring
The module Terminal/wire size
Alternating current module 4 mm2 screw terminal

1.5mm2 crimp terminal
BIO module, BI module and BO module
2.5 mm2 screw terminal
1.5mm2 crimp terminal
Power supply module
2.5 mm2 screw terminal
450
10 Test
Table 263 Insulation test
Implementation
Items Test method
standards
Faceplate: IP54
IEC60255-27
Protection level (IP) Side plate: IP52
IEC60529
Backplate: IP30
2KV, 50Hz (rated
voltage >63V) tested between
the following circuits:
 Power supply
 CT / VT input
IEC 60255-5
 Binary input
EN 60255-5
 Binary output
Insulation withstanding ANSI C37.90
Enclosure grounding (rated
GB/T 15145-2017
voltage ≤63V)
DL/T 478-2013
tested between the following
circuits:
 Communication port
 Time synchronization port
 Case earthing
5kV (rated voltage>60V)(
1kV (rated voltage≤60V)
1.2/50Μs, 0.5J
IEC60255-5 tested between the following
IEC 60255-27 circuits:
EN 60255-5  Power supply
Impulse voltage
ANSI C37.90  CT / VT input
GB/T 15145-2017  Binary input
DL/T 478-2013  Binary output
 Communication port
 Time synchronization port
 Case earthing
IEC60255-5
IEC 60255-27
EN 60255-5
Insulation resistance ≥100MΩ, 500V DC
ANSI C37.90
GB/T 15145-2017
DL/T 478-2013
Earthing resistance IEC60255-27 ≤0.1Ω
Flame rating IEC60255-27 Class V2
Table 264 EMC test

Implementation
Items Test method
standards
IEC60255-22-1
IEC60255-26 Class III
1MHz pulse group
IEC61000-4-18 2.5kV CM
interference test
EN 60255-22-1 1kV DM
ANSI/IEEE C37.90.1
451
Implementation
Items Test method
standards
IEC 60255-22-2 Class IV
Immunity degree of
IEC 61000-4-2 ±8kV electro-contact discharge;
electrostatic discharge
EN 60255-22-2 ±15kV air discharge;
Class IV
Radiated electromagnetic IEC 60255-22-3
10V/m, 80MHz~1GHz,
field immunity EN 60255-22-3
1.4GHz~2.7GHz
IEC 60255-22-4
Immunity degree of Class IV
IEC 61000-4-4
electrical fast transient pulse Communication port: 4KV
EN 60255-22-4
group Other ports: 2KV
ANSI/IEEE C37.90.1
Class IV
IEC 60255-22-5
Surge (impact) immunity 4.0kV CM
IEC 61000-4-5
2.0kV DM
Frequency scanning: 150kHz–80MHz
Calibration frequency: 27MHz and
Radio frequency IEC 60255-22-6
68MHz
interference test IEC 61000-4-6
10V
AM, 80%, 1kHz
Class A
Power frequency immunity
IEC60255-22-7 300V CM
test
150V DM
Class V
Power frequency magnetic
IEC 6 1000-4-8 100A/m greater than 30s
field immunity test
1000 A/m, from 1s to 3s
Class III
100KHz pulse-group noise
IEC61000-4-18 Communication port: 2KV
immunity
Other ports: 4KV
Damped oscillation Class V
IEC61000-4-10
magnetic field immunity 100A/m
Pulse magnetic field Class V
IEC61000-4-9
immunity test 1000A/m
Conducted emission IEC 60255-25 0.15MHz~30MHz, class A
Radiated emission IEC 60255-25 30MHz~1000MHz, class A
Table 265 Mechanical test

Implementation
Items Test method
standards
Sinusoidal vibration IEC60255-21-1 Class 1
response test EN 60255-21-1
Sinusoidal vibration and IEC60255-21-1 Class 1
endurance test EN 60255-21-1
IEC60255-21-2 Class 1
Impact response test
EN 60255-21-2
IEC60255-21-2
Impact and endurance test Class 1
EN 60255-21-2
Class 1
Collision test IEC60255-21-2
Seismic test IEC60255-21-3 Class 1
452
Table 266 Environmental test
Items Data
High and low temperature test -40 °C to +70°C
Temperature storage test -40°C to +70°C

Maximum relative humidity 95%, no
Humidity test
condensation
11 Structural design
Table 267 Structural design
Items Data
19
4U, 2 inch device
Dimension 4U×1/2 19 inches
Weight ≤9kg
4U, 19 inches device
Dimension 4U×19 inch
Weight ≤12kg
12 CE Certificate
Table 268 CE Certificate
Items Data
EN 61000-6-2 and EN61000-6-4 (EMC
EMC
Steering Committee 2004/108/EC)
LVD EN 60255-27 (LVD 2006/95 EC)
453
Chapter 39 Appendix
Chapter 39 Appendix
455
Chapter 39 Appendix
1 Equipment parameter
Table 269 Equipment parameter
Range Default value
No. Name Unit Remark
(In:5A/1A) (In:5A/1A)
1. VTPriVal 30～800 800 kV
2. VTSecVal 100～120 100 V
3. IEDCTPriVal 50～5000 5000 A
4. IEDCTSecVal 1～5 1 A
5. MeasureCTPriVal 50～5000 5000 A
6. MeasureCTSecVal 5 5 A
7. BISwitchSetGrp 1/0 0
1-C37.94
protocol;
0- G.703 protocol
is applied in optical
fiber pilot
8. C37.94Protocol 1/0 0
protection
(CSC-103 and
CSC-101 with
optical fiber pilot
protection)
The settings are all secondary values if there is no special note.
Impedance setting is set according to impedance of line.
The zero sequence current mentioned in this manual is 𝟑𝟑𝟑𝟑𝟎𝟎 .
1) "VTPriVal": It is set in accordance with the primary rated voltage, the
unit is kV.
2) "VTSecVal": It is set from 100V to 120V.
3) "IEDCTPriVal": It is set in accordance with the primary rated current,
the unit is A.
4) "IEDCTSecVal": It is set as 1A or 5A.
5) "MeasureCTPriVal": It is set in accordance with the primary rated
current, the unit is A.
6) "MeasureCTSecVal": It is fixed as 5A.
7) "BISwitchSetGrp": When the setting "BISwitchSetGrp" is set as 0, IED
will response to the faceplate or SCADA to switch the setting group;
when the setting "BISwitchSetGrp" is set as 1, IED will not response to
the faceplate or SCADA to switch the setting group, it will switch the
setting group automatically according to the status of binary input.
8) "C37.94 protocol": For optical fiber pilot protection function, that is,
CSC-103 and CSC-101 with optical fiber pilot protection.When C37.94
communication mode is applied, logic switch is 1.
456
Chapter 39 Appendix
2 Report list
About operation report and protection alarm report please see the report
list in the protection chapter.
2.1 Alarm report

IED contains alarm reports, which is shown as follow:
1) Class 1 alarm belongs to IED fault alarm. When class 1 alarm happens,
the alarm LED on the faceplate of the IED will be on, the Run LED will
be off, all of protection function will be out of service and the trip power
of protection will be blocked;
2) Class 2 alarm belongs to abnormal running alarm. When class 2 alarm
happens, the alarm LED on the front panel of the IED will flash. Class
II alarm won't block protection function.
Table 270 Report list of class 1 alarm
No. Report name Alarm code Description
1. SampleValErr 32769
2. IEDParmErr 32770
3. ROMSumChkErr 32771
4. SetErr 32772 Need to write setting again
5. UnconfirmConnMode 32773
6. SoftConnErr 32774
7. SystemCfgErr 32775
8. IED CPUModuleErr 32778
9. SetGrpPointerErr 32780
Need to download sf and esdc files

10. LogicFileErr 32798
again
11. CfgFileErr 35769
12. CfgFileInconsist 35770
Need to download sf and esdc files

13. IOMatrixErr 35771
again
Jumper setting on the BO module is

inconsistent with the software
14. BOChkNoResponse 33769
configuration, need to set the jumper
again
15. BOBreakdown 33770
457
Chapter 39 Appendix
16. BIBreakdown 33784
17. BIO CPU Err 33789
18. BIO ROMSumErr 33790
BI or BO module is not defined, need to

19. BIO EEPROMErr 32779
define it again
20. BIOCfgErr 32777
21. BISelfChkCircuitErr 33787
22. BOLatchedPropertyCfgErr 33793

Need to confirm the address jumper of
the module, insert the module firmly
23. BICommInterrupt 33781
and confirm that the binary input
program is correct
Need to confirm the address jumper of
the module, insert the module firmly
24. BOCommInterrupt 33782
and confirm that the binary output
program is correct
Table 271 Report list of class 2 alarm
1. SRAMSelfChkErr 33771
2. TestStateNotRst 33772
3. OperFail 33773
4. CanCommInterrupt 33775
5. FLASHSelfChkErr 33776
6. WorkInTestSetGrp 33783
7. BIInputErr 33785
8. DualPosnInputIncosist 33786
9. BIOInputPowerErr 33788
2.2 Operation report

Table 272 Operation report list
No. Report name Alarm code
1. SwitchSetGrpSuccess 32769
2. CopySetGrpSuccess 32789
458
Chapter 39 Appendix
No. Report name Alarm code
3. WriteIEDSetSuccess 32770
4. WriteParmSuccess 32771
5. WriteCfgSuccess 32772
6. AdjScaleSuccess 32773
7. AdjAngleSuccess 32788
8. HardConnOn/OffSuccess 32774
9. SoftConnOn/OffSuccess 32775
10. ClearCfg 32776
11. IEDRst(CPUReboot) 32778
12. FactoryRst 32779
13. BOTestSuccess 32780
14. ZeroDriftAdjSuccess 32782
15. ClearAllRptSuccess 32783
16. MaintModeOn 32785
17. MaintModeOff 32786
18. AutoRebootAfterCfg 32868
3 Analog list
Table 273 Analog list
No. LCD display Description Remark
1 Ua Phase A protection voltage
2 Ub Phase B protection voltage
3 Uc Phase C protection voltage
4 Ia Phase A Protection current
5 Ib Phase B Protection current
6 Ic Phase C Protection current
7 3I0 3 times of zero sequence current
8 IN Zero sequence current of adjacent line
459
Chapter 39 Appendix

9 Ux Reference voltage of synchronization
10 IaR Redundant current of phase A
11 IbR Redundant current of phase B
12 IcR Redundant current of phase C
3 times of zero sequence redundant

13 3I0R
current
14 UaR Redundant voltage of phase A
15 UbR Redundant voltage of phase B
16 UcR Redundant voltage of phase C
17 3U0 3 times of zero sequence voltage
18 Uab Phase A to phase B voltage
19 Ubc Phase B to phase C voltage
20 Uca Voltage of phase C-to-phase A
21 3U1 3 times of positive sequence voltage
22 3U2 3 times of negative sequence voltage
23 3I1 3 times of positive sequence current
24 3I2 3 times of negative sequence current
25 Za Phase A impedance
26 Zb Phase B impedance
27 Zc Phase C impedance
Phase A and phase B two-phase-to-earth

28 Zab
fault
29 Zbc BC phase-to-phase impedance
30 Zca CA phase-to-phase impedance
31 F Frequency
32 P1 Active power primary value
33 Q1 Reactive power primary value
34 P2 Active power secondary value
35 Q2 Reactive power secondary value
460
Chapter 39 Appendix

Thermal cumulative percentage of A
36 ThermalA
phase
Thermal
Thermal cumulative percentage of B overload
37 ThermalB
phase protection
function
Thermal cumulative percentage of C
38 ThermalC
phase
39 Idiff_A Differential current of phase A
40 Idiff_B Differential current of phase B
41 Idiff_C Differential current of phase C Differential

protection
42 Ires_A Restrict current of phase A function
43 Ires_B Restrict current of phase B
44 Ires_C Restrict current of phase C
45 Ia1 Grp1 Phase A Protection current In 3/2

connection
46 Ib1 Grp1 Phase B Protection current mode and
double CT
47 Ic1 Grp1 Phase C Protection current
Mode
48 3I01 Grp1 3 times of zero sequence current
49 Ia1R Grp1 redundant current of phase A
50 Ib1R Grp1 redundant current of phase B
51 Ic1R Grp1 redundant current of phase C
52 3I01R Grp1 3 times of zero sequence redundant
53 Ia2 Grp2 Phase A Protection current
54 Ib2 Grp2 Phase B Protection current
55 Ic2 Grp2 Phase C Protection current
56 3I02 Grp2 3 times of zero sequence current
57 Ia2R Grp2 redundant current of phase A
58 Ib2R Grp2 redundant current of phase B
59 Ic2R Grp2 redundant current of phase C
60 3I02R Grp2 3 times of zero sequence redundant
Note: in the protection analog, there are Ia and IaR, Ib and IbR, Ic and IcR
and other analogs. The difference is that the same analog has two
channels of A/D acquisition, and the reliability is ensured by the
comparison of the acquisition circuits. Where, Ia, Ib, Ic are the main
measurement analogs; the analogs with suffixes "R" such as IaR, IbR, IcR
has self-checking function.
461
Chapter 39 Appendix
4 Typical wiring
A. For single busbar or double busbar, a circuit breaker
wiring
A
B
C
Protection device
a1
b1 IA
a3
b3 IB
* * * a4
b4 IC
b6
a6 IN
a10
UA
a11
UB
a12
UC
b10、b11、b12
UN
a9
b9 U4
Figure 237 Typical wiring of single busbar or double busbar with one circuit breaker
(CT of 1A)
462
Chapter 39 Appendix
B. 3/2 circuit breaker circuit connection

A
B
C
* * *
Protection device
* * * a1
b1 IA
a3
b3 IB
a4
b4 IC
b6
a6 IN
a10
UA
a11
UB
a12
UC
b10、b11、b12
UN
a9
b9 U4
A
B
C
Figure 238 Typical wiring of 3/2 circuit breaker (CT of 1A)
463
Chapter 39 Appendix
C. Double circuit connection

A
B
C
Protection device
a1
b1 IA
a3
b3 IB
* * * a4 * * *
b4 IC
b6
a6 IN
a10
UA
a11
UB
a12
UC
b10、b11、b12
UN
a9
b9 U4
b7
a7 INM
Figure 239 Typical wiring of double circuit connection(CT of 1A)
464
Chapter 39 Appendix
D. 3/2 circuit breaker circuit connection(Double CT Mode)

A
B
C
* * *
保护装置
a1(AC1)
b1(AC1) IA1
a3(AC1)
b3(AC1) IB1
a4(AC1)
b4(AC1) IC1
b1(AC2)
a1(AC2) IN1
* * * a6(AC1)
b6(AC1) IA2
a7(AC1)
b7(AC1) IB2
a9(AC1)
b9(AC1) IC2
b3(AC2)
a3(AC2) IN2
a10(AC1)
UA
a11(AC1)
UB
a12(AC1)
UC
b10、b11、b12(AC1)
UN
a6(AC2)
b6(AC1) U4
A
B
C
Figure 240 Typical wiring of 3/2 circuit breaker In double CT Mode (CT of 1A)
465
Chapter 39 Appendix
5 Inverse time characteristic

5.1 Twelve types of inverse time characteristic curve of
IEC and ANSI
In setting, if inverse time characteristic curve is set, the corresponding
curve will be related. To support IEC and ANSI inverse time curve.
Table 274 Twelve types of inverse time characteristic curves of IEC and ANSI
Serial
number of Inverse time curve Parameter A Parameter P Parameter B
curve
1 IEC inverse time 0.14 0.02 0
2 IEC very inverse time 13.5 1.0 0
3 IEC extreme inverse time 80.0 2.0 0
4 IEC short inverse time 0.05 0.04 0
5 IEC long inverse time 120.0 1.0 0
6 ANSI inverse time 8.9341 2.0938 0.17966
7 ANSI SHORT INV. 0.2663 1.2969 0.03393
8 ANSI LONG INV. 5.6143 1 2.18592
9 ANSI moderate inverse time 0.0103 0.02 0.0228
10 ANSI very inverse time 3.922 2.0 0.0982
11 ANSI extreme inverse time 5.64 2.0 0.02434
12 ANSI definite inverse time 0.4797 1.5625 0.21359
5.2 User-defined properties

As for inverse time characteristic, if curve order is set 13, it belongs to
consumer set characteristic.
𝐀𝐀
𝐒𝐒 = � 𝐒𝐒 𝐩𝐩
+ 𝐁𝐁�T
� � − 𝟏𝟏
𝐈𝐈
Where:
A: time coefficient of inverse time
B: time delay of inverse time
P: inverse time index
T: inverse time constant
466
Chapter 39 Appendix
6 Explanation of abbreviations
6.1 Explanation of setting abbreviations
Table 275 Explanation of setting abbreviations
Abbreviations Explanation
AbruptChgCurrSet Abrupt change current setting
IEDRstTime IED reset time of the whole group
3I0DirectSensitiveAngle Sensitive angle of directional zero sequence
NSDSensitiveAngle Sensitive angle of directional negative sequence
OCHarmUnblkCurr Harmonic unblocking phase current of overcurrent
OC2ndHI2/I1Ratio I2/I1 of second harmonic of overcurrent
3I02ndHI02/I01Ratio I02/I01 ratio of second harmonic of zero sequence current
3I0HarmUnblkCurr Harmonic unblocking earth fault protection current
SyncPh Synchronization phase
SplitPhDiffHighSet High setting of split phase differential
SplitPhDiffLowSet Low setting of split phase differential
CTFailSplitPhDiffSet Split phase differential current setting after CT failure
REFSet Setting of restricted earth fault
REFTime Time of restricted earth fault
CTRatioCompCoef Compensation coefficient of CT ratio
LinePositiveSeqXcSet Positive sequence capacitive reactance setting of line
LineZeroSeqXcSet Zero sequence capacitive reactance setting of line
ShuntReactorPositiveSeqX Positive sequence reactance of shunt reactor
ShuntReactorZeroSeqX Zero sequence reactance of shunt reactor
LocalIDCode Local ID code
OppEndIDCode Opposite end ID
DTTTime direct transmit trip time
Compensation coefficient of distance zone 1 zero sequence
DistZ1ZeroSeqXCompCoef
reactance
Compensation coefficient of distance zone 1 zero sequence
DistZ1ZeroSeqRCompCoef
resistance
Compensation coefficient of other zones zero sequence
OtherZoneZeroSeqXCompCoef
reactance
Compensation coefficient of other zones zero sequence
OtherZoneZeroSeqRCompCoef
resistance
AdjacLineZeroSeqCompCoef Zero sequence compensation coefficient of the adjacent line
WholeLinePositiveSeqX Positive sequence reactance in the whole line
WholeLinePositiveSeqR Positive sequence resistance in the whole line
LineLengthSet Line length setting
SteadyLossStabilityCurrSet Current setting of steady loss stability
ResistanceSetOfPEZ1 Resistance setting of phase-to-earth zone 1
ReactanceSetOfPEZ1 Reactance setting of phase-to-earth zone 1
467
Chapter 39 Appendix
ResistanceSetOfPEExtZ1 Resistance setting of phase-to-earth extension zone 1
ReactanceSetOfPEExtZ1 Reactance setting of phase-to-earth extension zone 1
PEZ1Time Time of phase-to-earth zone 1
PEExtZ1Time Time of phase-to-earth extension zone 1
ResistanceSetOfPPZ1 Resistance setting of phase-to-phase zone 1
ReactanceSetOfPPZ1 Reactance setting of phase-to-phase zone 1
ResistanceSetOfPPExtZ1 Resistance setting of phase-to-phase extention zone 1
ReactanceSetOfPPExtZ1 Reactance setting of phase-to-phase extention zone 1
PPZ1Time Time of phase-to-phase zone 1
PPExtZ1Time Time of phase-to-phase extention zone 1
The offset angle of single phase distance zone 1 for MHO
PEZ1ShiftAngle
characteristic
Impedance setting of single phase distance zone 1 for MHO
MHOImpedSetOfPEZ1
characteristic
The offset angle of phase to phase distance zone 1 for MHO
PPZ1ShiftAngle
characteristic
Impedance setting of phase to phase distance zone 1 for
MHOImpedSetOfPPZ1
MHO characteristic
PEZ2ShiftAngle
characteristic
MHOImpedSetOfPEZ2
characteristic
PPZ2ShiftAngle
characteristic
MHOImpedSetOfPPZ2
MHO characteristic
PEZ3ShiftAngle
characteristic
MHOImpedSetOfPEZ3
characteristic
PPZ3ShiftAngle
characteristic
MHOImpedSetOfPPZ3
MHO characteristic
468
Chapter 39 Appendix
PEZ4ShiftAngle
characteristic
MHOImpedSetOfPEZ4
characteristic
PPZ4ShiftAngle
characteristic
MHOImpedSetOfPPZ4
MHO characteristic
PEZ5ShiftAngle
characteristic
MHOImpedSetOfPEZ5
characteristic
PPZ5ShiftAngle
characteristic
MHOImpedSetOfPPZ5
MHO characteristic
The offset angle of single phase distance extension zone 1
PEExtZ1ShiftAngle
for MHO characteristic
Impedance setting of single phase extention zone 1 for
MHOImpedSetOfPEExtZ1
MHO characteristic
The offset angle of phase to phase distance extension zone
PPExtZ1ShiftAngle
1 for MHO characteristic
Impedance setting of phase to phase extention zone 1 for
MHOImpedSetOfPPExtZ1
MHO characteristic
DistSOTFCurrSet Current setting of distance switch-on-to-fault
PEDist3I0 Zero sequence current of phase-to-earth distance
PEDist3U0 Zero sequence voltage of phase-to-earth distance
DistZ1InclinedAngle Inclined angle of distance zone 1
OtherZoneInclinedAngle Inclined angle of other zones
ResistanceLineAngle Resistance line angle
2ndQuadrantAngle The angle of second quadrant
4thQuadrantAngle The angle of fourth quadrant
PELoadEncroachmentAngle Load encroachment angle of phase-to-earth distance
PEDistLoadEncroachR Load encroachment resistance of phase-to-earth distance
PPLoadEncroachmentAngle Load encroachment angle of phase-to-phase distance
PPDistLoadEncroachR Load encroachment resistance of phase-to-phase distance
PowerSwingUnblkTime Time of power swing unblocking
FwdMOVBreakdownVoltSet Forward MOV breakdown voltage setting
SeriesCompXcSet Series compensation capacitive reactance setting
RvsPowerTime Time of reversed power
Pilot3I0Set Pilot earth fault setting
Pilot3I0Time Pilot earth fault time
OCStage1CurrSet Current setting of overcurrent stage 1
OCStage1Time Time of overcurrent stage 1
OCStage1Curve Curve of overcurrent stage 1
InvTimeOCStage1CoefA Coefficient A of inverse time overcurrent stage 1
InvTimeOCStage1IndexP Index P of inverse time overcurrent stage 1
InvTimeOCStage1TimeB Time B of inverse time overcurrent stage 1
InvTimeOCStage1ConstT Constant T of inverse time overcurrent stage 1
InvTimeOCStage1MinTime Minimum time of inverse time overcurrent stage 1
469
Chapter 39 Appendix
DirOCSensitiveAngle Sensitive angle of overcurrent direction
PPVoltBlkSet Blocking setting of phase-to-phase voltage
U2BlkSet Blocking setting of negative sequence voltage
HarmCrossBlkTime Harmonic cross blocking time
3I0Stage1CurrSet Current setting of earth fault protection stage 1
3I0Stage1Time Time of earth fault protection stage 1
3I0Stage1Curve Curve of earth fault protection stage 1
InvTime3I0Stage1CoefA Coefficient A of inverse time earth fault protection stage 1
InvTime3I0Stage1IndexP Index P of inverse time earth fault protection stage 1
InvTime3I0Stage1TimeB Inverse time B of earth fault protection stage 1
InvTime3I0Stage1ConstT Constant T of inverse time earth fault protection stage 1
InvTime3I0Stage1MinTime Minimum time of inverse time zero sequence current stage 1
470
Chapter 39 Appendix
3I2Stage1CurrSet Current setting of negative sequence current stage 1
3I2Stage1Time Time of negative sequence current stage 1
3I2Stage1Curve Negative sequence current stage 1 curve
Inverse time coefficient A of negative sequence current
InvTime3I2Stage1CoefA
stage 1
InvTime3I2Stage1IndexP Inverse time index P of negative sequence current stage 1
InvTime3I2Stage1TimeB Time B of inverse time of negative sequence current stage 1
Inverse time constant T of negative sequence current stage
InvTime3I2Stage1ConstT
1
Minimum time of inverse time negative sequence current
InvTime3I2Stage1MinTime
stage 1
stage 2
2
stage 2
stage 3
3
stage 3
stage 4
471
Chapter 39 Appendix
4
stage 4
OVStage1VoltSet Voltage setting of overvoltage stage 1
OVStage1Time Time of overvoltage stage 1
OVStage1Curve Curve of overvoltage stage 1
InvTimeOVStage1CoefA Coefficient A of inverse time overvoltage stage 1
InvTimeOVStage1IndexP Index P of inverse time overvoltage stage 1
InvTimeOVStage1TimeB Time B of inverse time overvoltage stage 1
InvTimeOVStage1ConstT Constant T of inverse time overvoltage stage 1
InvTimeOVStage1MinTime Minimum time of inverse time overvoltage stage 1
OVDropoffCoef Overvoltage dropoff coefficient
3U2Stage1VoltSet Voltage setting of negative sequence voltage stage 1
3U2Stage1Time Time of negative sequence overvoltage stage 1
3U2Stage1Curve Negative sequence voltage stage 1 curve
Coefficient A of inverse time of negative sequence voltage
InvTime3U2Stage1CoefA
stage 1
Index P of inverse time of negative sequence voltage stage
InvTime3U2Stage1IndexP
1
InvTime3U2Stage1TimeB Time B of inverse time of negative sequence voltage stage 1
Constant T of inverse time of negative sequence voltage
InvTime3U2Stage1ConstT
stage 1
Minimum time of inverse time negative sequence voltage
InvTime3U2Stage1MinTime
stage 1
472
Chapter 39 Appendix
stage 2
2
stage 2
stage 2
stage 3
3
stage 3
stage 3
stage 4
4
stage 4
stage 4
UVStage1VoltSet Voltage setting of undervoltage stage 1
UVStage1Time Time of undervoltage stage 1
UVStage1CurveSel Curve selection of undervoltage stage 1
InvTimeUVStage1CoefA Coefficient A of inverse time undervoltage stage 1
InvTimeUVStage1IndexP Index P of inverse time undervoltage stage 1
InvTimeUVStage1TimeB Time B of inverse time undervoltage stage 1
InvTimeUVStage1ConstT Constant T of inverse time undervoltage stage 1
InvTimeUVStage1MinTime Minimum inverse time of undervoltage stage 1
473
Chapter 39 Appendix
UVCurrSet Current setting of undervoltage
UVDropoffCoef Undervoltage dropoff coefficient
3PhUVBlkSet Undervoltage blocking setting of three-phase
ThermalOLCurrSet Current setting of thermal overload
ThermalTimeConst Hhermal time constant
ThermalOLCoolingCoef Cooling coefficient of thermal overload
ThermalOLAlarmCoef1 Coefficient 1 of thermal overload alarm
ThermalOLAlarmCoef2 Coefficient 2 of thermal overload alarm
PowerProtStage1PowerSet Power setting of power protection stage 1
PowerProtStage1Time Time of power protection stage 1
PowerProtStage2PowerSet Power setting of power protection stage 2
PowerProtStage2Time Time of power protection stage 2
CBFCurrSet Current setting of circuit breaker failure
CBF3I0Set Zero sequence current setting of circuit breaker failure
CBF3I2Set Current setting of circuit breaker failure negative sequence
CBFTime1 Time 1 of circuit breaker failure
CBFTime2 Time 2 of circuit breaker failure
Time delay three-phase trip time of circuit breaker failure
CBFStage1 1PhTrip3PhTime
stage 1
CBF BIAlarmTime Time of binary input alarm of circuit breaker failure
DZCurrSet Current setting of dead zone
DZTime Dead zone time
DZProt3I0Set Current setting of dead zone protection zero sequence
DZProt3I2Set Current setting of dead zone protection negative sequence
BIErrAlarmTime Time of binary input error alarm
StubCurrSet Current setting of stub protection
StubTime Time of stub protection
PD3I0Set Curent setting of pole discrepancy zero sequence
PD3I2Set Current setting of pole discrepancy negative sequence
PDTripTime Time of pole discrepancy trip
BrokenConductor3I2Set Current setting of negative sequence broken conductor
I1/I2Coef Current coefficient of positive and negative sequence
BrokenConductorTime Time of broken conductor
474
Chapter 39 Appendix
Df/dtBlkFreqSet Df/dt blocking frequency setting
UFLSStage1FreqSet Frequency setting of underfrequency load shedding stage 1
UFLSStage1Time Time of underfrequency load shedding stage 1
Df/dtBlkSet Blocking setting of frequency change rate
LoadShedCurrBlkSet Blocking setting of load shedding current
OFStage1FreqSet Frequency setting of overfrequency stage 1
OFStage1Time Time of overfrequency stage 1
LoadShedVoltBlkSet Blocking setting of load shedding voltage
FreqDf/dtStage1Set Setting of frequency change rate stage 1
FreqDf/dtStage1Time Time of frequency change rate of stage 1
DirModeDf/dtStage1 Directional mode of frequency change rate stage 1
Overfrequency threshold of stage 1 of frequency change
Df/dtStage1HFThreshold
rate
Underfrequency threshold of stage 1 of frequency change
Df/dtStage1LFThreshold
rate
rate
rate
rate
rate
rate
rate
FreqDf/dtVoltThreshold Voltage threshold of frequency change rate
FreqDf/dtHighThreshold High threshold of frequency change rate
475
Chapter 39 Appendix
FreqDf/dtLowThreshold Low threshold of frequency change rate
ImpedStayTime1 Impedance stay time T1
ImpedStayTime2 Impedance stay time T2
IntrZoneOutOfStepSlipTimes Out-of-step slipping times in internal zone
ExtrZoneOutOfStepSlipTimes Out-of-step slipping times in external zone
SOTF OCSet Current setting of switch-on-to-fault fault
SOTF3I0Set Zero sequence current setting of switch-on-to-fault fault
SOTFOCTime Time of manual closing overcurrent
SOTF3I0Time Time of manual closing zero sequence current
OpenPosnConfirmTime Confirm time of open position
SOTFStateLatchedTime Latched time of switch-on-to-fault state
BIErrTime Binary input abnormal time
OLAlarmCurrSet Current setting of overload alarm
OLAlarmTime Overload alarm time
SyncDetectTime Synchronization check time
SyncAngleDiffSet Setting of synchronization angle difference
SyncVoltDiffSet Setting of synchronization voltage difference
SyncFreqDiffSet Setting of synchronization frequency difference
ChkDeadVoltMaxVolt Maximum voltage of checking dead voltage
SyncChkMinVolt Minimum voltage of checking synchronization
MCSyncChkTime Time of manual closing check synchronization
MCWaitSyncTime Time of manual closing wait synchronization
MCSyncVoltDiffSet Setting of synchronization voltage difference
MCSyncAngleDiffSet Angle differential setting of manual closing synchronization
Frequency differential setting of manual closing
MCSyncFreqDiffSet
synchronization
MCChkDeadVoltMaxVolt Maximum voltage of manual close dead voltage check
MCSyncChkMinVolt Minimum voltage of manual close synchronization check
1PhARTime1 Time 1 of single phase auto-reclosing
3PhARTime1 Time 1 of three-phase auto-reclosing
ARPulse Auto-reclosing pulse
ARSuccessTime Auto-reclosing success time
SpringChargingTime Spring charging time
ARTimes Auto-reclosing times
ARChargingTime Auto-reclosing charging time
SyncDetectTimeOff Disable synchronization check time
Setting value of reclosing time of side circuit breaker locking
WaitMasterTime
intermediate circuit breaker
CTFail3I0Set Zero sequence current setting of CT failure
CTFailTime Time of CT failure
VTFailCurrSet Current setting of VT failure
VTFail3I0/I2 Zero and negative sequence current of VT failure
VTFailPEVolt VT failure phase-to-earth voltage
476
Chapter 39 Appendix
VTFailPPVolt VT failure phase-to-phase voltage
VTFailRstVolt Reset voltage of VT failure
VTFailAlarmTime Time setting VT failure alarm
VTFailRstTime Time of VT failure reset
VTFailBIErrTime Time of VT failure binary input abnormal
The zero-sequence current setting of zero sequence power
ZSPProt3I0Set
protection
ZSPProtPowerSet The power setting of zero sequence power protection
InvTimeZSPProtRef The reference of inverse time zero sequence power
InvTZSPProtDropoffCoefK Inverse time drop-off coefficient K of zero power protection
The fundamental time delay of zero sequence power
ZSPProtFundTime
protection
3I0DirectSensitiveAngle The sensitive angle of zero-sequence current direction
6.2 Explanation of logic switch abbreviations

Table 276 Explanation of logic switch abbreviations
ParallelLineMode Parallel line mode
EarthSystem grounding system
VoltFromLineVT Voltage connection line VT
PPFaultInitAR Phase-to-phase fault initiating auto-reclosing
3PhFaultInitAR Three phase fault initiates auto-reclosing
3PhTripMode Trip mode of three-phase
3/2BreakerConnectMode 3/2 breaker connection mode
3PhVoltConnect Three-phase voltage connection
VTFailProtOff Disable VT failure protection
Extr3I0 External zero sequence current
DiffOn Enable differential protection
AbruptChgDiffOn Enable abrupt change differential
MasterMode Master mode
ChanLoopTestOn Enable channel loop test
CompByCapacitiveCurr Compensation by capacitive current
CTFailBlkDiff CT failure blocking differential protection
CTFailBlk3Ph CT failure blocking three phase
REFInitAR Restricted earth fault initiates auto-reclosing
CTFailDetectOn Enable CT failure
DualChan Dual channels
SelExtrClockForChanA Select external clock for channel A
Sel64KRateForChanA Select 64K rate for channel A
SelExtrClockForChanB Select external clock for channel B
Sel64KRateForChanB Select 64K rate for channel B
DTTCtrlledByStartup Direct transmit trip is controlled by startup component
DTTCtrlledByZ2 Direct transmit trip is controlled by component Z2
DTTCtrlledByZ3 Direct transmit trip is controlled by component Z3
DistZ1On Enable distance zone 1
477
Chapter 39 Appendix
DistZ3RvsDir Reverse direction of distance zone 3
DistZ3SOTFOn Enable switch-on-to-fault of distance zone 3
DistExtZ1On Enable distance extension zone 1
DistZ1BlkByPowerSwing Distance zone 1 is blocked by power swing
DistZ4BlcByPowerSwing Distance zone 4 is blocked by power swing
DistExtZ1BlkByPowerSwing Distance extending zone 1 is blocked by power swing
DistZ2AccelOn Enable distance zone 2 acceleration
DistZ3AccelOn Enable distance zone 3 acceleration
AccelZBlkByHarm Distance acceleration zone is blocked by harmonic
DistZ2InitAR Distance zone 2 initiates auto-reclosing
PEDistLoadEncroachment Load encroachment of phase-to-earth distance
PPDistLoadEncroachment Load encroachment of phase-to-phase distance
FastDistZ1Prot Protection of fast distance zone 1
MHOCharac MHO characteristic
SeriesCompLS Series compensation logic switch
VTAtSeriesCompLineSide VT at series compensation capacitor line side
TestSmallRectangleZCharac Test small rectangle impedance characteristic
TestZCharac Test impedance characteristic
SOTFFaultChk2ndH Switch-on-to-fault checks second harmonic
WeakInfeedOn Enabled weak-infeed function
BlkModeLogicOn Enable blocking logic
PUTTModeOn Enable permissive underreach transfer trip mode
POTTModeOn Enabled permissive overreach transfer trip mode
PilotDistAccelOn Enable pilot distance acceleration
ParallelLinePhSendMsg Parallel line phase sending message
Pilot3I0On Enable pilot earth fault
Pilot3I0BlkByHarm Pilot earth fault is blocked by harmonic
Pilot3I0InitAR Pilot earth fault initiates auto-reclosing
OCStage1On Enable stage 1 of overcurrent
DirOCStage1 Directional overcurrent of stage 1
OCStage1FwdDir Forward direction overcurrent of stage 1
OCStage1BlkByVolt Overcurrent stage 1 is blocked by voltage
OC1BlkBy2ndH Overcurrent stage 1 blocked by second harmonic
478
Chapter 39 Appendix
3I0Stage1On Enable earth fault protection of stage 1
DefTime3I0Stage1SelTripOn Enable the definite time of zero sequence current selecting trip
of stage 1
Dir3I0Stage1 Directional earth fault stage 1
3I0Stage1FwdDir Forward direction of earth fault protection stage 1
3I0Stage1BlkBy2ndH earth fault protection stage 1 is blocked by second harmonic
of stage 2
of stage 3
of stage 4
3I0ChkU2I2DirOn Enable zero sequence check U2/I2 directional
3I0HarmonChkExtrI02/I01 Earth fault protection harmonic check external connection
I02/I01
CTFailBlk3I0 CT failure blocking earth fault protection
Non3PhOperBlkI2 Pole discrepancy blocks negative sequence overcurrent
3I2Stage1On Enable stage 1 of negative sequence current
OVChkPEVolt Overvoltage check phase-to-earth voltage
OVChk1Ph Overvoltage check 1 phase
OVStage1On Enable stage 1 of overvoltage
OVStage1Alarm Overvoltage stage 1 alarm
479
Chapter 39 Appendix
3U2Stage1On Enable stage 1 of negative sequence voltage
UVStage1On Enable stage 1 of undervoltage
UVStage1Alarm Undervoltage stage 1 alarm
UVChkCBState Undervoltage check circuit breaker state
UVChkCurrOn Enable undervoltage check current
UVChk1Ph Undervoltage check 1 phase
UVChkPEVolt Undervoltage check phase-to-earth voltage
UVChkExistedLiveVoltOn Enable existed live voltage checking of undervoltage
ThermalOLOn Enable thermal overload
ThermalOLAlarm1On Enable thermal overload alarm 1
ThermalOLAlarm2On Enable thermal overload alarm 2
ThermalCurve Hot curve
PowerProtStage1On Enable stage 1 of power protection
OutgoLineRvsPowerStage1On Enable stage 1 of outgoing line reverse power
PowerProtStage2On Enable stage 2 of power protection
OutgoLineRvsPowerStage2On Enable stage 2 of outgoing line reverse power
CBFOn Enable circuit breaker failure protection
1PhCBFOn Enable single phase circuit breaker failure
CBFStage1 1PhTrip3Ph Time of three-phase trip of circuit breaker failure stage 1
CBFChk3I0/3I2 Circuit breaker failure checks zero/negative sequence
currents
CBFChkCBPosn Circuit breaker failure check circuit breaker position
DZProtOn Enable dead zone protection
DZChk3I0/3I2 Dead zone protection check zero/negative sequence currents
StubOn Enable stub protection
PDProtOn Enable pole discrepancy protection
PDChk3I0/3I2 Pole discrepancy check zero/negative sequence current
BrokenConductorOn Enable broken conductor
BrokenConductorTripOn Enable Broken conductor protection trip
BrokenConductorChk3I2 Broken conductor protection check negative sequence current
BrokenConductorChkCBPosn Broken conductor protection check circuit breaker position
GenlUFLSOn Enable general underfrequency load shedding
UFStage1On Enable stage 1 of underfrequency
UFLSChkDf/dt Underfrequency load shedding checks Df/dt
480
Chapter 39 Appendix
UFLSChkCurrOn Enable current checking of underfrequency load shedding
OFStage1On Enable stage 1 of overfrequency
GenlFreqDf/dtOn Enable general frequency change rate
FreqDf/dtStage1On Enable stage 1 of frequency change rate
FreqDf/dtStage1DetectVolt Detection voltage of frequency change rate stage 1
Df/dtStage1ChkFreq Detection frequency of frequency change rate stage 1
OutOfStepProtOn Enable out-of-step protection
IntrZoneOutOfStepOn Enable out-of-step in internal zone
ExtrZoneOutOfStepOn Enable out-of-step in external zone
SelPositiveSeqImped Select positive sequence impedance
SelPhABPPZ Select AB phase-to-phase impedance
SelPhBCPPZ Select BC phase-to-phase impedance
SelPhCAPPZ Select CA phase-to-phase impedance
SOTFOn Enable switch-onto-fault
SOTFChkBI/Posn Switch on to fault fault check binary input and position
SOTFChkPosn Switch on to fault fault check position
SOTFChkBI Switch on to fault fault check binary input
OLAlarmOn Enable overload alarm
OverrideModeOn Enable override mode
SyncChkModeOn Enable synchronization check mode
ChkDLLBOn Enable check dead line live busbar
ChkLLDBOn Enable check live line dead busbar
ChkDLDBOn Enable check dead zone of both sides
DeadVoltChkFailSyncChk If dead voltage check fails, switch to synchro-check
MidBrkMode In 3/2 connection mode, as the intermediate circuit breaker
mode
AfterCloseSide
In 3/2 connection mode, as the after closing circuit breaker
mode
MCSyncOn Enable manual close synchronization

MCOverrideModeOn No synchronization check of manual closing
MCSyncChk Manual closing synchronization check
MCChkDLLBOn Manual close check dead line live busbar
MCChkLLDBOn Manual close check live line dead busbar
MCChkDLDBOn Manual close check dead line dead busbar
481
Chapter 39 Appendix
AROn Enable auto-reclosing
BISwitchARMode Binary output switches auto-reclosing mode
ARMode Auto-reclosing mode
ARTrip3Ph/BlkAR Auto-reclosing trip three-phase and blocking auto-reclosing
1PhSpontaneousTripInitAR Single phase spontaneous trip initiates auto-reclosing
3PhSpontaneousTripInitAR Three-phase spontaneous trip initiates auto-reclosing
1PhARChk3PhLiveVolt Single phase closing check three-phase live voltage
VTFailOn Enable VT failure
3PhVTFailCurr/PosnConfirm Three-phase VT failure current position comfirmation
3PhVTFailCurrConfirm Three-phase VT failure live current confirmation
BISwitchSetGrp Binary input switches setting group
ZSPDirProtOn Input the zero sequence power direction protection
CTFailBlkZSPDirProt CT failure blocks the zero sequence power direction protection
6.3 Explanation of trip report and alarm report

Table 277 Explanation of trip report and alarm report
SplitPhDiffTrip Trip of split phase differential
REFTrip Trip of restricted earth fault
DiffDevelopmentTrip Development trip of differential
DTTTrip Trip of direct transmit trip
TeleTransferCmd1BO Remote transmission command 1 binary output
TeleTransferCmd1Rst Remote transmission command 1 return
DiffWeakInfeedStartup Startup of differential weak-infeed
DiffRmtCallStartup Startup of differential remote call
3PhDiffCurr Three-phase differential current
3PhRestrCurr Three phase restraint current
DTT BI Direct transmit trip binary input
TeleTransferCmd1BI Remote transmission command 1 binary input
482
Chapter 39 Appendix
OppEndDiffTrip Differential trip of opposite end
SampleAsynchronization Sampling asynchronization
SampleSynchronized Sampling is synchronized
DataSrcChanA Data source channel A
DataSrcChanB Data source channel B
DiffSOTFTrip Differential switch-on-to-fault trip
SplitPhDiffPhATrip Phase A trip of split phase differential
SplitPhDiffPhBTrip Phase B trip of split phase differential
SplitPhDiffPhCTrip Phase C trip of split phase differential
ChanACommInterrupt Communication interruption of Channel A
ChanBCommInterrupt Communication interruption of Channel B
DTT BIErr Abnormal direct transmit trip binary input
ChanAAddrErr Address error of Channel A
ChanBAddrErr Address error of Channel B
ChanABErrorConnection Cross connection error of Channel AB
OppEndCommErr Communication error of opposite end
LocalCTFail Local CT failure
OppEndCTFail CT failure of opposite end
LongTermDiffCurr Long-term differential current
SyncModeSetErr Synchronization mode setting error
ChanALoopErr Loop error of Channel A
ChanBLoopErr Loop error of Channel B
NoSampleRptInChanA No sampling report in Channel A
NoSampleRptInChanB No sampling report in Channel B
LongTermChanLoopOn Enable channel loop for long time
DiffLSInconsist Inconsistent differential logic switch
ChanMaintDiffOff Channel maintenance differential disabled
IEDStartup IED startup
ImpedComponentStartup Startup of impedance component
ZeroSeqAuxStartup Auxiliary startup of zero sequence
SteadyLossStabilityStart Startup of steady loss stability
DistZ1Trip Trip of distance zone 1
DistExtZ1Trip Extension zone 1 impedance trip
DistSOTFAccelTrip Trip of distance switch-onto-fault protection
acceleration
PowerSwingBlkState Trip of power swing blocking
DistZ2AccelTrip Distance zone 2 acceleration trip
DistZ3AccelTrip Distance zone 3 acceleration trip
3PhTripFailTrip3Ph/BlkAR Three phases trip failure auto-reclosing
Intertrip3Ph Intertrip three-phase
3PhTripAfter1PhTripFail Trip three-phase after single phase trip fails
483
Chapter 39 Appendix
DistZ1DevelopmentTrip Distance zone 1 development trip
DistZ2DevelopmentTrip Distance zone 2 development trip
FaultLocation Fault location
FaultLocationImped Fault location impedance
PEZTrip Ground impedance trip
PPZTrip Phase-to-phase impedance trip
PEZDistPhATrip Trip of phase-to-earth of phase A
PEZDistPhBTrip Trip of Phase-to-earth of phase B
PEZDistPhCTrip Trip of Phase-to-earth of phase C
VTFailDistOff VT failure occurs, disable distance
PilotDistTrip Pilot distance trip
PilotDistDevelopmentTrip Pilot distance development trip
PilotDistStopMsg Stopping message of pilot impedance
PilotOpenPosnStopMsg Stopping message of pilot open position
PilotDistSendMsg Sending alarm of pilot impedance
PilotOpenPosnSendMsg Sending message of pilot open position
PilotWeakInfeedSendMsg Sending message of pilot weak in-feed
DTTSendMsg Sending message of direct transfer trip
DTTRcvMsg Receiving message of direct transfer trip
PilotTripStopMsg Stopping message of pilot trip
PilotTripSendMsg Sending message of pilot trip
PilotDistChanFault Channel fault of pilot distance
PilotLSErr Pilot logic switch error
Pilot3I0SendMsg Pilot earth fault sending message
Pilot3I0Trip Pilot earth fault trip
Pilot3I0StopMsg Stopping message of pilot earth fault
Pilot3I0ChanFault Channel fault of pilot earth fault
PilotWeakInfeedTrip Pilot protection trip of weak feed side
OCStage1Trip Trip of overcurrent stage 1
OCStage1PhATrip Overcurrent stage 1 phase A trip
OCStage1PhBTrip Overcurrent stage 1 phase B trip
OCStage1PhCTrip Overcurrent stage 1 phase C trip
InrushBlk Inrush blocking
OCAuxStartup Startup of overcurrent auxiliary
3I0Stage1Trip Trip of zero sequence current stage 1
484
Chapter 39 Appendix
3I0Stage1TripFail3PhTrip Trip three-phase after single phase trip
3I0Stage2TripFail3PhTrip Trip three-phase after single phase trip failure of
zero sequence current of stage 2
3I2Stage1Trip Trip of negative sequence current stage 1
OVStage1Trip Protection trip overvoltage stage 1
OVStage1Alarm Overvoltage stage 1 protection alarm
3U2Stage1Trip Trip of negative sequence voltage stage 1
UVStage1Trip Undervoltage stage 1 trip
ThermalOLTrip Protection trip of thermal overload
ThermalOLPhAFault Phase A failure of thermal overload
ThermalOLPhBFault Phase B failure of thermal overload
ThermalOLPhCFault Phase C failure of thermal overload
ThermalOLStartup Startup of thermal overload
ThermalOLStage1Alarm Alarm of thermal overload stage 1
ThermalOLStage2Alarm Alarm of thermal overload stage 2
PowerProtStage1Trip Trip of power protection stage 1
PowerProtStage2Trip Trip of power protection stage 2
Intr3PhInitCBF Internal three-phase initiates circuit breaker
failure
Extr3PhInitCBF External three-phase initiates circuit breaker
failure
IntrPhAInitCBF Internal phase A initiates circuit breaker failure
ExtrPhAInitCBF External phase A initiating circuit breaker failure
IntrPhBInitCBF Internal phase B initiates circuit breaker failure
485
Chapter 39 Appendix
ExtrPhBInitCBF External phase B initiating circuit breaker failure
IntrPhCInitCBF Internal phase C initiates circuit breaker failure
ExtrPhCInitCBF External phase C initiating circuit breaker failure
CBFStage1Trip Trip of circuit breaker failure stage 1
CBFStage1 1PhTrip3Ph Time of three-phase trip of circuit breaker failure
stage 1
CBFStage2Trip Trip of circuit breaker failure stage 2
PhACBFTrip Circuit breaker failure trip of phase A
PhBCBFTrip Circuit breaker failure trip of phase B
PhCCBFTrip Circuit breaker failure trip of phase C
3PhCBFTrip Trip of three-phase circuit breaker failure
CBF BIErr Circuit breaker failure binary input is abnormal
DZTrip Dead zone trip
DZ BIErrAlarm Binary input abnormal alarm of dead zone
protection
StubTrip Stub protection trip
PDStart Pole discrepancy start
PDTripPosnErr Abnormal trip position of pole discrepancy
PDTrip Pole discrepancy protection
BrokenConductorTrip Trip of broken conductor protection
BrokenConductorAlarm Broken conductor protection alarm
UFStage1Trip Trip of underfrequency stage 1
OFStage1Trip Trip of overfrequency stage 1
FreqDf/dtStage1Trip Trip of frequency change rate stage 1
IntrZoneOutOfStepTrip Out-of-step trip in internal zone
IntrZoneAccelOutOfStepAlarm Accelerate out-of-step alarm in internal zone
IntrZoneDecelOutOfStepAlarm Decrease out-of-step alarm in internal zone
ExtrZoneOutOfStepAlarm Out-of-step protection alarm in external zone
SOTF OCTrip Trip of switching on to fault overcurrent
SOTF 3I0Trip Trip of switch-on-to-fault zero sequence current
SOTF BIErrAlarm Binary input abnormal alarm of switch on to fault
OLAlarm Overload alarm
SyncVoltExchg Synchronization voltage exchange
MCVoltDiffFail Manual close voltage difference unsuccessful
MCFreqDiffFail Manual close frequency difference unsuccessful
MCAngleDiffFail Manual closing angle difference unsuccessfully
MCDeadVoltChkFail Manual close dead voltage check unsuccessful
MCSyncRequest Manual close synchronization request
MCSyncMet Manual close synchronization is met
MCSyncUVMet Manual close synchronization undervoltage is
486
Chapter 39 Appendix
met
MCSyncTimeout Manual close synchronization timeout
MCOverrideMode Manual close override mode
MCSyncVoltExchg Manual close synchronization voltage changing
MCMet Manual close condition is met
MCChkDLLBMet Manual close checkigng dead line and live
busbar is met
MCChkLLDBMet Manual close checking live line and dead busbar
is met
MCChkDLDBMet Manual close checking dead line and dead
busbar is met
SyncVoltErr Synchronization voltage abnormal
MCSyncVoltErr Manual close synchronization voltage is error
SyncPhSelConflict Synchronization phase difference selection
conflict
ChkARFail Check auto-reclosing unsuccessfully
3PhTripInitAR Three-phase trip initiates auto-reclosing
3PhSpontaneousTripInitAR Three-phase spontaneous trip initiates
auto-reclosing
1PhTripInitAR Single phase trip initiates auto-reclosing
1PhSpontaneousTripInitAR Single phase spontaneous trip initiates
auto-reclosing
ARProcessing Auto-reclosing is in process
3PhTripBlkAR Three-phase trip blocking auto-reclosing
1PhTripBlkAR Single phase trip blocks auto-reclosing
ARFail Auto-reclosing unsuccessfully
ARSuccess Auto-reclosing is successful
ARChkVoltDiffFail Auto-reclosing check voltage difference
unsuccessfully
ARChkFreqDiffFail Reclosing check frequency difference
unsuccessfully
ARChkAngleDiffFail Auto-reclosing check angle difference
unsuccessfully
ARDeadVoltChkFail Auto-reclosing check dead voltage
unsuccessfully
ARTrip3Ph/BlkAR Auto-reclosing trip three-phase and blocking
auto-reclosing
ARSyncRequest Auto-reclosing synchronization request
ARSyncMet Auto-reclosing synchronization is met
UVCondMet Undervoltage conditions are met
ARTrip Auto-reclosing trip
BlkAR Blocking auto-reclosing
ARWaiting Auto-reclosing waiting
SyncTimeout Synchronization timeout
AROverrideMode Auto-reclosing override mode
1stARTrip Trip of first-shot auto-reclosing
2ndARTrip Trip of second-shot auto-reclosing
3rdARTrip Trip of third-shot auto-reclosing
4thARTrip Trip of fourth-shot auto-reclosing
ARLSErr Auto-reclosing logic switch error
CTSecCircuitErr CT secondary circuit error
487
Chapter 39 Appendix
LineNonRunVTFail Line non-run VT failure
VTFailAlarm VT failure alarm
V3p_MCBAlarm V3p_MCB alarm
V3p_MCB BIAlarm V3p_MCB binary input alarm
The trip of zero sequence power direction
ZSPDirProtTrip
protection
Phase A circuit breaker is at open position and
TripPosnABIErr
there is current
Phase B circuit breaker is at open position and
TripPosnBBIErr
there is current
Phase C circuit breaker is at open position and
TripPosnCBIErr
there is current
Grp2 phase A circuit breaker is at open position
Grp2TripPosnABIErr
and there is current
Grp2 phase B circuit breaker is at open position
Grp2TripPosnBBIErr
Grp2 phase C circuit breaker is at open position
Grp2TripPosnCBIErr
6.4 Explanation of operation report abbreviations

Table 278 Explanation of operation report abbreviations
ChanACommRst Communication reset of channel A
ChanBCommRst Communication reset of channel B
OppEndIEDRst IED reset of opposite end
OppEndIEDOff The IED of opposite is disabled
DiffFcnOn Enable differential function
DiffFcnOff Disable differential function
RmtLoopbackOfChanA Remote loopback of channel A
ChanALoopbackEnd End of channel A loopback
RmtLoopbackOfChanB Remote loopback of channel B
ChanBLoopbackEnd End of channel B loopback
DistFcnOn Enable distance function
DistFcnOff Disable distance function
FcnPowerSwingOn Enable power swing blocking function
FcnPowerSwingOff Disable power swing blocking function
PilotDistFcnOn Enable pilot distance function
PilotDistFcnOff Disable pilot distance function
Pilot3I0FcnOn Enable pilot earth fault function
Pilot3I0FcnOff Disable pilot earth fault function
VTReturnToNormal VT returns to normal
VTFailFcnOn Enable VTDX function
VTDXFcnOff Disable VTDX function
TelectrlObject Telecontrol object
TelectrlCmdSrc Telecontrol command source
TelectrlResult Telecontrol result
TelectrlCmd Telecontrol command
TelectrlType Telecontrol type
FailReason Failure reason
488
Chapter 39 Appendix
6.5 Explanation of device menu abbreviations

Table 279 Explanation of device menu abbreviations
ViewInfo View information
IEDState IED State
Calc Analog quantity
Measure Measurement
Analog Analog input
PowerMetr Power metering
BIO Binary input output
GOState GOOSE state
StateMon State monitor
ChanInfo Channel info
AlarmInfo Alarm information
PriVal Primary value
SecVal Secondary value
ConventionalBI Conventional binary input
GOOriginBI GOOSE original binary input
ConventionalBO Conventional binary output
GOOSESubState Goose subscription state
GOOSEPubState GOOSE publication state
PresentErrCode Present error code
AllErrCode All error code
LostFrame The lost frame number
ViewSet View setting
ConState Connector state
VerInfo Version information
IEDSet Set IED
ProtSet1 IED setting 1
CalcSet Calculated setting
EquipParm Equipment parameter
BCUParm Bay control unit parameter
FunctionCon Function connector
GOOSEPubSoftCon GOOSE publishing soft connector
GOOSESubSoftCon GOOSE subscription soft connector
IED IDCode IED identification code
IEDVer IED version
VrtlTrmlChkCode Check code of virtual terminal
SyncMode Time synchronization mode
CommParm Communication parameter
EthernetSet Set Ethernet
IEDAddr IED address
Operate Running operation
ViewRpt View report
WriteSet Write setting
ConOn/Off Enable/Disable connector
SwitchSetGrp Switch setting group
489
Chapter 39 Appendix
LocalCtrl Local control
SLDCtrl Single line diagram control
GenlRpt General report
StartupRpt Startup report
TripRpt Trip report
AlarmRpt Alarm report
OperationRpt Operation report
BIChangeRpt Binary input change report
StartupDFRList Startup disturbance and fault record list
TripDFRList Trip disturbance and fault record list
ProtSet Protection setting
GrpCopy Copy setting group
Bay0 Bay 0
SubstationName Substation name
ProtEquipName Protection equipment name
IEDName IED name
TestMenu Test menu
BOTest Binary output test
CommChk Communication check
LEDTest LED Test
ManualRcd Manually controlled disturbance and fault record
FactoryTest Factory test
Print Print
GOOSE BO GOOSE binary output
FnAlarmChk Protection function alarm check
TripRepChk Trip report check
GOAlarmChk GOOSE alarm check
BIChk Binary input check
MSTAlarmChk MST alarm check
ConChk Connector check
AnalogChk Analog check
MeasureChk Measurement check
ViewZeroDrift View zero drift
ViewScale View scale
AdjZeroDrift Adjust zero drift
AdjScale Adjust scale
AngleCorrection Angle correction
SoftCon Soft connector
Rpt Report
SampVal Sampling value
TimeSet Set time
SetClock Modify clock
Language Set Language
OtherSet Set Other
CHN Chinese
ENG English
RUS Russian
NetTimeSyncIPSet Set Network time synchronization IP
490
Chapter 39 Appendix
TimeZone Set time zone
DST Daylight saving time
SerialSet Set serial port
ProtocolSet Protocol setting
PRPSet Set PRP
Password Set password
Contrast Contrast
DisplayMode Display mode
PowerMetrZeroing Power metering reset
Confirm Confirm switching
Mode1 Mode 1
Serial1Set Set serial port 1
491

SIFANG CSC-100EB Line Protection

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

SIFANG CSC-100EB Line Protection

Uploaded by

Copyright:

Available Formats

CSC-100

Line Protection IED

Notes: the company reserves the right to amend the introduction. If

is registered trademark of Beijing Sifang Automation Co., Ltd.

Manufacturer: Beijing Sifang Automation Co., Ltd.

Applicability of this Manual

Strictly follow the company and international safety regulations.

Do not touch any circuitry during operation. Potentially lethal

Using the isolated test pins when measuring signals in open

Never connect or disconnect wire and/or connector to or from IED

Do not disconnect the secondary connection of current

Do not remove the screw from a powered IED or from an IED

Using the certified conductive bags to transport PCBs (modules).

Do not connect live wires to the IED, internal circuitry may be

When replacing modules using a conductive wrist strap

When installing and commissioning, take care to avoid electrical

Changing the setting group will inevitably change the IEDs

About this chapter

Type Sub-type Description

The protective device is provided with many advanced functions, which

a) Current sudden-change startup component;

14) Special logic of pilot protection:

7 Earth fault protection 50N,51N,67N PVOC √ √

18 Stub protection 50STUB PTOC √ √

27 Overload alarm 50OL √ √

3.2 Monitoring function

Voltage current phase sequence monitoring

𝟑𝟑𝑰𝑰𝟎𝟎 Polarity monitoring

Three harmonic voltage monitoring

Check synchronization voltage monitor

Breaker auxiliary contacts monitoring

Primary broken circuit monitoring

Setting logic self-check

Fault phase display

Disturbance and fault record

Trip circuit monitoring

3.3 Measurement function

3.4 Control function

Position of circuit breaker, isolator and other switching devices control

3.5 Substation communication

Communication port on the faceplate

RJ45 Ethernet communication port

Isolated RS485 communication port

Ethernet electrical/optical communication port

Time synchronization port

IEC 61850 protocol

IEC 60870-5-103 protocol

DNP3.0 (supported by Master above 4.0)

MODBUS (supported by Master above 4.0)

3.6 Remote communication

Power line wave carrier interface

Digital communication network (through translator)

Chapter 2 General functions

About this chapter

1 Event record and analysis

1.2 Fault record

1.3 disturbance and fault record

1.4 Sequence of event (SOE)

through communication port. The protection SOE reports can be viewed

1.5 Operation record

2.2 Diagnostic principle

3 Time synchronization function

unified clock reference between the various devices.

3.2 Synchronization principle