Module-3 Combinational Circuits

Rashtreeya Sikshana Samithi Trust
RV Institute of Technology and Management®

(Affiliated to VTU, Belagavi)
JP Nagar, Bengaluru – 560076
Department of Computer Science and Engineering

Department of Information Science and Engineering
Course Name: Analog and Digital Electronics

Course Code: 18CS33
III Semester
2018 Scheme
Prepared By:
Dr. Jyothi A P
Assistant Professor,
Department of Computer Science and Engineering,
RVITM, Bengaluru – 560076
Dr. Niharika P. Kumar

Associate Professor,
Department of Information Science and Engineering,
RVITM, Bengaluru – 560076
Email: jyothiap.rvitm@rvei.edu.in
niharikapk.rvitm@rvei.edu.in
Module 3
Combinational Circuit Design and Simulation Using Gates
Syllabus:
Review of Combinational circuit design, design of circuits with limited Gate Fan-in ,Gate delays and
Timing diagrams, Hazards in combinational Logic, simulation and testing of logic circuits. Multiplexers,
three state buffers, decoders and encoders, Programmable Logic devices, Programmable Logic Arrays,
Programmable Array Logic.
Review of Combinational Circuit Design

Steps involved in the design of a combinational switching circuit:
1. Set up a truth table which specifies the output(s) as a function of the input variables. If a given
combination of values for the input variables can never occur at the circuit inputs, the corresponding output
values are don’t-cares.
2. Derive simplified algebraic expressions for the output functions using Karnaugh Maps, or Quine-
McCluskey method, or any other similar procedure. The resulting algebraic expressions are then
manipulated into the proper form, depending on the type of gates to be used in realizing the circuit.
3. When a circuit has two or more outputs, common terms in the output functions can often be used to
reduce the total number of gates or gate inputs.
4. Minimum two-level AND-OR, or NAND-NAND circuits can be realized using the minimum sum-of-
products. Minimum two-level OR-AND, or NOR-NOR circuits can be realized using the minimum product-
of-sums.
Design of Circuits with Limited Gate Fan-In

In practical logic design problems, the maximum number of inputs on each gate (or the fan-in) is limited.
Depending on the type of gates used, this limit may be two, three, four, eight, or some other number. If a
two-level realization of a circuit requires more gate inputs than allowed, factoring the logic expression to
obtain a multi-level realization is necessary.
Example 1 : Realize , , , = (0,3,4,5,8,9,10,14,15) using three input NOR gates. Solution specified in Fig. 3.1
III- Semester, Analog and Digital Electronics (18CS33) Page 2 of 33

Fig. 3.1 K Map for Example 1 Problem

The product-of-sum equation is:
f = ′+′+ +′+′ +′+ +++′ ′++′+′
As can be seen from the preceding expression, a two-level realization requires three-three input gates, two
four-input gates and one five-input gate. The expression for ′ is factored to reduce the maximum number of
gate inputs to three and, then, it is complemented. Circuit diagram is depicted in Fig 2.1 Or ′= ′+ ′ + ′ ′+ ′ ′ ′
+′
i.e., ′= ′+ ′ + ′ + ′( ′ ′+ )
Or =[ ′+ ′+ ] + ′ + ′ [ + ′ + + ′+ ′ ]
Fig. 3.2 Circuit Diagram for Example 1

Example 2: Realize the following functions using only two-input NAND gates and inverters. 1= Σ 0,2,3,4,5
2= Σ 0,2,3,4,7 3= Σ (1,2,6,7) Solution specified in Fig. 3.3:
Fig. 3.3 K Map for Example 2 Problem

Each function requires a three-input OR gate; so we will factor to reduce the number of gate inputs:
Also, we can eliminate the remaining three-input gate from f3 by noting that;
The following Fig 3.4 show the resulting circuits :

Fig. 3.4 Circuit Diagram for Example

2 Gate Delays and Timing Diagram
When the input to a logic gate is changed, the output will not change instantaneously. The transistors or
other switching elements within the gate take a finite time to react to a change in input, so the change in gate
output is delayed.
Timing diagrams as shown in Fig 3.5 show various signals in the circuit as a function of time.
Fig 3.5 Timing diagrams for various signals in the circuit as a function of time
In the circuit given below, each gate has a propagation delay of 20ns. B and C inputs are held constant with
values B=1 and C=0. When input A is changed from 0 to 1 at t=40 ns and 1 to 0 at t=100 ns. The output of
the gate G1 changes after A changes, and the output of gate G2 changes 20 ns after G1 changes as shown in
the below diagram Fig. 3.6.
Fig 3.6 output of gate G2 changes 20 ns after G1 changes

Timing diagram with addition delay element is represented in Fig 3.7
Fig 3.7 Timing diagram with addition delay element
Hazards in combinational Logic

• The unwanted switching transients that may appear at the output of a circuit are called hazards.
• The hazards cause the circuit to malfunction.
• The main cause of hazards is the different propagation delays at different paths.
Hazards when occur in a combinational circuits, may cause a temporary false output value. But when
such combinational circuits are used in the asynchronous sequential circuits, they may result in a
transition to a wrong stable state.
Types of Hazards
1. Static-1 hazard
2. Static-0 hazard
3. Dynamic Hazards
Static-1 Hazard
In a combinational circuit, if output goes momentarily 0 when it should remain a 1, the hazard is known
as static-1 hazard. The same is depicted in Fig 3.8
The following example explains static-1 hazard. If A= C = 1, then F=B + B' = 1, so F should remain
constant 1 when B changes from 1 to 0. But as each gate has a propagation delay of 10ns, E will go to 0
before D goes to 1, resulting in a momentary 0 (glitch caused by 1- hazard) appearing at the output F. As
soon as the B changes to 0, both inverter input (B) and output (B') are 0 until the propagation delay has
elapsed. Hence F momentarily goes to 0.

Fig 3.8 Static -1 Hazard

Detection and Removal of Static-1 Hazard
Consider the following K-map for the above circuit, which is minimally represented by F=AB' + BC. The
corresponding circuit is shown in fig b.
Consider, for this circuit input A=1 and C=1 and then B makes transition 1to 0. The output shows the glitch.
If we include one additional term AC for the above grouping the output becomes Y= AB' + BC + AC. The
corresponding circuit diagram is in fig d. This circuit though requires more hardware than minimal
representation, is hazard free. The additional term AC ensures F=1 for A=1, C=1 through the third input of
final OR gate and a 1 0 transition at B does not affect output. Now, there is no hazard possibility. The
inclusion of hazard cover does not alter the truth table in anyway as depicted in Fig 3.9. But F is no longer a
minimum sum of products.
Fig 3.9 Detection and Removal of Static-1 Hazard

Static-0 Hazard
If output goes momentarily 1, when it should remain a 0, the hazard is known as static-0 hazard. This type
of hazard occurs when Y=A.A' kind of situation occurs in a logic circuit as depicted in Fig 3.10 for certain
combination of other inputs and A makes a transition 0 to 1.

An A.A' condition should always generate 0 at the output i.e. static-0. But the NOT gate output takes finite
time to become 0 following a 0->1 transition of A. Thus for final AND gate there are two ones appearing at
its input for a small duration resulting a 1 at its output. This Y=1 occurs for a very small duration but may
cause malfunctioning of sequential circuit.
Fig 3.10 Static 0 Hazard

Consider the given truth table. The POS is given by Y= (B + C) (A + C') and corresponding circuit in fig b.
If B=0, A=0 and C makes a transition 0 1 there will be static-0 hazard occurring at the output. Static-0
Hazard Cover: To prevent this we add one additional group, (A+B) as in Fig 3.11 and the corresponding
circuit in fig d. The term (A+B) ensures Y=0 for A=0, B=0 through the third input of final AND gate and a
0 1 transition at C does not affect the output. Circuit in fig d is hazard free.
Note: When NOR gate with A and A' is connected at its input for certain input combination will give static-
0 hazard when A makes a transition 1 0 and requires hazard cover.
Fig 3.11 Static 0 Hazard Cover

Dynamic Hazard
Dynamic hazard occurs when circuit output makes multiple transitions before it settles to a final value while
the logic equation asks for only one transition.
When this hazard occurs, an output transition designed as
1->0 may give 1->0->1->0
0->1 may give 0->1->0->1
The output of logical equation in dynamic hazard degenerates into Y=A + A'.A or Y = (A + A') . A kind of
relations for certain combinations of other input variables. These occur in multilevel circuits having implicit
static-1 and/or static-0 hazards. By providing covers to each one of them, dynamic hazard can be prevented.
Detection of Hazards using K maps.
We can detect hazards in a two-level AND-OR circuit, using the following procedure:
1. Write down the sum-of-products expression for the circuit
2. Plot each term on the map and loop it.

3. If any two adjacent 1’s are not covered by the same loop, a 1-hazard exists for the transition between the
two 1’s.
4. 1-Hazards can be eliminated by covering such uncovered adjacent 1’s in common loop
5. Similarly 0-hazards can be eliminated by looping the additional prime implicants that cover the adjacent
0’s that are not already covered by a common loop as shown in the below example.
Remove the Static 0 hazard present in the given circuit using K map
Static 0 hazard can be removed as shown in the above K map using equation
F= (A+C) (A'+D') (B' + C' + D) (C + D') (A + B' + D) (A' + B' + C'). …………….. Eq 3.1
The resulting circuit requires seven gates in addition to the inverters.
Simulation and Testing of logic Circuits
Verifying the working of a logic circuit in computer is called simulation. Simulation is generally
easier, faster and more economical. As logic circuits become more complex, it is very important to
simulate a design before actually building it.
The reasons for simulation are:
1. Verification that the design is logically correct
2. Verification that the timing of the logic signals is correct
3. Simulation of faulty components in the circuit as an aid to finding tests for the circuit as depicted in Fig
3.12.
Fig 3.12 Simulation and Testing of logic Circuits

If a circuit output is wrong for some set of input values, this may be due to several possible causes
including:
1. Incorrect Design
2. Gates connected wrong
3. Wrong input signals to the circuit
4. Defective gates
5. Defective connecting wires
Debugging
The following example depicted in Fig 3.13 shows how to debug the circuit, if we are getting wrong output:

Fig 3.13 Debug the circuit
Multiplexers
It is a digital circuit with many inputs but only 1 output. By applying control-signals, we can steer any input
to output. Thus, it is also called a data-selector and control inputs are termed select inputs (Fig 3.1). The
circuit has n input signals, m control signals and 1 output signal. m control signals can select at the most 2m
input signals thus n ≤ 2m .
4:1 Multiplexer
• Depending on control inputs A and B, one of the 4 inputs D0 to D3 is steered to output Y as specified in Fig
3.14.
• The logic equation of the circuit (Fig: 3.1c) gives a SOP representation.
• Here, each AND gate generates a minterm which are finally summed by OR gate.
In other words, for AB=00, the first AND gate to which D0 is connected remains active and equal to D0 and
all other AND gate are inactive with output held at logic 0. If D0=0, Y=0 and if D0=1, Y=1.
Similarly, for AB=01, second AND gate will be active and all other AND gates remain inactive. Thus,
output Y=D1.
Fig 3.14 a) Multiplexer Block Diagram, (b) 4-to-1 multiplexer truth table, (c) Its logic circuit
Commercial multiplexer ICs come in integer power of 2, e.g. 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexers.
16-to-1 multiplexer
Fig 3.15 shows a 16-to-1 multiplexer. The input bits are labeled D0 to D15. Only one of these is transmitted
to the output. It depends on the value of ABCD, the control input. For instance, when ABCD= 0000
the upper AND gate is enabled while all other AND gates are disabled. Therefore, data bit D0 is transmitted
to the output, giving Y=D0. If D0 is low, Y is low; if D0 is high, Y is high. The output can be written as
Y= A'B'C'D'.D0 + A'B'C'D.D1 + A'B'CD'.D2 + ……… + ABCD'.D14 + ABCD.D15

74150
• The 74150 is a 16-to-1 TTL multiplexer. Pins 1 to 8 and 16 to 23 are for the input data bits D0 to D15.
Pins 11, 13, 14, 15 are for control bits ABCD. Pin 10 is the output pin and it equals to the complement of
the selected data bit.
• Pin 9 is for the STROBE (an input signal) that disables or enables the multiplexer.
• A low strobe enables the multiplexer, so that output Y equals the complement of the input data bit:
Y=D'n where n is the decimal equivalent of ABCD. Fig 3.3 shows the pinout diagram of IC
• On the other hand, a high strobe disables the multiplexer and forces the output into the high state. With a
high strobe, the value of ABCD doesn't matter.
Fig 3.15 16-to-1 multiplexer

Multiplexer logic
• Two standard methods for implementing a truth table are SOP and POS solutions. The third method is the
multiplexer solution. For example to use a 74150 to implement Table 3.1, complement each Y output to get
the corresponding data input.
D0=1'=0
D1=0'=1
….
….
D15=1'=0
• D0 is grounded, D1 is connected to +5V, D2 is grounded and so forth (Fig 3.16).
When ABCD=0000, D0 is the selected input. Since D0 is low, Y is high.
When ABCD=0001, D1 is the selected input. Since D1 is high, Y is low.
•The multiplexer is active (enabled) when the STROBE is low and inactive (disabled) when it is high.
Because of this, the STROBE is called an active low signal; it causes something to happen when it is low
rather than when it is high.
Fig 3.16 74150 IC and Truth Table

Multiplexer as Universal Logic Circuit
Multiplexer is called as universal logic circuit because a 2n-to-1 multiplexer can be used as a design
solution for any 'n' variable truth table.
We can implement the Truth Fig 3.17 using 8-to-1 multiplexer in following way:
Let's consider A, B and C variables to be fed as select inputs. The fourth variable D then has to be present as
data input. Here, EVM method can be used to convert 4-variable truth table into 3- variable truth table.

Fig 3.17 Multiplexer as Universal Logic Circuit and Truth Table

Nibble Multiplexers
Sometimes, we want to select 1 of two input nibbles. In this case, we can use a nibble multiplexer.
The control signal labeled SELECT determines which input nibble is transmitted to output (Fig: 3.18).
When SELECT=low, the four NAND gates on the left are activated. Therefore
Y3Y2Y1Y0=A3A2A1A0
When SELECT=high, the four NAND gates on the right are activated.
Therefore Y3Y2Y1Y0=B3B2B1B0
Fig 3.18 Nibble Multiplexer
Demultiplexers
It is a digital circuit with 1 input and many outputs (Fig: 3.19). By applying control signals, we can steer the
input signal to one of the output lines. The circuit has 1 input signal, m control or select signals and n output
signals where n ≤ 2m.
1:16 Demultiplexer
The input data bit (D) is transmitted to the data bit of output lines depending on the value of ABCD, the
control input. When ABCD=0000, the upper AND gate is enabled while other AND gates are disabled.
Therefore, data bit D is transmitted only to the Y0 output, giving Y0=D. If D=low, Y0=low. If D=high,
Y0=high. If the control nibble is changed to ABCD=1111, all gates are disabled except the bottom AND
gate. Then, D is transmitted only to the Y15 output and Y15=D.
Fig 3.19 Demultiplexer Circuit Diagram and Truth Table

The 74154
74154 is a 1-to-16 demultiplexer. Pin 18 is for the input DATA D. Pins 20 to 23 are control bits ABCD.
Pins 1 to 11 and 13 to 17 are for output bits Y0 to Y15. Pin 19 for STROBE, it is an active low input. Pin 24
for VCC and pin 12 for ground. STROBE must be low to activate the 74154. When the STROBE is low the
control input ABCD determines which output lines are low when the DATA input is low. When the DATA
input is high, all output lines are high. When STROBE is high, all output lines are high (Fig 3.20).

Fig 3.20 74154 is a 1-to-16 demultiplexer

Decoders
• It is a multiple-input, multiple-output logic circuit which converts coded inputs into coded outputs, where
the input and output codes are different (Figure: 3.10). It is similar to a demultiplexer with one exception
that there is no data input. The only inputs are the control bits.
1-of-16 Decoder
• 1-of-16 decoder is called so because only 1 of the 16 output lines is high.
• For instance, when ABCD=0001, only the Y1 AND gate has all inputs high, therefore only the Y1 output
is high. If ABCD=0100, only the Y4 AND gate has all inputs high, as a result Y4=high. For all
combinations, the subscript of the high output always equals the decimal equivalent of ABCD. Hence this
circuit is called as binary-to-decimal decoder.
IC 74154 is called a decoder-demultiplexer, because it can be used either as a decoder or as a demultiplexer.
To use this IC as decoder, we have to ground the DATA and STROBE inputs as shown in fig 3.11. Then,
the selected output line is in the low state. This is why bubbles are shown on the output lines. It means the
output line is low when it is active or selected. For instance, if the binary input is
ABCD= 0111
Then the Y7 output is low, while all other- outputs are high.
Fig. 3.21 1-of-16 Decoder

BCD to Decimal Decoders
BCD- Binary Coded Decimal. The BCD code expresses each digit in a decimal number by its nibble
equivalent. Example decimal 429 in BCD is represented as 0100 0010 1001. Some early computers
processed BCD numbers. The decimal numbers were changed into BCD numbers, which the computer then
added, subtracted, etc. The final answer was converted from BCD back to decimal numbers. BCD digits are
from 0000 to 1001. All combinations above this (1010 to 1111) cannot exist in BCD. BCD- to Decimal
Decoder
The circuit of Fig 3.12 is called a 1-to-10 decoder because only 1 of the 10 output lines is high. For instance
when ABCD=0011, only the Y3 AND gate has all high inputs; therefore, only the Y3 output is high. If
ABCD= 1000, then only Y8 output is high and similar for rest of the ABCD combinations. The subscript of
the high output always equals the decimal equivalent of the input BCD digit. Hence the circuit is also called
as BCD-to-decimal converter

Fig. 3.22 BCD to Decimal Decoders

The 7445
TTL IC 7445 is available to convert BCD to decimal as shown in fig 3.33. Pin 16 connects to supply voltage
VCC and pin 8 is grounded. Pins 12 to 15 are for the BCD input (ABCD), while pins 1 to 7 and 9 to 11 are
for the outputs. Here the active output line is in the low state. All the other output lines are in the high
state as shown in table 3.3. Invalid BCD input(1010 to 1111) forces all output lines into the high state.
Fig. 3.23 TTL IC 7445

Seven Segment Decoders

LED emits radiation when forward biased. This is because when free electrons recombine with holes near the
junction. As the free electrons fall from a higher energy level to a lower one, they give up energy in the form
of heat and light. The elements like gallium, arsenic, and phosphorus can emit red, green, yellow, blue, orange
and infrared (invisible) light.
Seven Segment Indicator
Fig 3.14 shows a seven segment indicator, i.e seven LEDs labeled a through g. By forward-biasing different
LEDs we can display digits from 0 to 9.
For example, to display 0, we need to light up segments a, b, c, d, e, and f.
To display 5, we need to light up segments a, c, d, f, and g.
Seven segment indicators may be the common-anode type where all anodes are connected together as in fig
3.15a or the common-cathode type where all cathodes are connected together as in fig 3.15b. With common
anode type, a current limiting resistor has to be connected between each LED and ground. The size of the
resistor determines how many current flows through the LED.
The typical LED current is between 1 and 50 mA. The common cathode type uses a current limiting resistor
between each LED and +VCC.
Fig. 3.24 Seven Segment Decoders

The 7446
A seven-segment decoder-driver is an IC decoder that can be used to drive a seven-segment indicator. There
are two types of decoder drivers. Both has 4 input pins(the BCD input) and 7 output pins(the a through g
segments)
7446- common- anode indicator
Fig 3.16a shows a 7446 driving a common anode indicator. Logic circuits inside 7446 convert the BCD
input to the required output. For instance, if the BCD input is 0111, the internal logic of 7446 will force
LEDs a, b and c to conduct. As a result digit 7 appears on seven segment indicator. External current limiting
resistor are used.
7448-Common- cathode indicator

Fig 3.16b shows 7448 driving a common cathode indicator. The internal logic converts the BCD input to the
required output. When the BCD input is 0100, the internal logic forces the LEDs b, c, f, and g to conduct.
The seven segment indicator then displays a 4. 7448 has its own current limiting resistor on the chip.
Fig. 3.25 7448-Common- cathode indicator

Encoders
• It converts an active input signal into a coded signal.
• There are ‘n’ input lines, only one of which is active. Internal logic within the encoder converts this active
input to a coded binary output with ‘m’ bits. (fig 3.17)
Decimal to BCD Encoders
• The switches are push-button switches like those of a pocket calculator (Figure: 3.18).
• When button 3 is pressed, the C and D OR gates have high inputs, therefore the output is
ABCD=0011
If button 5 is pressed, output ABCD=0101
If button 9 is pressed, output ABCD=1001

Fig. 3.26 Decimal to BCD Encoders

The 74147
Fig 3.37a shows the pinout diagram for 74147, a decimal to BCD encoder. The decimal input X1 to
X9, connect to pins 1 to 5, and 10 to 13. The BCD output comes from pins 14, 6, 7, and 9. Pin 16 is for
the supply voltage, and pin 8 is grounded. The label NC on pin 15 means no connection.
Fig 3.19b shows how to draw a 74147. The bubbles indicate active-low inputs and outputs. Table 3.4 gives
the truth table. When all X inputs are high, all outputs are high. When X9 is low, the ABCD output is
LHHL(complement of 1001 (9)). When X8 is the only low input, ABCD is LHHH etc.
Fig. 3.27 pinout diagram for 74147

The 74147 is called a priority encoder because it gives priority to the highest-order input. If all inputs X1
through X9 are low, highest of these, X9 has got highest priority and it is encoded. When X9 is high, X8 has
got next priority; it is encoded, if it is low.
Exclusive-OR Gates
This has a high output only when an odd number of inputs is high (Figure: 3.20).
• The upper AND gate forms the product A'B, while the lower one produces AB'. Therefore, the output of the
OR gate is Y=A'B+AB'
• This gate always produces an output 1 only when n-bit input has an odd number of 1s
Fig. 3.28 Exclusive-OR

Parity Generators and Checkers
• Even parity means an n-bit input has an even number of 1s. For e.g. 110011 has even parity because it
contains four 1s.
• Odd parity means an n-bit input has an odd number of 1s. For e.g. 110001 have odd parity because it
contains three 1s.
• The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that
checks the parity in the receiver is called a parity checker.
Parity Checker
• XOR gates can be used for checking the parity of a binary number because they produce an output 1 when
the input has an odd number of 1s. Therefore, an even parity input to an exclusive OR gate produces a low
output, while an odd parity input produces a high output
Fig. 3.29 Parity Checker

Parity Generation
• In a computer, a binary number may represent an instruction that tells the computer to add, subtract etc. In
this case, you sometimes will see an extra bit added to the original binary number to produce a new binary
number with even or odd parity (Figure 4.34).
• Suppose X7X6X5X4 X3X2X1X0=0100 0001.Then, the number has even parity, which means the XOR
gate produces an output 0. Because of the inverter X8=1 and the final 9-bit output is 1 0100 0001.

• If X7X6X5X4 X3X2X1X0=0110 0001. Now, this has odd parity. In this case, the XOR gate produces an
output 1. But the inverter produces a 0, so that the final 9-bit output is 0 0110 0001. Again, the final output
has odd parity.
• If the 8-bit input has even parity, a 1 comes out of the inverter to produce a final output with odd parity.
On the other hand, if the 8-bit input has odd parity, a 0 comes out of the inverter, and the final 9-bit output
again has odd parity.
Fig. 3.30 Parity Generation

Magnitude Comparator
Magnitude comparator compares magnitude of two n-bit numbers, say X & Y and activates one of the three
outputs: X > Y, X = Y, and X < Y. The logic diagram of n-bit comparator is as shown below:
Fig. 3.31 Magnitude Comparator

1-bit Magnitude Comparator
The truth table and logic circuit of 1-bit magnitude comparator is as shown below:
Fig. 3.32 1-bit Magnitude Comparator

Let G, L, E stands for Greater than, less than and equal to respectively.
The output expressions are:

(X>Y) = G= XY’
(X=Y) = X’Y’ + XY = (X’Y + XY’)’ = (G + L)’
(X<Y) = L= X’Y
2-bit Magnitude Comparator
The truth table of 2-bit magnitude comparator is as shown below:
Comparator Design
The generic procedure for 2-bit comparator design is given below. This can be easily extended to make any
n-bit magnitude comparator
• Define
1. Bit-wise greater than terms (G):
G1 = X1Y1’ G0 = X0Y0’
2. Bit-wise less than terms (L):
L1 = X1’Y1 L0 = X0’Y0
3. Bit-wise equality terms (E):
E1 = (G1 + L1)’ E0 = (G0 + L0)’
From the definitions of G, L and E, we have 2-bit comparator output as follows:

n-bit Magnitude Comparator

For any two n-bit numbers X: Xn-1 Xn-2….X0 and Y:Yn-1 Yn-2…Y0. The output expressions are listed
below:
The 7485 IC
It is a 4-bit magnitude comparator TTL IC. The functional diagram is as shown below:
Fig. 3.33 4-bit magnitude comparator

8-bit Comparator
The 8-bit comparator is realized using two 7485 ICs as shown below (Fig 3.34):

Fig. 3.34
Programmable Logic Devices (PLDs)

The block diagrams of the three PLDs are as shown below (Fig 3.35):
Fig. 3.35 Programmable Logic Devices

Programmable Array Logic
Programmable Array Logic (PAL) is a programmable array of logic gates on a single chip. It has a
programmable AND array and a fixed OR array. The x’s on the input side are fusible links, while the solid
black bullets on the output side are fixed connections. The structure of PAL is as shown below:

Fig. 3.36 Programmable Array Logic
Programming a PAL
We can burn in the desired fundamental products, which are then ORed by the fixed output connections.
Suppose we want to generate the following Boolean functions:
Y3 = ̅B D̅ + ̅BC ̅+ BCD̅ + ABC ̅
Y2 = ̅BC ̅+ ̅BCD + ABCD
Y1= ̅B ̅+ ̅BC+A ̅C+AB ̅
Y0 = ABCD
To start with ̅B ̅D, on the top input line, remove the first x, the fourth x, the fifth x, and the eight x. Then the
top AND gate has an output of ̅B ̅D.
By removing the xs on the next three input lines, we can make the top four AND gates produce the
fundamental products of Y3. The fixed OR connections on the output side imply that the first OR gate
produces an output of Y3 = B̅ D̅ + ̅BC ̅+ ̅BCD + ABC ̅
Similarly we can get solution for others. The following figure gives the solution

Fig. 3.37 Programming a PAL

PAL ICs
Some important PAL IC types are listed below:
PAL - Pros and Cons

PALs are not a universal logic solution. Only some of the fundamental products can be generated and ORed
at the final outputs. But PALs have enough flexibility to produce all kinds of complicated logic functions.
PALs have the advantage of 16 inputs compared to the typical limit of 8 inputs for PROM.
Programmable Logic Arrays
In Programmable Logic Arrays (PLAs) both the AND array and the OR array are programmable.
The structure of Programmable Logic Array (PLA) is as shown below:

Fig. 3.38 Programmable Logic Arrays

7 segment decoder using PLA
The PLA must have 4 inputs to represent the 10 decimal numbers. There must be 7 outputs (abcdefg), 1
output to drive each of the 7-segments of the indicator. The input AND-gate array is programmed such that
each AND gate decodes one of the decimal numbers.
For example, when ABCD = LHLH, segments afgcd are illuminated to display number 5.
Fig. 3.39 7 segment decoder using PLA

Arithmetic Building Blocks

Half-Adder
Half adder performs binary addition. It adds two bits. The following figure shows the circuit of half adder.
The output of EX-OR gate is called the SUM, while the output of AND gate is the CARRY.
The expression for SUM = B̅ + A ̅= A ⊕B
CARRY = AB
Fig. 3.40 Half-Adder

Full-Adder
Full adder can add three bits at a time (Fig 3.41). The third bit is a carry from a lower column.
Expressions:
Carry = AB+BC+AC
Sum = A ⊕B ⊕C
General representation of full-adder which adds i-th bit Ai and Bi of two numbers A and B and takes carry
from (i-1)th bit could be represented as below:
Ci = AiBi + BiCi-1 + AiCi-1
Ci = AiBi + (Ai + Bi)Ci-1
Si = Ai ⊕Bi ⊕Ci-1
Fig. 3.41 Full-Adder

Controlled Inverter
Fig. 3.42
As represented in Fig 3.42 When Invert = Low, output =
input Example: input = A7…..A0 = 0110 1110
output =Y7…..Y0= 0110 1110
Invert = High, output = 1’s Complement of the input
Example: input = A7…..A0 = 0110 1110
output =Y7…..Y0 = 1001 0001
Arithmetic Logic Unit
Arithmetic Logic Unit, called as ALU is multifunctional device that can perform both arithmetic and logic
function. ALU is an integral part of central processing unit or CPU of a computer. As a arithmetic unit it
performs addition, subtraction, increment, decrement operations etc. As logic unit it performs AND, OR,
NOT, EX-OR and many other complex logic functions. It has PRESET option, invoking which all function
outputs are made 1 and CLEAR option which makes all output as 0’s.
A mode selector input (M) decides whether ALU perform a logic operation or an arithmetic operation. In
each mode different functions are chosen by appropriately activating a set of selection inputs.
IC 74181 (Fig 3.43) is a 4-bit ALU that can generate 16 different kinds of outputs in each mode selected by
four selection inputs S3, S2, S1, S0. Note that carry is inhibited for M=1 mode. The functional diagram of
this IC with pin numbers and corresponding truth table is shown below,
Fig. 3.43 Arithmetic Logic Unit

Example 1:
To perform LOIGCAL AND operation
1. Choose M=1 mode
2. Select appropriate input A3, A2, A1, A0=1101 and B3, B2, B1, B0= 0111
3. Make S3, S2, S1, S0 = 1011 (It performs logical AND operation)
4. The output F3, F2, F1, F1= 0101
Example 2:
To perform ARITHMETIC ADDITION operation
1. Choose M=1 mode
2. Select Cin (active low pin) = 1
3. Select appropriate input A3, A2, A1, A0=0110 and B3, B2, B1, B0= 0100
4. Make S3, S2, S1, S0 = 1001 (It performs addition operation)
5. The output F3, F2, F1, F1= 1010
Three State Buffers

A gate output can only be connected to a limited number of other device inputs without degrading the
performance of a digital system. A simple buffer may be used to increase the driving capability of a gate
output. The following Fig 3.44 shows a buffer connected between a gate output and several gate inputs.
Because no bubble is present at the buffer output, this is a non-inverting buffer, and the logic values of the
buffer input and output are the same, that is, F = C.

Fig. 3.44 Circuit diagram Three State Buffer

Normally, a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices
are directly connected to each other. Use of three-state logic permits the outputs of two or more gates or
other logic devices to be connected together. The following Figure shows a three-state buffer and its logical
equivalent.
Fig. 3.45 Working of Buffer
When the enable input B is 1, the output C equals A; when B is 0, the output C acts like an open circuit (Fig
3.45). In other words, when B is 0, the output C is effectively disconnected from the buffer output so that no
current can flow. This is often referred to as a Hi-Z (high-impedance) state of the output because the circuit
offers a very high resistance or impedance to the flow of current. Three-state buffers are also called tri-state
buffers. The following Fig 3.46 shows the truth tables for four types of three-state buffers.
Fig. 3.46 truth tables for four types of three-state buffers

In Figures (a) and (b), the enable input B is not inverted, so the buffer output is enabled when B = 1 and disabled
when B = 0. That is, the buffer operates normally when B = 1, and the buffer output is effectively an open circuit
when B = 0. We use the symbol Z to represent this high-impedance state. In Figure (b), the buffer

output is inverted so that C = A’ when the buffer is enabled. The buffers in Figures (c) and (d) operate the
same as in (a) and (b) except that the enable input is inverted, so the buffer is enabled when B = 0. In the
following Figure, the outputs of two three-state buffers are tied together. When B = 0, the top buffer is
enabled, so that D = A; when B = 1, the lower buffer is enabled, so that D = C Fig 3.47. Therefore, = ′ + .
This is logically equivalent to using a 2-to-1 multiplexer to select the A input when B = 0 and the C input
when B = 1.
Fig. 3.47 Working of Buffer

When we connect two three-state buffer outputs together, as shown in the following Figure, if one of the
buffers is disabled (output = Z), the combined output F is the same as the other buffer output. If both buffers
are disabled, the output is Z. If both buffers are enabled, a conflict can occur. If A = 0 and C = 1, we do not
know what the hardware will do, so the F output is unknown (X). If one of the buffer inputs is unknown, the
F output will also be unknown. The table in the following Figure summarizes the operation of the circuit. S1
and S2 represent the outputs the two buffers would have if they were not connected together. When a bus is
driven by three-state buffers, we call it a three-state bus. The signals on this bus can have values of 0, 1, Z,
and perhaps X.
Fig. 3.48 summary the operation of the circuit

A multiplexer may be used to select one of several sources to drive a device input. For example, if an adder
input must come from four different sources; a 4-to-1 MUX may be used to select one of the four sources
(Fig 3.49). An alternative is to set up a three-state bus, using three-state buffers to select one of the sources
(see the following Figure). In this circuit, each buffer symbol actually represents four three-state buffers that
have a common enable signal.
Fig. 3.49 4-to-1 MUX may be used to select one of the four sources

Integrated circuits are often designed using bi-directional pins for input and output. Bi-directional means
that the same pin can be used as an input pin and as an output pin, but not both at the same time as depicted
in Fig 3.50. To accomplish this, the circuit output is connected to the pin through a three-state buffer, as
shown in the following Figure. When the buffer is enabled, the pin is driven with the output signal. When
the buffer is disabled, an external source can drive the input pin.
Fig. 3.50 Bi-directional Input

Module-3 Combinational Circuits

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Module-3 Combinational Circuits

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Rashtreeya Sikshana Samithi Trust

RV Institute of Technology and Management®

JP Nagar, Bengaluru – 560076

Department of Computer Science and Engineering

Course Name: Analog and Digital Electronics

Dr. Niharika P. Kumar

Review of Combinational Circuit Design

Design of Circuits with Limited Gate Fan-In

III- Semester, Analog and Digital Electronics (18CS33) Page 2 of 33

Fig. 3.1 K Map for Example 1 Problem

Fig. 3.2 Circuit Diagram for Example 1

Fig. 3.3 K Map for Example 2 Problem

III- Semester, Analog and Digital Electronics (18CS33) Page 3 of 33

Fig. 3.4 Circuit Diagram for Example

Fig 3.6 output of gate G2 changes 20 ns after G1 changes

III- Semester, Analog and Digital Electronics (18CS33) Page 4 of 33

Timing diagram with addition delay element is represented in Fig 3.7

Fig 3.7 Timing diagram with addition delay element

Hazards in combinational Logic

III- Semester, Analog and Digital Electronics (18CS33) Page 5 of 33

Fig 3.8 Static -1 Hazard

Fig 3.9 Detection and Removal of Static-1 Hazard

III- Semester, Analog and Digital Electronics (18CS33) Page 6 of 33

Fig 3.10 Static 0 Hazard

Fig 3.11 Static 0 Hazard Cover

2. Plot each term on the map and loop it.

Fig 3.12 Simulation and Testing of logic Circuits

III- Semester, Analog and Digital Electronics (18CS33) Page 8 of 33

Fig 3.13 Debug the circuit

Y= A'B'C'D'.D0 + A'B'C'D.D1 + A'B'CD'.D2 + ……… + ABCD'.D14 + ABCD.D15

Fig 3.15 16-to-1 multiplexer

III- Semester, Analog and Digital Electronics (18CS33) Page 10 of 33

Fig 3.16 74150 IC and Truth Table

III- Semester, Analog and Digital Electronics (18CS33) Page 11 of 33

Fig 3.17 Multiplexer as Universal Logic Circuit and Truth Table

Fig 3.18 Nibble Multiplexer

Fig 3.19 Demultiplexer Circuit Diagram and Truth Table

III- Semester, Analog and Digital Electronics (18CS33) Page 13 of 33

Fig 3.20 74154 is a 1-to-16 demultiplexer

Fig. 3.21 1-of-16 Decoder

III- Semester, Analog and Digital Electronics (18CS33) Page 15 of 33

Fig. 3.22 BCD to Decimal Decoders

Fig. 3.23 TTL IC 7445

III- Semester, Analog and Digital Electronics (18CS33) Page 16 of 33

Fig. 3.24 Seven Segment Decoders

III- Semester, Analog and Digital Electronics (18CS33) Page 17 of 33

Fig. 3.25 7448-Common- cathode indicator

III- Semester, Analog and Digital Electronics (18CS33) Page 18 of 33

Fig. 3.26 Decimal to BCD Encoders

Fig. 3.27 pinout diagram for 74147

III- Semester, Analog and Digital Electronics (18CS33) Page 19 of 33

Fig. 3.28 Exclusive-OR

Fig. 3.29 Parity Checker

III- Semester, Analog and Digital Electronics (18CS33) Page 20 of 33

Fig. 3.30 Parity Generation

Fig. 3.31 Magnitude Comparator

Fig. 3.32 1-bit Magnitude Comparator

The output expressions are:

III- Semester, Analog and Digital Electronics (18CS33) Page 22 of 33

n-bit Magnitude Comparator

Fig. 3.33 4-bit magnitude comparator

III- Semester, Analog and Digital Electronics (18CS33) Page 23 of 33

Programmable Logic Devices (PLDs)

Fig. 3.35 Programmable Logic Devices