VHDL Operators

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The operators provided by VHDL can be classified in the following main categories.

 Assignment Operators
 Logical Operators
 Relational Operators
 Arithmetic Operators
 Concatenation Operator

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Assignment Operators

Operator "≔"

We use operator "≔" for either initial value assignment or to assign a value to a variable,
constant or generic.

Note that "≔" is used for signal objects only for initial value assignment. It is not used for
signal objects in any other cases.

Example-1.16:

signal my_signal: integer≔10; -- Initial value assignment

my_signal<=30; -- Value assignment

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Example-1.17:

variable my_signal: integer≔10; -- Initial value assignment

my_signal:=40; -- Value assignment

Example-1.18:

constant my_number: natural≔214; -- Initial value assignment

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Operator "<="

We use the operator "<=" to assign a value to a signal object.

Example-1.19:

signal my_signal: bit_vector(3 downto 0)≔"10011"; -- Initial value

assignment

my_signal<= "11011"; -- Value assignment

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Operator "=>" and "others" keyword

We use operator "=>" to assign values to vector elements. The operator "=>" is usually
employed with the reserved word others which indicates the index values of the unassigned
vector elements.

Example-1.20: After the program line

signal x_vec: std_logic_vector(5 downto 1):=(4|3=>'1', others=>'0');

we have x_vec="01100", and after the line

x_vec<=(1 to 3=>'1', others=>'0');

we have x_vec="00111",

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Example-1.21: After the program line

variable x_vec: std_logic_vector(0 to 10):=(1|3|5=>'1', 2=>'Z', others=>'0');

we have x_vec="01Z10100000", and after the line

x_vec:=(1 to 5=>'0', others=>'Z');

we have x_vec="Z00000ZZZZZ",

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 Logical Operators and Shift Operators

The logical operators are used for data types bit, std_logic, std_logic_vector, std_ulogic,
std_ulogic_vector, and Boolean.

Logical operators are used for the implementation combinational logic circuits. The logical
operators and shift operators can be summarized as in Table 1.3.

Table 1.3 Logical and shift operators.

Logical Operators and, or, nand, nor, xor, xnor, not

Shift Operators sll, srl, sla, sra, rol, ror

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Shift Operators

Let’s briefly explain the logical shift operators briefly.

SLL: Shift Left Logical

The bits are shifted to the left and new positions are filled by zeros.

Example-1.22: If
𝑥 <= ′10101111
then
𝑦 <= 𝑥 𝐬𝐥𝐥 2
produces
𝑦 <= ′10111100′ .

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SLA: Shift Left Arithmetic

The bits are shifted to the left and new positions are filled by the value of the rightmost
bit.

Example-1.23: If
𝑥 <= ′11111110′
then
𝑦 <= 𝑥 𝐬𝐥𝐚 3
produces
𝑦 <= ′11110000′ .

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SRL: Shift Right Logical

The bits are shifted to the right and new positions are filled by zeros.

Example-1.24: If

𝑥 <= ′10101111′

then

𝑦 <= 𝑥 𝐬𝐫𝐥 2

produces

𝑦 <= ′00101011′ .

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SRA: Shift Right Arithmetic

The bits are shifted to the right and new positions are filled by the value of the leftmost bit.

Example-1.25: If

𝑥 <= ′01111111′
then
𝑦 <= 𝑥 𝐬𝐫𝐚 3
produces
𝑦 <= ′00001111′ .

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ROL: Rotate Left

The bits are shifted towards left, and the new positions on the right are filled with the bits
dropped from the left edge.

Example-1.26: If

𝑥 <= ′01111111′
then
𝑦 <= 𝑥 𝐫𝐨𝐥 3
produces
𝑦 <= ′11111011′ .

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ROR: Rotate Right

The bits are shifted towards right, and the new positions on the left are filled with the bits
dropped from the right edge.

Example-1.27: If
𝑥 <= ′111111000′
then
𝑦 <= 𝑥 𝐫𝐨𝐫 3
produces
𝑦 <= ′000111111′ .

Note: Multiplying an unsigned integer by two is the same as shifting the number to the left
by one bit. In a similar manner, dividing an unsigned integer by two is the same as shifting
the number to the right by one bit.
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Example-1.28: Write a VHDL program described as follows. The program inputs an 8-bit
number. Let’s denote this number by 𝑥. The program sends the numbers are 𝑦1 = 24 × 𝑥, 𝑦2 =
2−3 × 𝑥 to its ports.

Solution-1.28: With the given information, we can write the entity part of the program as in
PR 1.96.
entity power_two_operations is
port( inp: in bit_vector(7 downto 0);
outp1: bit_vector(7 downto 0);
outp2: bit_vector(7 downto 0) );
end power_two_operations;
PR 1.96 Program 1.96.

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The operations 𝑦1 = 24 × 𝑥, 𝑦2 = 2−3 × 𝑥 can be achieved using the shift operators shl and
shr as in PR 1.97.

architecture logic_flow of power_two_operations is

begin
outp1<=x sll 4;
outp2<=x srl 3;
end logic_flow;
PR 1.97 Program 1.97.

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Relational Operators

Relational operators are used for comparison purposes. The following relational operators
can be used in VHDL programming are

= → 𝐸𝑞𝑢𝑎𝑙 𝑡𝑜
≠ → 𝑁𝑜𝑡 𝑒𝑞𝑢𝑎𝑙 𝑡𝑜
> → 𝐺𝑟𝑒𝑎𝑡𝑒𝑟 𝑡ℎ𝑎𝑛
< → 𝐿𝑒𝑠𝑠 𝑡ℎ𝑎𝑛
>= → 𝐺𝑟𝑒𝑎𝑡𝑒𝑟 𝑡ℎ𝑎𝑛 𝑜𝑟 𝑒𝑞𝑢𝑎𝑙 𝑡𝑜
<= → 𝐿𝑒𝑠𝑠 𝑡ℎ𝑎𝑛 𝑜𝑟 𝑒𝑞𝑢𝑎𝑙 𝑡𝑜.

The result of the relational operator is a Boolean value, i.e., true or false.

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