Perform mechanical and electrical testing after fabrication

Comparable to the frontend domain in software development

Front-end
Frontend design includes steps up to DFT insertion
Two Stages Deals with hidden design aspects like chip layout

Comparable to the backend domain in software development

Back-end
Backend design starts from the floor planning step

pin count

fuctionalities

Determine the specifications timing diagrams

power specifications
System Specification dimensions

Define operational condition

Create a system-level block diagram

Decompose functionalities into components/modules

Architecture Design
Define interconnect protocols

Written in hardware description languages like VHDL or Verilog

Break down complex module functionalities into Boolean equations

RTL Design
Register transfer level

Design Verify functions

Crucial step

Design Verification Carried out in parallel with RTL design step

UVM
Automated test bench
OVM

Convert RTL code into gate-level netlists

Wire
Does not delve into the specifics of how the design will be implemented
Register
Focuses on what the design should do without detailing how it will be implemented Converted into the physical components Standard Cell
Synthesis Gates
High-level description languages like Verilog or VHDL
MUX
Boolean equations, specifying logical relationships
Having I/O pins & interconnection b/w them is also synthesized
Truth tables, showing input-output mappings Can be expressed through various methods Behavioral Representation
Insert test circuits to detect post-manufacturing issues
Finite state machines, used for sequential behavior
Design for Testability
Algorithms written in standard programming languages (e.g., C, Java) DFT Insertion
Use scan chain techniques
Using Boolean equations to express logical relationships between inputs and outputs
Verify the correctness of netlists
Creating truth tables to document all possible input-output combinations Examples
If the Boolean equations of RTL code and netlists are the same, then netlist is correct
Employing finite state machines to represent sequential behavior Formal Verification
Flow Different from functional verification
t
Describes how the design is implemented, including components and their interconnec
ions Different Angles Block placement

Specifies the specific gates (AND, OR, etc.) used and their interconnections Gate-level representation Block placement
Structural Representation
Provides details on how transistors are connected to implement the design Transistor-level representation Planning different rooms for a house design partitioning
Can be represented at different levels of abstraction Floor Planning
p
Incorporates additional elements like resistors and capacitors, offering a more detailed pin placement
hysical view Circuit-level representation
Starting backend domain of ASIC design flow
Integrated circuits (chips)
Involves specifying the actual layout and placement of components Place standard cells within blocks efficiently.
Circuit boards (boards)
Standard cells are placed inside the blocks/partition created in pre-step
Cell Layout
sDeals with the concrete implementation of the design, considering physical component Physical Representation
Desi gn Rep res en tatio n Planning the interior of each room
ASIC Route the clock to different circuits/cells
Typically used in the manufacturing and fabrication stages of electronic components
Clock Tree Synthesis Optimize clock path length for timing constraints
Details how to move from high-level design to low-level implementation
Layout vs Schematic verifying that the geometry, layout matches schematic /netlist
Describes what the design is supposed to do at a high level Significance
Physical Verification Design Rule Check verifying that the design meets the constraints given by the foundry
Defines functionality without specifying implementation Purpose Behavioral Axis
Extracted RC value: calculate actual path delay of clock
Uses languages like Verilog, VHDL, or truth tables to convey behavior Examples
Static timing analysis
Details how the design is built and connected Significance Y Diagram Post Layout STA
Verify that timing constraints are met
Provides insights into internal structure and components. Purpose Structural Axis
Convert the design into GDSII files for manufacturing
Describes components and connections at different abstraction levels Examples
Graphical Database System for Information Interchange
Deals with the real-world, physical implementation Significance GDSII Creation
Tapeout
Essential for manufacturing and fabrication Purpose Physical Axis
Fabricate the chip in accordance with the required technology node
Specifies layout details, sizes, process layers, and geometries Examples
Perform mechanical and electrical testing after fabrication
Fabrication
Make silicon wafers from sand Silicon Wafer Production Entire process is complicated and comprises of many steps

Define patterns on wafers using masks Photolithography alidate the chip using FPGAs or other techniques after receiving it from the foundry

emove unwanted material from wafers Etching Carried out after receiving physical chip from foundry

Introduce impurities to change properties Ion Implantation Post Silicon Validation being validated against the system specification by using it in real scenario

Add thin layers of material Deposition Physical test bench Carry out this validation mainly using FPGAs
IC Man uf ac tu rin g Pro cess
Smooth wafer surfaces CMP (Chemical Mechanical Polishing) Intergrated circuit

Cut wafers into individual chips Dicing Signal processing units AI/ML
What ?
Encapsulate ICs in protective packages Packaging focus on particular task

Ensure ICs work correctly Testing higher design costs

Transistor invention (1947)

Create a connectivity list of the circuit Net-List Shift from vacuum tubes to solid-state devices
Decide where major blocks go on the silicon Floor Planning IC Discrete circuits with solid-state devices (1950s)
Assign locations to gates efficiently Placement History
Monolithic IC concept by Jack Kilby and Robert Noyce (1958)
Add clock signals to the circuit for timing control Clock Insertion Small Scale Integration (SSI) in the early 1960s
Ph ys ic al Des ig n Pr oc es s
onnect components using metal wires Routing Medium Scale Integration (MSI) in the late 1960s
VLSI
Modify design for easy manufacturing Design for Manufacturability Large Scale Integration (LSI) in the 1970s
Convert design into photomasks for manufacturing Tapeout and Mask Generation Very Large Scale Integration (VLSI) in the 1980s, with increasing transistor densities

Developed by Gateway Design in 1984 Transistor invention (1947)

IEEE 1364 Verilog Shift from vacuum tubes to solid-state devices
Maintained by Accellera Discrete circuits with solid-state devices (1950s)
Developed by the U.S. Department of Defense in 1983 Origin Monolithic IC concept by Jack Kilby and Robert Noyce (1958)
Hi sto ry
Verbose, text-based syntax with strong typing Syntax Small Scale Integration (SSI) in the early 1960s
Common in Europe and aerospace, often for safety-critical systems Usage Medium Scale Integration (MSI) in the late 1960s
VLSI
Used for both design and verification, but favored for verification Verification Large Scale Integration (LSI) in the 1970s
VHDL
Well-established, especially in Europe Industry Adoption Very Large Scale Integration (VLSI) in the 1980s, with increasing transistor densities
Strongly typed language, ensuring design accuracy
Languages Data converted to binary and process in binary
Supports concurrent and sequential programming

Rich library of predefined data types Main Features Switches are basic building blocks

Suitable for complex, safety-critical systems Sequential (with memory)

Types
Extensive support for design documentation and modeling Combinational (without memory)

An extension of Verilog, developed in the early 2000s Origin AND

Concise, C-like syntax Syntax OR

Popular in the semiconductor and EDA industries Usage NOT

Designed for verification, supports advanced methodologies like UVM Verification Logic Gates XOR
SystemVerilog Fu nd am en tal s of Digi tal Cir cu its
Commonly used in semiconductor design and verification Industry Adoption HDL (Har dw are Des cr ipt io n Lang u ag e) NOR

Combines hardware description with software constructs NAND

Building Blocks
Enhanced support for verification with built-in testing constructs XNOR

Integration of object-oriented programming (OOP) features Main Features D FFs

Interfaces and classes for more structured designs Flip Flops memory cells JK FFs

Strong support for constrained random testing in verification T FFs

describe the circuit behavior in a high-level manner Purpose All Gates and Flip Flops can be made from transistors

EDA tools are used to convert the written HDL program into a mask diagram used in th
e
fabrication process