WC1.

1 (Invited)
9:00 AM – 9:30 AM

Soft-decision FEC for 100 Gb/s DSP based Transmission

Takashi Mizuochi

Information Technology R&D Center, Mitsubishi Electric Corporation,

5-1-1 Ofuna, Kamakura, Kanagawa 247-8501, Japan, Mizuochi.Takashi@df.MitsubishiElectric.co.jp

Abstract — Recent progress in soft-decision based FECs for
100 Gb/s class optical communications is reviewed. High
speed 2-bit soft-decision LSI made with SiGe BiCMOS
technology is introduced. The implementation of soft-
decision based 100 Gb/s FEC is discussed.
I. INTRODUCTION
Very high-speed optical transport systems, e.g. 100 Gb/s, need
increasingly powerful but practical forward error correction
(FEC) to enhance the transmission range. Several types of
powerful FEC for use at 10 to 40 Gb/s have seen intensive
development. For example, the dual orthogonally interleaved
BCH coding of ITU-T G.975.1 shows a 6.9 dB Q limit at 10
Gb/s with 25% redundancy. A Block Turbo code (BTC) LSI
has been reported with a Q limit of 6.3 dB at 10 Gb/s [1]. OTN
compatible enhanced FEC LSI has been developed with a Q
limit of 9.1 dB at 43 Gb/s [2]. However, no FEC LSI applicable
to the 100 Gb/s region and showing comparable performance
Net coding gain – Bit rate product (Gb/s)
(defined in terms of a post-FEC BER of 10-13)
FEC BER of 10-13 and bit rate in Gb/s. The three sets of data
points represent the different FEC schemes: 1st generation FEC
using linear block codes represented by RS(255,239); 2nd gen.
concatenated codes; and 3rd gen. FEC based on soft decision
and iterative decoding. A clear trend can be seen in that an
improvement of 1.4 times has been achieved every year. This
improvement has been achieved not by FEC algorithm
improvements, but by LSI technology evolution. The red open
triangle at the top shows the research target for 100 Gb/s FEC.
In order to keep the 100 Gb/s BER the same as that of a
standard RS(255,239) FEC-based 40 Gb/s system with a Q-
limit of 11.2 dB, at least 4 dB (=10log10(100/40)) greater
coding gain (NCG > 9.8dB at post-FEC BER of 10-13) is
necessary. In order to realize such high coding gain, soft
decision would be necessary.
104
Shannon limit
(Soft decision, 25% redundancy) 100Gb/s (target)

has been seen yet. 100Gb/s

Soft decision decoding is a promising way to improve error 103
40Gb/s
RS(255,239)
correction capability. Most current FEC LSIs for optical 100Gb/s
communications use hard decision decoding. We have 10Gb/s 40Gb/s
developed 3-bit soft decision LSIs with a flush type 3-bit 102
analogue-to-digital converter (ADC) operating at 12.4 Gb/s, 2.5Gb/s 10Gb/s
using 0.18 μm SiGe BiCMOS with 120 GHz fT. Combining
with the BTC LSI yields a record Q-limit, but still at 12.4 Gb/s 101 2.5Gb/s

due to the difficulty in speeding up the soft decision LSI,

especially the high sensitivity ADC circuitry. Only a few fast 1st gen.
2nd gen.
ADCs have been reported to date, e.g. a 3-bit 40 Gsample/s 100 X1.4 every year
3rd gen.
flush type ADC in 0.12 μm SiGe BiCMOS [3], a 5-bit 22 Year
Gsample/s flush type ADC in 0.13 μm SiGe BiCMOS [4], and ‘86 ‘88 ‘90 ‘92 ‘94 ‘96 ‘98 ‘00 ‘02 ‘04 ‘06 ‘08 ‘10 ‘12 ‘14 ‘16 ‘18
a 24 Gsample/s 6-bit ADC in 90 nm CMOS using a time Fig. 1: Progress in FECs for optical communications
interleaved architecture [5]. However, no soft decision LSI
with an ADC operating at over 12.4 Gsample/s has been
reported to date. This is because the soft decision LSI needs not
only a fast ADC but also the follow-up functions, i.e. a fast
interface, a precision phase-locked loop, an M-bit encoder to
create the confidence bits, and a fast deserializer.
In this paper, we review the recent progress in FECs for
optical communications. We report a newly developed 2-bit
soft decision LSI operating at 32 Gsample/s. This is currently
[1 11]

[0 10]

[1 00]
[1 10]

[0 00]

[0 01]
[0 11]

[1 01]

the fastest soft decision LSI known to exist. A novel FEC

scheme and OTU4V framing structure based on the low-
density parity-check (LDPC) codes are introduced, with the "certainly 1" "certainly 0"
"very likely 0" "it could be 0"
potential to realize an NCG of higher than 9dB at 125.3 Gb/s
for optical transmission systems. The implementation of soft- Fig. 2: Soft decision
decision FEC for 100 Gb/s DSP based transmission is
discussed. III. SOFT DECISION FOR 100 GB/S FEC
Soft decision decoding is one of the most promising
II. ULTIMATE PERFORMANCE OF FEC technologies for 100 Gb/s FECs. Soft decision is performed by
Fig. 1 plots the progress in FECs for optical communication providing 2M-1 decision thresholds, M being the number of
systems over the past 20 years. The vertical axis shows the quantization bits as shown in Fig. 2. The difference in error
product of (linear) net coding gain defined in terms of a post- correction performance between hard and soft decision

978-1-4244-3914-0/09/$25.00 ©2009 IEEE 107

Authorized licensed use limited to: Renmin University. Downloaded on August 21,2023 at 13:30:07 UTC from IEEE Xplore. Restrictions apply.
 decoding with infinite quantization bits and near-infinite
redundancy is π/2: about 2 dB. With 25% redundancy, the
difference is about 1.5dB.
A higher-speed soft decision LSI was developed for LDPC
decoding employing the following approach: using M = 2
quantization bits for good FEC gain with practical circuit size;
operating at half-rate to relax the bandwidth requirement; and
using 0.13 μm SiGe BiCMOS technology with a transit
frequency fT of 200 GHz. Fig. 3 is a photograph of the 9.7 mm
x 6.9 mm chip, which consumes 14 W at +3.3 V. Since the chip
needs about 570 I/O pads including ground and power supply,
flip-chip bonding was used to mount the chip on the 30 mm x
29 mm x 2.15 mm custom BGA package. The LSI operates
well at 32 Gsample/s with 25 mV sensitivity [6].
Fig. 3: The 32 Gsample/s soft decision LSI chip
VI. FEC SCHEME FOR 100 GB/S TRANSMISSION
One potential candidate for the 100 Gb/s application is a 3rd
gen. low-density parity-check (LDPC) code FEC. LDPC codes
were intensively studied for optical fiber communications by
Djordjevic et al. [7]. We proposed a new LDPC algorithm, i.e.
the cyclic approximated δ-minimum algorithm, in order to
reduce the circuit complexity of the decoder to enable 100 Gb/s
throughput [8]. The proposed algorithm can reduce the circuit
size to approximately 1/5 compared to the well known shuffled
belief propagation algorithm. The undesired error floor, which
often occurs with LDPC codes, needs to be eliminated for 100
Gb/s systems, for which we propose the concatenation of
LDPC and RS codes [9]. An LDPC code is used as the inner
code, with RS as the outer code.
Fig. 4: A part of FPGA board for emulating 125 Gb/s FEC
An OTU4V frame structure for 100GbE transport has been
proposed for the concatenated LDPC(9216,7936) +
RS(992,956) codes with soft decision decoding, taking the
restrictions of the OTN framing rules into account [10]. Fig. 4
shows the high speed FPGA board to emulate the proposed
FEC performance based on the OTU4V framing. The
encoder/decoder for the LDPC code is located at the front-end
as an inner coder. The RS encoder/decoder wraps the LDPC
code in an outer code. The three stages of interleaving and de-
interleaving are located between the OTU4V framer/deframer,
the RS encoder/decoder, and the LDPC encoder/decoder,
978-1-4244-3914-0/09/$25.00 ©2009 IEEE
Authorized licensed use limited to: Renmin University. Downloaded on August 21,2023 at 13:30:07 UTC from IEEE Xplore. Restrictions apply.
respectively. The input Optical Channel (OCh) is regenerated
and the 2-bit soft decision variables are input to the frame
alignment circuit. After de-scrambling and de-interleaving,
iterative decoding of the LDPC code is achieved.
V. FEC SCHEME FOR 100 GB/S TRANSMISSION
Fig. 5 shows a typical block diagram of a 100 Gb/s class line
card. The incoming 100GbE signal is wrapped by an OTU4V
framer followed by an FEC encoder and a symbol
mapper/driver, then the signal is multi-level modulated. The
received signal is mixed with a local oscillator in an optical
hybrid followed by balanced photo-detectors. The regenerated
electrical signals are quantized by four sets of 6-bit ADCs.
Each tributary is processed by the receiver DSP, the outputs
from which are processed into soft-outputs. In the FEC decoder,
a soft-in/soft-out processor and iterative decoder efficaciously
correct any errored bits. A critical issue is the interface of the
OTU4/FEC LSI. When 3-bit soft decision is used, four 125
Gb/s I/Os (500 Gb/s in total) become necessary. One solution
for reducing the I/O ports is integrating the FEC functionality
into the DSP. Nearly 100 million gates would be required.
Framer LSI DSP LSI
Mapper
I/Q
Pre-processor
OTU4V Mod.
Framer
100GbE
FEC 6-bit ADC
Encoder
/decoder 6-bit ADC Opt.
Soft Hyb.
6-bit ADC
6-bit ADC
125G x 4 = 500G
Fig. 5: Typical block diagram of a 100 Gb/s class line card
VI. CONCLUSION
We have reviewed soft-decision decoding based forward
error correction in optical communications. A newly
developed 2-bit soft decision LSI operating at 32
Gsample/s was introduced. A novel FEC scheme and
OTU4V framing structure based on low-density parity-
check (LDPC) codes were presented. The
implementation of soft-decision FEC for DSP based 100
Gb/s line card was discussed.
This work was in part supported by a project of the National Institute
of Information and Communications Technology, as part of a program
of the Ministry of Internal Affairs and Communications of Japan.
REFERENCES
[1] T. Mizuochi, J. Selected Topics in Quantum Electron. vol. 12, no. 4,
pp.544-553, (2006).
[2] Y. Kisaka, et al., OFC/NFOEC2007, OThL1, Anaheim, CA.
[3] W. Cheng, et al., ISSCC 2004, pp. 262 - 263, San Francisco.
[4] P. Schvan, et al., ISSCC 2006, pp. 2340 - 2349, San Francisco.
[5] P. Schvan, et al., ISSCC 2008, pp. 544 - 634, San Francisco.
[6] T. Kobayashi, et al., OFC/NFOEC2009, OWeE2, San Diego, CA.
[7] I. B. Djordjevic, et al., ECOC2008, P.4.04, Brussels, Belgium.
[8] Y. Miyata, et al., OFC/NFOEC2007, OWE5, Anaheim, CA.
[9] Y. Miyata, et al., OFC/NFOEC2008, OTuE4, San Diego, CA.
[10] Y. Miyata, et al., OFC/NFOEC2009, NThB2, San Diego, CA.
108