EEEE2046 – Practical Engineering Design Solutions and Project Development

Electronics Project – Project Week 4

1. Introduction to Electronics Project Week 4

Welcome back. This semester you will be designing and constructing a remote display board, based
on a Xilinx complex programmable logic device (CPLD). The remote display board is a self-contained
unit that receives the serial data from the STM32-NUCLEO-L476RG and displays the detected
speed on 2 seven segment LED displays. To reduce the development time, the digital circuit will be
implemented by a complex programmable logic device. This allows the design to be tested and
updated without changing the hardware.
The communication interface between the STM32-NUCLEO-L476RG and the CPLD will be done
using and industrial standard, RS485.

2. RS-485 communication standard

There are 4 main serial communication standards broadly used for computers and devices: RS232,
RS423, RS422 and RS485. The first and most popular one is RS232. It can connect one data
terminal equipment (DTE) to one data communication equipment (DCE) at a maximum speed of 20
kbps with a maximum cable length of 15m.
With the need of faster communication rates, over longer distances and the flexibility of creating a
network of devices without the need of using modems, the remaining three standards appeared
(RS423, RS422 and RS485). From these, RS485 is the most versatile communication standard in
the standard series defined by the Electronic Industries Alliance (EIA).
In contrast with RS232, RS485 signals are floating and each signal is transmitted over a Sig+ line
and a Sig- line. The RS485 receiver compares the voltage difference between both lines, instead of
the absolute voltage level on a signal line making it immune to ground loops which are a common
source of communication problems.

2.1. RS485 Transceiver

Although the STM32-NUCLEO-L476RG has several universal asynchronous receiver
transmitter (UART,USART) devices integrated onto the chip, it does not have the
necessary RS485 drivers. Since the specifications require the use of a RS485 link, an
RS485 transceiver will need to be added to the Semester 1 PCB providing the
necessary interface logic that is required. The transceiver we will be using is the Texas
Instruments SN65HVD1780P.
Figure 19 of the SN65HVD178x datasheet [1] provides an example of an RS-485
Transceiver with External Transient Protection. Please note that in your

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Electronics Project – Project Week 4

implementation you will not use the ESD Suppressors / TVS Diodes and therefore
only a 120 ohm resistor will be placed between wires A and B at both ends.

Figure 1: RS-485 Transceiver with External Transient Protection (figure 19 of the

SN65HVD178x datasheet)

2.2. 7 segment led display board

RS485 logic levels are not compatible with the CPLD (Xilinx XC2C64A chip) and like
the STM32-NUCLEO-L476RG, an RS485 transceiver chip will be required to convert
back the signal into a compatible standard.

3. Display board
The core of the remote display board is centred around the CPLD chip Xilinx XC2C64A [2]. This chip
will receive the serial data, decode it and provide the necessary logic to the seven segment led
displays [3]. There are several aspects to the CPLD design:
- What does the interface between the CPLD and the seven segment displays going to look
like? Do you need additional drivers? Xilinx have produced a helpful application note
providing details on LED interfacing [4].
- The Xilinx XC2C64A chip does not include an oscillator and so an external oscillator will be
required. A common crystal oscillator for UARTs is 1.8432MHz. In this project we will be
using a through hole 5v or 3.3V HCMOS QANTEK crystal oscillator [5]. Please do not solder
this directly to the Veroboard and use the socket provided. The Xilinx XC2C64A require
logical levels of 3v and therefore a vcc of 3.3v should be used in your design.

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Electronics Project – Project Week 4

1 - Not connected
7 – GND
8 – Output
14 – Vcc

Figure 2: HCMOS QANTEK crystal oscillator pinout.

4. Power supplies
The CPLD chip Xilinx XC2C64A has the following recommended operation conditions:
Symbol Description Minimum Maximum
VCC Supply voltage relative to ground 1.7V 1.9V
VCCIO Supply voltage for output drivers and JTAG 3.0V 3.6V
Table 1: Xilinx XC2C64A recommended operation conditions.

To improve switching speeds and power consumption, modern digital circuits have a variety of power
supplies. The specifications state, the board will only be supplied with a nominal 5V supply and so
an appropriate LDO regulator for required DC supply needs to be designed. To avoid delays, all
designs must use the Maxim Integrated Low Dropout (LDO) regulator MAX882 [6]. Placing a higher
voltage than expected on a IC power pin can damage the IC, the power supplies should be isolated
and tested from the rest of the remote display board circuit before they are connected.

5. Xilinx XC2C64A complex programmable logic device

The Xilinx XC2C64A complex programmable logic device (CPLD) is only packaged in surface mount
packages which are incompatible with the development of circuits using veroboard. To use the
device either a prototype PCB needs to be designed or a carrier PCB needs to be used. The carrier
printed circuit board (PCB) provided for the project is compatible with standard 0.1 inch veroboard,
and provides access to all the signal pins of the 44pin VQFP XC2C64A device. Please make sure
you do NOT solder the CPLD PCB to the Veroboard. Use the female headers provided. The
carrier assumes VAux, VCCIO1 and VCCIO2 are all connected to the same carrier supply pin
VCCIO(3V3). Each power pin of the XC2C64A device is decoupled with a 100nF capacitor. This
data sheet should be read in conjunction with the XC2C64A data sheet [2] and the corresponding
application notes.

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Electronics Project – Project Week 4

Figure 3: XILINX XC2C64A CARRIER PCB pin descriptions

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Electronics Project – Project Week 4

Tasks 9– 12: Project Weeks 4

Task 9.a: RS485 communications link (software)

This task involves configuring the STM32-NUCLEO-L476RG to output the calculated velocity via
UART/USART to be displayed on the 2 seven segment LED display. The calculated speed must still
be displayed on the LCD display.
Since only a single twisted pair is used for the communication between the STM32-NUCLEO-
L476RG and the remote display, the communication channel must operate in half-duplex mode. The
data direction of the Texas Instruments SN65HVD1780P chip can be controlled by the DE pin. This
can be set on the STM32-NUCLEO-L476RG IOC.
The baud rate of the serial line between the STM32-NUCLEO-L476RG and the remote display board
shall be 57600 Baud, no parity and one stop bit. The data shall be transmitted using 8 bits. The
speed shall be encoded as two 4-bit binary coded decimal numbers.

Suggested approach:
• Configure the UART for the above mentioned settings using the STM32Cube IDE IOC.
• Use an oscilloscope to monitor the output of the Tx pin. What are you expecting to see?
• As we are only sending data and not receiving, make sure you set the DE pin correctly.

Task 9.b: RS485 communications link (hardware)

Following the work undertaken in task 9a, you are required to develop a daughter board as described
in session 2.1 and build the display RS485 receiver.

Suggested approach:
• Read the Texas Instruments SN65HVD1780P datasheet [1].
• On the example application provided in the datasheet a circuit with transient protection is
presented. As we are not adding a transient protection in our system, the ESD
Suppressors / TVS Diodes are not required and only a 120 ohm resistor will be placed
between wires A and B at both ends.
• Build the display board receiver in one corner of the veroboard (Figure 4).
Task 10: Power supplies

The aim of this task is to build the required power supplies for the display board.

Suggested approach:
• Build the two power supplies in one corner of the veroboard (see Figure 4).
• All necessary information on how to set the power supply is available on the MAX882
data sheet [6].
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Electronics Project – Project Week 4

RS485
receiver

Oscillator
CPLD
carrier PCB

7 seg LED
display Power
supplies

Figure 4: Display board suggested layout – connections between the CPLD and 7 segment LED have been
covered to avoid using the same connections.

Task 11: External clock

This is a straightforward task. Make sure you connect the output of the oscillator into the right Xilinx
carrier PCB pin.

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Electronics Project – Project Week 4

Task 12: LED interfacing to the CPLD

The aim of this task is to develop the physical interface between the two 7 segment LED displays
and the CPLD. Please read the application note developed by Xilinx [4] on how to Drive LEDs
with Xilinx CPLDs.

Suggested approach:

• Read the application note developed by Xilinx [4].

• Decide what CPLD pin connections you are going to use to interface the LED display and
take note of them:
o Segment 1 (LS DIGIT):
Display Xilinx XC2C64A pin XILINX XC2C64A CARRIER PCB
segment pin
a
b
c
d
e
f
g

o Segment 2 (MS DIGIT):

Display Xilinx XC2C64A pin XILINX XC2C64A CARRIER PCB pin
segment
a
b
c
d
e
f
g

Task 13: Clock divider

The aim of this task is to divide the external 1.8432MHz clock (CLKEXT) and output an internal clock
(CLKINT) which is suitable to detect a 57600 baud serial signal. Before you design this block you
will need to decide the frequency of the internal clock.

Suggested approach:

• Revise “divide-by-2” counters.

• Build a test bench to test your schematic design.

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Electronics Project – Project Week 4

Task 14: BCD-7 segment decoder

The measured speed data is sent from the STM32-NUCLEO-L476RG as two 4-bit BCD digits
combined into one byte. To display these on the LEDs, the appropriate decoders need to be
designed.

Suggested approach:

• construct the truth table listing the 7 display input signals, decimal number and
corresponding 4 digit binary numbers;
• find the Boolean expressions of each output functions;
• Construct the Karnough’s map for each output term and then simplify them to obtain a
logic combination of inputs for each output;
• Draw a combinational logic circuit for each output signal.
• Make your schematic based on your logic circuit or write a VHDL using combinational
logic.

Remember to record all of your results and keep notes of the tests that you carry out.

References
[1] T. Instruments, “SN65HVD178x datasheet,” [Online].
Available: http://www.ti.com/lit/ds/symlink/sn65hvd1781.pdf. [Accessed 20 1 2019].
[2] Xilinx, “XC2C64A CoolRunner-II CPLD datasheet,” [Online].
Available: https://www.xilinx.com/support/documentation/data_sheets/ds311.pdf.
[Accessed 20 1 2019].
[3] Kingbright, “Kingbright - SA56-11SURKWA single digit numeric display,” [Online].
Available: www.kingbrightusa.com/images/catalog/SPEC/SA56-11SURKWA.pdf.
[Accessed 20 1 2019].
[4] Xilinx, “Driving LEDs with Xilinx CPLDs - XAPP805 (v1.0) April 8, 2005,” [Online].
Available: https://www.xilinx.com/support/documentation/application_notes/xapp805.pdf.
[Accessed 20 1 2019].
[5] Quantek, “QX14 Series - 14 pin Dual-in-Line HCMOS Clock Oscillator,” [Online].
Available: https://www.qantek.com/tl_files/products/oscillators/QX14.pdf.
[Accessed 20 1 2019].
[6] Maxim, “Maxim - Max882 5v-3.3v or adjustable 200mA linear regulator,” [Online].
Available: https://datasheets.maximintegrated.com/en/ds/MAX882-MAX884.pdf.
[Accessed 20 1 2019].