EC4068D- Analog MOS Integrated Circuits

Dhanaraj K. J.
Associate Professor
ECED, NIT Calicut

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 2
2  1 
I out   1  
W  2  K
 nCox   RS
 L N

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3
4
 The diode-connected device M5
provides a current path from VDD
through M3 and M1 to ground upon
start-up.
 Thus, M3 and M1, and hence M2 and
M4, cannot remain off.
 This technique is practical only if VTH1
+ VTH5 + |VTH3| < VDD and VGS1 + VTH5
+ |VGS3| > VDD, the latter to ensure
that M5 remains off after start-up.

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 Ideally, source/drain should end right at the edge of gate oxide.
 But actually it is not so, due to lateral diffusion
 Effective channel length L=Ld -2xd

Overlap Capacitance:
CGSO  CGDO  Cox xdW  CoW
xd  technology determined

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Channel Capacitance:

 It depends on the region of operation.

 All the electric field lines starting from
gate will terminate in bulk.

Cut off region:

 No channel exists. Hence total channel capacitance appears between

gate and body.

CGCB  CoxWL
 CGC  CoxWL
CGCS  CGCD  0

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Channel Capacitance:
Linear region:

 Channel exists between source and

drain.
 All the electric field lines starting from
gate will terminate at the channel.
 Body will be shielded from the gate and drain.

CGCB  0

1  CGC  CoxWL
CGCS  CGCD  CoxWL
2

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Channel Capacitance:
Saturation region:

 Channel exists between source and

drain, but more at the source side.
 All the electric field lines starting from
gate will terminate at the channel.

CGCB  0
CGCD  0
2
CGCS  CoxWL
3
2
 CGC  CoxWL
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Variation of gate-source and gate-drain capacitances versus VGS

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1. Razavi B. Design of Analog CMOS Integrated Circuits, 2001. New
York, NY: McGraw-Hill. 2017;587(589):83-90
2. P. Allen & D. Holberg, CMOS Analog Circuit Design, 3rd Edition,
Oxford University Press, 2013
3. Gray, Hurst, Lewis and Meyer, Analysis and Design of Analog
Integrated Circuits, , 5th Edition, Wiley India, 2011

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