SYNTHESIS

1. What are the different steps in synthesis?

Elaborate

Uniquify

Syn_generic

Syn_map

SYN_optimization

Syn_optimization -incremental

2. What are the inputs required to start synthesis?

ANS: RTL files which has the source code, .libs for hard macros, Standard cell libraries.
Constraints are required to fine tune the synthesis.

3. If you are given an RTL tag which is not getting linked properly, what
workarounds have you done?

ANS: If designer is there try to ask to fix it .If not hack the RTL, Fix the syntax mistakes, to
get it linked. Even unsynthesisable code can be present in the RTL; which gives Error in the
elaborate stage. Whatever changes we make in the RTL should be informed and get it
confirmed from the designer.

4. Can you keep proceeding if LINT Errors are present?

ANS: LINT Errors needs attention and Lint with small numbers have higher priority. It
needs fix from the designer. But for the time being, to keep going with synthesis, to generate
a netlist these can be suppressed.

5. How you can detect whether transparent latch is inferred while

elaboration?
ANS: We can turn on the variable "hdlin_check_no_latch", so that design compiler issues a
warning message, if transparent latches are inferred.

6. Which command do you use to get it compiled?

ANS: compile_ultra
7. What are the requisites for compile stage?

ANS: Fully elaborated database is the minimum requirement. Additional information for
compile is the constraints. Initial compile can be done without constraints, if they are not
ready. But this will take huge runtime.

8. What are the constraints?

(OR)

9. What are the different constraints needed for synthesis

ANS:
Design rule constraints: set_max_transition

set_max_capacitance

set_max_fanout

Design optimization constraints: create_clock

set_clock_latencey

set_propagated_clock

set_clock_uncertainty

set_clock_transition

set_input_delay

set_output_delay

set_max_area

10. Which design rule constraint will be given the maximum prior it by
design compiler?

ANS: max_transition

11. What are the different steps to optimize a timing path?

ANS: 1.Specify critical range-If no critical range is specified, design compiler works only
on the worst negative slack end point in each path group. i.e., it works only on WNS. But if
we specify a critical range say 0.5, then it works on all paths in that clock group with slack
below 0.5ns. i.e., it works to reduce total negative slack

2. Enable the boundary optimization - To enable more optimization either timing or area
across the boundaries of the blocks.
 3. Tighten the constraint - Either increases the clock frequency by 10% or increase the clock
uncertainty.

4. Give timing_effort high along with the compile_ultra command.

5. Remove the area constraints like set_max_area 0

6. Try with incremental compile. Since it goes through a different algorithm chances are
there to improve the timing.

7. If the timing critical path is Reg to Reg, then just do an incremental compile with putting
IO paths as false paths.

8. Enable registers retiming: Commands in the design compiler are optimise_register and
balance_register. The register retiming will change or optimise the register positions. It also
changes the register names or pins. Retiming can add/remove registers too.

12. How is path groups used in design compiler?

ANS: Path groups in Design Compiler (DC) are a way to group related paths in a digital
design for various purposes such as timing analysis, optimization, or reporting. They help
designers manage and analyse specific paths within a design more efficiently. Here's how
path groups are typically used in Design Compiler:

Timing Analysis:

Setup and Hold Time Analysis: Path groups are often used to specify the paths that need to
meet setup and hold time requirements. You can create separate path groups for critical paths,
interface paths, or any other groupings that are relevant to your design's timing constraints.

Slack Analysis: You can analyse the slack (the amount of time available before a path
violates a timing constraint) for specific path groups. This can help identify which parts of the
design may require further optimization.

Optimization:

Area Optimization: Path groups can be used to target specific parts of the design for area
optimization. For example, you can create a path group for non-critical paths and apply
aggressive area optimization settings to reduce their area footprint.

Power Optimization: Similar to area optimization, you can use path groups to apply specific
power optimization strategies to different parts of the design.

Reporting:

Reporting Timing Violations: Path groups can help you generate detailed reports for timing
violations in specific areas of the design, making it easier to identify and address issues.
Design Hierarchies: Path groups can be used to maintain a hierarchy of paths in your design,
which can be useful when generating reports for different parts of a large design.

Constraints:

Applying Constraints: Path groups can be used when defining timing constraints in the
Design Constraint Language (SDF or SDC files). You can set constraints for specific path
groups to ensure they meet the desired timing requirements.

Optimization Directives:

You can use path groups to guide the synthesis and optimization process by specifying
directives or preferences for certain paths. For example, you can instruct the tool to prioritize
optimizing paths in a specific group.

13. If you have a violating path after synthesis, how to optimize it?

ANS: Group that path with -from -to option and give weightage value and do an incremental
compile.

14. Explain the steps for inserting clock gating in your design?

ANS: Clock gating can be inserted using power compiler, which gets invoked, along with
design compiler.

Clock gating can be inserted with two commands – compile_ultra -gate_clock and
insert_clock_gating. Insert_clock_gating command can be used for inserting clock gating
in RTL alone. It cannot be used for clock gating insertion in GTECH or Netlist. For this, we
can use the command compile_ultra -gate_clock.

15. Once the compile is done with. What are the different reports which
you browse through?

ANS: We will check with the synthesis log files because there only we see any warnings or
errors. We will check timing report, power report and area report.

16. Which library will you generally use as target library, if your standard
cell library consists of multiple threshold voltage cells?

ANS: We use normal threshold voltage cells as target library for synthesis

17. What corner will you use for synthesis?

ANS: Worst corner

18. What is the information we get from check_timing report?

Check_timing:

Unconnected/logic driven clocks

Sequential data pins driven by a clock signal

Sequential clock pins without clock waveform

Sequential clock pins with multiple clock waveforms

Generated clocks without clock waveform

Generated clocks with incompatible options

Generated clocks with multi-master clock

Paths constrained with different clocks

Loop-breaking cells for combinational feedback

Nets with multiple drivers

Timing exceptions with no effect

Suspicious multi_cycle exceptions

Pins/ports with conflicting case constants

Inputs without clocked external delays

Outputs without clocked external delays

Inputs without external driver/transition

Outputs without external load

Exceptions with invalid timing start-/endpoints

19. If you have multiple modes, where a single clock’s frequency differs,
how will you constraint it in synthesis?

ANS: We take the highest frequency for this clock while doing synthesis to optimise
maximum.

20. What is the information we get from check_design report?

Check_design:

Unresolved References

Empty Modules

Unloaded Port(s)

Unloaded Sequential Pin(s)

Unloaded Combinational Pin(s)

Assigns

Undriven Port(s)

Undriven Leaf Pin(s)

Undriven hierarchical pin(s)

Multidriven Port(s)

Multidriven Leaf Pin(s)

Multidriven hierarchical Pin(s)

Multidriven unloaded net(s)

Constant Port(s)

Constant Leaf Pin(s)

Constant hierarchical Pin(s)

Preserved leaf instance(s)

Preserved hierarchical instance(s)

Feedthrough Modules(s)

Libcells with no LEF cell

Physical (LEF) cells with no libcell

Subdesigns with long module name

Physical only instance(s)

Logical only instance(s)

21. What is a wire load model, explain its contents and how will it help your
synthesis?
ANS: Wire load modeling allows us to estimate the effect of wire length and fanout on the
resistance, capacitance, and area of nets. Synthesizer uses these physical values to calculate
wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on
statistical information specific to the vendors’ process. The models include coefficients for
area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating
net lengths (the number of fanouts determines a nominal length).

22. If we have timing violations after synthesis which one we will fix?

ANS: Here we mainly focus on setup violations fixes after synthesis. We don’t fix hold
violation after synthesis because regarding clock path actual values will be present after clock
tree synthesis only.

23. What is the information we get from check_library report?

ANS: It will check the consistency between logical library and physical library and it will
report if any cell is missing with lib file or physical (LEF) file.

24. Do we add macro library in link library/target library?

ANS: No, we do not add macro libraries in the target library. Macro libraries are used to
store macros, which are pre-defined blocks of logic. Macros are not synthesized by the design
compiler but are instead used as references in the design. The target library contains the cells
that are used to synthesize the design. The link library contains the libraries that are used to
reference macros and other cells that are not synthesized by the design compiler.

25. What is mean by link library?

ANS: A link library is a collection of cells that are used to describe the function of mapped
cells prior to optimization. The link library is typically used to provide cells that are not
available in the target library, such as RAMs, ROMs, and macros. The link library can
contain cells from any technology library, but it is typically recommended to use the same
technology library for the target library and the link library.

26. What is mean by target library?

ANS: The technology library you want to map to during synthesis. Target library is used for
technology mapping. All the combo (AND, NAND, NOT, etc) and the sequential (SDFF,
DFF, etc) are mapped to equivalent gates from the target. Synthesis is about converting RTL
to gates.

27. What is mean by UPF? Is it required for synthesis?

ANS: UPF stands for "Unified Power Format" and it is a standard format used in the field of
electronic design automation (EDA) to describe and control power intent in integrated circuit
(IC) designs. Power intent refers to the specification of how power is managed and controlled
within a digital design, including aspects such as power domains, power modes, voltage
levels, and power-saving strategies. UPF is particularly important for designs that are
intended to operate under various power-saving modes, such as low-power or battery-
operated devices. It provides a standardized way to communicate the power intent from the
design team to the tools and methodologies used for synthesis, place and route, timing
analysis, and other stages of the chip design flow. UPF is not directly required for
synthesis itself, but it is crucial for ensuring that the synthesized design adheres to the
specified power management and control requirements.

30. What is mean by operating condition?

ANS: Operating conditions refer to the environmental conditions under which a chip is
expected to operate. These conditions include the process, voltage, and temperature (PVT) of
the chip.

31. What is mean by design rule constraints?

ANS: Design rules and constraints ensure that the logical and physical aspects of your
design meet your design requirements. Proper design rule definition automates your design
process ensuring quick, effortless, and error-free design manufacturing.

32. What is optimization in VLSI?

ANS: Optimization is the process of iterating through a design such that it meets timing,
area and power specifications. Three types of optimizations are possible-area, power and
timing. We have optimization constraints related to all these. Synthesis tools assign higher
priority to timing constraints over area and power constraints.

33. Can we do synthesis without giving timing constraints?

ANS: Yes, it is possible to do synthesis without giving timing constraints. However, the
resulting design may not meet the timing requirements of the design.

Timing constraints are used by the synthesis tool to ensure that the design meets its timing
requirements. The timing constraints specify the maximum delay that is allowed for each path
in the design. The synthesis tool will then try to synthesize the design in such a way that all of
the paths meet their timing requirements.

The design may not meet its timing requirements.

The design may be slower than expected.

The design may consume more power than expected.

The design may be less reliable.

34. Can we do scan insertion while synthesis/before synthesis/after synthesis?

Scan insertion can be done at three different stages in the design flow:

During synthesis: This is the most common approach, as it allows the scan insertion tool to
optimize the scan chains for performance and area.

Before synthesis: This approach is less common, but it can be used to improve the testability
of the design before any optimizations are performed.

After synthesis: This approach is the least common, as it is the most disruptive to the design
flow. However, it can be used to add scan to a design that was not originally designed for
testability.

The best approach to scan insertion depends on the specific design and the requirements of
the project. In general, scan insertion during synthesis is the best approach for most designs.

35. How do you perform synthesis activities in multi vt libraries?

ANS: For area calculation chooses the worst case lib (low voltage) for synthesis and for
power calculation chooses the best case lib (high voltage) for synthesis. Default use worst
case lib for synthesis. Also worst case lib for setup and best case lib for hold.

36. Why max and min capacitance required?

ANS: The maximum and minimum capacitance is the total capacitive load that an output pin
can drive. The min_capacitance rule specifies the minimum load a cell can drive.
max_capacitance is available only for output pins.