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EEE 415 - Microprocessors and Embedded Systems

EEE Introduction to
Embedded Systems Design

415 Lecture 8.1


Week 08

Dr. Sajid Muhaimin Choudhury, Assistant Professor


Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology

Introduction to Embedded Systems


• What is an embedded system?
• Application-specific computer system
Embedded
• Interacting with its environment
System
• Build into a larger system
• Often with real-time computing constraints

• What is the motivation for building an embedded system?


Macroscopic view on a device level
• Better performance
• More functions and features
Embedded Computer
• Lower cost e.g. through automation Input from Software Output to
Environment Environment
• More dependable Hardware

• Lower power

User Interface Link to


Other Systems
Microscopic view on a functionality level
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From a Processor to an Embedded System


• Microprocessor (central processing unit, CPU)
• Typically defined as a single processor core that supports at least instruction fetching,
decoding, and executing
• Normally can be used for general-purpose computing, but needs to be supported with
memory and Input/Outputs (IOs)

Instruction fetcher Memory Interface To memory


blocks
Instruction decoder

Register banks

ALU
Microprocessor

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From a Processor to an Embedded System


• Microcontroller (microcontroller unit, MCU)
• Typically has a single processor core
• Has memory blocks, digital IOs, analog IOs, and other basic peripherals
• Typically used for basic control purpose, such as embedded applications

Microprocessor (CPU) Program Memory Data Memory

System Bus

Digital IO Analog IO Timer Other Peripheral

Microcontroller

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Example of an Arm M4-MCU Architecture

Source: https://developer.arm.com/ip-products/subsystem/corstone-foundation-ip/cortex-m-system-design-kit
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From a Processor to an Embedded System


• Embedded system
• Typically implemented using MCUs
• Often integrated into a larger mechanical or electrical system
• May have real-time constraints

Embedded
System

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Benefits of Embedded Computer Systems


• Greater performance and efficiency
• Software makes it possible to provide sophisticated control
• Lower costs
• Less expensive components can be used
• Manufacturing costs reduced
• Operating costs reduced
• Maintenance costs reduced

• More features
• Many not possible or practical with other approaches
• Better dependability
• Adaptive system which can compensate for failures
• Better diagnostics to improve repair time

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Attributes of Embedded Systems


• Concurrent, reactive behaviors
• Must respond to sequences and combinations of events
• Real-time systems have deadlines on responses
• Typically, must perform multiple separate activities concurrently

• Fault handling
• Many systems must operate independently for long periods of time, requiring
system to handle likely faults without crashing
• Often fault-handling code is larger and more complex than normal-case code

• Diagnostics
• Help service personnel determine problem quickly

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Example Embedded System: Bike Computer

Input:
Inputs: Wheel rotation
Functions:
- Wheel rotation indicator Mode key
- Speed measurement
- Mode key
- Distance measurement

Output:
Constraints: - Liquid crystal display
- Size
- Cost Use low-performance
- Power and energy microcontroller: Output:
- 9-bit, 10 MIPS Display speed and
- Weight distance

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Example: Gasoline Automobile Engine Control Unit


Functions:
- Fuel injection Many inputs and outputs:
- Air intake setting - Discrete sensors and
- Spark timing actuators
- Exhaust gas circulation - Network interface to
- Electronic throttle control rest of car
- Knock control

Constraints:
Use high-performance
- Reliability in harsh microcontroller:
environment
- E.g. 32-bit, 3 MB flash
- Cost memory, 50-300 MHz
- Size

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Introduction to the Internet of Things (IoT)


• IoT generally refers to a world in which a large range of
objects are addressable via a network

Objects can include:


Why IoT? • Smart buildings and home
appliances
• Items can have more • Fridges, TVs, cookers
functionality and become
more intelligent • Civil engineering structures
IoT
• Bridges, railways
• Items can be managed more
easily • Wearable devices
• Smart watches, glasses
• More information becomes
available • Medical devices
• Smart inhaler, embedded
pills

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Internet of Things: Why Now?

• Embedded chips are becoming: Price


• Cheaper
• Smaller
• Lower power

• Energy harvesting

• Communication is becoming faster and


more efficient
Number of embedded systems

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Challenges to the Internet of Things

• Large number of chips required


• Chips have become even cheaper and • Power consumption
smaller
• Low power chips, longer battery life

• Big data demand • Security


• Large volume of data will be generated,
• Large amount of private data needs to be
data centre storage needs to be increased
protected

• Computation requirement • Standards


• High performance e.g. for cloud computing
• Official standards are required, such as
network protocols

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Options for Building Embedded Systems


Implementation Design Unit Upgrades Size Weight Power System
Cost Cost & Bug Fixes Speed

Discrete logic low mid hard large high ? very fast


Dedicated
Hardware

ASIC high ($500K/


mask set)
very low hard tiny – 1 die very low low extremely fast

Programmable low to mid mid easy small low medium to high very fast

logic – FPGA, PLD

Microprocessor + low to mid mid easy small to medium low to moderate medium moderate
Software Running on

memory +
Generic Hardware

peripherals
Microcontroller low mid to low easy small low medium slow to moderate

(int. memory &


peripherals)

Embedded PC low high easy medium moderate to high medium to high fast

Microcontroller based embedded system


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Constraints of Embedded Systems


• Cost
• Competitive markets penalize products which don’t deliver adequate value for
the cost

• Size and weight limits


• Mobile (aviation, automotive) and portable (e.g. handheld) systems

• Power and energy limits


• Battery capacity
• Cooling limits

• Environment
• Temperatures may range from -40°C to 125°C, or even more
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Impact of Constraints
• Microcontrollers used (rather than microprocessors)
• Include peripherals to interface with other devices, respond efficiently
• On-chip RAM, ROM reduce circuit board complexity and cost

• Programming language
• Programmed in C rather than Java (smaller and faster code, so less expensive
MCU)
• Some performance-critical code may be in assembly language

• Operating system
• Typically no OS, but instead simple scheduler (or even just interrupts + main
code (foreground/background system)
• If OS is used, likely to be a lean RTOS

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Benefits of Microcontroller-based Embedded Systems

• Greater performance and efficiency • More features


• Software makes it possible to provide • May not be possible or practical with other
sophisticated control approaches

• Lower costs for mixed signal- • Better dependability


processing systems • Adaptive system which can compensate for
• Less expensive components can be used failures
• Manufacturing costs reduced • Better diagnostics to improve repair time
• Operating costs reduced
• Maintenance costs reduced

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Impact of Constraints
• Microcontrollers used (rather than microprocessors)
• Include peripherals to interface with other devices, respond efficiently
• On-chip RAM, ROM reduce circuit board complexity and cost

• Programming language
• Programmed in the C language rather than Java (resulting in smaller and faster code – less
expensive MCU)
• Some performance-critical code may be in assembly language

• Operating system
• Typically no OS, but instead a simple scheduler
• If OS is used, it is likely to be a lean RTOS

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Summary: Building Embedded Systems using MCUs


• In most embedded systems, MCUs are the best solution as they offer:
• Low development and manufacturing cost
• Easy porting and updating
• Light footprint
• Relatively low power consumption
• Satisfactory performance for low-end products

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EEE 415 - Microprocessors and Embedded Systems

EEE The ARM Cortex-M4


Processor Architecture

415 Lecture 8.2


Week 08

Dr. Sajid Muhaimin Choudhury, Assistant Professor


Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology

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Recap: Arm Architectures and Processors


• Arm architecture is a family of RISC-based processor architectures
• Well known for its power efficiency
• Widely used in mobile devices, e.g. smartphones and tablets
• Designed and licensed by Arm to a wide ecosystem of partners

• Arm
• The company that designs Arm-based processors
• Arm does not manufacture, but it licenses designs to semiconductor partners who add their own
intellectual property (IP) on top of Arm’s OP, which they then fabricate and sell to customers
• Arm also offers IP other than processors, such as physical IPs, interconnect IPs, graphics cores and
development tools

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Recap: Arm Processor Families


Cortex-A5 Cortex-A55
Cortex-A7 Cortex-A57
Cortex-A8 Cortex-A65
Cortex-A9 Cortex-A65AE
Cortex-A Cortex-A15
Cortex-A17
Cortex-A72
Cortex-A73
• Cortex-A series (Application) Cortex-A32 Cortex-A75
Cortex-A34 Cortex-A76
• High performance processors capable of full operating system (OS) Cortex-A35 Cortex-A75AE
Cortex-A53 Cortex-A77
support
• Applications include smartphones, digital TV, smart books
Cortex-R4
Cortex-R5

• Cortex-R series (Real-time) Cortex-R Cortex-R7


Cortex-R8
Cortex-R52
• High performance and reliability for real-time applications
• Applications include automotive braking systems, powertrains
Cortex-M0
Cortex-M7
Cortex-M0+
Cortex-M Cortex-M1
Cortex-M23
Cortex-M33
• Cortex-M series (Microcontroller) Cortex-M3
Cortex-M4
Cortex-m35P
• Cost sensitive solutions for deterministic microcontroller applications
• Applications include microcontrollers, smart sensors
SecurCore SC000 Processor
SC300 Processor
• SecurCore series for high security applications

Arm7
• Earlier classic processors including Arm7, Arm9, Arm11 families Classic Arm9
Arm11

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Arm Cortex-M Series Cortex-M0


Cortex-M0+
Cortex-M7
Cortex-M Cortex-M1
Cortex-M23
Cortex-M33
Cortex-M3
Cortex-m35P
• Energy-efficiency Cortex-M4

• Low energy cost, long battery life

• Smaller code
• Lower silicon costs

• Ease of use
• Faster software development and reuse

• Embedded applications
• Smart metering, human interface devices, automotive and industrial control systems, white
goods, consumer products and medical instrumentation

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How to Design an Arm-based SoC


1. Select a set of IP cores from Arm and/or other third-party IP vendors
2. Integrate IP cores into a single-chip design
3. Give design to semiconductor foundries for chip fabrication

IP libraries SoC
Cortex-A9 Cortex-R5 Cortex-M4 Arm
ROM RAM
processor
Arm7 Arm9 Arm11
System bus Arm-based
DRAM ctrl FLASH ctrl SRAM ctrl SoC
Peripherals
AXI bus AHB bus APB bus

GPIO I/O blocks Timer


External Interface

Licensable IPs SoC Design Chip Manufacture

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Arm Processors vs. Arm Architectures


Arm architecture Arm processor
• Describes the details of instruction set, programmer’s model, • Developed using one of the Arm architectures
exception model, and memory map • More implementation details, such as timing information
• Documented in the ‘Architecture Reference Manual’ • Documented in processor’s ‘Technical Reference Manual’

Armv4/v4T Armv5/v4E Armv6 Armv7 Armv8


Architecture Architecture Architecture Architecture Architecture

E.g. Arm7TDMI E.g. Arm9926EJ-S E.g. Arm1136 Armv7-A Armv8-A


E.g. Cortex-A9 E.g. Cortex-A53,
Armv6-M Cortex-A57
Architecture Armv7-R Armv8-R
E.g. Cortex-M0, E.g. Cortex-R4
M1
Armv8-M
Armv7-M
E.g. Cortex-M4

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ARM Cortex-M Series Family


ARM Core Hardware Hardware Saturated DSP Floating
Processor Thumb® Thumb®-2
Architecture Architecture Multiply Divide Math Extensions Point

Cortex-M0 ARMv6-M Von Neumann Most Subset 1 or 32 cycle No No Software No

Cortex-M0+ ARMv6-M Von Neumann Most Subset 1 or 32 cycle No No Software No

Cortex-M1 ARMv6-M Von Neumann Most Subset 3 or 33 cycle No No Software No

Cortex-M3 ARMv7-M Harvard Entire Entire 1 cycle Yes Yes Software No

Cortex-M4 ARMv7E-M Harvard Entire Entire 1 cycle Yes Yes Hardware Optional

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Cortex-M4 Processor Overview


• Cortex-M4 Processor
• Introduced in 2010
• Designed with a large variety of highly efficient signal processing features
• Features extended single-cycle multiply accumulate instructions, optimized SIMD arithmetic,
saturating arithmetic and an optional Floating Point Unit.
• High Performance Efficiency
• 1.25 DMIPS/MHz (Dhrystone Million Instructions Per Second / MHz) at the order of µWatts / MHz
• Low Power Consumption
• Longer battery life – especially critical in mobile products
• Enhanced Determinism
• The critical tasks and interrupt routines can be served quickly in a known number of cycles

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Cortex-M4 Processor Features


• 32-bit Reduced Instruction Set Computing (RISC) processor
• Harvard architecture
• Separated data bus and instruction bus
• Instruction set
• Include the entire Thumb®-1 (16-bit) and Thumb®-2 (16/ 32-bit) instruction sets
• 3-stage + branch speculation pipeline
• Performance efficiency
• 1.25 – 1.95 DMIPS/MHz (Dhrystone Million Instructions Per Second / MHz)
• Supported Interrupts
• Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
• 8 to 256 interrupt priority levels

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Cortex-M4 Processor Features


• Supports Sleep Modes
• Up to 240 Wake-up Interrupts
• Integrated WFI (Wait For Interrupt) and WFE (Wait For Event) Instructions and Sleep On Exit
capability (to be covered in more detail later)
• Sleep & Deep Sleep Signals
• Optional Retention Mode with ARM Power Management Kit
• Enhanced Instructions
• Hardware Divide (2-12 Cycles)
• Single-Cycle 16, 32-bit MAC, Single-cycle dual 16-bit MAC
• 8, 16-bit SIMD arithmetic
• Debug
• Optional JTAG & Serial-Wire Debug (SWD) Ports
• Up to 8 Breakpoints and 4 Watchpoints
• Memory Protection Unit (MPU)
• Optional 8 region MPU with sub regions and background region

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Cortex-M4 Processor Features


 Cortex-M4 processor is designed to meet the challenges of low dynamic power constraints while retaining
light footprints
 180 nm ultra low power process –157 µW/MHz
 90 nm low power process – 33 µW/MHz
 40 nm G process – 8 µW/MHz

ARM Cortex-M4 Implementation Data

180ULL 90LP 40G


Process
(7-track, typical 1.8v, 25C) (7-track, typical 1.2v, 25C) 9-track, typical 0.9v, 25C)

Dynamic Power 157 µW/MHz 33 µW/MHz 8 µW/MHz

Floorplanned Area 0.56 mm2 0.17 mm2 0.04 mm2

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Cortex-M4 Block Diagram Optional


component
Cortex-M4 Processor
Interrupts and Nested Cortex-M4 Core
power control Vectored Embedded
Interrupt Floating Point Trace
Controller Unit (FPU) Macrocell
(NVIC)

Wake-up
Interrupt
Controller
Memory
(WIC) Flash Data
Protection
Patch Unit (MPU)
Watchpoint

Serial-Wire AHB Trace Port


Bus Instrumentation
or JTAG Access Trace Interface
Debug Port Port Matrix Macrocell Unit

Serial-wire or Trace Port


JTAG Debug Interface
Interface CoreSight ROM
ICode AHB-Lite DCode AHB- System AHB- table PPB APB debug
insruction interface Lite data Lite system system
interface interface interface
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Cortex-M4 Block Diagram


• Processor core
• Contains internal registers, the ALU, data path, and some control logic
• Registers include 16x 32-bit registers for both general and special use

• Processor pipeline stages


• Three-stage pipeline: fetch, decode, and execution
• Some instructions may take multiple cycles to execute, in which case the pipeline will be stalled
• Speculatively prefetches instructions from branch target addresses
• Up to two instructions can be fetched in one transfer (16-bit instructions)

Instruction 1 Fetch Decode Execute

Instruction 2 Fetch Decode Execute

Instruction 3 Fetch Decode Execute

Instruction 4 Fetch Decode Execute

Time
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Cortex-M4 Block Diagram


• Nested vectored interrupt controller (NVIC)
• Up to 240 interrupt request signals and an NMI
• Automatically handles nested interrupts, such as comparing priorities between interrupt requests and the
current priority level

• Wake-up interrupt controller (WIC)


• For low-power applications, the microcontroller can enter sleep mode by shutting down most of the
components
• When an interrupt request is detected, the WIC can inform the power management unit to power up the
system

• Memory protection unit (MPU)


• Used to protect memory content, e.g., make some memory regions read-only or preventing user
applications from accessing privileged application data

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Cortex-M4 Block Diagram


• Bus interconnect
• Allows data transfer to take place on different buses simultaneously
• Provides data transfer management, e.g. write buffer, bit-oriented operations (bit-band)
• May include bus bridges (e.g. AHB-to-APB bus bridge) to connect different buses into a
network using a single global memory space
• Includes the internal bus system, the data path in the processor core, and the AHB LITE
interface unit

• Debug subsystem
• Handles debug control, program breakpoints, and data watchpoints
• When a debug event occurs, it can put the processor core in a halted state, so developers can
analyse the status of the processor, such as register values and flags, at that point

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Cortex-M4 Registers (Identical to ARMv7 Chapter 06)


• Processor registers
• The internal registers are used to store and process temporary data
within the processor core
• All registers are inside the processor core, hence they can be
accessed quickly
• Load-store architecture
 To process memory data, they have to be first loaded from memory to registers,
processed inside the processor core using register data only, and then written back to
memory if needed

• Cortex-M4 registers
• Register bank
 Sixteen 32-bit registers (thirteen are used for general-purpose);
• Special registers

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Cortex-M4 Registers
• APSR
• N: negative flag – set to one if the result from ALU is negative
• Z: zero flag – set to one if the result from ALU is zero
• C: carry flag – set to one if an unsigned overflow occurs
• V: overflow flag – set to one if a signed overflow occurs
• Q: sticky saturation flag – set to one if saturation has occurred in saturating arithmetic
instructions, or overflow has occurred in certain multiply instructions
• IPSR
• ISR number – current executing interrupt service routine number
• EPSR
• T: Thumb state – always one since Cortex-M4 only supports the Thumb state (more on
processor states in the next module)
• IC/IT: Interrupt-Continuable Instruction (ICI) bit, IF-THEN instruction status bit

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Cortex-M4 Registers
• Interrupt mask registers
• 1-bit PRIMASK
 Set to one will block all the interrupts apart from nonmaskable interrupt (NMI) and the hard fault exception
• 1-bit FAULTMASK
 Set to one will block all the interrupts apart from NMI
• 1-bit BASEPRI
 Set to one will block all interrupts of the same or lower level (only allow for interrupts with higher priorities)

• CONTROL: special register


• 1-bit stack definition
 Set to one: use the process stack pointer (PSP)
 Clear to zero: use the main stack pointer (MSP)

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Cortex-M4 Registers
PRIMASK

PRIMASK Reserved

FAULTMASK

FAULTMASK Reserved

BASEPRI

BASEPRI Reserved

CONTROL Reserved

bit31 bit24 bit16 bit8


Stack definition

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ARM CORTEX-M4 PROCESSOR


MEMORY MAP

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Cortex-M4 Memory Map


• The Cortex-M4 processor has 4 GB of memory address space
• Support for bit-band operation (detailed later)

• The 4GB memory space is architecturally defined as a number of


regions
• Each region is given for recommended usage
• Easy for software programmer to port between different devices

• Nevertheless, despite of the default memory map, the actual usage


of the memory map can also be flexibly defined by the user, except
some fixed memory addresses, such as internal private peripheral
bus
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Cortex-M4 Memory Map


Reserved for other purposes Vendor specific 0xFFFFFFFF
ROM table
Memory 0xE0100000
512MB
Private peripherals Private Peripheral Bus 0xE00FFFFF External PPB
e.g. NVIC, SCS (PPB) 0xE0000000 External PPB
0xDFFFFFFF
Embedded trace macrocell
Mainly used for external peripherals Trace port interface unit
e.g. SD card External device 1GB
Reserved
0xA0000000
0x9FFFFFFF System Control Space, including
Mainly used for external memories Nested Vectored Interrupt
e.g. external DDR, FLASH, LCD External RAM 1GB Controller (NVIC) Internal PPB
0x60000000 Reserved
Mainly used for on-chip peripherals 0x5FFFFFFF
Fetch patch and breakpoint unit
e.g. AHB, APB peripherals Peripherals 512MB
0x40000000 Data watchpoint and trace unit
0x3FFFFFFF
Mainly used for data memory
e.g. on-chip SRAM, SDRAM SRAM 512MB Instrumentation trace macrocell
0x20000000
0x1FFFFFFF
Mainly used for program code
Code 512MB
e.g. on-chip FLASH 0x00000000

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Cortex-M4 Memory Map


• Code Region
• Primarily used to store program code
• Can also be used for data memory
• On-chip memory, such as on-chip FLASH
• SRAM Region
• Primarily used to store data, such as heaps and stacks
• Can also be used for program code
• On-chip memory; despite its name “SRAM”, the actual device could be SRAM, SDRAM or other types
• Peripheral Region
• Primarily used for peripherals, such as Advanced High-performance Bus (AHB) or Advanced Peripheral
Bus (APB) peripherals
• On-chip peripherals

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Cortex-M4 Memory Map


• External RAM Region
• Primarily used to store large data blocks, or memory caches
• Off-chip memory, slower than on-chip SRAM region
• External Device Region
• Primarily used to map to external devices
• Off-chip devices, such as SD card
• Internal Private Peripheral Bus (PPB)
• Used inside the processor core for internal control
• Within PPB, a special range of memory is defined as System Control Space (SCS)
• The Nested Vectored Interrupt Controller (NVIC) is part of SCS

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Cortex-M4 Memory Map Example


Chip
Silicon
PPB NVIC
Cortex-M4 SCS
Debug Ctrl

AHB bus

On-chip FLASH On-chip SRAM Timer UART GPIO


(Code Region) (SRAM Region) Peripheral Region

External memory interface External device interface


(External RAM Region) (External Device Region)

External SRAM,
External LCD SD card
FLASH

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Cortex-M4 Program Image


• The program image in Cortex-M4 contains
• Vector table -- includes the starting addresses of exceptions (vectors) and the value of the main stack
point (MSP);
• C start-up routine;
• Program code – application code and data;
• C library code – program codes for C library functions.

Code region
External Interrupts

SysTick
PendSV
Reserved
Start-up routine & Debug monitor
Program code & SVCall
C library code Reserved
Program
Image Usage fault
Bus fault
MemManage fault
Hard fault vector
NMI vector
Vector table Reset vector
0x00000000 Initial MSP value
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Cortex-M4 Program Image

• After Reset, the processor:


Reset

• First
reads the initial MSP value; Fetch initial value for MSP
• Then reads the reset vector; (Read address 0x00000000)

• Branches to the start of the programme


Fetch reset vector
execution address (reset handler); (Read address 0x00000004)

• Subsequently executes program instructions


Fetch 1st instruction
(Read address of reset vector)

Fetch 2nd instruction


(Read subsequent instructions)

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Cortex-M4 Endianness
• Endian refers to the order of bytes stored in memory
• Big endian: lowest byte of a word-size data is stored in bit 0 to bit 7
• Big endian: lowest byte of a word-size data is stored in bit 24 to bit 31
• Cortex-M4 supports both little endian and big endian
• However, Endianness only exists in the hardware level

Address [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]

0x00000008 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3


Word 3 Word 3

0x00000004 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3


Word 2 Word 2

0x00000000 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3


Word 1 Word 1

Little endian 32-bit memory Big endian 32-bit memory

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ARM and Thumb® Instruction Set


• Early ARM instruction set
• 32-bit instruction set, called the ARM instructions
• Powerful and good performance
• Larger program memory compared to 8-bit and 16-bit processors
• Larger power consumption

• Thumb-1 instruction set


• 16-bit instruction set, first used in ARM7TDMI processor in 1995
• Provides a subset of the ARM instructions, giving better code density compared to 32-bit
RISC architecture
• Code size is reduced by ~30%, but performance is also reduced by ~20%

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ARM and Thumb Instruction Set


• Mix of ARM and Thumb-1 Instruction sets
• Benefit from both 32-bit ARM (high performance) and 16-bit Thumb-1 (high code density)
• A multiplexer is used to switch between two states: ARM state (32-bit) and Thumb state (16-bit), which
requires a switching overhead

0
ARM
Incoming Instructions
Instruction
Instructions Executing
Thumb remap decoder
1
to ARM
T bit, 0: select ARM,
1: select Thumb
• Thumb-2 instruction set
• Consists of both 32-bit Thumb instructions and original 16-bit Thumb-1 instruction sets
• Compared to 32-bit ARM instructions set, code size is reduced by ~26%, while keeping a similar
performance
• Capable of handling all processing requirements in one operation state

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Cortex-M4 Instruction Set


• Cortex-M4 processor
• ARMv7-M architecture
• Supports 32-bit Thumb-2 instructions
• Possible to handle all processing requirements in one operation state (Thumb state)

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• Why Are We Using C instead of Java (or Python, or your other


favorite language)?
• C is the de facto standard for embedded systems because of:
– Precise control over what the processor is doing.
– Modest requirements for ROM, RAM, and MIPS, so much cheaper system
– Predictable behavior, no OS (e.g. Garbage Collection) preemption
• Why Did We Learning assembly language?
• The compiler translates C into assembly language. To understand whether the
compiler is doing a reasonable job, you need to understand what it has
produced.
• Sometimes we may need to improve performance by writing assembly
versions of functions.
• .
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Useful Resources
• Architecture Reference Manual:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html
• Cortex-M4 Technical Reference Manual:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439d/DDI0439D_cortex_m4_processor_r0p1_trm.pdf
• Cortex-M4 Devices Generic User Guide:
http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf

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Cortex-M4 Instruction Set


• ARM assembly syntax:
label
mnemonic operand1, operand2, … ; Comments
• Label is used as a reference to an address location;
• Mnemonic is the name of the instruction;
• Operand1 is the destination of the operation;
• Operand2 is normally the source of the operation;
• Comments are written after “ ; ”, which does not affect the program;
• For example
MOVS R3, #0x11 ;Set register R3 to 0x11
• Note that the assembly code can be assembled by either ARM assembler (armasm) or assembly tools
from a variety of vendors (e.g. GNU tool chain). When using GNU tool chain, the syntax for labels and
comments is slightly different

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Data Insertion and Alignment


• Insert data inside programs
• DCD: insert a word-size data
• DCB: insert a byte-size data
• ALIGN:
– used before inserting a word-size data
– Uses a number to determine the alignment size

• For example

ALIGN 4 ; Align to a word boundary
MY_DATA DCD 0x12345678 ; Insert a word-size data
MY_STRING DCB “Hello”, 0 ; Null terminated string

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