EEE415-Week02-Assembly Language

DRAFT 6/26/2023
EEE 415 - Weekly Lecture Plan

Week Lectures Topic Textbook
01 1-3 Patterson 1
Fundamentals of microprocessor and computer design, processor data
path, architecture, microarchitecture, introduction to CISC and RISC,
complexity, metrics, and benchmark
02 4-6 Assembly Language, Harris 6.1-6.3
03 7-9 Assembly Language Programming, Harris 6.3
04 10-12 Machine Language, Compiling, Assembling, Harris 6.4
05 13-15 Performance Analysis, Single Cycle and Multicycle Processor Harris 7.1-7.4
06 16-18 Pipelining, Hazards, Advanced Microarchitecture Harris 7.5,7.7
07 19-21 Memory Systems – Cache and Virtual Memory Harris 8.2-8.4
08 20-24 Introducing Embedded System Design, IoT, Arm Cortex m4 Lecture Slides
09 25-27 General Purpose Input Output Zhu 14
10 28-30 General Purpose Timers Zhu 15.1-15.3
11 31-33 Interrupts Zhu 11, 15.4
12 34-36 ADC + DAC Zhu 20,21
13 37-39 Serial Communication Zhu 22
Dr. Sajid Muhaimin Choudhury 1
EEE 415 - Department of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015

01 1-3 Patterson 1
12 34-36 ADC + DAC Zhu 20,21
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DRAFT 6/26/2023
EEE 415 - Microprocessors and Embedded Systems
EEE Computer Architecture and

Assembly Language
415 Lecture 2.1
Week 2
Dr. Sajid Muhaimin Choudhury, Assistant Professor

Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
Topics this Week

• Jumping up a few levels of abstraction
• Architecture: programmer’s view of computer
– Defined by instructions & operand locations

– Textbook: Harris Chapter 6

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Programming
• A computer is useless
without the software
• We need a “language” to
communicate our
instructions/commands to a
computer
Cartoon: Rand Reinfro

Peter Rob: Big Blue Basic (1985)

Computer Language coding

• Commands in a computer’s language
• High-level languages:
– e.g., C, Java, Python
– Written at higher level of abstraction
• Low-level languages:
• Assembly language: human-readable format of instructions
• Machine language: computer-readable format (1’s and 0’s)
• Architecture specifies which Instruction Sets will be used by a computer.

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Introduction to Architecture
• The architecture is the programmer’s view of a computer.
• The first step in understanding any computer architecture is to learn its language.
The words in a computer’s language are called instructions. The computer’s
vocabulary is called the instruction set.
• All programs running on a computer use the same instruction set. Even
complex software applications, such as word processing and spreadsheet
applications, are eventually compiled into a series of simple instructions such
as add, subtract, and branch
• Computer hardware understands only 1’s and 0’s, so instructions are encoded as
binary numbers in a format called machine language. Just as we use letters to
encode human language, computers use binary numbers to encode machine
language.
• However, humans consider reading machine language to be tedious, so we
prefer to represent the instructions in a symbolic format called assembly
language.
EEE 415 - Department of EEE, BUET
Slides Courtesy: Dr. Md. Zunaid Baten
7
Introduction
• The instruction sets of different architectures are more like different dialects than
different languages. Almost all architectures define basic instructions, such as
add, subtract, and branch, that operate on memory or registers. Once you have
learned one instruction set, understanding others is fairly straightforward.
• A computer architecture does NOT define the underlying hardware

implementation. Often, many different hardware implementations of a single
architecture exist.
• For example, Intel and Advanced Micro Devices (AMD) both sell various
microprocessors belonging to the same x86 architecture.
• They all can run the same programs, but they use different underlying
hardware and therefore offer trade-offs in performance, price, and power.

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Introduction
• We introduce the ARM architecture. This architecture was first developed in the
1980s by Acorn Computer Group, which spun off Advanced RISC Machines Ltd.,
now known as ARM. Over 10 billion ARM processors are sold every year.
• ARM is a reduced instruction set computer (RISC) architecture.

Architectures with many complex instructions, such as Intel’s x86 architecture,
are complex instruction set computers (CISC).
• We start by introducing assembly language instructions, operand locations,

and common programming constructs, such as branches, loops, array
manipulations, and function calls.
• We then describe how the assembly language translates into machine language
and show how a program is loaded into memory and executed.

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ARM Architecture
• Developed in the 1980’s by Advanced RISC Machines – now
called ARM Holdings
• Nearly 10 billion ARM processors sold/year
• Almost all cell phones and tablets have multiple ARM
processors
• Over 75% of humans use products with an ARM processor
• Used in servers, cameras, robots, cars, pinball machines, etc.
Once you’ve learned one architecture, it’s easier to learn others

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Architecture Design Principles

Underlying design principles, as articulated by Hennessy and Patterson:
1. Regularity supports design simplicity

2. Make the common case fast
3. Smaller is faster
4. Good design demands good compromises

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Instruction: Addition
C Code ARM Assembly Code

a = b + c; ADD a, b, c
• ADD: mnemonic – indicates operation to

perform
• b, c: source operands
• a: destination operand

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Instruction: Subtraction
Similar to addition - only mnemonic changes
C Code ARM assembly code

a = b - c; SUB a, b, c
• SUB: mnemonic
• b, c: source operands
• a: destination operand

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Design Principle 1: Regularity supports design simplicity
• Consistent instruction format

• Same number of operands (two sources and one destination)
• Ease of encoding and handling in hardware

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Multiple Instructions
More complex code handled by multiple ARM instructions.
Instead of having a separate instruction for x+y-z, we can
combine 2 statements
C Code ARM assembly code

a = b + c - d; ADD t, b, c ; t = b + c
SUB a, t, d ; a = t - d

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Design Principle 2: Make the common case fast
• ARM includes only simple, commonly used instructions

• Hardware to decode and execute instructions kept simple, small, and fast
• More complex instructions (that are less common) performed using multiple
simple instructions

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Operand Location
Physical location in computer
– Registers
– Constants (also called immediates)
– Memory

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Operands: Registers
• ARM has 16 registers
• Registers are faster than memory
• Each register is 32 bits
• ARM is called a “32-bit architecture”
because it operates on 32-bit data

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Design Principle 3: Smaller is Faster
• ARM includes only a small number of registers

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ARM Register Set

Name Use
R0 Argument / return value / temporary variable
R1-R3 Argument / temporary variables
R4-R11 Saved variables
R12 Temporary variable
R13 (SP) Stack Pointer
R14 (LR) Link Register
R15 (PC) Program Counter

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Operands: Registers
• Registers:
– R before number, all capitals
– Example: “R0” or “register zero” or “register R0”

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Operands: Registers
• Registers used for specific purposes:
– Saved registers: R4-R11 hold variables
– Temporary registers: R0-R3 and R12, hold
intermediate values
– Discuss others later

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Instructions with Registers

Revisit ADD instruction

; R0 = a, R1 = b, R2 = c
a = b + c ADD R0, R1, R2

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Operands: Constants / Immediates

• Many instructions can use constants or immediate operands
• For example: ADD and SUB
• value is immediately available from instruction
• Immediate is denoted by # symbol

; R0 = a, R1 = b
a = a + 4; ADD R0, R0, #4
b = a – 12; SUB R1, R0, #12

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Generating Constants
Generating small constants using move (MOV):
//int: 32-bit signed word ; R0 = a, R1 = b
int a = 23; MOV R0, #23
int b = 0x45; MOV R1, #0x45
Constant must have < 8 bits of precision

Note: MOV can also use 2 registers: MOV R7, R9
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Generating Constants
Generate larger constants using move (MOV) and or (ORR):

# R0 = a
int a = 0x7EDC8765; MOV R0, #0x7E000000
ORR R0, R0, #0xDC0000
ORR R0, R0, #0x8700
ORR R0, R0, #0x65

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Operands: Memory
• Too much data to fit in only 16 registers
• Store more data in memory
• Memory is large, but slow
• Commonly used variables still kept in registers

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Byte-Addressable Memory
• Each data byte has unique address
• 32-bit word = 4 bytes, so word address increments by 4

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Reading Memory
• Memory read called load
• Mnemonic: load register (LDR)
• Format:
LDR R0, [R1, #12]
Address calculation:
– add base address (R1) to the offset (12)
– address = (R1 + 12)
Result:
– R0 holds the data at memory address (R1 + 12)
Any register may be used as base address

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Reading Memory
• Example: Read a word of data at memory address 8 into R3
– Address = (R2 + 8) = 8
– R3 = 0x01EE2842 after load
ARM Assembly Code

MOV R2, #0
LDR R3, [R2, #8]

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Writing Memory
• Memory write are called stores
• Mnemonic: store register (STR)

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Writing Memory
Example: Store the value held in R7 into memory word 21.
Memory address = 4 x 21 = 84 = 0x54
ARM assembly code

MOV R5, #0
STR R7, [R5, #0x54]
The offset can be written in

decimal or hexadecimal

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Accessing Memory
Address of a memory word must be multiplied by 4
Examples:
– Address of memory word 2 = 2 × 4 = 8
– Address of memory word 10 = 10 × 4 = 40

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Big-Endian & Little-Endian Memory

• How to number bytes within a word?
– Little-endian: byte numbers start at the little (least significant) end
– Big-endian: byte numbers start at the big (most significant) end

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Big-Endian & Little-Endian Memory

• Jonathan Swift’s Gulliver’s Travels: the Little-Endians broke their eggs on the
little end of the egg and the Big-Endians broke their eggs on the big end
• It doesn’t really matter which addressing type used – except when two
systems share data

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Big-Endian & Little-Endian Example

Suppose R2 and R5 hold the values 8 and 0x23456789
After following code runs on big-endian system, what value is in R7?
In a little-endian system?
STR R5, [R2, #0]
LDRB R7, [R2, #1]
Big-Endian Little-Endian
Big-Endian Little-Endian
Word Word
Byte Address 8 9 A B Address B A 9 88 9Byte
Byte Address A Address
B Address B A 9 8 Byte Address
Data Value 23 45 67 89 0 Data23 45 6723
Value 8945Data Value 0
67 89 23 45 67 89 Data Value
MSB LSB MSB LSB
MSB LSB MSB LSB
Big-endian: 0x00000045 Little-endian: 0x00000067

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– Little-endian: byte numbers start at the little (least significant) end

(a) 42 × 4 = 168 = A8h – Big-endian: byte numbers start at the big (most significant) end
(b) 4 bytes, A8, A9, AA, AB

(c)

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R1 = 0x0ABCD876
Big Endian Little Endian
103 102 101 100 103 102 101 100
76 D8 BC 0A 0A BC D8 76
R2=0xBC R2=0xD8
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Summary
• ARM Instruction Format
• Addition
• Subtraction
• Operand Location
• Constant/Immediate
• Register
• Memory
• Endianness

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EEE Assembly Language:

Programming
415 Lecture 2.2
Week 2

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ARM Architecture
EEE 415 – Microprocessor Architecture EEE 415 – Embedded Systems

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Case Study: The Arm Architecture
Armv1 – 1985
Armv2 – 1989
Armv3 – 1991
Armv4 – 1996
2000 2004 2006 Announced 2011

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Arm v9

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• For our course, we are using ARMv7 instruction set.
• To compile and execute instructions, we use Keil uVision compiler

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Executing ARMv7 A code in μVision (1/9)

• Latest version of Keil μVision version 4 free edition
cannot debug ARMv7 codes 😔
• Install Keil μVision version 4

• Download link:
http://www.keil.com/demo/eval/armv4.htm
• Install Tutorial:
https://www.youtube.com/watch?v=mVqhyKR4xZU

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Step 1: Click Project> New uVision Project… Step 2: Make Empty folder and give file name and
click save

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Step 3: Select ARM7 CPU Architecture Step 4: New project is created
click ok

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Step 5: Right source group Step 6: Select Asm file (.s)
Select “Add New Item Group…” Give File Name, and click “Add”

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Step 7: Type Assembly Code AREA MYCODE, CODE, READONLY
Click the Build Button / Press F7

MOV R3, #12
MOV R1, #12
MOV SP, #0x00000000
PUSH {R3, R1}
ADD R0, R1, #42
SUB R2, R3, #0xFF0
POP {R3, R1}
STOP MOV R0, R0 ;NOP

B STOP
END ;End of the program
AREA STACK, NOINIT, READWRITE, ALIGN=3

Stack_Mem SPACE Stack_Size

49

Step 8: Click Start/Stop Debug session Button / Press Ctrl+F5
Debug session would start
Step 9: A message will appear.

Press ok

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Step 9: Press F11 or click on Step button to step through code

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Step 10: To view stack press Memory and Type address to see content of memory

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We can see how the memory

content is translated to
assembly code. But how is the
instruction encoded?
We find out in the next few

lectures!

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Assembly Programming Example

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01 1-3 Patterson 1
12 34-36 ADC + DAC Zhu 20,21
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EEE Assembly Language:

Data Processing, Branch,
415 Conditional Execution

Lecture 2.3
Week 2

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Programming Building Blocks

• Data-processing Instructions
• Conditional Execution
• Branches
• High-level Constructs:
 if/else statements
 for loops
 while loops
 arrays
 function calls

57

• Branches
 for loops
 while loops
 arrays
 function calls

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Data-processing Instructions
• Logical operations
• Shifts / rotate
• Multiplication
Basics already covered in EEE 303. For recap, read chapter 5 of Sarah Harris’ DDCA

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Logical Instructions
• AND
• ORR
• EOR (XOR)
• BIC (Bit Clear)
• MVN (MoVe and NOT)

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Logical Instructions: Examples

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Logical Instructions: Uses

• AND or BIC: useful for masking bits
Example: Masking all but the least significant byte of
a value
0xF234012F AND 0x000000FF = 0x0000002F
0xF234012F BIC 0xFFFFFF00 = 0x0000002F
• ORR: useful for combining bit fields

Example: Combine 0xF2340000 with 0x000012BC:
0xF2340000 ORR 0x000012BC = 0xF23412BC

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Shift Instructions
• LSL: logical shift left
Example: LSL R0, R7, #5 ; R0 = R7 << 5
• LSR: logical shift right

Example: LSR R3, R2, #31 ; R3 = R2 >> 31
• ASR: arithmetic shift right

Example: ASR R9, R11, R4 ; R9 = R11 >>> R47:0
• ROR: rotate right

Example: ROR R8, R1, #3 ; R8 = R1 ROR 3

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Shift Instructions: Example 1

• Immediate shift amount (5-bit immediate)
• Shift amount: 0-31

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Shift Instructions: Example 2

• Register shift amount (uses low 8 bits of register)
• Shift amount: 0-255

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Multiplication
• MUL: 32 × 32 multiplication, 32-bit result
MUL R1, R2, R3
Result: R1 = (R2 x R3)31:0
• UMULL: Unsigned multiply long: 32 × 32
multiplication, 64-bit result
UMULL R1, R2, R3, R4
Result: {R2,R1} = R3 x R4 (R3, R4 unsigned)
• SMULL: Signed multiply long: 32 × 32
multiplication, 64-bit result
SMULL R1, R2, R3, R4
Result: {R2,R1} = R3 x R4 (R3, R4 signed)

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• Branches
 for loops
 while loops
 arrays
 function calls

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Conditional Execution
Don’t always want to execute code sequentially
• For example:
 if/else statements, while loops, etc.: only want to
execute code if a condition is true
 branching: jump to another portion of code if a
condition is true
• ARM includes condition flags that can be:
 set by an instruction
 used to conditionally execute an instruction

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ARM Condition Flags

Flag Name Description
N Negative Instruction result is negative
Z Zero Instruction results in zero
C Carry Instruction causes an unsigned carry out
V oVerflow Instruction causes an overflow
• Set by ALU (recall from EEE 303 / Chapter 5)

• Held in Current Program Status Register (CPSR)

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Flag Affecting Instructions

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ARM ALU

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Setting the Condition Flags: NZCV

• Method 1: Compare instruction: CMP
Example: CMP R5, R6
 Performs: R5 - R6
 Does not save result
 Sets flags.
If result:
• Is 0, Z=1
• Is negative, N=1
• Causes a carry out, C=1
• Causes a signed overflow, V=1
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Example: CMP R5, R6
 Performs: R5 - R6
 Sets flags: If result is 0 (Z=1), negative (N=1), etc.
• Method 2: Append instruction mnemonic with S

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Example: CMP R5, R6
 Performs: R5-R6
• Method 2: Append instruction mnemonic with S
Example: ADDS R1, R2, R3
 Performs: R2 + R3
 Saves result in R1

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Condition Mnemonics
• Instruction may be conditionally executed
based on the condition flags
• Condition of execution is encoded as a
condition mnemonic appended to the
instruction mnemonic
Example: CMP R1, R2
SUBNE R3, R5, R8
 NE: not equal condition mnemonic
 SUB will only execute if R1 ≠ R2
(i.e., Z = 0)

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Condition Mnemonics
cond Mnemonic Name CondEx
0000 EQ Equal 𝑍
0001 NE Not equal 𝑍̅
0010 CS / HS Carry set / Unsigned higher or same 𝐶
0011 CC / LO Carry clear / Unsigned lower 𝐶̅
0100 MI Minus / Negative 𝑁
0101 PL Plus / Positive of zero 𝑁
0110 VS Overflow / Overflow set 𝑉
0111 VC No overflow / Overflow clear 𝑉
1000 HI Unsigned higher 𝑍̅𝐶
1001 LS Unsigned lower or same 𝑍 𝑂𝑅 𝐶̅
1010 GE Signed greater than or equal 𝑁⊕𝑉
1011 LT Signed less than 𝑁⊕𝑉
1100 GT Signed greater than 𝑍̅(𝑁 ⊕ 𝑉)
1101 LE Signed less than or equal 𝑍 𝑂𝑅 (𝑁 ⊕ 𝑉)
1110 AL (or none) Always / unconditional ignored
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Example:
CMP R5, R9 ; performs R5-R9
; sets condition flags
SUBEQ R1, R2, R3 ; executes if R5==R9 (Z=1)

ORRMI R4, R0, R9 ; executes if R5-R9 is
; negative (N=1)

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Example:
CMP R5, R9 ; performs R5-R9
; sets condition flags
SUBEQ R1, R2, R3 ; executes if R5==R9 (Z=1)

ORRMI R4, R0, R9 ; executes if R5-R9 is
; negative (N=1)
Suppose R5 = 17, R9 = 23:

CMP performs: 17 – 23 = -6 (Sets flags: N=1, Z=0, C=0, V=0)
SUBEQ doesn’t execute (they aren’t equal: Z=0)
ORRMI executes because the result was negative (N=1)

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ORR R0, R1, R2

MVN R0, R0
AND R0, R1, R2

MVN R0, R0
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ORR R0, R1, R2

MVN R0, R0
AND R0, R1, R2

MVN R0, R0
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DRAFT 6/26/2023

EEE 415 - Weekly Lecture Plan

EEE 415 - Weekly Lecture Plan

EEE 415 - Microprocessors and Embedded Systems

EEE Computer Architecture and

415 Lecture 2.1

Dr. Sajid Muhaimin Choudhury, Assistant Professor

Topics this Week

– Defined by instructions & operand locations

Dr. Sajid Muhaimin Choudhury 4

Cartoon: Rand Reinfro

Dr. Sajid Muhaimin Choudhury 5

Computer Language coding

• Architecture specifies which Instruction Sets will be used by a computer.

Dr. Sajid Muhaimin Choudhury 6

• A computer architecture does NOT define the underlying hardware

Dr. Sajid Muhaimin Choudhury 8

• ARM is a reduced instruction set computer (RISC) architecture.

• We start by introducing assembly language instructions, operand locations,

Dr. Sajid Muhaimin Choudhury 9

Once you’ve learned one architecture, it’s easier to learn others

Dr. Sajid Muhaimin Choudhury 10

Architecture Design Principles

1. Regularity supports design simplicity

Dr. Sajid Muhaimin Choudhury 11

C Code ARM Assembly Code

• ADD: mnemonic – indicates operation to

Dr. Sajid Muhaimin Choudhury 12

C Code ARM assembly code

Dr. Sajid Muhaimin Choudhury 13

Design Principle 1: Regularity supports design simplicity

• Consistent instruction format

Dr. Sajid Muhaimin Choudhury 14

C Code ARM assembly code

Dr. Sajid Muhaimin Choudhury 15

Design Principle 2: Make the common case fast

• ARM includes only simple, commonly used instructions

Dr. Sajid Muhaimin Choudhury 16

Dr. Sajid Muhaimin Choudhury 17

Dr. Sajid Muhaimin Choudhury 18

Design Principle 3: Smaller is Faster

• ARM includes only a small number of registers

Dr. Sajid Muhaimin Choudhury 19

ARM Register Set

Dr. Sajid Muhaimin Choudhury 20

Dr. Sajid Muhaimin Choudhury 21

Dr. Sajid Muhaimin Choudhury 22

Instructions with Registers

C Code ARM Assembly Code

a = b + c ADD R0, R1, R2

Dr. Sajid Muhaimin Choudhury 23

Operands: Constants / Immediates

C Code ARM Assembly Code

Dr. Sajid Muhaimin Choudhury 24

Constant must have < 8 bits of precision

C Code ARM Assembly Code

Dr. Sajid Muhaimin Choudhury 26

Dr. Sajid Muhaimin Choudhury 27

Dr. Sajid Muhaimin Choudhury 28

Dr. Sajid Muhaimin Choudhury 29

ARM Assembly Code

Dr. Sajid Muhaimin Choudhury 30

Dr. Sajid Muhaimin Choudhury 31

ARM assembly code