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Bansilal Ramnath Agarwal Charitable Trust’s

VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE


(An autonomous Institute affiliated to Savitribai Phule Pune University)

Department Of Electronics and Telecommunication


Engineering

Institute Vision:
To be globally acclaimed Institute in Technical Education and Research for holistic Socio-economic
development.

Institute Mission:
• To ensure that 100% students are employable and employed in Industry, Higher Studies, become
Entrepreneurs, Civil / Défense Services / Govt. Jobs and other areas like Sports and Theatre.
• To strengthen Academic Practices in terms of Curriculum, Pedagogy, Assessment and Faculty
Competence.
• Promote Research Culture among Students and Faculty through Projects and Consultancy.
• To make students Socially Responsible Citizen.

Department Vision
To be a centre of Academic Excellence in Electronics, Telecommunication and Related Domains through
Continuous Learning and Innovation

Department Mission
• To provide state of art education in Electronics and Telecommunication Engineering to meet current
and future needs of society, industry and academia.
• To strengthen collaborations with industries and institutes of repute to foster research culture among
faculty members and students.
• To promote ethically conscious engineers demonstrating sustainable entrepreneurship and
professional maturity in social context.

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Course Outcomes
CO1: Differentiate communication channels and noise sources.

CO2: Analyze amplitude and frequency modulated signal and their spectrum.

CO3: Illustrate working of analog receivers.

CO4: Discuss sampling and waveform coding tecgniques.

CO5: Analyze modulation techniques with respect to bandwidth, Euclidian distance.

CO6: Evaluate performance of optimum filter.

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Index

1. List of experiments ……………………………………………… 4

2. Lab experiment writeups………………………………………… 5

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

List of Experiments

Page
Sr No. Experiment Name No.

1. Observe spectral components of time-domain signal using Digital 5-10


Storage Oscilloscope (DSO).

2. Experiment with Double side band suppressed carrier (DSBSC) 11-16


modulator and demodulator.

3. Experiment with Single side band suppressed carrier (SSBSC) 17-20


modulator and demodulator.

4. Experiment with Frequency modulator (FM). 21-23

5. Simulation of Analog communication system. 24-25

6. Experiment with Pulse Amplitude modulation. 26-28

7. Experiment with Pulse Code modulation and demodulation. 29-31

8. Experiment with Delta modulation and demodulation. 32-34

9. Experiment with Quadrature phase shift keying modulation and 35-38


demodulation.

10. Experiment with frequency shift keying modulation and 39-40


demodulation

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 1
Name of Student:

Class & Batch: Branch:


Roll No.: Gr.No.:

Objective: To measure spectral components of sine, square and triangular signals using DSO

Aim: Study of spectral components of time-domain signals using Digital Storage


Oscilloscope (DSO).

Equipments: Digital Storage Oscilloscope, signal generator, probes

Theory:

DSO (Digital Storage Oscilloscope):

A digital storage oscilloscope is an oscilloscope which stores and analyses the signal
digitally rather than using analog techniques. It is now the most common type of
oscilloscope in use because of the advanced trigger, storage, display and measurement
features which it typically provides.

The input analog signal is sampled and then converted into a digital record of the
amplitude of the signal at each sample t ime. The sampling frequency should be not
less than the Nyquist rate to avoid aliasing. These digital values are then turned back
into an analog signal for crystal/TFT display.

The front panel of the DSO consists of different controls; some of them are given
below
1 Auto -

2 Measure-

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

3 Cursor-

4 Trigger-

5 Math-

6 Store and recall-

7 Volts/div-

8 Sec/div-
9 Ch1 And Ch2 -

10 Displa y-

11 Horizontal and vertical knob

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Procedure:
1. Switch on the DSO and function generator
2. Set the function generator for the signal – sine wave 1 KHz and amplitude 2
Vp- p
3. Connect the probes from the function generator to the DSO
4. Press AUTO button on the front panel of the DSO. The volts /div and time/div
will be set automatically for the given input signal.
5 Voltage measurement
• Press cursor button on the front panel of DSO
• Move the horizontal knobs to the base and the other horizontal knob to the
top of the signal to be measured.
• The DSO will show the difference between the values of the two cursors
points. That will multiply with volts/div. which gives the Vpp of the signal.
• Voltage can also be measured using the measure button on the front panel
of the DSO.
• Note the readings

6 Time Period and frequency measurement

• Press cursor button on the front panel of DSO


• Move the vertical knobs to the beginning of the cycle and the other vertical
knob at the end of the cycle to be measured.
• The DSO will show the difference between the values of the two cursors
points. That will be the Time Period (T) of the signal.
• The frequency can be determined by taking the inverse of Time Period
• The Time Period and frequency can be measured directly using the measure
button on the front panel of the DSO.
• Note the readings
7 Measurement of spectral component

• Apply sine (square, triangular) signal from signal generator to the DSO. Keep
frequency = 10 KHz and amplitude = 2 Vp-p.
• Keep DSO in FFT mode
• Measure the magnitude and frequency of the spectral components displayed on
the screen.

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Observation Tables:

Table 1: Sine signal (Frequency , Amplitude )

Harmonic Number Magnitude Frequency (KHz)

Table 2: Square signal (Frequency , Amplitude )

Harmonic Number Magnitude Frequency (KHz)

Table 3: Triangular signal (Frequency , Amplitude )

Harmonic Number Magnitude Frequency (KHz)

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Table 4: Sawtooth signal (Frequency , Amplitude )

Harmonic Number Magnitude Frequency (KHz)

Table 5: Pulse signal (Frequency , Amplitude )

Harmonic Number Magnitude Frequency (KHz)

Table 6: TTL signal (Frequency , Amplitude )

Harmonic Number Magnitude Frequency (KHz)

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Conclusion:

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 2

Name of Student:
Class & Batch: Branch:
Roll No.: Gr.No.:

Objective: To understand DSB modulation and demodulation

Aim: To study DSB MODEM based on IC 1496.

Equipments: DSB generation kit, Cathode Ray Oscilloscope / DSO, Signal Generator, Connecting
wires.

Theory:

When a carrier signal is modulated by an information signal, new signals at different frequencies are
generated. These are called sidebands or side frequencies. The amplitude modulation generates two
sets of sidebands known as upper and lower sidebands. This technique is called as a DSB modulation.
The relation is:

fUSB = f c + fm

fLSB = fc - f m

where, fUSB = Frequency of the upper side band, fLSB = Frequency of the lower side band fc = Carrier
signal frequency, fm = Modulating signal frequency
The total bandwidth is given by:
B.W. = fUSB - fLSB

The carrier signal is just used to transmit the signal and does not contain any information. Only
sidebands contain the useful information. Most of the power is wasted in transmitting the carrier signal
and a very small portion of it is allotted to the sidebands. This type of signal containing both carrier
signal and the sidebands is called as Double Side Band Full Carrier (DSBFC) signal.

When the carrier signal is suppressed and the resulting signal contains only the sidebands, it is
called as Double Side Band Suppressed Carrier (DSBSC) signal. Demodulation of DSB signal can be
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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

achieved by multiplying it with locally generated carrier voltage at the receiver. It is important that
carrier be as closely synchronized in frequency and phase with original carrier as possible. Therefore
in our kit we use carrier from transmitter i.e. Balanced Modulator. In our kit we have used MC 1496
multiplier IC for this purpose of demodulator. This IC is used where output voltage is product of an
input voltage signal and switching carrier. Typical applications include suppress carrier AM i.e. DSB,
SSB.

Features of 1496 are as follows :


1. Excellent carrier suppression, 65 dB type at 500 KHz, 50 dB at 10 MHz
2. Adjustable gain and signal handling.
3. Balanced input and output.
4. High common mode rejection 85 dB typical.

Block Diagram of DSB Generation using Diode Ring Modulator:

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Procedure:
1] Apply a modulating signal of 10 KHz frequency to the fm input of the DSB modulator.
2] Apply a carrier signal of 500 KHz frequency to the fc input of the DSB modulator. The amplitude of
the modulating signal must be less than that of the Carrier signal to avoid distortion. Observe DSB
output in time domain and frequency domain. Plot spectrum and calculate bandwidth of DSBSC signal
3] Connect the output of the DSB modulator to the buffer input.
4] Connect the buffer output to the input of the DSB demodulator. Observe and sketch the demodulator
output.
5] Apply the output of the DSB demodulator to the input of the low pass filter.
Observe and sketch the LPF output.

Observations:
1] DSB signal in time domain and frequency domain.
2] DSB demodulator output
3] Low pass filter output

Graph:
1] Modulating signal, Carrier signal
2] DSB wave in time domain
3] Spectrum of DSB signal
4] Output of DSB demodulator
5] Output of low pass filter.

Conclusion:

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13
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 3
Name of Student:
Class & Batch: Branch:
Roll No.: Gr.No.:

Objective: To understand SSB modulation and demodulation

Aim: To study the SSB generation using Spectrum Analyzer.

Equipments: SSB generation kit, CRO, Spectrum Analyzer, Connecting wires& probes

Theory:
The DSB spectrum has 2 sidebands viz. the upper sideband (USB) and the lower sideband (LSB), both
containing information of the baseband signal. A scheme in which only one sideband is transmitted without
any loss of information is known as single sideband (SSB), which requires only one half the bandwidth of
the DSB signal. SSB modulation has been quiet possibly the fastest spreading form of analog modulation.
It offers so many advantages that a very large number of communication systems have been changed to it,
and have used it. Amongst its great advantages is the ability to transmit good quality communications
signals by using a very narrow bandwidth. Two methods are commonly used to generate SSB signals: -
Selective filtering method and Phase shift method.
In filtering method, band pass filter selects desired sideband and rejects the other. This methods equires,
highly selective band pass filters and stable filter design.
In phase shift method, two balance modulators are used. Modulating signal and shifted carrier signal
are the two inputs for first balance modulator. Shifted modulating signal and original carrier signal are the
two inputs for second balance modulator. In adder block, output signals from both balance modulators are
added together, which forms a SSB signal.
Major benefits offered by the SSB transmission are
1. Conservation in spectrum space
2. Less required power
3. Less noise
4. Less fading

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Block Diagram of SSB Generation using Phase Shift Method:

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Procedure:
1] Connect signal generator output with frequency 25KHz to divide by 4 network.
2] Observe output waveform of divide by 4 network.
3] Connect one output to input of divide by 2 network and other to input of other divide by 2 network.
4] Connect outputs of divide by 2 networks to input of respective filters.
5] Observe outputs of 2 filters and using respective amplitude adjust pots, adjust amplitude up to 200 mV p-p
for both filters.
6] Observe 2 Fc waveforms and again by using their respective amplitude adjust pots, adjust their amplitude
to nearly 300 mV p-p.
7] Connect 2 Fm signals and 2 Fc signals to DSB generator blocks.
8] By varying DSB generator carrier amplitude adjust pots, adjust DSB loops with equal amplitude.
9] Connect these two outputs to 2 inputs of adder and observe SSB output. You will get a single carrier
frequency at SSB output point.
10] Observe and sketch the SSB signal in time domain and frequency domain.
11] For SSB demodulation, connect SSB output to DSB demodulator. Also, connect the carrier signal to
another terminal of DSB demodulator. Draw resultant signal.

12] Connect DSB demodulator output terminal to LPF input and observe its output.

Calculation:

The bandwidth required for SSB =

Graph:
1. Modulating signal and carrier signal with and without phase shift
2. Output of both DSB modulators
3. SSB signal in time domain
4. SSB spectrum.
5. DSB demodulator output
6. LPF output

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Conclusion:

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 4

Name of Student:

Class & Batch: Branch:


Roll No.: Gr.No.:

Objective: To understand frequency modulation and demodulation

Aim: Study of FM generation using IC 8038 and detection using PLL.

Equipments: FM generator kit, spectrum analyzer, CRO.

Theory:
In case of Frequency Modulation, frequency of high frequency carrier signal varies in accordance with
modulating signal. Frequency modulation has higher noise immunity.

In FM kit, FM Generator is obtained using function Generator IC 8038. Frequency of IC 8038 depends on
voltage at pin No.8. This property of IC 8038 is used. Modulating signal is given to pin No.8 through
decoupling capacitor. Output of IC 8038 is buffered.

For FM demodulation, phase locked loop IC 565 is used. Free running frequency of PLL must be equal to
carrier frequency. PLL tracks FM Generator output & output of phase detector is demodulated signal. This
output is filtered using second order low pass filter.

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Circuit Diagram of FM Generation using Varactor Diode:

Procedure:

1. Switch on the power supply.

2. Adjust the output of IC 8038 carrier generator to 50 KHz using frequency adjust pot.

3. Apply modulating signal to the input of FM modulator block. Observe FM signal in time domain and
frequency domain.

4. Estimate bandwidth of FM signal using Carson’s rule and from actual spectrum.

5. Calculate modulation index.

6. Note the effect of increase in modulating voltage and increase in modulating frequency on FM output
in time domain.

7. Adjust free running frequency of PLL to 50 KHz using frequency adjust pot.

8. Connect buffered output of IC 8038 to input of PLL.

9. Now vary the frequency of 8038 and observe its effect on output of PLL & verify whether PLL
tracks the frequency of 8038.

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Observation:

1. Bandwidth of FM signal using


a. Carson’s Rule: ( deviation = , modulating frequency = )
BW = 2  ( f + fm )

b. Actual Spectrum on DSO:

( deviation = , modulating frequency = )

BW = 2  N  fm where N represents the number of sidebands

2. Modulation Index=

3. Effect of increase in:

a. Modulating voltage on FM output ____________________________________________


________________________________________________________________________

b. Modulating frequency on FM output ____________________________________________


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Graph: (Attach separately)

1] Modulating and carrier signal


2] FM signal in time and frequency domain

Conclusion:

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 5

Name of Student:

Class & Batch: Branch:


Roll No.: Gr.No.:

Objective: Implementation of DSF-FC/ DSB-SC/ SSB/ FM modulator using MATLAB

__________________________________________________________________________________
Aim : Design and implementation of analog communication system based on DSF-FC/ DSB-SC/ SSB/ FM in
MATLAB environment

Apparatus: PC / LAPTOP with MATLAB software

Theory:
Modulator (write theory of modulator which is selected for implementation)

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Procedure:
1] Use Simulink model for implementation or editor for programming to develop modulator system.
2] Plot following graphs using MATLAB.

Graphs to be plotted in MATLAB:


1] Modulating, carrier and modulated signal 2] Spectrum of modulated signal

Conclusion:
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25
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 6

Name of Student:

Class & Batch: Branch:


Roll No.: Gr.No.:

Objective: To understand Pulse Amplitude Modulation

Aim: Study of Pulse Amplitude Modulation using Natural Sampling and Flat Top Sampling.
Equipments: PAM MODEM kit, Connecting wires, probes, CRO.
Theory:
According to sampling theorem, sampling rate be rapid enough so that at least two samples are taken
during the course of the period corresponding to the highest frequency spectral component. i.e. if our signal
frequency is 1 kHz then sampling frequency must be 2 kHz minimum for proper reproduction of original
signal from sampled signal. It is called as Nyquist criteria.
In this kit two different types of sampling methods are available -
1] Natural Sampling.
2] Flat Top Sampling
1] Natural Sampling: -
In this case the sampled signal consists of sequence of pulses of varying amplitude whose tops are
not flat but follow the waveform of I/p signal.
2] Flat Top Sampling: -
A Flat-topped pulse has constant amplitude established by the sample value of the signal at some
point within the interval. We have arbitrarily sampled the signal at the beginning of the sampling pulse. To
generate flat top sample the signal is held using a holding capacitor after sampling pulse. Please refer to
circuit diagram. After holding time the capacitor is dumped using a dump pulse. So that between sampling
pulse & dump pulse we get a Flat-topped sample pulse. In this kit we have provided 1 kHz sine wave &
crystal clock to observe stable waveforms on normal oscilloscope. To verify sampling theorem, you can vary
frequency of I/p signal from minimum to maximum & observe reconstructed output. Or IC 555 clock is

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

given. By varying basic clock frequency sampling frequency can be varied & its effect on reconstructed
signal can be observed.

Also, at receiver side, effect of value of holding capacitor (sample & hold circuit) & reconstructed signal
can be observed.

Procedure:

[A] Natural sampling:


1] Connect Crystal CLK O/P to the CLK point of the Control block.
2] Connect Sampling CLK (point A) to Sampling I/P of Natural sampling block & also
to HOLD CLK of receiver section.
3] Connect fixed sine wave at O/P of frequency divider block to I/P of natural sampling block.
4] Observe O/P of buffer i.e. sampled O/P.
5] Connect PAM O/P to I/P of receiver.
6] Connect O/P of S/H circuit (point D) of receiver to capacitor Cl and observe O/P of buffer.
7] Then connect O/P of S/H circuit (point D) of receiver to capacitor C2 and observe O/P of buffer.
8] Connect O/P of receiver buffer to I/P of LPF & Observe LPF O/P.
9] Now connect O/P of 555 CLK to CLK I/P of control block & by varying frequency of 555, Vary the sampling
frequency to verify Sampling Theorem & Aliasing effect. {For Aliasing frequency connect variable frequency
sine wave to I/P of natural sampling block}
[B] Flat top sampling:
1] Connect the crystal CLK O/P to the CLK point of control block.
2] Observe sampling CLK (point B) & dump CLK (point C) of control block on dual trace CRO.
For Flat top sampling, I/P waveform is sampled using sampling pulse (Point B) & its value is hold using
capacitor & then capacitor is dumped using dump CLK (point C). Therefore, time period between sampling
CLK & Dump CLK (i.e point B & C) is used as flat top sample.
3] Now connect sampling CLK (point B) of control block to Sampling CLK I/P of Flat top sample block & hold
CLK of receiver.
4] Also connect dump CLK (point C) of control block to dump CLK I/P of Flat top Sample block.
5] Connect fixed sine wave to I/P of Flat top sample block & Observe O/P of Flat top Sample block.
6] Connect O/P of Flat top sample block to I/P of receiver.
7] Connect O/P of S/H circuit (point D) to capacitor Cl in receiver block. Observe buffer O/P.

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Observation:
1. Modulating signal (Sine Wave)
2. Crystal Clock
3. Sampling clk & O/P of Natural Sampling
4. O/P of S/H with C1 / C2 w.r.t clock in the receiver
5. O/P of LPF w.r.t modulating signal
6. O/P at Point B i.e. sampling clk of control Block & O/P at Point C i.e. dump clk of control
block
7. O/P of Flat Top Sampling w.r.t sampling clock
8. O/P of Flat Top Sampling w.r.t dump clock
9. O/P of S/H with C1 / C2 w.r.t clock in the receiver
10. O/P of LPF w.r.t modulating signal
11. O/P of LPF & Modulating signal for the case fs < 2 fm for observing the downward
frequency translation

Conclusion:

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28
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 7

Name of Student:

Class & Batch: Branch:


Roll No.: Gr.No.:

Objective: To understand Pulse Code Modulation

Aim: Study of Pulse Code Modulation and Demodulation.


Equipments: PCM kit, Connecting wires, probes, CRO.
Theory:
By Nyquist theorem, if signal contains no frequency components for Fs > B. W., it is completely described
by instantaneous sample values uniformly spaced in time with period Ts < ½ .BW. If a signal has been
sampled at the Nyquist rate or greater (Fs > 2.BW) & the sample values are represented as weighted
impulses, the signal can be exactly reconstructed from its samples by an ideal LPF of bandwidth B.W.
Pulse code Modulation is a digital transmission of samples of analog signal. In PCM Generator we have
sampler, Analog to digital converter & parallel to serial data converter & serial transmission. In PCM
Receiver there is serial reception of data, this serially Received data is then converted to parallel from &
then fed to digital to analog converter. The output of DAC is fed to low pass filter & we get transmitted
analog signal. PCM performance as an analog communication system depends primarily on the
quantization noise introduced by ADC.
In our kit for PCM transmitter we have used ADC0809, Multiplexer IC74151, Latch IC74373, Counter
IC4040, IC7404, IC7432 & IC7408 for required Logic implementation.
The conversion time of ADC limits maximum sampling rate & therefore Bandwidth of transmitter. All
control signals are derived from basic clock. To derive control signals IC7408, 7432, 4017 are used. After
analog to digital conversion signal is fed to Multiplexer IC. Control for IC 74151 is from IC4040. Every
time IC4040 counter gives 8 combinations & transmits 8 bit data corresponding to every sample.
In Receiver section we have used shift register IC 74198 in serial in & parallel out form. For
synchronization clock at Receiver must be same to clock at transmitter. After serial reception of data
output of shift register is latched using 74373 & fed to DAC (R-2R Ladder). Output of DAC is fed to
filter.

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Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

To observe stable waveform on CRO the sampling frequency must be exactly integer multiple of signal
frequency. In our kit signal frequency is obtain by frequency divider & filter circuit.

Procedure:
1. Switch on the power supply.
2. Observe 1 MHz clock o/p signal on panel.
3. Connect this 1 MHz clock to ADC 0809 clock.
4. Observe o/p of divide by 2 network (point A) & connect it to i/p of divide by 8 n/w (point B).
5. Observe outputs of both divide by 8 n/ws & calculate their frequencies.
6. Connect output of 2nd divide by 8 network to start conversion input of ADC 0809 i.e. 'SC' point on
panel.
7. Observe Start of Conversion (point 'SC') & End of Conversion(point 'EOC')signals simultaneously on
dual trace oscilloscope & find out conversion period (Tc )of A/D. Conversion period(Tc) - Time between
falling edge of 'SC' & rising edge of 'EOC'.
8. Two generators are provided on panel. Right most is fixed frequency, Sine wave & the other is variable
frequency, Sine & square wave generator. To vary its frequency, a potentiometer is provided on panel.
Connect fixed sine wave to input of ADC 0809.
9. Observe End of Conversion (‘EOC’) and Output Enable ('OE') pin of 74373 latch simultaneously on
dual trace scope. Also observe Reset ('RST') & Clock ('Clk') pins of IC 4040 along with 'OE'.
10. Observe 'PCM OUTPUT & connect it to input to receiver i.e. serial input to shift register 74198.
11: Observe Clock ('CLK') of'74198 along with Clock ('Clk') of 4040 on dual trace scope.
12. Observe Latch Enable ('LE') pin of 74373, latch next to shift register with 'CLK' of 74198.
13. Now you can draw timing diagram of the system.
14. Observe DAC o/p. Calculate its frequency & peak-to-peak amplitude.
Observe this with fixed sine wave.
15. Connect DAC o/p to input of filter & observe o/p of filter.

Observations:
1. Modulating input m(t) and SC i/p.
2. SOC and EOC o/p.

30
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

3. EOC and OE.


4. OE and PCM o/p.
5. Clock of 4040 & RST of 4040.
6. PCM o/p and clock of IC 4040.
7. DAC o/p and LE at receiver.
8. LPF output and DAC.
9. LPF output and modulating i/p m(t).

Conclusion:

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______________________________________________________________

31
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 8
Name of Student:
Class & Batch: Branch:
Roll No.: Gr.No.:

Objective: To understand Delta Modulation

Aim: Generation and detection of Delta Modulation and demodulation with Noise measurement
Equipments: Delta MODEM kit, Connecting wires, probes, Signal Generator and CRO.
Theory:
Sample values of analog waveform derived from physical Process often exhibit predictability in the sense
that the average change from Sample to sample is small. Hence you can make a reasonable guess of the
next sample value based on previous values. The predicted values has some error off course, but the range
of the error should be much, less than the Peak - to peak signal Range Predictive coded modulation scheme
exploit this property by transmitting just the prediction errors. An identical prediction circuit at the
destination combines the incoming errors with its own predicted values to reconstruct the waveform.
Delta modulation employee’s prediction to simplify hardware in exchange for increased signaling
rate compared to Pulse code modulation.
At DM transmitter, every sample of message waveform is compared with previous sample. To have
previous sample available, dummy receiver is required at transmitter. If sample at any instant is larger in
magnitude than previous one, then one is transmitted. If sample at any instant is smaller than previous value
‘O’ is transmitted. Thus DM one bit per sample is transmitted. In our kit we have provided IC8038 based
function generator Sine, triangular & Square wave is provided. A fixed sampling (8 KHz) frequency is
provided. By varying I/p signal frequency different sampling rates & its effect on reconstructed message
signal can be observed. Also variable step-size is provided. For square wave slope-overload prominently
occurs, it can reduce by increasing step-size or increasing sampling rate.
At DM Receiver our aim is to reconstruct transmitted message signal from train of ‘1’ & ‘0’. In our
kit Receiver is built with complete hardware. flip-flops ( IC4013 ), Decade counter ( IC4017 ), Binary
Adders ( IC 7483 ), Latches ( 74373 ), OR Gate ( IC7432 ), Not Gate ( IC7404 ), Digital to analog converter
(OP-AMP based R-2R Ladder) are used for this purpose.
At receiver timing is very critical. We have to perform different operation such as addition,
subtraction, latching. Therefore, different control signals for sequential operation are derived by dividing
Basic Clock using (IC4017). Before taking new I/p pulse, previous sample value is latched using (IC74373)
& transfer to binary adder & subtractor. Subtraction is carried out using binary adder (IC7483) using 2’s
32
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

complement method. If received signal is ‘One’ then ‘1’ is added to previous value, else it is subtracted
from previous value. The result of addition/ subtraction is again latched & transfer to adder/ substrate. So
it can used as previous sample for next sample. Result is fed to DAC. O/p of DAC is reconstructed message
signal.

Procedure:
1. Switch on the power supply.
2. Connect O/P of Flip-Flop (Point A) to I/P of Control Block (Point B).
3. Connect DAC output to inverting terminal of the comparator & to the input of row pass filter.
4. Connect fixed frequency, fixed amplitude sine wave modulating signal to non-inverting terminal of the
comparator.
5. Observe sampling clock of Flip-flop (IC 4013) & modulating signal simultaneously. Measure amplitude
& frequency for both the waveforms.
6. Observe delta modulator output & modulating signal simultaneously. Measure amplitude & frequency
of DM output.
7. Observe DAC O/P & modulating signal simultaneously. Observe DAC & sampling clock
simultaneously. Measure amplitude & time Ts of DAC output. Measure step size 'S' of DAC output.
Observe the effect of pot of DAC on step size.
8. Observe OE signals of adder & subtract each w.r.t DM output. Measure amplitude, time period of OE
signals. Observe common latch enable LE signal w.r.t sampling clk. Measure amplitude & frequency of
LE.
9. Observe Low Pass Filter output. Measure amplitude & frequency.
10. Now by connecting variable sine wave to non-inverting terminal, observe DAC output & sine wave
simultaneously. See the effect of step size & sampling frequency when the frequency of sine wave is
varied. Repeat this step for square wave modulating input. Measure amplitude and frequency of square
wave input and DAC output.

Observation:
1. Modulating input and sampling clock.
2. Modulating input and DM output.
3. OE of adder and OE of subtractor.
4. LE of common latch and sampling clock.
5. DAC output and modulating signal.
33
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

6. DAC output and sampling clock.


7. LPF output and modulating signal.
8. Square wave input and, DAC output.

Calculation:
Measure the slope overload error for DM as follows
Slope of Analog message Signal > Slope of DAC. --- Slope overload error occurs.
i.e A* wm > S/Ts
Procedure for Noise Measurement:
1. Switch on the power supply.
2. Observe and measure the output of signal generator, set the minimum frequency signal generator by
frequency pot.
3. Connect the output of signal generator to Non-inverting terminal of comparator.
4. Connect ‘A’ point of sampler to the ‘B’ of control block.
5. Observe the Non-inverting terminal of comparator and DAC output on DSO simultaneously. Adjust
the output of DAC gain by gain adjustment till both signal should match with each other. To see both
signals on DSO, both channel of DSO should be on ‘ AC’ positions.
6. Remove i/p signal Non-inverting terminal of comparator and observe the output of DAC that should
be varying in the single step only.
7. Now connect signal generator output to Non-inverting terminal of comparator, ‘A’ Point of sampler to
‘B’ point of control and take the readings of Noise level meter.

Conclusion:

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34
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 9
Name of Student:

Class & Batch: Branch:


Roll No.: Gr.No.:

Objective: To understand Quadrature Phase Shift Keying Modulation and Demodulation

Aim: Generation and reception of QPSK with noise generator and adder.
Equipments: QPSK modulator and demodulator kit, Connecting wires, probes and CRO.
Theory:
To transmit digital data on analog lines (Viz. telephone) or even into space, modulation of analog signal is
required. Simplest way is BPSK Where one phase of carrier is transmitted for ‘1’ and inverted carrier is
transmitted for digital ‘0’. Here if bit rate is “Tb’ then bandwidth required is ‘2Tb’. To reduce this
bandwidth requirement QPSK can be used. For QPSK bandwidth required is ‘Tb’ i. e. half that of BPSK.
‘QPSK’ technique comes under ‘carrier modulation’ type. Here I/P to the transmitter is digital data, in
between processing is in analog form & finally O/P of receiver is again digital data same as fed to
transmitter. ‘Q’ in ‘QPSK’ means quadrature i.e. 4, four phases of carrier are transmitted depending upon
bit pattern. E.g. we know that incoming bit pattern is divided into ‘odd’ & ‘even’ bit patterns. Odd pattern
is multiplied by sine wave, & even pattern is multiplied by cosine wave. Sine & cosine waves are 90-degree
phase shifted. Now resulting two PSK’s are added & we get vector addition O/P i. e. if both odd & even
pattern bits are ‘1’ we get 45 degree phase shifted carrier. If odd bit is 1 & even bit is 0 we get 135-degree
phase carrier. If odd bit is 0 & even also 0 we get 225 degree. If odd bit is 0 & even bit is 1 we get 315
degree. In QPSK, two consecutive bits are stored & for resulting four combinations (4) different phases of
carrier are transmitted. By using ‘D’ flip-flop type arrangement incoming bit pattern is divided into two bit
patterns Viz. Odd pattern & even pattern, for obtaining this, basic clock whose frequency is ‘fb’ is divided
by two, resulting odd & even clock frequencies are ‘fb/2 ‘& they are complementary. Each bit is stored for
2Tb. time period. Odd pattern will have bit no. 1,3,5,7, etc. each stored for ‘2Tb’ & even bit pattern will
have bit no.2, 4,6, etc. stored for ‘2 Tb’. Here active edges of, odd & even clocks are separated by time
‘Tb’. So out of two bits only one bit is changing (either odd or even) after each ‘Tb’ period but every bit is
there for 2 Tb time; so in this offset QPSK system every time phase changes by 90 degree only. At receiver
carrier is recovered from QPSK Signal itself. This is Synchronous reception. To recover carrier QPSK
signal is raised to power four by using analog multiplier. Then resulting signal is passed through Band pass
filter whose center frequency is adjusted to 4 times carrier Frequency. Then O/p of band pass filter is
divided by 4 to get carrier Frequency. In this kit IC 1496 is used as analog multiplier. Then QPSK signal
is multiplied by ‘SINE & COS’ carrier waves. As a result we get odd & even patterns after filtering &
35
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

integrating multiplier Outputs. Now by combining these two patterns we can get original bit Patterns. This
is done by using switch (analog switch). To observe QPSK, we have given two bit patterns (i. e. repeated
after 5 bits.) so that on analog CRO we can observe the wave forms. Here carrier phase changes every after
time ‘tb’ ( bit period ) depending upon odd & even bit combination. It is difficult to observe this on analog
CRO. Details of these phase changes are shown in diagram attached. To observe QPSK we can use lissajous
patterns. i. e. If we connect ‘SINE’ wave to one channel & ‘COS’ wave to the other channel & press ‘XY’
button of CRO we get circle on screen. (This is lissageous pattern for 90 degree phase shifted waves)

Now if we connect ‘SINE’ & its associated PSK signal to two channels & press ‘XY’ mode button we get
two crossed lines. (One of 0 degree & the other for 180 degree phase)

180 0

If ‘SINE’ & ‘QPSK’ signals are connected to two channels, on ‘XY’ mode get two crossed ellipses. This
is because for 45, 135, 225 & 315 degree we get ellipse as lissageous fig.

135,315 45,225

Also at transmitter observe that ‘SINE’, ‘COS’ wave amplitudes are lesser than resulting ‘QPSK’ wave
because of vector addition. We are doing this complex processing to save on bandwidth requirement of
the system. This can be observed on CRO also. Observe bit pattern on CRO along with odd or even bit
pattern, you will come to know that odd or even bit pattern frequency is lesser than original bit pattern
frequency
Carrier recovery section:
Here we extract original carrier from transmitted QPSK signal itself. To raise QPSK signal to power 4
first we use squaring ckt. & then again one more squaring ckt to raise QPSK to power 4 ,if we observe
O/P of 1st SQ. ckt its frequency is double that of original ‘SINE’ wave at transmitter (observe these two
signals simultaneously on dual trace CRO) also O/P’s of both SQ. ckts are not exact SINE wave shape
,since it contains other harmonics also. O/P of 2nd SQ. ckt is having 4 times freq. that of ‘SINE’ to
suppress other harmonics we use band pass filter whose center freq. is 4 times original ‘SINE’ wave freq.

36
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Then we divide this freq by four. Since 4 possible phases are transmitted, finally we get exact ‘SINE’
wave but it will have 4 diff possible phase shifts. So we can not use same carrier directly at receiver. This
recovered carrier has to be passed through all pass N/W to match phase shift. This is not included in this
kit to avoid complexity.

Procedure:
1. Observe ‘CLK’O/p, measure its frequency. This is nothing but ‘Fb’
2. Connect ‘CLK’O/p to I/p of ‘Odd & Even CLK Gen’ observes ‘O’CLK (i. e.
Odd CLK) & ‘E CLK’ Frequency is ‘fb/2’.
3. Observe two patterns of pattern gen. & connect first pattern to I/p of O & E Data
generator.
4. Observe ‘O Data’ (i. e. Odd Data) & ‘E’ Data along with I/p pattern on dual trace
CRO.
5. Connect ‘O’ Data to ‘O’ Data pt. Pf 1496 Multiplier. [i.e. 1496 Multiplier].
6. Connect ‘E. Data’ to ‘E data’ pt. of 1496 ‘Multiplier.
7. Observe ‘SINE & COS waves & measure their frequencies. & also observe on ‘XY’ mode of CRO.
8. Observe pt. A with ‘O. Data’ on dual trace CRO. This is PSK signal of ‘O’ Data.
9. Observe pt. A with sinewave on CRO.( ‘XY’ mode)
10. Observe pt. ‘B’ with ‘E’ Data’, this is PSK signal of ‘E. Data’
11. Observe pt. B with coswave on CRO.( ‘XY’ mode)
12. Observe QPSK O/p with bit pattern. & then with Sine wave. Press ‘XY’ mode & observe two
ellipses.
13. Connect QPSK O/p to I/p of ‘1496 Sq. 1’ block, Observe its O/p, this is squared O/p. (frequency
doubled).
14. Connect O/p. of above to I/p of ‘1496 sq. 2’ block & observe its O/p, it is powered 4 O/p (its
frequency is 4 times carrier Frequency).
15. Connect O/p of 1496 Sq. 2’ to I/p of ‘BP Filter 4F’ adjust pot given above this block to get carrier
properly at the O/p of BP Filter.
16. Connect O/p of ‘BP Filter’ to I/p of -:- 4 N/W’ observe SINE & COS O/ps.
17. Connect QPSK O/p to common I/p pt of 2, 1496 Multiplier blocks.
18. Connect SINE wave from transmitter section to SINE of 1496 MUL block.
37
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

19. Connect COS wave from transmitter section to COS of 1496 Multiplier block.
20. Observe final O/p with the original I/p bit pattern. There is delay between i/p & o/p why?
21. Observe pt. ‘C’ & ‘D’. These are odd & even bit patterns received at receiver.

Observations:
1. Main clock and odd clock
2. Main clock and even clock
3. Odd clock and data
4. Even clock and even data
5. Odd data and BPSK output (point A)
6. Even data and BPSK output (point B)
7. QPSK output and main clock- use truth table for drawing the phase of QPSK output
8. QPSK output and sine carrier on XY mode,
[XY plot (4 phases 45o, 135 o, 225 o, 180 o)]
9. Square law output with sine carrier
10. BPF output with sine carrier adjust the pot for varying the frequency of recovered carrier by varying
the BPF’s tuned frequency.
11. Recovered data and transmitted data – (fine tuning of BPF’s pot is needed)

Conclusion:

______________________________________________________________
______________________________________________________________
______________________________________________________________
______________________________________________________________
______________________________________________________________
______________________________________________________________

38
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

Experiment No. 10
Name of Student:

Class & Batch: Branch:


Roll No.: Gr.No.:

Objective: To understand Frequency Shift Keying Modulation and Demodulation

Aim: Generation and detection of Frequency Shift Keying.

Equipments: Frequency Shift Keying Modulator & Demodulator kit, Connecting wires, probes, CRO.

Theory:
In computer peripheral & radio (wireless) communications, the binary data or code is transmitted by means
of a carrier frequency that is shifted between two-preset frequencies. Since a carrier frequency is shifted
between two preset frequencies, the data transmission is said to use a frequency shift keying technique.
The frequency shift is usually accomplished by driving a VCO with the binary data signal so that the
two resulting frequencies correspond to the logic “0” & logic “1” states of the binary data signal. The
frequencies corresponding to logic “1” & logic “0” states are commonly called as the mark & space
frequencies. Several standards are used to set the mark & space frequencies. For example, when
transmitting teletypewriter information using MODEM system a 1070HZ –1270HZ (mark -space) pair
represents the originate signal, while 2025HZ-2225HZ (mark -space) pair represents the answer signal.
In our kit we have used XR2206 IC for FSK Generation. Mark & space frequencies can be
independently adjusted by the choice of timing resistors. In our kit mark frequency is fixed & space
frequency can be adjusted using pot provided on panel. Detail ckt diagram is also provided. Baud rate of
our system is 330HZ.
At receiver our aim is to distinguish two frequencies. For this purpose XR2211, a monolithic
phase-locked Loop IC is used. The circuit consists of a basic PLL for tracking an I/p signal within the
pass-band, a quadrature phase detector, which provides carrier detection & a FSK Voltage comparator
that provides FSK demodulation.
Procedure:
1] Switch on the power supply.
2] Connect pattern “P1” or “P2” as input to FSK generator i.e.XR2206 I/p. Measure the bit period “Tb”.
3] Adjust potentiometer of FSK generator such that two frequencies can be easily distinguished & a neat
FSK waveform is observed on dual CRO.
39
Bansilal Ramnath Agarwal Charitable Trust’s
VISHWAKARMA INSTITUTE OF TECHNOLOGY, PUNE
(An autonomous Institute affiliated to Savitribai Phule Pune University)

4] Connect i/p of FSK generator to Vcc (5V), logic “1” state & measure FSK o/p frequency, say “f1”.

5] Connect i/p of FSK generator to GND i.e. logic “0” state & measure FSK o/p frequency, say “f2”.

6] Now using pot of FSK generator, adjust f2 such that (f2 = f1 + 200).

7] Calculate PLL center frequency f0, f0 = (f1 + f2)/ 2

8] Connect point ‘A’ of XR2211 to point ‘B’, so that we can observe free running frequency of PLL at
point ‘D’.

9] Using ‘VCO FREQ ADJ’ pot, adjust free running frequency of PLL to f0.

10] Disconnect point ‘A’ from ‘B’ & connect point ‘A’ to point ‘C’.

11] Now connect FSK output to input of capacitor near point ‘C’ & observe detected output of XR
2211, which is received o/p.

Observation:
1. FSK output and input of FSK [grounded input]
2. FSK output and input of FSK [VCC input]
3. FSK output and input bit pattern. Adjust the pot in the modulator so that f 1 and f2 frequencies in the
FSK output can be clearly distinguished
4. Free running frequency of VCO is adjusted to (f1 + f2) / 2
5. Output of demodulator (LPF inside the IC) and input bit pattern.

Conclusion:

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40

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