• LNA

ADC
INL DNL ADC

-
ADC
• INL
ADC
INL DNL N ADC
INL DNL 0 1

INL
ADC

INL =  [(VD-VZERO)/VLSB-IDEAL]-D
0 < D < 2N - 1
INL DNL
VD D N ADC
DNL LSB V ZERO
1a VLSB-IDEAL
ADC DNL = 0LSB
1LSB 1LSB = VFSR/2N INL DNL
VFSR N ADC INL DNL
1LSB DNL
≤1LSB
ADC DAC DUT
PC X-Y
DNL

DAC
ADC
DNL =  [(VD+1 - VD)/VLSB-IDEAL - 1]
0 < D < 2N - 2
ADC DAC
VD D N
ADC DAC
ADC VLSB-IDEAL
V DIFF
DNL
X-Y INL DNL
ADC
- SNR
VDIFF
SFDR
INL
LSB FSR INL ADC

INL
INL ( 1b)

13
 DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE

11111111 FULL-SCALE RANGE (FSR)

ACTUAL ADC TRANSFER
. 11111111 INL ERROR
. IDEAL TRANSFER FUNCTION BEFORE OFFSET
. EXAMPLE: FUNCTION (BEST-STRAIGHT-LINE INL)
. AND GAIN CORRECTION
. ADJACENT PHYSICAL VALUE IDEAL SPACING .
. BETWEEN TWO .
. VD+1 CORRESPONDS TO
.
. DIGITAL OUTPUT CODE D+1 ADJACENT CODES . ACTUAL ADC TRANSFER CURVE
. VLSB - IDEAL = 1LSB . AFTER OFFSET AND GAIN
. EXAMPLE: .
. PHYSICAL VALUE VD . CORRECTION
. .
. CORRESPONDS TO REAL .
DIGITAL OUTPUT CODE D TRANSFER .
00000110 INL ERROR
FUNCTION (ENDPOINT INL)
WITH 00000111
CODE WIDTH = 2LSB
00000011 ONE 00000110
0.5 BEST-STRAIGHT-
LSB MISSING 00000101
00000010 LINE FIT
CODE 00000100
IDEAL 50% IDEAL TRANSFER
00000011 CURVE
00000001 TRANSITION POINT 00000010
00000001 V OFFSET (LSB)
IDEAL CODE CENTER
00000000 ANALOG INPUT 00000000 ANALOG INPUT
FIRST TRANSITION LAST TRANSITION

1a. ADC DNL 1b. ADC

≤1LSB

ADC

50% ADC
50%

1b

ADC
2
ADC ADC

ADC
MAX108 INL/DNL
PC N
3
2N-1
MAX108
P
Q

P > QOUT

DVM

14
• dV/dt
INL/DNL
4a , 4b INL
• 50%
S

•
L
SAR
L DAC

•
5

DUT
RAMP dV =
I
dt C
-
N-BIT
ADC N N
+
INTEGRATOR N
2 -1
DIGITAL CODES
MAGNITUDE UNDER
CLOCK COMPARATOR TEST
PRECISION FROM
DVM PC
CURRENT
SOURCES

ISINK SIGNAL LINES ‘>’ AND ‘<’ OF THE MAGNITUDE

COMPARATOR DIRECTLY CONTROL THE CURRENT
FLOW OF THE TWO CURRENT SOURCES. > <

2.

1.5GHz, +4dBm
HP8662/3A
SINE-WAVE SOURCE EXTERNAL 50Ω TERMINATION
TO GNDI

CLK- CLK+

+5V ANALOG
VIN+
SERVO-LOOP -5V ANALOG
CIRCUIT VIN- MAX108EVKIT
+5V DIGITAL

+3.3V DIGITAL
QOUT P

PC
16 DATA
HP16500C
DATA ANALYSIS POWER
GPIB SYSTEM SUPPLIES
DREADY+

3. MAX108EVKIT MAX108 INL DNL

15
DAC • DAC
DAC
N ADC 16
DAC ADC 1/8LSB INL DNL
ADC

SNR N
SNR
2M SNRdB = N 6.02 + 1.76
M

SNR
2M-1

SAR
16

INL DNL
• TOC

INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE vs. DIGITAL OUTPUT CODE
(LOW-FREQUENCY SERVO-LOOP DATA) (LOW-FREQUENCY SERVO-LOOP DATA)
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
DNL (LSB)
INL (LSB)

0 0
-0.1 -0.1
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE

4a. MAX108 ADC INL 4b. MAX108 ADC DNL

16
 SUCCESSIVE
APPROXIMATION READ L BACK AFTER
REGISTER END OF CONVERSION

SAR
L-BIT N-BIT
L DAC ADC N N
L>N
EOC N
DIGITAL 2 -1
END
OF MAGNITUDE CODES
CLOCK UNDER
CONVERSION DATA CLOCK COMPARATOR
TEST
FROM
PC
‘DATA’ COUNTER COUNTS WHEN
‘>’ OUTPUT OF THE MAGNITUDE
COMPARATOR IS A ‘1’.

>
DIVIDE-BY
M-1
2
SR
FLIP FLOP
RESET
S
Q
CLOCK 1
R RDIVIDE-BY ‘1’
M
2
CLK
RESET
REFERENCE COUNTER COUNTS
EVERY CLOCK PULSE
DIGITAL AVERAGER

5. DAC

SAR References
SAR Johns, D., and K. Martin. 1997. Analog Integrated
SAR/DAC Circuit Design.
Plasche, R. van de. 1994. Integrated Analog-to-
1/2FSR Digital and Digital-to-Analog Converters.
1/4FSR 1/4FSR Sanchez-Sinencio, E., and A. G. Andreou. 1999.
Low-Voltage/Low-Power Integrated Circuits and
Systems—Low-Voltage Mixed-Signal Circuits.
N MSB LSB SAR
MAX108 data sheet. Rev. 1, 5/99. Maxim
N SAR Integrated Products.
DAC
MAX108EVKIT data sheet. Rev. 0, 6/99. Maxim
Integrated Products.

17