Analysis and Design of Analog Integrated Circuits

Lecture 23

Analog to Digital Conversion

Michael H. Perrott
April 25, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Outline of Lecture

 ADC Topologies
- Flash
- SAR
- Pipeline
- Interleaved
- Sigma-Delta
 Special focus on the emerging area of VCO-based
ADCs

M.H. Perrott 2
 Analog to Digital Conversion
D 2 D 1D 0
111

D0
D1
Vin ADC
DN-1
1 LSB
001
000 Vin
1V 7V
0
8 ref 8 ref

 Analog input is typically voltage

 Digital output consists of bits, Dk, with values 0 or 1
 Key characteristics similar to DAC
- Full scale = V
ref
- Resolution = V /2 = 1 LSB
ref
N

- Nonlinearity measured with INL, DNL, Monotonicity

M.H. Perrott 3
 Flash ADC
N-Stage
Resistor
Ladder Pre-Amp Comparator

A 0

A 1
Vref
N
A 1

IN CLK
 Fastest ADC structure (> 1 GHz)
- Performs direct comparison of an input signal to a set of
voltage references using parallel comparators
- Typically limited to 8-bit resolution
- Relatively large area and power for higher resolution
M.H. Perrott 4
 SAR ADC
Vref

DN-1 DN-2 D2 D1 D0

D0
Vdac 2N-1C 2N-2C 4C 2C C Φ0
D1
DAC
DN-1
Vdac
Vin CLK C Vin CLK

 Leverages a DAC to sequentially compare its output

values to the input voltage
- Minimal analog complexity - requires only one
comparator and a capacitor DAC
- Successive Approximation Algorithm (SAR) is efficient
comparison algorithm for comparing DAC to input value
- Has recently become very attractive in advanced CMOS
for modest resolution (i.e., 8 to 10 bits) applications 5
M.H. Perrott
 SAR Algorithm
Vref

Vin

Gnd
D5=0 D4=1 D3=1 D2=0 D1=0 D0=0

 We can efficiently compare the DAC output to the

input voltage, Vin, by successively subdividing the
range from MSB to LSB
- Number of comparisons ≈ number of bits
 Example: 10-bit SAR ADC requires roughly 10
comparisons per sample
M.H. Perrott 6
 Pipeline ADC

Vin Vresidue1 Vresidue2

K K
D0 Vdac1 D0 Vdac2
ADC DAC ADC DAC
DJ-1 DJ-1
CLK

 Resolves ADC bits in several stages

- Earlier stages resolve MSB bits
- Calculate residue for later stages through subtraction of
MSB estimate
 Amplify residue so that all stages operate over similar
voltage ranges
 Pipeline trends
- 1-bit per stage in the past; now going to multi-bit per stage
- For advanced CMOS, interleaved SAR architectures are
starting to look more attractive than pipelines
M.H. Perrott 7
 Interleaved ADC

D0 CLK1
Vin D1
ADC
DN-1 CLK2
CLK1
D0
CLK3
D1
ADC
DN-1 CLK4
CLK2
D0
ADC
D1  Clocking several ADC structures
DN-1 at different clock phases allows
CLK3 much higher effective sample rate
D0
D1
- Can interleave Flash, SAR, or
ADC Pipeline ADCs

CLK4
DN-1
 Key challenges include clock
skew, mismatch between ADCs,
higher input capacitance
M.H. Perrott 8
 Sigma-Delta ADC (Discrete-Time)
Multi-Level
Quantizer
IN OUT
H(z)

clock
DAC

 Oversampled input
- Clock rate is much higher than bandwidth of input
signal
 Noise shaped quantization noise
- Uses similar concepts as Sigma-Delta DAC considered
in Lecture 22
 Leads to high effective precision despite having a coarse
quantizer
M.H. Perrott 9
 Sigma-Delta ADC (Continuous-Time)

Multi-Level
Quantizer
IN OUT
H(s)

clock
DAC

 Similar to Discrete-Time, but important differences

- Sampler occurs after the filtering
 Allows removal of high frequency noise before sampling
- Only the quantizer and DAC need to settle during each
sample
 Allows higher speed

M.H. Perrott 10
 Time-to-Digital Conversion

Delay Delay Delay

tin(t)

D Q D Q D Q

Reg Reg Reg

e[k]
clk(t)

Delay TDC
tin(t) Time e[k]
tin(t) 1 Characteristic
-to-
1 Digital
1 e[k]
0 e[k]
0 clk(t)
clk(t)
Δt Δt
 Quantization in time achieved with purely digital gates
- Easy implementation, resolution improving with Moore’s law
How can we leverage this for quantizing an analog voltage? 11
M.H. Perrott
 Adding Voltage-to-Time Conversion

in(t) Voltage tin(t) Time out[k]

-to- -to-
Time Digital

clk(t)
Naraghi, Courcy, Flynn, ISSCC 2009

 Analog voltage is converted into edge times

- Time-to-digital converter then turns the edge times into
digitized values
 Key issues
- Non-uniform sampling
- Noise, nonlinearity
Is there a simple implementation for
the Voltage-to-Time Converter?
M.H. Perrott 12
 A Highly Digital ADC Implementation
Ring Oscillator Delay Delay Delay
tin(t)
Vtune(t)
in(t)
tin(t)
D Q D Q D Q

Reg Reg Reg

out[k]
clk(t)

in(t) Voltage tin(t) Time out[k]

-to- -to-
Time Digital

clk(t)

 A voltage-controlled ring oscillator offers a simple

voltage-to-time structure
- Non-uniform sampling is still an issue
We can further simplify this implementation and
lower the impact of non-uniform sampling 13
M.H. Perrott
 Making Use of the Ring Oscillator Delay Cells
Ring Oscillator Delay Delay Delay
tin(t)
Vtune(t)
in(t)
tin(t)
D Q D Q D Q

Reg Reg Reg

out[k]
clk(t)

Ring Oscillator
tin1(t) tin2(t) tin3(t)
Vtune(t)
in(t)
D Q D Q D Q
tin3(t)
Reg Reg Reg
tin2(t) out[k]
tin1(t) clk(t)

 Utilize all ring oscillator outputs and remove TDC delays

- Simpler implementation
 TDC output now samples/quantizes phase state of oscillator
M.H. Perrott 14
 Improving Non-Uniform Sampling Behavior
Ring Oscillator Delay Delay Delay
tin(t)
Vtune(t)
in(t)
tin(t)
D Q D Q D Q

Reg Reg Reg

out[k]
clk(t)

Ring Oscillator
tin1(t) tin2(t) tin3(t)
Vtune(t)
in(t)
D Q D Q D Q
tin3(t)
Reg Reg Reg
tin2(t) out[k]
tin1(t) clk(t)

 Oscillator edges correspond to a sample window of the input

 Sampling the oscillator phase state yields sample windows
that are much more closely aligned to the TDC clk 15
M.H. Perrott
 Multi-Phase Ring Oscillator Based Quantizer
Vtune N-Stage Ring Oscillator
Vtune N-Stage Ring Oscillator

Ref N-bit Register

Sample 1

N-bit Register

Sample 2
N XOR Gates

Adder

Out Sample 3

 Adjustment of Vtune changes

how many delay cells are visited Sample 4
by edges per Ref clock period
- Quantizer output corresponds to the number of delay cells
that experience a transition in a given Ref clock period 16
M.H. Perrott
 More Details …
Vtune N-Stage Ring Oscillator Example: Progression of
9-Stage Ring Oscillator Values
Vtune

Ref
Ref N-bit Register
010110101 110101010 101010010
N-bit Register
101010101 010110101 110101010
N XOR Gates
111100000 100011111 011111000
Adder

Out Out = 4 Out = 6 Out = 5

 Choose large enough number of stages, N, such that

transitions never cycle through a given stage more than once
per Ref clock period
- Assume a high Ref clock frequency (i.e., 1 GHz)
 XOR operation on current and previous samples provides
transition count
M.H. Perrott 17
 A First Step Toward Modeling
Vtune N-Stage Ring Oscillator First Order
VCO Quantizer Difference
Vtune Out
Quantized 1- z-1
VCO Phase
Ref
Ref N-bit Register Sampler
T
Wismar, Wisland,
N-bit Register
Andreani, ESSCIRC 2006
First Order
N XOR Gates
Difference
100011111 011111000
Adder

Out Quantized Out = 6 Out = 5

VCO Frequency

 VCO provides quantization, register provides sampling

- Model as separate blocks for convenience
 XOR operation on current and previous samples
corresponds to a first order difference operation
- Extracts VCO frequency from the sampled VCO phase signal
M.H. Perrott 18
 Corresponding Frequency Domain Model
First Order
 VCO modeled as integrator
Vtune
VCO Quantizer Difference
and Kv nonlinearity Out
1- z-1
 Sampling of VCO phase Ref
modeled as scale factor of 1/T
 Quantizer modeled as
T

addition of quantization noise

 Key non-idealities:
- VCO K nonlinearity
v
- VCO noise VCO
Noise
Quantization
Noise
Output
Noise
- Quantization noise -20 dB/dec 20 dB/dec

f f f
Vtune Out
2πKv 1
1- z-1
s T
VCO Kv VCO Sampler First Order
Nonlinearity Difference
M.H. Perrott 19
 Example Design Point for Illustration
Simulated ADC Output Spectrum
60  Ref clk: 1/T = 1 GHz
40  31 stage ring oscillator
20
- Nominal delay per
stage: 65 ps
Amplitude (dB)

0
 KVCO = 500 MHz/V
-20 - 5% linearity
-40  VCO noise: -100 dBc/Hz
-60
at 10 MHz offset

-80
VCO Quantization Output
-100 5 6 7 8
Noise Noise Noise
10 10 10 10 -20 dB/dec 20 dB/dec
Frequency (Hz)
f f f
Vtune Out
2πKv 1
1- z-1
s T
VCO Kv VCO Sampler First Order
Nonlinearity Difference 20
M.H. Perrott
 SNR/SNDR Calculations with 20 MHz Bandwidth
Simulated ADC Output Spectrum
60 Conditions SNDR
40
Ideal 68.2 dB
20
VCO Thermal
Amplitude (dB)

0 65.4 dB
Noise
-20
VCO Thermal
-40 32.2 dB
+ Nonlinearity
-60

-80
VCO Quantization Output
-100 5 6 7 8
Noise Noise Noise
10 10 10 10 -20 dB/dec 20 dB/dec
Frequency (Hz)
f f f

VCO Kv nonlinearity is Vtune

2πKv 1 Out
1- z-1
the key performance s T
bottleneck VCO Kv VCO Sampler First Order
Nonlinearity Difference 21
M.H. Perrott
 Classical Analog Versus VCO-based Quantization
N-Stage N-Stage Ring Oscillator
Resistor IN
Ladder Pre-Amp Comparator

A 0
Vdd

A 1 Buffer
Vdd
N CLK
N-bit Register
A 1

IN CLK 0 1 1 1 0

 Much more digital implementation

 Offset and mismatch is not of critical concern
 Metastability behavior is potentially improved
 Improved SNR due to quantization noise shaping
Implementation is high speed, low power, low area
M.H. Perrott 22
 Key Performance Issues: Nonlinearity and Noise

 Very hard to build a Vtune N-Stage Ring Oscillator

simple ring oscillator

with linear Kv
Ref
N-bit Register
 Noise floor set by VCO
phase noise is typically N-bit Register

higher than for analog

amplifiers at same power N XOR Gates

dissipation
Adder

Out
Quantization Noise
20 dB/dec
VCO Noise
f
Vtune Out

VCO Kv Nonlinearity 23
M.H. Perrott
 Feedback Is Our Friend
Ref (1 GHz) Iwata, Sakimura, TCAS II, 1999
In
Naiknaware, Tang, Fiez, TCAS II, 2000
Gain and Vtune VCO-based Out
Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out
DAC

Ref
N-bit Register

 Combining feedback with

front end gain acts to N-bit Register

suppress impact of quantizer N XOR Gates

noise and nonlinearity
- Scale factor from input to Adder
output is also better controlled
- Structure is a continuous-time Sigma-Delta ADC Out

 Issue: must achieve a highly linear DAC structure

M.H. Perrott
- Otherwise, noise folding and other bad things happen … 24
 A Closer Look at the DAC Implementation
Ref (1 GHz)

In Gain and Vtune VCO-based Out

Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out
DAC

Ref
N-bit Register

N-bit Register

 Consider direct
N XOR Gates
connection of the
quantizer output to a 1-Bit DACs
series of 1-bit DACs
- Add the DAC outputs
together
DAC Out

What is so special about doing this?

M.H. Perrott 25
 Recall that Ring Oscillator Offers Implicit Barrel Shifting
Ref (1 GHz)

In Gain and Vtune VCO-based Out

Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out
DAC
Sample 1

Sample 2
 Barrel shifting
through delay
Sample 3
elements
- Mismatch between
delay elements is Sample 4
first order shaped

M.H. Perrott 26
 Implicit Barrel Shifting Applied to DAC Elements
Ref (1 GHz)
Miller, US Patent (2004)
In Gain and Vtune VCO-based Out
Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out Implicit

DAC Barrel-Shift
DEM
Ref
N-bit Register

N-bit Register
Ref
N XOR Gates
111100000 100011111 011111000
1-Bit DACs

 Barrel shifting action of

quantizer transferred to
1-bit DAC elements DAC Out

M.H. Perrott
- Acts to shape DAC mismatch and linearize its behavior 27
 First Generation Prototype
973 MHz

VIN
Vtune VCO-based D OUT Barrel-Shift
Quantizer & DEM
VA VB

Quantizer Element
Barrel-Shift
DEM

31
IDAC1 IDAC2

Sample
 Second order dynamics achieved with only one op-amp
- Op-amp forms one integrator
- I and passive network form the other (lossy) integrator
dac1
- Minor loop feedback compensates delay through quantizer
 Third order noise shaping is achieved!

M.H. Perrott
- VCO-based quantizer adds an extra order of noise shaping 28
 Custom IC Implementing the Prototype
973 MHz
Straayer, Perrott
VIN VLSI 2007
Vtune VCO-based D OUT
VA Quantizer &
VB Barrel-Shift
DEM

31
IDAC1 IDAC2

 0.13u CMOS
 Power: 40 mW
 Active area: 700u X 700u
 Peak SNDR: 67 dB (20 MHz BW)
 Efficiency: 0.5 pJ/conv. step
M.H. Perrott 29
 Measured Spectrum From Prototype
Normalized FFT, FIN = 1 MHz
60
20 MHz Input Bandwidth
40 SNR 66.4 dB
SNDR 65.7 dB
20
Amplitude (dB)

0
Distortion
-20

-40

-60

-80
0.1 1 10 100 1000
Frequency (MHz) 30
M.H. Perrott
 Measured SNR/SNDR Vs. Input Amplitude (20 MHz BW)
SNR/SNDR vs. Amplitude, FIN = 1 MHz
90
80
SNR
70 SNDR Kv nonlinearity
60
limits SNDR to
SNR/SNDR (dB)

67 dB
50

40
30
20

10
0

-10
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
Amplitude (dBFS) 31
M.H. Perrott
 Summary

 ADC design is an active area of research

- Many topologies possible
- Much innovation is still ongoing, especially as new CMOS
fabrication processes are introduced
 Key topologies
- Flash
- SAR
- Pipeline
- Sigma-Delta
 VCO-based ADCs are a new area of interest
- Take advantage of high speed of new CMOS processes
- Leverage digital circuits
- Can achieve good performance, but innovation still needed
M.H. Perrott 32