module mac(

input [15:0] x,
input [15:0] y,
input reset,
input clock
reg output [31:0] z
);
wire t;
multiplier (x,y,t);
accumulator (t,clock,reset,z);
endmodule

module multiplier(
input [15:0] x,
input [15:0] y,
reg output [31:0] t
);
initial assign t = x * y;
endmodule

module accumulator(
input [31:0] t,
input clock,
input reset,
reg output [31:0] z = 0
);
always@(posedge clock)
initial
begin
if (reset = 1)
z = 0;
else
begin
z = z + t;
x = 0;
y = 0;
end
end
endmodule

module mactb();
reg [15:0] x,y;
reg reset,clock;
wire [31:0] z;
mac uut (x,y,reset,clock,z);
initial
begin
clock=0;
reset=0;x=4'h0034;y=4'h0002;#100;
reset=0;x=4'h0021;y=4'h0003;#100;
reset=0;x=4'h0011;y=4'h0004;#100;
reset=1;#100;
reset=0;x=4'h0009;y=4'h0005;#100;
end
always #10 clock = ~clock
endmodule