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  • Lab 4

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    Tuhin Shaikh
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    The document describes two Verilog modules. The first module moore11 contains inputs Clock, Reset, w and outputs z, y, Y. It uses y and w to determine the next state of Y, and sets z based on the current y value. The second module labfile2 also contains Clock, Reset, w inputs and z, y, Y outputs. It uses w and the current y value to determine the next state of Y and value of z, with two possible states A and B.

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    The document describes two Verilog modules. The first module moore11 contains inputs Clock, Reset, w and outputs z, y, Y. It uses y and w to determine the next state of Y, and sets z based on the current y value. The second module labfile2 also contains Clock, Reset, w inputs and z, y, Y outputs. It uses w and the current y value to determine the next state of Y and value of z, with two possible states A and B.

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    © All Rights Reserved
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    4 views4 pages

    Lab 4

    Uploaded by

    Tuhin Shaikh
    The document describes two Verilog modules. The first module moore11 contains inputs Clock, Reset, w and outputs z, y, Y. It uses y and w to determine the next state of Y, and sets z based on the current y value. The second module labfile2 also contains Clock, Reset, w inputs and z, y, Y outputs. It uses w and the current y value to determine the next state of Y and value of z, with two possible states A and B.

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    © All Rights Reserved
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    of 4

    module moore11(Clock, Reset, w, z,y,Y);

    input Clock, Reset, w;

    output reg z;

    output reg [1:0] y,Y;

    parameter [1:0] A = 0, B = 1, C = 2;

    always @(posedge Clock, posedge Reset)

    begin

    if (Reset == 1)

    begin

    y = 0;

    Y=0;

    end

    else

    begin

    y=Y;

    case(y)

    A: if (w) Y= B;

    else Y= A;

    B: if (w) Y = C;

    else Y = A;

    C: if (w) Y = C;

    else Y = A;

    default: Y = 2'bxx;

    endcase

    end

    end

    always @(w, y)

    begin
    case (y)

    A: z =0;

    B: z =0;

    C: z =1;

    endcase

    end

    endmodule

    module labfile2(Clock, Reset, w, z,y,Y);

    input Clock, Reset, w;

    output reg z;

    output reg y,Y;

    parameter A = 0, B = 1;

    always @(posedge Clock, posedge Reset)

    begin

    if (Reset == 1)

    begin

    y = 0;
    Y=0;

    z=0;

    end

    else

    begin

    y=Y;

    case(y)

    A: if (w)

    begin

    Y= B;

    z=0;

    end

    else

    begin

    Y= A;

    z=0;

    end

    B: if (w)

    begin

    Y= B;

    z=1;

    end

    else

    begin

    Y= A;

    z=0;

    end

    default: Y = 1'bx;

    endcase
    end

    end

    endmodule

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