21 Multi-level Inverters based on Cascaded H-

Bridge Converter using Nearest Level Modulation

R. Raja (  rpaper732@gmail.com )
Muthayammal Engineering college
V. Sudha
Sona College of Technology
C. Kalaivani
Pondicherry Engineering College Pondicherry

Research Article

Keywords: Multi-Stage Converter (MSC), multi-level inverters, phase-disposition sinusoidal pulse width
modulation, carrier phase shift pulse width modulation, nearest level modulation, Cascade, Full Bridge,
Total Harmonic Distortion

Posted Date: September 27th, 2022

DOI: https://doi.org/10.21203/rs.3.rs-2091432/v1

License:   This work is licensed under a Creative Commons Attribution 4.0 International License.
Read Full License
 21 Multi-level Inverters based on Cascaded H-Bridge Converter using Nearest Level
Modulation
*1
Dr.R.Raja , 2Dr.V.Sudha, 3Dr.C.Kalaivani

*1
Associate Professor, Department of EEE, Muthayammal Engineering College,
Rasipuram-637408
2
Assistant Professor, Department of ECE, Sona College of Technology, Salem-636005
3
Department of Electrical and Electronics Engineering, Pondicherry Engineering College
Pondicherry, India
*1
rpaper732@gmail.com, sudha.ece@sonatech.ac.in, 3kalaivani46@pec.edu
2

*Corresponding Author: Dr.R.Raja, rpaper732@gmail.com

Abstract:
In recent years, due to the increasing demand for electricity from grid users and the emergence of
high-power energy-consuming industries, the energy demand from society for grids has
significantly increased, which has led to an increase in the global power generation from
traditional energy sources. Therefore, the penetration of renewable energy (wind power,
photovoltaic power) resources into the grid has increased significantly, making the grid unstable
due to fluctuations in its output. In order to overcome grid fluctuations, this research proposes 21
multi-level inverters (MLI) based on cascaded H-bridge inverters to solve the problems
mentioned above in large-scale energy storage systems. This article focuses on the number of
components in a variety of multi-level converters with different topologies (neutral point
clamped inverter (NPC), flying capacitor inverter (FC), cascaded H-bridge multi-level
converter), the control program and the complexity of the hardware circuit, the power state and
the system loss are studied and compared, and the inverter with the cascaded H-bridge as the
main topology is established and its characteristics are studied. This paper depicts the three
different modulation techniques, namely phase-disposition sinusoidal pulse width modulation
(PD-SPWM), carrier phase shift pulse width modulation (CPS-SPWM), and nearest level
modulation (NLM) applied to modular Multiple Stage (MMCs). It further details the
implementation and analysis of each modulation technique. The performance of
5,7,9,11,13,15,17,19 and 21 level MMC with three aforementioned modulation techniques is
evaluated and compared in terms of output voltage, current and harmonic distortion. The
simulation is carried out using Matlab/Simulink software. The simulation results are presented
and validated.
Key words: Multi-Stage Converter (MSC); multi-level inverters; phase-disposition sinusoidal
pulse width modulation; carrier phase shift pulse width modulation ; nearest level modulation ;
Cascade; Full Bridge; Total Harmonic Distortion

Introduction:
Government incentives and reforms in favor of renewable energy (RE), as well as technology
advancements and cost reductions in solar photovoltaic (PV) and power converters, have resulted
in fast growth in the installation of large-scale solar PV and wind facilities across the world
[1].Renewable energy sources such as solar PV and wind, on the other hand, are extremely
intermittent and variable, and their integration presents significant technological problems to the
electrical system. The power variability in the generation is steadily increasing as more
renewables are connected to the grid. Consistent generation is extremely desired from the
standpoint of the supply grid. By buffering energy in the region where power fluctuations occur,
battery energy storage systems (BESS) can help to decrease this effort. [2].BESS was almost
solely utilized as the uninterruptible power supply in the low voltage utility grid in the past
(UPS). It is feasible, although not always practical, to transfer existing low-voltage technology
directly to the medium-voltage range. This is due to several factors:

1）It is impossible to reduce switching frequencies without increasing the need for harmonic
filtering in the process.

2）Non-modular topologies have no intrinsic redundancy, but modular topologies have.

3）To cope with the high DC-link voltage, several switches must be linked in series, increasing
the control complexity.

4 ） High ∂v/∂v voltage transients might cause problems in terms of insulation wear and
electromagnetic compatibility (EMC) difficulties.

These systems must be directly connected to the medium voltage distribution grid to get a high-
power output per deployed unit. Modern solutions are based on traditional multilevel power
converters with a restricted output voltage that need large line transformers to connect to the
medium-voltage grid. Increasing the number of voltage levels (and therefore the output voltage)
would indicate a steady increase in complexity.

Modular multilevel topologies can be used to circumvent all of the above issues while also
saving money due to the large quantities of modules and components required. These topologies
also enable the realization of a large number of output voltage levels by serially connecting
multiple identical power electronic modules. Additional modules may be readily added to the
design to offer redundancy, thus increasing the overall system's dependability. A large number of
output voltage levels results in superior output current quality with minimum filtering effort and
enables the converter to be installed in the medium-voltage distribution grid without the need of
a line transformer. The MMC converter has been suggested for ultra-fast charging of electric cars
in [3], while [4] proposes an MMC converter based on H-bridge cells as a self-contained high-
power battery energy storage system based on split batteries. [5] propose an MMC converter as a
grid-tied inverter with integrated split battery storage capabilities, nevertheless, no exhaustive
design approach has been provided.

The power electronics academic community and industry have responded in two distinct ways to
this demand: by improving semiconductor technology to provide greater nominal voltages and
currents (now 8 kV and 6 kA) [6]. The first technique benefited from well-known circuit
topologies and control mechanisms. However, modern semiconductors are more costly, and
when power levels rise, additional power-quality criteria must be met, necessitating the use of
power filters. The second method employs well-known and less expensive semiconductors, but
the more complicated circuit topologies provide numerous implementation and control
difficulties. Nonetheless, these difficulties were quickly transformed into new possibilities as
more complicated circuit architectures allowed additional control degrees of freedom that could
be utilized to enhance power conversion in a variety of ways, including power quality and
efficiency.

This fact has fueled the development of multiple-stage converters during the past two decades,
with constant progress. Multiple stage is presently regarded as industrial solutions for high
dynamic performance and power-quality demanding applications with power ratings ranging
from 1 to 30 MW [7].

Literature Survey:

The multiple-stage converters are based on the standard two-level converter, with the
architecture optimized to meet the high voltage and high-power output needs of the system. The
larger the number of levels, the lower the harmonic content and overall distortion rate of the
output waveform and the better the waveform quality. Multiple stage converters, unlike
traditional two-level converters, have a lower switching frequency and may effectively avoid the
voltage and current equalization issues that direct series-parallel switching devices create.
Multiple technologies have achieved success in the field of high-voltage high-power converters
and have been realistically employed in energy internet smart devices such as solid-state
transformers (SST) and high voltage direct current (HVDC), thanks to the advantages of its
topology.
Scholars in China and abroad have conducted a lot of theoretical research on the topology
of multilevel inverters. Multiple converters are now classed mostly on the power supply
technique. The most prevalent power supply techniques are divided into two groups: single DC
power supply and multi-DC power supply. For a single DC power supply, there are three main
types of multiple converters: Diode Clamped Multiple Converter (DCMC) [8 that proposed by
A.Nabae of Nagaoka University of Science and Technology in the 1980s, Flying Capacitor
Multiple Converter (FCMC), and Modular Multiple Converter (MMC) [9]; for multi-dc power
supply, Cascaded H-bridge Multiple Converter (CHMC) [10]. Both CHMC and MMC use a
modular design structure that is easy to extend and adapt to the requirements of various voltage
levels. These four converter types' topologies are briefly detailed below.
The four multiple-stage converters feature superior output voltage waveform quality,
reduced harmonic content, and more stable operation than two-level converters. The topologies
of DCMC and FCMC are similar, but the clamping components employed in each are different:
DCMC utilizes diodes, while FCMC utilizes capacitors. The DCMC is a multilevel converter
proposed by A [11]. Nabase that achieves dynamic voltage equalization of power switching
devices by introducing clamping diodes, reduces voltage stress on the devices, and improves
system stability to some extent by avoiding the negative effects of connecting the switching
devices directly in series.
A DC bus is included in the DCMC architecture, which allows for back-to-back connections
and is commonly utilized in harmonic compensation, active filtering, and low- and medium-
voltage current conversion. When the voltage level is high and the number of levels is large,
however, the DCMC circuit structure becomes complicated, requiring a large number of
clamping diodes and capacitors for voltage equalization control, which raises the hardware cost
and complicates the capacitor voltage equalization control algorithm. The benefit of FCMC that
is shown in figure 1.3 over DCMC is that there are more redundant switch combinations, and the
dynamic balancing of capacitor voltage can be achieved by an appropriate distribution of switch
combinations, and the control is more flexible and may be freely mixed. However, it has the
drawback of not being appropriate for higher voltage levels [12]. Higher voltage levels
necessitate a greater number of levels due to the switching devices' voltage resistance, which
increases the number of clamping capacitors. The volume of the capacitor is large, the cost is
high, and the reliability is poor; as the number of levels increases, the number of required
capacitors has increased dramatically, A large number of capacitors causes the inverter to be
bulky, Complex electrical connection and control, not easy to modularize, At the same time, the
frequent charging and discharging of the flying capacitor affects the life and reliability of the
system.
Compared with the previous two types of converters, CHMC does not require clamping
switch devices, which avoids the high hardware cost, high voltage, and high voltage applications.
The CHMC adopts a modular design concept, and each unit has the same structure. The CHMC
adopts a modular design concept, and each unit has the same structure, which is easy to be
expanded, but each sub-module unit needs an independent power supply and cannot be operated
in four quadrants. However, each sub-module requires a separate power supply and cannot
operate in four quadrants. In addition, because there is no DC bus in the topology, the CHMC is
not suitable for HVDC applications. The application of CHMC in HVDC and other fields is also
limited to a certain extent [13].
The concept and topology of modular multilevel converter (MMC) were first proposed by
German scholar Rainer Marquardt. The topology of the MMC in each phase comprises two
bridge arms with N submodules on each arm, and the phases are linked by a DC bus. Unlike
CHMC, MMC's sub-modules do not require an independent power source, and the voltage
stability of the sub-module capacitors is done by the sub-modules voltage equalization control.
Furthermore, the MMC topology's DC bus may support bidirectional energy transfer, and the
load can be active or passive, with separate power supplies for the passive network and
imbalanced operation [14]. However, the MMC structure also has disadvantages such as large
demand for power devices and energy storage capacitors, unbalanced sub-module capacitor
voltage regions, and complicated control implementation.
There will generally be imbalanced voltages at each level when there are several converter
output voltage levels. Scholars in the home and overseas have studied capacitor voltage
balancing management techniques. The capacitor voltage balancing management methods of
various multi-level inverters may be loosely split into two categories: hardware control and
software control. The former just employs extra hardware circuits to perform capacitor voltage
balancing management. The NPC architecture, for example, employs additional circuits to inject
or extract charge from the capacitor; the CHB topology, on the other hand, employs a capacitor
to match the DC power supply manner and achieve capacitor voltage clamping [15]. Using this
method, the complexity of the control software is considerably reduced. Loss increase, on the
other hand, is incompatible with cost decrease.
In summary, the work of domestic and foreign scholars mainly focuses on the improvement
of basic topologies such as NPC, FCC, and CHB in the research of multi-level inverter topology.
Still, it failed to completely solve the problems exposed when the basic topology was expanded
to a high level. Among the basic topologies, NPC and FCC are only suitable for occasions with a
small number of levels. When there are more levels, the cascaded H-bridge type, and MMC type
are more suitable. Compared with the cascaded H-bridge topology, the MMC topology is easier
to supply, when there are more levels, small in size, and more economical. In the traditional
multilevel inverter topology, MMC is more suitable for high-voltage and multi-level applications
than the other topologies [16].

Contribution:
In view of the multiple-stage converter for large-scale energy storage, working
characteristics and design difficulties are high. This study proposes a multi-level inverter
topology with cascaded full-bridge sub-modules and uses this topology as the main topology to
build a prototype of a multiple-stage converter for large-scale energy storage, use the minimum
number of semiconductor devices to achieve the required voltage output that meets expectations
[17]. The main research contents of this thesis are as follows:
1）Comparative Research on the topologies of the multiple-stage converter for large-scale
energy storage.
2）Research on the sub-module Topology
 3）Design and selection of power switching devices, sub-module power supply schemes,
main control microprocessors, power switching device drive schemes, and drive circuits of
multiple-stage converter for large scale energy storage;
4）Develop a prototype of a low-voltage multi-level waveform converter with a total
number of sub-modules N=10;

Proposed System Design:

Modular Multiple-Stage Converter Implementation:

The construction of a three-phase MMSC with two arms in each phase is shown in Figure
(𝑛
1(a). Each arm is composed of ⁄2) series-connected submodules (SMs), with 𝑛 equal to the
number of SMs in each phase, and an arm inductor, LMMC. The Direct-Current bus (DC-bus)
voltage (UDC) is divided evenly across all SMs, with the DC voltages, Uc, of each SM equal to is
given Eqn. (1),
U
U c  DC (1)
n
2
As shown in Figure 1(b), the SMs of the MMC utilized in this research is complete H-
bridges. Each SM is composed of four (04) switches (IGBT or MOSFET with reverse diode) and
a DC storage capacitor. Complementary signals, S1, S2, S3, and S4, are used to control the
IGBTs, with two possible combinations in the SM's output voltage 𝑈𝑆𝑀 . When S1, S4 = 1, 𝑈𝑆𝑀 =
𝑈𝐶 and when S2, S3=1, 𝑈𝑆𝑀 =-𝑈𝐶 . If S3, S4 = 0, 𝑈𝑆𝑀 = 0 V.

(a) (b)
Figure 1: (a) Modular Multilevel converter; (b) Full Bridge Submodule (SM)
The cascaded multiple-stage converter's system structure is shown in Figure 3.2. It is
composed of 10 cascaded modules. Due to system modularity, the voltage output waveform can
be split into equal voltage steps produced by basic modules. The desired peak-to-peak voltage
was approximately 90V, with one voltage step is 4.2V, implying that each elementary module
should be charged to approximately 5V.
Each basic module is a full-bridge MMC cell similar to those used in HVDC transmission
systems. As a result, the output voltage level capability of the 2N basic modules will be 2N+1,
while the conventional half-bridge MMC converter will only be N+1. To guarantee the
capacitors' durability, the MMC capacitors are rated at 10V. Figure 2 also depicts Multiple stage
converter system structure. A separate isolated DC source is utilized for each cell capacitor. The
primary power source is linked to the primary winding of a transformer through an AC voltage
regulator, while the secondary windings of separate transformers are connected to rectifier
bridges to get DC power and power for each submodule.
On the one hand, this avoids mutual effect between the charging circuit and the multiple-
stage converter; on the other hand, the output voltage wave's amplitude may be quickly changed
within a specified range using the AC voltage regulator. Whether inserted or not, each cell
capacitor is constantly charged, guaranteeing the output waveform's stability. To further decrease
the size of the charging circuit, a PWM DC/DC full-bridge converter can be used. Additionally,
to facilitate integration, each module's MOSFET driver and isolating circuit are powered by a
dedicated digital isolator. However, it should be noted that the input voltage range must be
sufficiently broad to guarantee a wide range of adjustable output voltage. Apart from that, the
converter's control interface consists of a few basic tasks such as choosing the kind of output
waveform and adjusting the frequency, which may be accomplished through a key panel on the
MCU board.
Virtual Battery Bank

S01 S03
Drive
Power
S02 S04
#1

S11 S13
Drive
Power
S12 S14
#2
LOAD

AC

L6 L2

S51 S53
Drive
Power
S52 S54
#9

S61 S63
Drive
Power
S62 S64
#10

GND

Figure 2: Multiple stage converter system structure

Pulse Width Modulation (PWM) Techniques:

The following measured parameters decide the quality of output voltage for the various
PWM techniques:
 1）The amount of harmonic content present in the output of the inverter.
2）Switching losses.
3）The magnitude of the fundamental component of the output.
4）Implementation.
5）Controllability
Though there are many carrier wave arrangements is shown in Figure 3, the following three
PWM methods have been carried out. THD values for these three strategies for various
modulation Index and different levels are compared.
1）Phase-disposition sinusoidal pulse width modulation (PD-SPWM)
2）Carrier phase shift pulse width modulation (CPS-SPWM)
3）Nearest level modulation (NLM)

Figure 3: Multilevel Converter Modulation Methods

Phase-Disposition Sinusoidal Pulse Width Modulation (PD-SPWM):

In an n-level inverter, n-1 carriers with the same frequency fc and amplitude Ac are
distributed in such a way that the bands they occupy are continuous. The reference waveform has
a maximum amplitude 𝐴𝑚 , a frequency 𝑓𝑚 and it’s zero-centered in the middle of the carrier set.
Continuously compare the reference with each carrier signal. If the reference is higher than a
carrier signal, the associated IGBT or MOSFET is turned on. If the reference is smaller than a
carrier signal, the associated IGBT or MOSFET is turned off [18]. Carrara et al. initially
suggested carrier-based disposition PWM methods [19].
Previous work on PWM methods shows that for the same number of total switches
transitions the diode clamped and CPS-PWM for cascaded inverter five climbs to the same
harmonic profile. These methods can be used effectively for Diode Clamped and Cascaded
Multilevel Inverter. The phases of carrier signals are altered to create three distinct methods for
signal disposition known as PD, POD, and APOD [20]. The carrier placement technique
distributes identical N-1 carrier waveforms in continuous bands to fill the inverter's linear
modulation range. The reference or modulating wave is centered in the carrier set and is
constantly compared to the carriers in order to produce the required gating pulses. The amplitude
modulation index (ma) of a multilayer inverter is the ratio of the reference amplitude (Am) to the
carrier amplitude (Ac) is given in Eqn. (2),
A
ma  m (2)
(m  1) Ac
The frequency ratio (𝑚𝑓 ) is the ratio of the carrier frequency (𝑓𝑐 ) to reference frequency
(𝑓𝑚 ).
In this PD-SPWM technique, all the carrier waveforms will be phase-shifted and will be in
phase with each other. The carrier signals are compared with the modulating sinusoidal wave
form. A pulse is generated during the intersection of the sinusoidal waveform and the carrier
signal, as shown in Figure 4. The four pulses are generated. The generated control signal is given
to the corresponding switches of each phase.

Figure 4: Modulation and carrier waves of PD-SPWM (5-level)

The simulation is carried out for 5-21level MMC using the PD-SPWM technique using the
simulation. The carrier and modulating signal comparison are illustrated in Figure 4. The 5 and
21level output voltage of the MMC using PD-SPWM is given in Figure 5(a, b) and Figure 6(a,
b). The %THD and FFT analysis are as shown in Figure 7(a, b) and Figure 8(a, b).

(a) (b)
Figure 5: 5-level PD-PWM output (a) without load; (b) with load
 (a) (b)
Figure 6: 21-level PD-PWM output (a) without load; (b) with load

(a) (b)
Figure 7: 5-level PD-PWM FFT analysis (a) without load; (b) with load

(a) (b)
Figure 8: 21-level PD-PWM FFT analysis (a) without load; (b) with load
The simulation is repeated for 5,7,9,11,13,15,17,19 and 21 level inverters. It is observed
that with the increase in level, the output voltage increases, and the harmonic content in the
output is also reduced considerably from 51.49% to 15.57. The voltage increases from 6.43V to
39.34V.
Carrier Phase Shift Pulse Width Modulation (CPS-SPWM):

CPS-SPWM is a PWM extender that adds Multiple Stages [21]. The technique is based on
the use of n/2 carrier signals separated by a phase shift, that denoted by θ is given in Eqn. (3):
360 (3)

n
2
The carrier phase shift modulation strategy technology compares a series of carrier triangle
waves with a fixed phase shift angle to a sine wave and determines whether the unit module
corresponding to the triangle wave is in a forward or backward conduction state based on the
comparison result. The benefit of this modulation technique is that it allows for phase shifting of
the output waveform to double the switching frequency, which has obvious advantages over
conventional PWM modulation. Simultaneously, since each unit module operates comparably
throughout its working cycle, the switching load of each unit module is balanced. We discovered
two methods for modulation in the literature: N + 1 and 2N + 1, N is the number of subunits
[22]. The output voltage is proportional to the number of SM connected in each arm. Figure 9
depicts the fundamental diagram of carrier phase shift modulation. In the case of four-unit
modules, there are four triangular carriers. Consider them in comparison to the sine modulation
wave. When the unit module carrier is less than the modulation wave, it is in forwarding
conduction, and the module's output voltage is Uc; when it is in reverse conduction, the module's
output voltage is -Uc. Finally, the output waveform is obtained by adding the voltages of each
unit module.
4 3 2 1

Modulation
Wave
Carrier

t/s

Carrier
Output Votage

t/s

Figure 9: CPS-SPWM schematic diagram

. Considering a 21-level MMC, the phase shift between the five carriers, 𝑉𝐶𝑥 is θ = 36°. The
output waveform is the sum of all the signals, as shown in Figure 10. The CPS-PWM is an
extension of the conventional PWM method applied for MMC. The principle of operation for 5-
level and 21-level are shown in Figures 10(a, b).
 (a) 5-level (b)21-level
Figure 10: CPS-SPWM carrier waves (a) 5-level; (b) 21-level
Each H-bridge inverter uses the identical modulation sinusoidal signals, Vx-ref and -Vx-ref,
which are 180 degrees out of phase with one another. They are responsible for a specific H-
bridge inverter's left and right arm switches. The simulation is carried out for 5-21level MMC
using the CPS-PWM technique using the simulation parameters. The carrier and modulating
signal comparisons are illustrated in Figure 10 (a, b). The 5 and 21level output voltage of the
MMC using CPS-SPWM is given in Figure 11(a, b) and Figure 12(a, b). The %THD and FFT
analysis are as shown in Figure 13(a, b) and Figure 14(a, b).

(a) without load (b) with load

Figure 11: 5-level CPS-PWM output (a) without load; (b) with load

(a) without load (b) with load

Figure 12: 21-level CPS-PWM output (a) without load; (b) with load

(a) (b)
 Figure 13: 5-level CPS-PWM FFT analysis (a) without load; (b) with load

(a) (b)
Figure 14: 21-level CPS-PWM FFT analysis (a) without load; (b) with load
The simulation is repeated for 7,9,11,13,15,17,19 and 21 level inverters. It is observed that
with the increase in level, the output voltage increases, and the harmonic content in the output is
also reduced considerably from 59% to 32%. The voltage increases from 6.8V to 33.45V.
Nearest Level Modulation (NLM):

When the number of SMs is very high, NLM is a very interesting modulation method to
employ. Considering that there are MMCs that easily surpass 200 SMs today [23], The benefit of
NLM over CPS-SPWM or PD-PWM is self-evident: CPS-SPWM requires 100 carrier signals
with a 3.6° phase angle, this would need the use of a very accurate carrier generator. The NLM
technique is based on the generation of the reference voltage utilizing two distinct voltage levels.
By applying each voltage level sequentially over a certain time, can produce a signal with a
mean value equal to the required value. The working principle is shown in Figure 15.

Uref

N-1
d d-1

Figure 15: Operation principle of the NLM

The number of voltage levels into which the output signal may be split in the MMC is
proportional to the number of SMs, with an extra level added for each new SM. There is a
formula for any level is given Eqn. (4),
U ref  U N .d  U N 1 (1  d ) (4)
 where Vref is the intended output voltage that lies between VN and V(N-1), and d denotes the
duty cycle. The duty cycle of each phase is calculated in Eqns. (5) and (6):
N  [U ref ] (5)
d  U ref  [U ref ] (6)
The closest level modulation method is based on the output waveform and uses a specific
control strategy to input or bypass each level of unit modules, resulting in a multi-level output.
The waveform approaches the waveform to be output at every moment. The control method is
relatively simple, all switching devices have a breaking frequency that is just twice the output
waveform, and the program control circuit is simple to implement. Since a multi-level waveform
is used to approximate the waveform that needs to be output, when the number of output levels is
large enough, the output waveform of this control method is closer to the ideal waveform, and
the harmonic components are lower. Therefore, this modulation strategy is suitable for occasions
with many power unit modules, such as MMC converters in high-voltage flexible direct current
transmission, and the number of cascaded unit modules can reach hundreds. The harmonic
distortion also reduces when the number of the level becomes higher. The schematic diagram of
the recent level approaching modulation is shown in Figure 16.

Figure 16: NLM modulation technique

Since the number of submodules invested in the main circuit can only be an integer, it is
necessary to round 𝑁𝑡 , the commonly used rounding functions include rounding up, rounding
down, and rounding to nearest. Using the nearest level approximation modulation can determine
the number of sub-modules that need to be invested in the main circuit at each moment,
However, the selection of which sub-modules are used depends on the capacitor voltage
equalization control strategy of the sub-modules. When the capacitor of the sub-module works
normally, its voltage value fluctuates due to the charging and discharging of the capacitor. To
keep its fluctuation near a constant value, and the fluctuation range as small as possible, the
choice of input sub-module is very important, which involves the equalization control strategy.
The simulation is carried out for 5-21level MMC using the NLM modulation strategy, and the
output voltage is shown in Figures 17(a, b) and Figure 18(a, b). It is noted that an output voltage
of 8.92 is achieved where % THD is observed to be 22.03% for 5-level and 13.20% for 21-level
as shown in Figures 19(a, b) and 20(a, b).
 (a) without load (b) with load
Figure 17: 5-level NLM output (a) without load; (b) with load

(a) without load (b) with load

Figure 18: 21-level NLM output (a) without load; (b) with load

(a) (b)
Figure 19: NLM FFT analysis for 5-level (a) without load; (b) with load
 (a) (b)
Figure 20: NLM FFT analysis for 21-level (a) without load; (b) with load
The simulation is repeated for 7,9,11,13,15,17,19 and 21 level inverters. It is observed that
with the increase in level, the output voltage increases, and the harmonic content in the output is
also reduced considerably from 22.03% to 13.27%. The voltage increases from 8.92V to 42.94V.
The output voltage and FFT analysis of 21 levels of MMC are presented in Figures 16 and 17,
respectively. Table 1 depicts the comparison results of CPS-PWM, PD-PWM, and NLM (21
levels).

Table 1: Comparison results of CPS-PWM, PD-PWM, and NLM (21 levels)

Compare items CPS-SPWM PD-PWM NLM
Output voltage
THD large THD large THD smaller
quality
Operating
High frequency (𝑓𝑠 ) High frequency(𝑓𝑠 ) Low frequency (𝑓)
frequency

Modulation Strategy Comparison:

Figure 21 illustrates the waveform produced using each modulation method (a, b, c). The
picture illustrates the output waveform generated by the three modulation methods for the same
voltage reference. As shown in the image, each modulation method produces a unique pattern
that affects the output waveform. As a result, the Total Harmonic Distortion (THD) and
harmonic content of each modulation method vary very significantly.

(a) CPS-PWM (b) PD-PWM

NLM
 Figure 21: Waveform obtained by each modulation technique
Comparative Performance Analysis of Pulse Width Modulation (PWM) Techniques for
cascade H bridge Multiple Stage converter:

The performance of 5,7,9,11,13,15,17,19, and 21 level MMC is compared using the three
different modulation strategies PD-SPWM, CPS-SPWM, and NLM modulation methods. The
comparison results are presented in the Tables 2 and 3. It is observed that irrespective of the
PWM methods employed the output increase with the increase in levels. There is a reduction in
harmonic content by increasing the number of levels.

Table 2: Comparative Analysis of %THD for Different Level MMC with PD-SPWM,
CPS-PWM, and NLM PWM Methods
NLM THD (%) PD-SPWM THD (%) CPS-SPWM THD (%)
Levels
Without Without Without
With Load With load with load
load load load

5-Level 17.60 22.03 26.77 51.49 30.53 59.70

7-Level 12.23 18.22 18.08 31.88 20.68 45.07

9-Level 9.36 16.58 13.63 26.32 15.61 40.07

11-Level 7.59 15.78 10.98 22.76 12.42 38.27

13-Level 6.38 14.58 9.18 19.38 10.49 35.34

15-Level 5.50 13.78 7.90 18.78 8.99 35.41

17-Level 4.84 13.40 6.92 16.99 7.83 33.65

19-Level 4.32 13.24 6.17 16.50 6.94 33.37

21-Level 3.90 13.20 5.57 15.91 6.26 32.87

Table 3: Comparative Analysis of Output voltage for Different Level MMC with PD-
SPWM, CPS-PWM, and NLM PWM Methods
NLM Output(V) PD-SPWM Output (V) CPS-SPWM Output(V)
Levels
Without
Without load With Load Without load With load With load
load

5-Level 9.34 8.92 7.72 6.43 8.55 6.81

 7-Level 13.78 13.02 12.1 10.45 12.84 10.26

9-Level 18.24 17.17 16.56 14.53 17.11 13.53

11-Level 22.72 21.33 21.01 18.59 21.46 16.95

13-Level 27.2 25.52 25.49 22.78 25.67 20.2

15-Level 31.68 29.71 29.96 26.88 29.93 23.44

17-Level 36.17 33.89 34.45 31.06 34.19 26.82

19-Level 40.67 38.07 38.93 35.21 38.5 30.17

21-Level 45.15 42.24 43.39 39.34 42.73 33.45

Figures 22 and 23 shows output voltage and %THD of 5 ,7,9,11,13,15,17,19 and 21 level
MMC for three different PWM methods. It is inferred that for all the levels NLM method gives
higher output voltage with reduced harmonic content. Further, PD-PWM produces a nearly 10%
increase in output compared to CPS-PWM. NLM produces a nearly 14% increase in output. The
%THD also reduced from 32.87% to 13.20%.

Figure 22: Output voltage for MMC with different levels using PD, CPS, and NLM
methods
 Figure 23: Harmonic analysis for MMC with different levels using PD, CPS, and NLM
methods

Hardware Design of Main Circuit:

Selection of Power Switches:

The overall efficiency of the multiple-stage converter would be determined by the

parameters of the power switching unit. The maximum withstands voltage of the device, the
maximum passable current, switching speed, and loss are the essential criteria that must be
regarded during the selection phase of power switching devices. The power switching system
must use a full-control device due to the versatile operating status of the sub-modules in the
multiple-stage converter. Gate turn-off thyristor (GTO), power transistor (GRT), power field-
effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) are examples of entirely
regulated instruments. GTO and GTR are current-driven devices with a solid driving force and a
complex driving circuit, and a sluggish switching speed. MOSFET and IGBT are voltage-driven
devices with a primary driving circuit and a quick switching speed. The circuit is low power so
MOSFET is a good choice [24]. A useful MOSFET model must describe all the important
properties of the devices from the application’s point of view. This task can be very complicated
since different results want to be obtained depending on the analysis of the application.
MOSFET has a high operating frequency and reasonable thermal stability.
The output voltage limit value of a single sub-module is determined by the withstand
voltage value of a MOSFET. The number of cascaded sub-modules in the main circuit is
inversely proportional to the upper limit of the multiple-stage converter output voltage
amplitudes. The number of sub-modules influences the number of output voltage waveform
levels, so the MOSFET's withstand voltage value indirectly affects the output voltage waveform
rating. The power transmission style is a sinusoidal voltage waveform; the higher the MOSFET
withstand voltage value, the less the cascaded sub-modules and the fewer the output levels. The
waveform's harmonic content is higher, and vice versa. The waveform has a low harmonic
content [25].
 In the multiple-stage converter for large-scale energy storage, the output waveform needs to
reach several volts due to the low power prototype. And the peak to peak would be 90V. As a
result, using a MOSFET with a maximum withstand voltage of 60V between the drain and
source is considered in this study [26]. Select a MOSFET module model based on the voltage
parameters determined: IRFB7545PbF, its maximum drain current is 95A. There is no gate
diode. Figure 24 shows the physical and internal circuit structure diagram of this type of
MOSFET module.

Figure 24: IRFB7545PbF and its circuit structure diagram

Sub-module Power Supply Scheme:

The charging circuit of the sub-module capacitor is shown in Figure 25. For each sub-
module capacitor, use an isolated DC power supply. The initial power supply is connected to the
primary winding of the transformer through an AC voltage regulator, and the secondary winding
is connected to the rectifier bridge; after rectification, it is converted into direct current to supply
power for each sub-module capacitor. On the one hand, the charging scheme avoids the mutual
influence between the charging circuit part and the multi-level voltage generating amount; On
the other hand, the AC voltage regulator can instantly adjust the amplitude of the output voltage
within a specific range [27]. In addition, each sub-module capacitor, whether invested or not, is
charged continuously to ensure the output waveform's stability. The input terminal of the
primary voltage regulator supply is connected to 220VAC, and the output terminal can output
05V DC.
To improve integration, the power of the MOSFET drive circuit of each sub-module is
provided by an independent secondary power source produced by a secondary voltage power
supply. The input voltage of the power supply is 220V. The output voltage is 15V, and the output
power is about 15W.
 Figure 25: Schematic diagram of primary and secondary power supplies
Control Circuit Design:
The main control microprocessor, as an important part of the multiple stage converter
control system, needs to have the following functions:
1）Can realize information display.
2）It can realize signal acquisition and A/D conversion.
3）I/O port can output PWM control signal.
4）Provide a reference clock for the control system.
Given the above tasks, the application requirements are summarized as: The number of I/O
pins is greater than 60, Can complete digital signal processing, and has a relatively high-
precision ADC converter. To meet system functional requirements, after comparing a variety of
microprocessors and finally selected ARTIX-7 FPGA DEVELOPMENT BOARD AX7035,
Build the software project of system control with Xilinx Vivado Design Suite HLx Editions
2018x64 software as the platform. Unlike existing products, its unique advantage is reflected in
the applicability of FPU and DSP instruction sets to digital signal control; it can realize efficient
processing of different digital signals. The excellence of FPGA is reflected in the following
aspects [28]:
1）Xilinx ARTIX-7 Series FPGA Chip XC7A35T-2FGG484I with 484-Pin
2）A large-capacity 2Gbit (256MB) high-speed DDR3 SDRAM can be used as a buffer for
FPGA chip data
3）A 50Mhz active crystal onboard provides a stable clock source for the FPGA system
4）2-channel 40-pin expansion port (Reserve 2 40-pin 2.54mm pitch expansion ports,
which can be connected to various ALINX modules (binocular camera, TFT LCD screen, high-
speed AD module, etc.). The expansion port contains 1 channel 5V power supply, 2 channel
3.3V power supply, 3-way ground, 34 IOs port).
5）It has 6 LEDs, 1 power indicator, 1 DONE configuration indicator, 2 serials transmit
and receive indicators, 4 user LEDs.
6）It has 4 user keys and 1rest key.

MOSFET Drive Circuit Design:

The drive circuit is the key link between the primary and control circuits; it plays a vital role
in the conversion process of the control signal and switches signal. MOSFET (irs2186) drive
circuit can realize input signal amplification, Functions such as increasing the steepness of the
leading and trailing edges of the pulse So that the MOSFET can be turned on and off usually.
When the driving circuit applies a positive bias between the gate and the emitter, The MOSFET
is turned on. Turn-on time and on-state voltage drop decrease with the increase of +VGE, the
turn-on loss, and on-state loss can be reduced within a specific range. When the load is short-
circuited, short-circuit current obtained increases with the increase of +VGE; simultaneously, the
time that the MOSFET bears the short-circuit current becomes shorter. Therefore, the
recommended value is +15V after careful consideration.
According to the selected MOSFET module, this article sets the MOSFET dedicated driver
chip IRS2186, to design the corresponding drive circuit; the chip can drive MOSFET below
4A/600V. By controlling the peripheral circuit of the IRS2186 chip, the blind zone time of the
drive signal, the soft turn-off speed, and the restart time after a fault can be adjusted. The
collector-emitter voltage threshold can also be changed by fine adjustment of the resistance [29].
Therefore, the chip has short-circuited protection and over-current protection functions. The
IRS2186 chip has a total of 8 pins; the functions of each pin are shown in Table 4. Figure 26
shows the pin diagram of the IRS2186.

Figure 26: IRS2186 chip external pin diagram

Table 4: Effect of Inductance to the APF
Pin
Pin Function Pin Number Pin Function
Number

Logic input for high side gate Low side and logic fixed
1 5
driver output supply

Logic input for low side gate High side floating supply
2 6
driver output return

3 Low side return 7 High side gate drive output

4 Low side gate drive output 8 High side floating supply

Calculation of MOSFET Operating Loss Power and Drive Chip Output Power:
MOSFET and Diode Losses:

Power losses PI in any component operating in the switch-mode can be divided into three
groups:
1）Conduction losses (Pc)
2）Switching losses (PSW)
3）Losses due to leaking (Pb), Normally ignored
Therefore, Eqn. (7) is given as follows:
PI  PC  PSW  Pb  PC  PSW (7)

Conduction Losses:

Power loss due to conduction MOSFET resistance can be determined by comparing it to the
drain-source on-state resistance (𝑅𝐷𝑆𝑜𝑛 ) is given in Eqn. (8):
uDS (iD )  RDSon (iD ).iD
(8)
The values of 𝑢𝐷𝑆 and 𝑖𝐷 denote the drain-source voltage and current, respectively. The
usual 𝑅𝐷𝑆𝑜𝑛 value can be determined from the data-sheet diagram, as shown in Figure 27, where
𝑖𝐷 denotes the MOSFET on-state current specified by the application. As a result, the
instantaneous value of MOSFET conduction losses is given in Eqn. (9):

RDS(on),
Drain-to
-Source
On
Resistan
ce (m)

Figure 27: Drain Current and On-Resistance

pCM (t )  uDS (t ).iD (t )  RDSon .i 2 D (t ) (9)

The average value of the MOSFET conduction losses is determined by integrating the
instantaneous power losses throughout the switching cycle 𝐼𝐷𝑟𝑚𝑠 ; on-state current rms value is
given in Eqn. (10):
 1 Tsw 1 Tsw
PCM 
TSW 
0
P
CM
(t )dt 
TSW 0
(R
DSon
.i 2 D (t ))dt  RDSon .i 2 Drms (10)

Check the datasheet of IRFB7545PbF to get 𝑅𝐷𝑆𝑜𝑛 =6.3mΩ, 𝐼 2 𝐷𝑟𝑚𝑠 =2.8A, Therefore,
P≈0.049W.
Turn-on Transient Loss Calculation:

1）The driver circuit switches from 0V to 𝑈𝐷𝑟 , at which point the gate voltage increases to
the threshold voltage (𝑈𝐺𝑆(𝑡ℎ) ), with the time constant specified by the gate resistor and the
corresponding MOSFET input capacitance (𝐶𝑖𝑠𝑠 = 𝐶𝐺𝐷 + 𝐶𝐺𝑆 ). The output remains constant
until the gate voltage hits the 𝑈𝐺𝑆(𝑡ℎ) .
2）After reaching 𝑈𝐺𝑆(𝑡ℎ) , the drain current increases and takes over the load current. The
free-wheeling diode continues to conduct throughout the current increase period, and the drain-
source voltage remains 𝑈𝐷𝐷 .
3）To turn off the diode, all minority carriers must be eliminated. The MOSFET must
absorb this reverse-recovery current, resulting in further power losses. The worst-case reverse-
recovery charge (𝑄𝑟𝑟 ) and duration (𝑡𝑟𝑟 ) values that will be utilized to calculate power loss.
4）After the diode is turned off, the drain-source voltage decreases from 𝑢𝐷𝑆 = 𝑈𝐷𝐷 to
𝑢𝐷𝑆 =𝑅𝐷𝑆𝑜𝑛 𝐼𝑜𝑛 . The Miller effect occurs, resulting in the clamping of the gate-source voltage at
𝑢𝐺𝑆 = 𝑈(𝑝𝑙𝑎𝑡𝑒𝑎𝑢) . Drain-source voltage slope is determined by the gate current flowing via the
gate-drain capacitance 𝐶𝐺𝐷 = 𝐶𝑟𝑠𝑠 . To calculate the voltage fall-time (tfu) with acceptable
precision, it is necessary to account for the gate-drain capacitance's non-linearity. This kind of
non-linearity is difficult to integrate into engineering equations. That is why we utilize a two-
point approximation. If the drain-source voltage is in the range 𝑢𝐷𝑆 ∈[𝑈𝐷𝐷 /2,𝑈𝐷𝐷 ], it is assumed
that the gate-drain capacitance has the value 𝐶𝐺𝐷1 = 𝐶𝐺𝐷 (𝑈𝐷𝐷 ).If the drain-source voltage is
within the range 𝑢𝐷𝑆 ∈ [ 0𝑉, 𝑈𝐷𝐷 /2 ], the gate-drain capacitance is equal to 𝐶𝐺𝐷2 =
𝐶𝐺𝐷 (𝑅𝐷𝑆𝑜𝑛 𝐼𝑜𝑛 ) . The drain-source voltage during the fall period is using the two-point
approximation. Given that this approximation is utilized solely to calculate the voltage fall time
(as well as the rise time during switch off) and that the drain-source voltage is assumed to be
linear, it is apparent that this analysis represents the worst-case scenario for calculating switching
losses.
Calculate the gate current during 𝑡𝑓𝑢 is given in Eqn. (11):
U Dr  U ( plateau )
I Gon  (11)
RG
The voltage fall time can now be calculated as a median of the fall times defined through
the gate current and the capacitances 𝐶𝐺𝐷1 and 𝐶𝐺𝐷2 is given in Eqn. (12) (13) and (14):
 tfu1  tfu 2
tfu  (12)
2
Where;
tfu1  U DD  RDSon .I Don )
CGD1
I Gon
 
 U DD -RDSon .I Don .R G .
CGD1
U Dr  U ( plateau )
(13)

tfu 2  U DD  RDSon .I Don )

CGD 2
I Gon

 U DD -RDSon .I Don .R G .  CGD 2
U Dr  U ( plateau )
(14)

Turn-off Transient Loss Calculation:

The switch-off procedure is identical to the MOSFET's switching-on operation in reverse

order and will therefore not be described in depth. There are two critical distinctions [30]:
1）No reversal of fortune occurs.
2）The gate current and the time required for the voltage to increase can be represented in
Eqns. (15) (16) (17) and (18):
U ( plateau )
I Goff   (15)
RG
tru1  tru 2
tru   (16)
2
C C
tru1  (U DD  RDSon .I Don ) GD1  (U DD  RDSon .I Don ).RG . GD1 (17)
I Goff U plateau
CGD 2 C
tru 2  (U DD  RDSon .I Don )  (U DD  RDSon .I Don ).RG . GD 2 (18)
I Goff U plateau

Switching Energies and Losses:

According to earlier discussions [31], the worst-case turn-on energy losses in power
MOSFETs (𝐸𝑜𝑛𝑀 ) may be computed as the total of the switch-on energy without regard for the
reverse recovery process ( 𝐸𝑜𝑛𝑀𝑖 ) and the switch-on energy produced by the free-wheeling
diode's reverse recovery (𝐸𝑜𝑛𝑀𝑟𝑟 ) is given in Eqn. (19):
tri tfu
tri  tfu
EonM  
0
uDS (t ).iD (t )dt  EonMi  EonMrr  U DD .I Don .
2
 Qrr .U DD (19)

The reverse-recovery current peak can compute in Eqn. (20):

2Q
I Freepeak  rr (20)
trr
The diode's turn-on energy is mostly comprised of reverse-recovery energy (𝐸𝑜𝑛𝐷 ) is given in
Eqn. (21):
 tri tfu
1
EonD  
0
uD (t ).iF (t )dt  EonDrr  Qrr .U Drr
4
(21)

Whereas 𝑈𝐷𝑟𝑟 is the reverse recovery voltage across the diode. This voltage can be
approximated in the worst-case scenario by a supply voltage. [32] Similar calculations may be
made for the MOSFET's switch-off energy losses. Normally, the diode's switch-off losses are
ignored. Therefore, in Eqn. (22) is given as follows:
tri tfu
tri  tfu
EoffM  
0
uDS (t ).iD (t )dt  U DD .I Doff .
2
(22)

In MOSFETs and diodes, switching losses are calculated as the product of switching energy
and switching frequency is given in Eqns. (23) and (24):
PswM  ( EonM  EoffM )  f sw (23)
PSwD  ( EonD  EoffD ). f sw  EonD . f sw (24)

Loss Balance:

Power losses in MOSFETs and free-wheeling diodes can be calculated as the total of
conduction and switching losses is given in Eqn. (25) as follows:
PM  PCM  PswM  RDSon .I 2 Drms  ( E onM  EoffM ). f sw (25)

PD  PCD  PswD  uD 0 .I Fav  RD .I 2 Frms  E onD . f sw (26)

Performance Test of Low Voltage Multiple Stage Converter:

Output Characteristics of Low-Voltage Multiple Stage Converter:

The prototype of the multiple-stage converter is shown in Figures 4-6. The total number of
sub-modules N=10, Sub-module capacitance Cc =5F. Sub-module capacitor voltage under the
condition of output voltage f =50Hz, the typical waveforms for 5 and 21 level output by the
converter of the simulation and hardware with filter and without filter are shown in Figure 28.
 Figure 28: Drive circuit input and output waveforms
Since the number of sub-modules is 10 each unit capacitor is charged to 5V, the peak-to-
peak voltage of the output waveform can reach 45V [33]. By increasing the number of sub-
modules in the main circuit or increasing the voltage value on the capacitor of each sub-module,
the output voltage value can be further increased. By accelerating the switching frequency of the
MOSFET in programming, a higher operating frequency can be achieved. The upper limit
operating frequency of MOSFET depends on the performance of the control chip when the
control algorithm is executed [34]. In addition, switching devices with faster turn-on/turn-off
processes also help to achieve higher performance.
As shown in figures 29 (a,b), 30 (a,b), 31 (a,b) and 32 (a,b) the THD of the 5-level and 21-
level with filter and without filter, respectively. The hardware results are near to the simulation
results, table 5 is the comparison of the hardware and simulation results for 5 and 21-level
multiple-stage converter [35].

(a) without filter (b) with filter

Figure 29: 5-level (simulation)

(a) without filter (b) with filter

Figure 30: 5-level (hardware result)

(a) without filter (b) with filter

 Figure 31: 21-level (simulation)

(a) without filter (b) with filter

Figure 32: 21-level (hardware result)
Table 5: Comparison of experimental results
HARDWARE SIMULATION

5-level 5-level

Without filter With filter Without filter With filter

Voltage 8.24 11.8 8.93 11.55

THD% 25.08 1.63 21.95 5.61

21-level 21-level

Without filter With filter Without filter With filter

Voltage 41.63 39.8 42.35 54.87

THD% 13.62 1.47 13.15 5.56

Conclusion:
This paper analyzed the three different PWM techniques, namely PD-SPWM, CPS-SPWM,
and NLM strategy for MMSC converter. The performance of three different methods is analyzed
individually for 5,7,9,11,13,15,17,19, and 21 level MMSCs, and results are presented. The
results are compared in terms of output voltage and %THD for all levels using three methods. It
is clear from the result that the NLM PWM method offers a better solution than PD-PWM and
CPS-PWM. Moreover, the output voltage is increased from 33.45V to 42.24V for a 21-level
MMSC. The harmonic content also reduced from 32% to 13% for 21-level MMSC using the
NLM method. The nearest level modulation can increase the number of output levels
exponentially without adding sub-modules, and the output harmonics can be significantly
improved. The MMSC has been pointed to as a potential contender in high power transmission
systems. In high power systems, the performance of the converter plays a vital role. Therefore,
the improvement of high-power transmission systems in the converter stage has become more
important. The hardware is designed and selects the power switching devices, main control
microprocessor, isolated drive circuit of power switching devices, etc., and optimizes the design
and other characteristics of the device, and finally builds a prototype converter for large scale
energy storage. The output characteristics of the converter, the effect of dead time on the output
waveform, and the strategy based on the nearest level modulation strategy are experimentally
studied, and the switching characteristics of the converter waveform control strategy are
obtained.
Following is the brief point of this chapter
1）Researched the drive system of power switching devices, the signal output terminal of
the microprocessor is isolated from the main circuit by the isolator.
2）A multiple-stage converter prototype with a total number of sub-modules of N=10 was
built, and also designed a single-stage high voltage h-bridge converter.
3）The final performance test of the prototype of the developed multiple-stage converter
was carried out, the results show that it can work stably at the working voltage peak-to-peak
value of 45V and a fundamental frequency of 50Hz, and it can realize the flexible adjustment of
the output waveform, output level number, and output frequency.

Declarations

Availability of data and materials

Data sharing not applicable to this article as no datasets were generated or analysed during the
current study.

Competing interests

The authors declare that they have no competing interests.

Funding

No funding received by any government or private concern.

Author’s contribution:

R.R contributed to technical and conceptual content, architectural design.V.S contributed to

guidance and C.K counseling on the writing of the paper.

Acknowledgements

Not applicable.

References:

[1] N M Kumar, M P Subathra, J E Moses. On-grid solar photovoltaic system: components, design
 considerations, and case study [C]. IEEE International Conference on Electrical Energy Systems,
Chennai, India, 2018.
[2] PRM Junior, Optimum Design of Modular Multilevel Converters for Variable-Speed Electrical
Drives [D]. 2021.
[3] M Ahmed, M Bilal, and M Mudassar, Specialized cascaded multilevel inverter for distributed
generation [J]. International Journal of Renewable Energy Engineering IJREE, 2021.
[4] M V Kumar, A New Multilevel Inverter [M]. 2019. 151-188.
[5] M Ghias, A M Yusuf, Tang, et al., Hybrid Multilevel Converters [C]. The Annual Conference of the
IEEE Industrial Electronics Society, Lisbon, Portugal, 2019.
[6] B Nasir, Power Electronics [M]. 2021.
[7] A Rehman, Modern Power Electronics Converter Technologies [M]. 2018.
[8] S Chakraborty, S Maiti, A Novel Modular Multilevel Converter for Medium Voltage Variable Speed
Induction Motor Drives [C]. Annual Conference of the IEEE Industrial Electronics Society, Lisbon,
Portugal, 2019, 1: 6049-6054.
[9] Kucuk, F. and T. Nakamura Low-Cost Permanent Magnet-Assisted Switched Reluctance Motor for
Adjustable Speed Drive Applications [J]. IEEE Transactions on Electrical and Electronic
Engineering, 2020.
[10] I Zyubin, S Pankratov, A Petrov, et al., The Use of Variable Frequency Drives of Centrifugal Pumps
atthe Pumping Station [C]. IOP Conference Series: Materials Science and Engineering, Moscow,
Russia, 2020. 779: 012008.
[11] J Büdel, J Teigelkötter, A Stock, et al., Qualification and verification of high-power battery systems
for traction application [C]. European Conference on Power Electronics and Applications, Warsaw,
Poland, 2017, 1-10.
[12] P. Gaur, Y P Verma, P Singh, Design and Implementation of an Asymmetric Cascaded H-bridge
Fifteen Level Inverter with Minimum Number of Switches for Smart Grid Applications [C]. IOP
Conference Series: Materials Science and Engineering, Punjab, India, 2021, 1033.
[13] K Kalyan, A Ojha, R Singh, Applications of Multilevel Inverter for Grid Integration of Renewable
Energy Sources [C]. International Conference on Electrical Energy Systems (ICEES), Chennai,
India, 2021, 206-211.
[14] C Gopinath, M Rajvikram, A Pathway to Explore the Hidden Specialty in the Design of Fifteen
Level Inverter in Grid Connected PV System [J]. Computer Modeling in Engineering and Sciences,
2019. 115: 359-386.
[15] Khan, M S Ullah, Multilevel Converter–based Wind Power Conversion [M]. Advanced Multilevel
Converters and Applications in Grid Integration, 2018. 413-432.
[16] P Poblete, J Pereda, F Nunez, et al, Distributed Current Control of Cascaded Multilevel Inverters
[C]. IEEE International Conference on Industrial Technology, Melbourne, Australia 2019. 1509-
1514.
[17] A Singh, Hybrid Cascaded H-bridges Multilevel Motor Drive Control for Electric Vehicles [J].
International Journal for Research in Applied Science and Engineering Technology, 2020. 8: 553-
556.
[18] S Singh, R Gupta, S Rajasekar, Grid Connected Cascaded Multilevel Inverter for Photovoltaic
Application [C]. International Conference on Energy Efficient LED Lightening and Solar
Photovoltaic System, Kanpur, India, 2020.
[19] A Tomar, G Shrivastava, Editorial: Grid Integration of Renewable Energy Sources [M]. 2020. 13: 6-
 7.
[20] Xiu-Juan Ma, Jia-Yi Teng, Hua-Qiang Zhang, et al., Circulating Current Suppression Strategy of
Modular Multilevel Converter [J]. International Journal of Engineering Research & Technology,
2018, Volume 07, Issue 03.
[21] L Dejun, B Liming, L Wenqi, et al., The research on control strategy of cascade STATCOM [C].
Chinese Control and Decision Conference (CCDC), Shenyang, China, 2018, 4171-4176.
[22] A H Bhat, V Muneer, A Firdous, et al, Performance Investigation of Nine-level Cascaded H-bridge
Inverter Based STATCOM for Various Power System Applications [J]. International Journal of
Industrial Electronics and Drives, 2018.
[23] N Rode, S Gaigowal, P Patil, Cascaded H-Bridge Inverter based PV-STATCOM [C]. International
Conference on Smart Electric Drives and Power System, Nagpur, India, 2018. 99-104.
[24] A Christe, IA Polanco Lobos, et al., Auxiliary Submodule Power Supply for a Medium Voltage
Modular Multilevel Converter [J]. CPSS Transactions on Power Electronics and Applications, 2019.
4: 204-218.
[25] S Haq, SP Biswas, MK Hosain, et al. A Modular Multilevel Converter with an Advanced PWM
Control Technique for Grid-Tied Photovoltaic System [J]. Energies, 2021. 14: 331.
[26] D Chen, B Le, N Mei, et al., ±320kV Xiamen Bipolar Flexible HVDC Project System Design [J].
Automation of Electric Power Systems, 2018, 42(14): 180-185.
[27] I Mayergoyz, S Tyagi, Pulse Width Modulation in Power Electronics [M]. 2021.
[28] F Alsokhiry, Y Al-Turki, I Abdelsalam, et al., Multi-port Converter for Medium and High Voltage
Applications [C]. 7th International Conference on Renewable Energy Research and Applications,
Paris, France, 2018. 150-155.
[29] Z Lim, Active Neutral-Point-Clamped Inverter [M], 2018, 275-318.
[30] R Tiwari, R Nilsen, A Nysveen, Active NPC Converter for Variable Speed Operation of Pumped
Storage Hydropower Plant [J]. Annual Conference of the IEEE Industrial Electronics Society, 2020,
1211-1216.
[31] Q Cheng, C Wang, Z Chen, et al, A Capacitor Voltage Balancing Method Based on Optimal Zero
Sequence Voltage Injection in Stacked Multicell Converter [J]. IEEE Journal of Emerging and
Selected Topics in Power Electronics, 2020, 1-1.
[32] L.Ashok Kumar, S.Albert Alexander, Madhuvanthani Rajendran, Inverter topologies for solar PV
[M]. 2021, 1-39.
[33] J Rodriguez, LG Franquelo, S Kouro, et at, M. Multilevel Converters: An Enabling Technology for
High Power Applications [J]. Proceedings of the IEEE, 97(11), 2019.
[34] B Li, R Yang, D Xu, et al, Analysis of the Phase-Shifted Carrier Modulation for Modular Multilevel
Converters [J]. IEEE Trans. Power Electron. 2018, 30, 297–310.
[35] G Konstantinou, M Ciobotaru, V Agelidis, Selective harmonic elimination pulse-width modulation
of modular multilevel converters [J]. IET Power Electron. 2019, 6, 96–107.