IEEE ISIE 2006, July 9-12, 2006, Montreal, Quebec, Canada
DC Link Balancing Method in Back-to-Back
System with Multi-Level Converters
Lech M. Grzesiak, Jacek Tomasik
Warsaw University of Technology
Institute of Control and Industrial Electronics
Warsaw 00-662, Poland
Email: L.Grzesiak@isep.pw.edu.pl, tomasikjgwebmail.co.za
Abstract- Paper presents a novel topology of a grid-connected
back-up uninterruptible power supply (UPS) system with multi-
level converters. The star-configuration three-phase "back-to-
back" topology with a five-level diode-clamped rectifier (5LDCR)
and a five-level diode-clamped inverter (5LDCI) supplies a three
phase output load. The proposed multi-level current mode
control techniques in both converters provide an effective
solution to an imbalance problem with the capacitor voltages in a
dc link network. The interfaced battery energy storage (BES),
which constitutes an integral part of the entire UPS system,
supplies the dc link capacitor voltages to the 5LDCI in a standby
emergency mode because the proposed balancing method is
constrained to the "back-to-back" operation only. Importantly,
the UPS system is able to operate with an asymmetrical, a
nonlinear and an impact loads in three phases and it provides the
power factor correction on the grid side.
I. INTRODUCTION
In a modern electrical energy conversion the back-up system
plays a very important role. It not only facilitates a transfer of
an electrical energy from an input to the output but it also
conditions the characteristics of the source in such a manner
that the output characteristics are equal to those required by
the standards of a utility and the appliances connected into it.
Thus it can also serve as an interface between the utility and
compensate for undesirable effects such as: unbalanced loads,
nonlinear loads, impact loads which can cause the dips or a
harmonic distortion in the utility. Many applications were a
result of such a research in this field, predominantly with the
standard two-level converters incorporated in such systems
[1], [2], [3], [4]. With an advent of the multi-level converter
technologies the UPS system can be further explored with a
potential of increasing power levels, especially in a medium
and a high voltage applications. Moreover, the advantages of a
multi-level modulation over a conventional two-level one e.g.
[5], [6] make such a system an attractive alternative. Therefore
one of the goals of this paper was to introduce a new structure
of a back-up system with an extension to the multi-level
converters based on the five-level diode clamped topology.
In an ac-dc-ac energy conversion, generalized with a multi-
level diode clamped topology, the capacitor imbalance
problem can be handled in two ways: firstly, via supplying a
particular voltage level from an isolated winding transformer
and a four full-wave bridge rectifiers, whereas a primary is
interconnected with the input ac-side or secondly, via a back-
1-4244-0497-5/06/$20.00 C 2006 IEEE
UPS
to-back connection of a front-end ac-dc multi-level converter
with a back-end multi-level dc-ac converter.
The first solution is impractical from a size-wise and a cost
point of view [7] and additionally the system without a power
factor correction generates a non-negligible amount of
harmonics which are restricted by the utility regulations.
The second alternative solution many-times reported in a
literature e.g. [8], [9] seems to be a suitable one since it was
shown in an operation with the back-end active-rectifier
interfaced to a constant frequency mains and a fixed-input
voltage of the standard utility. The front-end constitutes a
voltage source inverter which generates a set of symmetrically
loaded voltages for a variable speed drive (VSD) operation.
The back-end boost active-rectifier with power factor
correction (PFC) on an input-ac side, meets a criteria of the
utility regulations in an aspect of the harmonic distortion.
Entire converter system operates in a four-quadrant mode with
the front-end voltage source inverter feeding an ac-drive with
a capability to regenerate the energy back to the utility.
II. SYSTEM TOPOLOGY
The proposed concept in this paper is different from the
above mentioned in terms of energy conversion, a control
strategy used and its application. The main focus of realization
here is the modified discrete delta modulation scheme which
provides the set of balanced voltages across capacitors in the
dc bus network. The diagram of the proposed system is shown
in the Figure 1. The following assumptions were made in a
definition of the new back-to-back UPS system concept:
* The five-level diode-clamped rectifier (5LDCR) is
supplied from the grid and neutral leader is connected
with a centre-tap of the dc-link network.
* The five-level diode-clamped inverter (5LDCI) is
supplied from the dc-link voltage which is conditioned by
the 5LDCR and the neutral leader of the output is
accessible.
* The 5LDCI is capable to operate with the balanced loads
(symmetrical phases) or with a fully unbalanced loads
(asymmetrical phases) in each phase individually, whereas
an imbalance should not affect the output voltage
regulation.
* The neutral leaders of the grid as well as of the output
load in the 5LDCI are connected with the centre-tap of the
908
 split dc link network, so that a path for an unbalanced
current flow is created. Therefore, the neutral leader is
referenced to the zero of a star.
* The proposed power generating system can be either
interfaced with a utility or used as an autonomous back-up
UPS system.
In an imbalanced load applications with a conventional two-
level [4], [12] or a multi-level [13] inverting systems, it has
been accepted that the neutral current flow effect must be
compensated. It can be achieved using two solutions: a split-
capacitor dc link, where the voltages need to be stabilized
across an upper and a lower half of the capacitor bank and in
this case a voltage ripple is handled by the capacitors or a four-
legged topology, where the neutral current flow is handled by
an additional inverter leg. In any event, either the larger
capacitors are required or an additional phase-leg is required.
In the proposed concept, due to connection of the neutral
leaders in the system, the neutral current flow can be handled
by both converters. Moreover, the inherent problem with the
voltage imbalance across four dc-link capacitors is much
simplified and the additional hardware in form of the balancer
circuit [10], [11] or the fourth leg in the 5LDCI can be
PHASAEG OF 5LDC R15LDC1
'wI
STEP STEP-DDWN CHOPP ER
AL DI wilh BATTE RY ENERGY STORAGE
D4 .. ...i
;t..
EEEER
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Fig. 1 Grid-connected back-up system with multi-level converters.
909
omitted. Inclusion of the 5LDCR on the mains side (grid)
provides the PFC. In consequence the quasi-sinusoidal
currents are drawn from the grid which further mitigates the
harmonic emission.
It has been revealed in [8] that a back-to-back structure with
the five-level diode clamped topologies is not a "self-
balancing structure". Thus, it is not possible to attain the
capacitor balancing in all the operating conditions without the
interference on the control signals.
Further, it can be achieved by adjusting the commutation
angles in both controllers on the 5LDCR side and on the
5LDCI side respectively [8], or via a proper selection of
redundant states in the SVM or via adding a certain amount of
DC offset to the control signals in both converters [7].
In the proposed power generating system the interface is made
with the BES 1:4 through the step-up/down choppers
SUI 4/SD1 4. Therefore the voltages across each of the
capacitors can be sensed and fed-back to the five-level
modulators on the 5LDCR side and on the 5LDCI side. These
can further be used to modify the switching decisions in the
controllers thus providing a new balancing scheme.
eirflctiow
pow
1i
o
~- *
i;
-. 2
.. ~ ~ M 3 Vd..
I -
4 v_
 III. STRATEGY OF BALANCING FOUR DC LINK VOLTAGES ex inv (k) Kinv VX
=
out (k) vx -out(k)] ix-inv(k), (3)
In order to maintain all four dc link capacitor voltages equal, where:
then the average DC currents flowing into the nodes 1,2,3,4,5 ex inv iS instantaneous value of the error signal in the 5LDCI controller, v*. out
on the 5LDCR side must be equal to the average DC currents and vx out are instantaneous values of the reference and the actual output
voltage respectively, Kinv is voltage loop gain, ix/inv is instantaneous value of
drawn out from the same nodes on the 5LDCI side [8]. The the inductor phase current in the 5LDCI, k is sampling step in DSP.
proposed balancing strategy relays on detection of the
instantaneous potentials in the nodes 2 and 4 which are Analogically, definition of the five-segment switched
derived from the differences between the respective capacitor waveform in the 5LDCI, which is determined by the control
voltages, whereas an adequate modification is made to the error in (3), is derived from:
multi-level modulators in both converters. The dc link voltage (4)
on the 5LDCR is regulated at the desired level v*dc via feeding
back the actual dc link voltage signal Vdc to the proportional a) Positive output 2
< vx inv (k) < 4

controller, therefore the potentials in nodes 1 and 5 are 0)1

inherently controlled. The node 3 constitutes a reference point iex > A1 > (SW2x(k + 1) =1 )& (SW5x(k + 1)
inv (k)
to control the upper two voltages (vdc] and Vd,2) and the lower ex inv(k) < A1 > (SW2x(k + 1) = 0 ) & (SW5x(k + 1)
two voltages (Vd,3 and Vd,4) and it handles the unbalanced load
current (neutral current). The discrete control law for a b) Positive output( 4C< vx inv(k)<OJ0
generalized anyone phase (x=a, b, c) of the 5LDCR is given
by: ifex inv (k) > A2 (SW 2X(k + 1) = 1I) & (SW 6x(k + 1) =i)f
lex inv(k) < A2 ='(SW 2x(k + 1) = O ) & (SW 6x(k + 1):
e, rec(k) = Krec[v;c(k) - Vdc(k)]vxi,(k) -ix rec(k), (1)
c) Negative output 0<v xinv(k) < DCS
where:
e, rec is an instantaneous value of the error signal in the 5LDCR controller, V*d, iex inv(k) > A3 (SW3x(k + 1) 1 ) & (SW7x(k + 1)
and Vd, are instantaneous values of the reference voltage and actual dc link
voltage respectively, Kre is voltage loop gain, vi is instantaneous value of
the phase-to-neutral voltage from the grid and ix rec is instantaneous value of
ex inv(k) < A3 = (SW3x(k + 1) 0 ) & (SW7x(k + 1) = I)f'
the inductor phase current in the 5LDCR, k is sampling step in DSP. d) Negative output(- 4 <Vx inv(k) < VDCj
2)
The definition of the five-segment switched waveform in the Jfexinv(k) > A4 > (SW4x(k + 1) = 1) & (SW8x(k + 1) = 0)
5LDCR, which is determined by the control error in (1), is
derived from: ex inv(k) < A4 > (SW 4x(k + 1) = 0 ) & (SW8x(k + 1) = 1)
(2)
The dc offset displacements in control scheme without the
a) Positive output L 2 < Vx (k) < 4 capacitor balancing strategy are defined by:
rex(k) > B, (SW1x(k+1) = 1 )& (SW 5x(k +1) 0)1 tA1
I

if
> B1 +2A,
rex(k) < B, > (SW1x(k+1) = )& (SW5x(k +1) 1) A2 B2 (5)
A3 B3 -A,
b) Positive output v<Vxre (k) < :
A4 B4 -2A,
ex rec (k) > B2 > (SW 2x(k + 1) )& (SW 6x(k + 1) 0) where:
lex rec (k) < B2 > (SW 2x(k + 1) 0 )& (SW 6x(k + 1) 1){ A is a constant determined from normalized dc link voltage: A=VDC/8.

c) Negative output 0 < Vx e,(k)< 4

In the Figure 2 there are shown non-modified multi-level
comparators for the 5LDCR/5LDCI respectively. In such
if reC(k) > B, i>(SW3x(k+1) =1)& (SW7x(k+1) -0)1 mode, the absolute balancing of the four dc capacitor voltages
=1)f' is not possible in an entire load range and a modulation index
Lex reG(k) <B3 =
(SW3x(k+1) = 0 )& (SW7x(k+1)
range as it was shown in [7], [8], [9]. Let the differences
Negative output 4 <Vx_rec(k) <- 2V :)J between the upper two and the lower two capacitor voltages
be defined as:
f rex (k) > B4 >(SW4x(k+1) =1 )&(SW8x(k+1)
AvdC 12 (k) = Vdc (k) V dc 2 (k),
lex reG(k) <B4 > (SW4x(k+1) = 0 )& (SW8x(k+1) = 1) . AvdC 34 (k) =V dc 3 (k) V dc 4 (k),
(6)
Similarly, the discrete control law for a generalized anyone where:
phase (x=a, b, c) of the 5LDCI is given by: JVdc]2 and JVdd34 are instantaneous values of the dc offsets describing potential
variation in the nodes 2 and 4 respectively.

910
 Non-modified operation of 51LDCRJ5LDCI simultaneously with a complementary pair of the devices
SW2x & NOT(SW6x) they altogether will be switching
between the voltage 0 and VDC/4.
-r-
In consequence, a falling positive potential in the node 2
(referenced to the node 3), which results from zVdc]2<0 is
SWix B SW5x suppressed via selecting such switching vectors that they will
0
-d~44 cause a raising of the potential in this node until a condition
II &W AVdc]2 =0 has been reached.
9V2X & §W&x
0
I+A A et In the Figure 3b, if voltage Vdc] is larger than Vdc2 on the
I2AIA
MA
SW x & SW
0 -2A Aef,lX 5LDCI side, then a reference offset A2 is shifted left from a
point A to 0. In result, a complementary pair of the devices
d41 SW2x & NOT(SW6x), which were normally switching between
SWxS x the voltages 0 and VDC/4, now they will only be switching to
I I 2a ;m (x=a,b,c) the voltage VDC/4. In the Figure 4b, under the same condition
on 5LDCR side, a reference offset B2 is shifted right from a
point A to 2A. In result, a complementary pair of the devices
Fig.2 Control scheme without capacitor bal,lancing strategy. SW2x & NOT(SW6x), which were normally switching between
the voltages 0 and VDC/4, now simultaneously with a
Therefore, from comparison between a( two dc link
voltages, the following modifications aire proposed to the iJacent complementary pair of the devices SWJx & NOT(SW5x) they
altogether will be switching between the voltages 0 and VDC/2.
control strategy in the 5LDCI {see the Fig ure 3()d),h
Similarly, in such a case the voltage VDC/4 is never exceeded
satisfy the following conditions: across the both complementary pairs because the clamping
diodes always block the voltage VDC/4. In consequence, a
o A7
tif (Avdl12 (k) < 0) > A1 +A
+
raising positive potential in node 2, which results from
if (AVdC 12 (k) > 0) > A2 (7) AVdc]2>0 is suppressed via selecting such switching vectors
if(Avdc34 (k) < 0) > A3 O that will cause a reversing of the potential in this node until
,if (AvdC34 (k) > 0) > A4 -A condition AVdc]2=0 has been reached.
Analogically, in the Figures 3c, 3d and the Figures 4c, 4d
Similarly, from comparison between tvvo adjacent dc link respectively, the potential in node 4 will be controlled whereas
voltages, the following modifications aire proposed to the the comparators will commutate to the negative rails of the dc
control strategy in the 5LDCR {see thi%,iF- ire -tka)
i,i6ui%, d(. ku)f,
(F1Yr link.
which satisfy the following conditions:
IV. SIMULATIONS
tif (A vdcl2 (k) < 0) > B1 +3A Model of the proposed system was implemented in a PSIM
if (Av dc12 (k) > 0) > B2 +2A (8) package with the following 5LDCR/5LDCI parameters.
if (Av dc34 (k) < 0) > B3 -2A
Input/output phase-to-neutral voltage .................. 230[V]rms
Iif (A v dc34 (k) < 0) > B4 -3A
Input/output frequency .......................... 50[Hz]
Regulated DC link voltage .......................... 750[V]dc
Discussion of the modifications made and their influence on
the charge redistribution between the consecutive voltage The type of load is asymmetrical and every an interval of
levels will follow. In the Figure 3a, if the voltage Vdc is 0.5[s], a new resistive step load is switched on the output of
smaller than the Vdc2 on the 5LDCI side, then a reference offset the 5LDCI. Below, there are compared the simulation results
Ai is shifted left from a point 2A to A. In result, a during the system operation with the modified switching
complementary pair of the devices SWJx & NOT(SW5x), scheme {see the Figures 5(a): 5(e)} versus operation with the
which were normally switching between the voltages VDC/4 free-running modulators {see the Figures 6(a) 6(e)}. In the
and VDC/2, now simultaneously with a complementary pair of Figure 5a is shown a set of balanced voltages across all four
the devices SW2x & NOT(SW6x) they altogether will be capacitors in the dc link network which contain a ripple
switching between the voltages 0 and VDC/2. Note, that in such resulting from an asymmetrical three-phase output load. The
case the voltage VDC/4 is never exceeded across the both dc link regulation is rigid in an entire load range and the
complementary pairs because the clamping diodes always discernible dips result from transients in the step-load changes
block the voltage VDC/4. In the Figure 4a, under the same on the output. In the Figures 5(b) 5(e), there are shown the
condition on 5LDCR side, the reference offset Bi is shifted phase-to-neutral and the line-to-line PWM voltages in the
right from a point 2A to 3A. In result, a complementary pair of 5LDCR/5LDCI respectively. Number of steps in the
the devices SWJx & NOT(SW5x), which were normally waveforms reveals a five-level modulation. In the Figure 6a, it
switching between the voltages VDC/4 and VDC/2, now is evident that the capacitor voltages tend to diverge.

911
 'Adt A3l

c)AVd,34 <0
Modified operation of 5LDCI
a) AVdcl2 < 0 b) AVdcl2 > 0

0 Ai=A 2A

'1
+ J~ ~ ~ ~-
! I '1,''§thlSIC

l...
A4A

d) Av
A L

4
-_J

>0
At=2A
A.
4 Inv x
B4B~
a) AVcl2

C) AVdc34
+
Modified operation of 5LDCR
<

1]d
0

0 B2zA

<0
1
0

d
Ae
Pet,0
b) Av&12 > 0

d) AV&4> 0
I
8-2
...................
~~~~~Ael

A4-2A A3=OAe. 2A At4=- _ B'- 2A -A B4=-3A Biz-A o

ro 4<
A2 Ai 0 A2 Ai o 08B2 Bi 0li~ 0OBBi
-Fk4 ~~ ~ ~~~-<
........................

Fig.3 Operation of 5LDCI with capacitor balancing strategy. Fig.4 Operation of 5LDCR with capacitor balancing strategy.

a) Voltages across DC link capacitors a) Voltages across DC link capacitors

Vdcl Vdc2=Vdc3Vdc4-VdcJ4
.................... r pl
Vdc2Vdc3=Vdct2

1 0.00
Vdc2, Vdc3 are increasing
.a V1tag ripple
100 00 Vdicr Vdc4 are decreasing

50§00

0.00 Vdcl WVc40

;W0 0,50 1M0 a 50
Time (s)
va_rec b) Phase-to-neutral voltage in 5LDCR

Va rec
,,040v
rec ,b) Phase-to-neutral voltage in 5LDCR

......................................................................................................................................................................................................................................................

vabfrec ........................
c) Lineto-line voltage in 5LDCR vab fec c) Line-to-line voltage in 5LDCR
V ab r Vab rec

~40K
d) Phase-to-neutral voltage in 5LDCI
............
nva 1d) Phase4o-neutral voltage in 5LDCI

Va Ij VaJ Iv

ab-Olw e) Line-to-line voltage in 5LDCI vab ihv e) Lineto-line voltage in 5LDCI

Vab Vab inv
31.00K4
O1OK
X00X 18MO 183M 185. 1M&O 184.00 8043100 1820 O20
1 131
06H BE
Ti.me (Ms
Fig.5 Simulations of back-to-back system with modified modulators. Fig.6 Simulations of back-to-back system with free-running modulators.

912
The group of voltages Vdc2 and Vdc3 immediately raises
towards a half of the dc link voltage VDC/2, while the group
of voltages Vdc] and Vdc4 decreases until it reaches zero. In the
Figures 6(b) 6(e), there are shown the phase-to-neutral and
the line-to-line PWM waveforms in the 5LDCR/5LDCI,
without a balancing scheme implemented. It is evident that
in this scenario, number of steps in the switched PWM
waveform remains smaller than in the previous case. It
implies, that if there is no correct balancing scheme used,
then a five-level modulation takes a format of the three-level
modulation and the control becomes incorrect.
V. EXPERIMENTAL RESULTS
Prototype of the back-to-back UPS system with the
proposed control strategy was implemented in Motorola
DSP56807EVM. The PWM waveforms of the phase-to-
neutral and the line-to-line voltages in the 5LDCR/5LDCI
are shown in the Figure 8. The dc link four balanced
capacitor voltages are shown in the Figure 9.
Fig.7 Experimental waveforms from top down:
(1) - trace of phase-to-neutral PWM voltage in 5LDCR.
(2) - trace of phase-to-phase (line) PWM voltage in 5LDCR.
(3) - trace of phase-to-neutral PWM voltage in 5LDCI.
(4) - trace of phase-to-phase (line) PWM voltage in 5LDCI.
1) [Tek TDS2000 Series].,CHI 20 V 60 r
}3 [Tek TDS2000 Seriesj.ECH3 20 V 50 s Control, H-Bridge Tri-Level Inverter For Power Quality
f4 [~eI FDS2pO0,Seriesj]Crj 29 V.~ I Ir9s
Fig. 8 Experimental waveforms of voltages across the four dc-link
capacitors regulated at VDC REF=440 [V] i.e. 4 1I1IO[V] dc.
913
VI. SUMMARY
In this paper a new topology of the back-up system with
the multi-level converters has been presented. The proposed
control strategy which forces balancing of four dc link
capacitors has been given. Effectiveness of the strategy has
been verified in the simulations, whereas comparison has
been made between the proposed and the free-running
method. The experimental tests performed on the laboratory
model, has proven the concept. In conclusion, the proposed
multi-level back-to-back system can be used in medium or
high voltage UPS applications.
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