ECE3111 Mid-Term Content

Overview of 8086 Microprocessor
8086 Microprocessor is an enhanced version of 8085 Microprocessor that

was designed by Intel in 1976. It is a 16-bit Microprocessor having 20
address lines and 16 data lines that provides up to 1MB storage. It consists
of powerful instruction set, which provides operations like multiplication
and division easily.
The most prominent features of a 8086 microprocessor are as follows −
✓ It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
✓ It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal
data bus, and 16-bit external data bus resulting in faster processing.
✓ It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
✓ Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue.
✓ Execute stage executes these instructions.
✓ It has 256 vectored interrupts.
✓ It consists of 29,000 transistors.
How the ALP is stored in the memory chip and then fetched, decoded & execute is done by the microprocessor
Assembly-level language program Machine-level language program
MOV AX, 2001 D80120H=1101 1000 0000 0001 0010 0000

MOV BX, 2002 BB0220H=1011 1011 0000 0010 0010 0000
ADD AX, BX 03C3H=0000 0011 1100 0011
Assembler software
H00000
0 0 1 0 0 0 0 0 00011H
0 0 0 0 0 0 0 1 00010H
1 1 0 1 1 0 0 0 00001H
00000H
Microprocessor 8086
11011000 Memory chip
Architecture/ Internal Block Diagram of the 8086 (10Marks Theory-Important)
Internal block diagram has been partitioned into two logical units;
ES/DS CS SS
(1) the Bus Interface Unit (BIU) (2) the Execution Unit (EU)
ADDRESS BUS
AH(8) AL(8) AX ෍
BH BL BX Data 20 bits
registers
CH CL CX
DH DL DX segment
ES
SP (16 bit) registers
Address CS
BP(16 bit) 8
registers SS 0
SI(16 bit)
DS 8
DI(16 bit)
IP 6
BUS
CONTROL
B
UNIT
16 bits U
S
TEMPORARY REGISTERS INSTRUCTION QUEUE
EU
ALU CONTROL 1 2 3 4 5 6
UNIT 8 bits
FLAGS
EXECUTION UNIT (EU) BUS INTERFACE UNIT (BIU)
The Execution Unit (EU)
EU contains the arithmetic and logic unit (ALU), the control unit, an internal
bus, plus a few registers
Register sets:
AX AH AL ACCUMULATOR
BX BH BL BASE REGISTER
CX CH CL COUNT REGISTER
DX DH DL DATA REGISTER
SP STACK POINTER
BP BASE POINTER
SI SOURCE INDEX
DI DESTINATION INDEX
IP INSTRUCTION POINTER
FLAGH FLAGL STATUS FLAG
CS CODE SEGMENT REGISTER

DS DATA SEGMENT REGISTER
SS STACK SEGMENT REGISTER
ES EXTRA SEGMENT REGISTER
The Execution Unit
It contains the arithmetic and logic unit (ALU), the control unit, an internal bus, plus a few registers
Register sets:
8086 has four 16-bit general-purpose registers labeled as AX, BX, CX and DX. Each of these registers can also be used as two
separate and exclusive 8-bit registers also i.e., AX has two parts AH and AL, where H and L stands for the high and low portions
respectively.
AX: AL /AX is sometimes called the accumulator, but the relevance of the accumulator is less for 8086 compared to the earlier
8085 in which one operand is implied to be in the A register for many instructions.
BX, CX and DX:
These are the other working registers of the 8086, which means that temporary data storage, arithmetic calculations and data
manipulation can be done with these registers
Base register BX is frequently used as an address register in many based addressing modes.
Counting register CX is used as a counter in many instructions.
Data register DX is used in I/O instructions as a pointer to data by storing the address of the I/O port.
Pointer and Index Registers : SP, BP, SI and DI are address registers, and can be used only as
16-bit registers
BP and SP : They are the Base pointer and Stack pointer respectively. SP always points to the top of the stack, while BP can
point to any location in the stack.
SI and DI These are Index registers, labeled as Source Index and Destination Index respectively.
They function as address registers in various addressing modes
The Execution Unit contd..
Flag Register
It is a 16-bit register, of which 7 bits are unused. 6 bits are used as conditional flags. The
others are control flags. The conditional flags available are the Carry (CF), Zero (ZF), Parity
(PF), Overflow (OF) and the Sign Flag (SF).
conditional flag bits explanation
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
× × × × OF DF IF TF SF ZF × AF × PF × CF
Overflow flag bit: Parity flag bit:

Sign flag bit:
OF=1 if either of these conditions is true: PF=1 if there is
SF=1 if the result
i) there is an overflow into the MSB (8th or even number of
contains a
16th bit) from the bit of lower significance, 1s in lower 8-bits
negative number
but no carry out from the MSB, Auxiliary flag
ii) there is a carry out from the MSB, but Carry flag bit:
Zero flag bit: bit: CF=1 if there is a carry
no carry into the MSB. AF =1 if there
ZF=1 if arithmetic out from the MSB bit
or logic operation is carry from
is zero, bit D3 into D4.
Flag register: Control flag explanation
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
× × × × OF DF IF TF SF ZF × AF × PF × CF
This flag is specifically used Interrupt Flag (I) – This flag Trap Flag (T) –If TF=1, the CPU
in string instructions. is for interrupts. automatically generates an
If DF=1, then access the If IF=1, the microprocessor internal interrupt after each
string data from higher will recognize interrupt instruction, allowing a
memory location towards requests from the program to be inspected as it
lower memory location. peripherals. executes instruction by
If DF=0, then access the If IF=0, the microprocessor instruction.
string data from lower will not recognize any If TF=0, no function is
memory location towards interrupt requests and will performed.
higher memory location. ignore them.
The Execution Unit contd..
Solved Example on carry Flag
Q. Find the status of the flags CF, SF, AF after the following instructions are executed.
MOV AL, 35H
ADD AL, 0CEH
35H 0011 0101
+ CEH 1100 1110
103H 1 0000 0011
CF = 1 since there is a carry out from D7.
SF = 0 since the sign bit (MSB) of the 8-bit destination is 0.
AF = 1 since there is an overflow from D3 to D4.
Example 1.2 Show the effect of the following instructions on the CF, ZF and OF bits of the flag register.
MOV BX, 45ECH
ADD BX, 7723H
Solution: This is the case of 16-bit addition
45ECH 0100 0101 1110 1100
7723H 0111 0111 0010 0011
BD0FH 1011 1101 0000 1111
The sum will be in BX, which is the destination register.
CF = 0 since there is no carry-out from D15. ZF = 0 since the destination is not zero. OF = 1 since there is an overflow into
the MSB D15.
Bus Interface Unit (BIU)
This unit BIU is responsible for address calculations, pre-fetching instructions for the
queue and sequencing instructions one by one.
The Instruction Queue
✓ Instructions are found in memory, from where they are fetched and decoded as and when they need to be
executed.
✓ However in 8086, there is a queue which fetches instructions ahead of the execution time and places them
in a 6-byte first-in-first-out (FIFO) queue. This pre-fetching is done when the buses are free i.e., not being
used for the execution of the current instruction.
✓ The advantage of pre-fetching is that when a particular instruction is to be executed, there is a good chance
of finding it in the queue (which is on-chip), rather than having to go to memory to fetch it.
✓ This pre-fetching belongs to a class of ideas called pipelining, which means that both execution and
fetching take place at the same time i.e., while the execution of one instruction is going on, the fetching of
another one can be done.
✓ Pipelining greatly speeds up processing.

Concept of Pipelining Memory opcode Instructions
address
6-byte pre-fetch queue:
An 8086 microprocessor exhibits the property of pipelining the 2000 06 MOV BL, 78H
instructions in a queue while performing decoding and 2001 78
execution of the previous instruction. This saves the processor
time of operation by a large amount. This pipelining is done in 2002 3E MOV AL,F2H
a 6-byte queue 2003 F2
2004 80 ADD AL, BL
2005 76 HLT
Pre-fetching of next opcode is done
Decode and
execution of first 3E F2 80 76 ---- ----
instruction code 06
78 in ALU 6-byte Instruction queue
EU
BIU
Processor
Memory Segmentation
Segmentation is the process in which the main memory of the computer is logically divided into different segments and each
segment has its own base address. It is basically used to enhance the speed of execution of the computer system so that the
processor is able to fetch and execute the data from the memory easily and fast.
The four-segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments.
Advantages of the Segmentation The main advantages of segmentation are as follows:
❑ It provides a powerful memory management mechanism.
❑ Data-related or stack-related operations can be performed in different segments.
❑ Code related operations can be done in separate code segments.
❑ It allows to processes to easily share data.
❑ It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit registers to give an
addressing capability of 1 Megabytes. Without segmentation, it would require 20 bit registers.
❑ It is possible to enhance the memory size of code data or stack segments beyond 64 KB by allotting more than one
segment for each area.
Memory Segmentation
The stack is used to keep aside address and data
temporarily, when a subprogram is called
Base address Extra segment use to store data in a special way
SS
A0000H
Segment Register
ES These registers are all 16-
90000H A000H SS
bit in size. Each register
9000H ES stores the base address of
7000H DS the corresponding
DS Segment.
70000H 5000H CS
Total 216=65,536=64K address

locations & each location can
CS store 1 byte data
50000H
Data segment use to store data

The code segment contains code only
50000H= 0101 0000 0000 0000 0000 ➔20 bit address
Calculation of a physical address from the logical address for a data segment
Let a data byte is stored in a data segment, whose base address is 22220H.
Then the data segment register (DS) will contain the number 2222H.
The data at any location within this segment is referenced by an offset
(displacement) with respect to the base address.
Thus, if a data at a location has a logical address specified as 2222H : 0016H, the
number 0016H is the off set or displacement with respect to the base address.
Example for physical address calculation see figure given below
Address byte
22236H
-
Physical address -
=22220H + - Data
0016H - OFFSET=0016H (displacement) Segment
22236H
BYTE-2
BYTE-1
Base address
22220H BYTE-0 2222H DS Register
Memory Segmentation contd…
The Code Segment and the Instruction Pointer
✓ The code segment is the area of memory where code alone is stored.
✓ The offsets within the code segment are referenced using the Instruction Pointer (IP),
which is a 16-bit register.
✓ The IP sequences the instructions, and always points to the next instruction to be
executed.
✓ Whenever an instruction byte has to be fetched from memory, the bus interface unit (BIU)
performs the address calculation using the contents of CS register and the IP.
✓ This 20-bit address is then placed on the address bus and the instruction byte is fetched.
Thus the logical address for an instruction bye is of the form CS : IP.
Example Address byte
The contents of the following segment registers are as
-
given. -
CS = 1111H -
IP = 1232H. -
Calculate the corresponding physical addresses for the BYTE-2
addressed byte in a) CS BYTE-1
Base address
Ans: The base address of the code segment is 11110H. 11110H BYTE-0 1111H
The address of the next instruction to be CS Register
executed is referenced by CS and IP which is given by
11110H + 1232H = 12342H.
The Stack Segment and the Stack Pointer
✓ The stack is an area of memory that is used in a special way.
✓ There is a 16-bit register called Stack Pointer (SP) which points to the top of the stack.
✓ The upper 16 bits of its base address is available in the SS register.
✓ A stack address of the form 4466H : 0122H means that the SS register contains 4466H, the
stack pointer (SP) contains the number 0122H, and the physical address of the top of the
stack is 44660H + 0122H = 44782H
✓ The 8086 has a stack which grows downwards (i.e., to lower memory addresses).
✓ Thus the format SS : BP is also a logical address.
The Data Segment and Extra Segment
✓ Both these segments store data, but in certain special cases (string instructions),
it may be necessary to list them separately.
✓ There is an Extra Segment (ES) register to store the upper 16 bits of the base
address of the extra segment.
✓ The offset within the data segment is also termed as an ‘effective address’.
✓ The effective address calculation depends on the mode of addressing.

Table Segments and Corresponding Registers Used for Specifying Offsets
Segment Offset Registers Function

CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Addresses in the stack
ES BX, DI, SI Address of destination data
(for string instructions)
Advantages of Segmentation
1. It allows all address registers to have the same size as the data registers (16-bit),
while allowing the use of 20-bit physical addresses.
2. All addresses in memory are re-locatable. This means that any program or data
can be loaded in any address in memory. A re-locatable program is one which can
be placed in any area of memory and executed without change. Data is also re-
locatable. Changing the base address of the corresponding segment is the only
action we need to perform, in order to re-locate. All addresses within the
program are relative to the base address, as they are of the form Base address:
off set. All processors in the x86 family have this kind of segmentation.
Addressing Modes (10Marks Theory-Important)
For computations in assembly language, we need an opcode and operands
The way in which operands are specified in an assembly language instruction is called its
addressing mode.
Let us use the MOV instruction for understanding these modes. This has the format
MOV destination, source ………. source data is copied into the destination.
The basic assumptions in this context are

1. the operands can be in registers, in memory, or may be in the instruction itself. However
the 8086 does not have an addressing mode in which both operands are in memory
locations,
e.g. MOV [3456H], [3001H] --------------is wrong.
2. in the case of two operands, one of them can be in memory, but the other will have to be
placed in a register,
e.g. MOV [3456], BX ----------is right.
3. data types should match – i.e., the source and destination should both be either bytes or
words.
Addressing Modes contd…
1) Register Addressing
Here both the source and destination are registers. No memory access is involved.
See the following instructions.
MOV AL, AH ;copy the content of AH to AL
MOV CH, BL ;copy the content of BL to CH
MOV SI, BX ;copy the content of BX to SI

MOV ES, AX ;copy the content of AX to ES
Note that the first two are byte operations, while the other two are word
operations.
MOV AX, BL ;gives an error as AX is 16 bit and BL is 8 bit
MOV BL, AX ;gives an error for the same reasons
2) Immediate Addressing
In this mode, the source will be a constant data
MOV AL, 45H ;copy 45H to AL
MOV BX, 34E3H ;move the hex number 34E3H to BX
MOV CL, ‘Q’ ;move the ASCII value of Q to CL
MOV PRICE, 40 ;move the hex number 40 to the memory location with label
PRICE
MOV NUMS, 0FC6H ;move the hex number 0FC6H to the memory location NUMS
Segment registers are not allowed to use this mode of addressing.
MOV DS, 2300H ;gives an error as DS is a segment register
3) Direct Addressing
Here either the source or the destination will be a memory address.
MOV AX, [2345H] ;move the word in location 2345H into AX
MOV [1089H], AL ;the byte in AL is moved to location 1086H
It is to be remembered that the addresses in the instructions are off sets within the data
segment (i.e., the logical address). We need to know the content of DS to calculate the
physical address.
The size of the registers indicate the size of the operand. Hence, in the first instruction, a
data word is referred to; while in the second, a data byte is moved. The square brackets are
necessary to indicate that the number is an address and not data. However, we may use
labels for addresses, and re-write the above two instructions.
MOV AX, PRICE
MOV COST, AL
We must then ensure that the referred addresses have been defined earlier with these
labels.
4) Register Indirect Addressing
In this mode, the address of the data is held in a register. The register acts as a
pointer to the data.
The registers must be enclosed in square brackets to indicate that they function as
pointers. We also use the term effective address for the address of the operand.
For this mode of addressing, the address registers allowed are BX, SI and DI.
EA = {[BX]/[DI]/[SI]}
MOV AL, [BX] ;move into AL the content of the location whose address is in BX
MOV [SI], CL ;move the content of CL to the address pointed by SI
MOV [DI], AX ;move the content of AX to the address pointed by DI
In the third instruction, AX contains two bytes. Hence the content of AL will be
moved to the
address pointed by DI. The content of AH will be moved to the address [DI + 1].
5) Register Relative Addressing
In relative addressing mode, a number or displacement is part of the effective address.
EA = {[BX]/[DI]/[SI]/[BP]} + 8-bit or 16-bit displacement
MOV CL, 10[BX] ;move the content of the address specified by adding the content of BX & 10.
Thus the effective address is [BX + 10 ]. Once the effective address is computed, the physical
address is calculated as the sum of the segment base address and the effective address. The
displacement can be a 16-bit signed/unsigned number or an 8-bit sign extended number.
However the displacement should not be so large as to make the effective address go beyond
the range of the maximum size of a segment. The above instruction can also be written as
MOV CL, [BX + 10]
MOV CL, [BX] + 10 or
MOV CL, [BX][10] or
MOV CL, PRICE [BX]
In the last case, PRICE has to be defined earlier as a displacement of 10.
6) Based Indexed Mode
In this mode, an index register and a base register together carry the effective
address. The content of these two registers are added and called the effective
address.
MOV AL, [BX][SI] ;move the content of the effective address pointed by [BX] and [SI]
into AL
The effective address is obtained by adding the content of BX and SI. Since the
destination register is an 8-bit register, this is a byte operation. The following is a
word operation as the source register CX is 16-bit in size.
MOV [BX][DI], CX ;move the content of CX to the effective address pointed by [BX]
and [SI]
7) Relative Based Indexed Mode
This is the case when the ‘effective address’ is specified with a base register, an
index register as well as a displacement. The ‘effective address’ is the sum of the
two registers and the displacement.
For example, the following use the relative-based indexed mode of addressing
MOV DL, 5[BX][DI] ;EA = 5 + BX + DI
MOV 5[BP][SI], AX ;EA = 5 + BP + SI
MOV CL, COST[BX][SI] ;EA = COST + BX + SI ;COST has to be defined as a
displacement earlier
Example of physical memory address calculation-Important for numerical questions :
Find the address of physical memory for the following
instructions if the content of the required registers are as
given below
SS = 2344H, DS = 4022H, BX = 0200H, BP = 1402H, SI = 4442H
i) MOV CL, 1234H[SI]
CL=0101 0000 after executing MOV CL,
ii) MOV AL, 5[SI][BP]
1234H[SI]
Solution
This is a case of register relative addressing. The effective Data segment
address is obtained from the instruction, to be the sum of 0101 0000 45896H
the displacement and SI
Effective address = 1234H +
4442H
5676H
The segment base address is obtained from DS to be 40220H DS=40220H
The physical address is the sum of the segment base address
Base address
and the effective address. i.e.,
40220H = starting address
5676H= Effective address (offset value)
45896H=Physical address
ii) MOV AL, 5[SI][BP]
This is a case of relative based indexed mode. The effective address is calculated as
the sum of the displacement and the contents of the registers SI and BP.
Effective address = 0005H +
4442H
1402H
5849H= Effective address (offset value)
The physical address is the sum of the segment base address and the effective
address. In this case, as BP is one of the address registers, the segment referred is
the stack segment.
Physical address is 23440H (base address of the stack segment)
+ 5849H
28C89H= Physical address
Example :
The content of DS is 345BH. The amount of data that
is to be stored in the data segment is Data segment memory chip
12K bytes. Where in memory, will this segment be
Last address
located?
375B0H
Solution
DS contains the number 345BH.
This number corresponds to the upper 4 hex digits of
12×1024
the starting (base address) of the data =12288
segment.
The base address of the segment is 345B0H.
The last address will have an off set of 12K from the
base address. 345B0H
1K = 1024 bytes. Base address
12K = 12 × 1024 = 12288 = 3000H.
The last address of the segment = 345B0H + 3000H =
375B0H.
Hence the data segment occupies the memory
addresses from 345B0H to 375B0H
Show the location of data in memory, after
the execution of each of these instructions, if
the content of registers are as given
DS = 1112H, AX = EE78H and BX = 3400H
i) MOV [0422H], AL
ii) ii) MOV [0424H], AX
iii) iii) MOV [BX], AX
Find the address of physical memory for the
following instructions if the content of the
required registers are as given below
SS = 2344H, DS = 4022H, BX = 0200H, BP =
1402H, SI = 4442H
ii) ii) MOV AL, 5[SI][BP]
PIN Details of 8086 contd…
Minimum Mode Pins
√ √
❖ A set of 16 pins designated as AD. i.e., AD0–AD15. These
√
√ are the address / data pins.
√ ❖ The notation ‘AD’ means that these pins are used for
√ address as well as data.
√ ❖ They are multiplexed for data and address, which means
√ that at a particular time they carry address and at other
√ times they carry data.
√ ❖ The reason for having multiplexed pins : To reduce the
√ number of pins of the chip.
√ ❖ Since the data bus and address bus have to be separate
√
and because the ‘address’ has to be available at all
√
√ times, the address-data lines have to be ‘demultiplexed’
√ i.e., separated. This is done by the use of latches
A19 A18 A17 A16 AD AD AD AD AD AD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
15 14 13 12 11 10
Multiplexed for data and address

Block diagram of the de-multiplexed address /data bus
The address
values is saved
in LATCH when
ALE=1
These lines
are free to
carry data
when ALE=0
Minimum Mode Pin Functions
Pin No. Designation Function Type
16 to 2, 39 AD0–AD14, 16 multiplexed address / data lines Bidirectional
AD15 which carry address when ALE is high,
and later functions as data lines
D0–D15, when ALE is low
35 to 38 A19 / S6– Address lines A19 to A16, which are Output
A16 / S3 multiplexed with status signals S6 to S3.
The status bits function are as follows:
S6 – always 0
S5 – condition of the interrupt flag (IF)
S4 and S 3 show the current segment in
use as below:
S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or no Segment
1 1 Data Segment
32 𝑅𝐷 When this signal is low, data can be received from Output
memory or input devices
29 𝑊𝑅 When this signal is low, it is an indication that the Output
data on the data lines are available for writing into
memory or outputting to output devices
19 CLK This is the clock pin to which a clock with at least 33% Input
duty cycle is to be supplied
21 RESET This is an active high signal which signals the Input
microprocessor to reset itself provided the pin is held
high for at least 4 clock periods
22 READY For the bus cycle to proceed normally, the READY pin Input
should be found to be at logic high when it is
sampled. If it is at logic low, WAIT states are inserted
into the current bus cycle
23 𝑇𝐸𝑆𝑇 This pin is used usually when an arithmetic co- Input
processor is in the system. This pin is tested by the
WAIT instruction. If the pin is at logic zero, the ‘WAIT’
instruction becomes a NOP instruction. Otherwise, the
processor waits until this pin becomes logic zero
25 ALE Address Latch Enable’ – this signal goes high in the Output
beginning of a bus cycle and indicates that the
multiplexed address bus contains address
information
26 𝐷𝐸𝑁 Data Enable’ – This active low signal functions as an Output
activation signal for the external data bus buffers
27 DT/𝑅ത Data Transmit / Receive’ – The logic value of this signal Output
indicates whether the data is received (in a read cycle
DT / R = 0) or transmitted (in a write cycle DT / R = 1).
Thus, it is used as a direction pin for external data bus
buffers
28 M/𝐼𝑂 For I / O access this pin is low, and for Output
memory access, it is high
31 HOLD (See This is a signal from a peripheral requesting direct Input
slide no. 91) memory access (DMA). If the signal is high, the
processor issues a Hold Acknowledge signal and tri-
states its data, address and control bus
30 HLDA(See Hold Acknowledge’ indicates the acknowledgement of Output
slide no. 91) the HOLD request
33 𝑀𝑁/𝑀𝑋 This pin is used to select the mode of operation – Input
minimum or maximum. For minimum mode, the pin is to
be connected to the 5 V supply
34 𝐵𝐻𝐸/𝑆7 BHE stands for Bus High Enable. It is available at pin 34 Output
and used to indicate the transfer of data using data bus
D8-D15. This signal is low during the first clock cycle,
thereafter it is active.
1, 20 GND Ground’ – The common point is to be connected to two -----
pins. Two Ground pins are used so as to prevent having
to connect them together internally, due to possible
noise in the internal routing of the pins
40 VCC The power supply must be + 5V + /−10% -----
18 INTR(See Interrupt Request – this is used by an external device to Input

slide no. 91) interrupt the processor, which responds, only if the
interrupt flag (IF) is set, by lowering the INTA line, and
initiating an ‘interrupt acknowledge’ machine cycle input
24 𝐼𝑁𝑇𝐴(See Interrupt Acknowledge‘ is an active low signal Output
slide no. 91) acknowledging the interrupt request placed on the INTR
pin
17 NMI Non maskable interrupt request which is placed by an Input
external device – similar to INTR, but the Interrupt Flag
(IF) does not have to be set for it to be serviced. It is a
high priority interrupt
Timing Diagrams contd…
Read Machine Cycle
The steps involved in a typical read machine cycle are:
1. Place on the address bus, the address of the location whose content is to be read. This
action is performed by the processor.
2. Assert the read control signal which is part of the control bus.
3. Wait until the content of the addressed location appears on the data bus.
4. Transfer the data on the data bus to the processor.
5. De-activate the read control signal. The read operation is over and the address on the
address bus is not relevant anymore.
Step-1: Address of instruction code is placed on

Address bus
Microprocessor Instruction
Step-2: RD signal is sent to Memory chip codes are
(Instruction
code is decoded stored inside
and executed) Memory-chip
Step-3: Content of the address location is placed
on data bus from memory chip
Timing Diagram for Memory Read machine cycle
❖ In T1, the address is placed on the lines AD0 to AD15 and

A16 to A19 .
❖ BHE’ is high or low depending on the type of data (byte /
word) to be accessed. ALE goes high.
❖ M / IO’ signal is high from T1 to T4.
❖ Also the DT/ R’ is low from T1 to T4 indicating that data is
to be ‘received’ by the processor.
❖ In T2, the address information is removed from AD0 to
AD15. The address information is removed from A16 / S3
to A19 / S6 and BHE’ / S7 also, and these lines now carry
status information. In T2, the RD’ signal (which is the READ
control signal) is made low. In T2, DEN’ goes low to enable
the data bus buffer outputs
❖ The clock cycle T3 is to allow ‘access time’ for bringing data
from memory / IO and put it on the data bus. Thus, after
the data appears on the data bus, it is transferred to the
8086 at the end of T3.
❖ In T4, all the bus signals are de-activated in preparation for
the next bus cycle. This machine cycle ends with T4, and
the next machine cycle is scheduled to start.
Timing Diagrams contd…
Write Machine Cycle
The steps in a write machine cycle are :
1. Place on the address bus, the address of the location to which data is to be written.
2. On the data bus, place the data to be written.
3. Assert the write control signal which is part of the control bus.
4. Wait until the data is stored in the addressed location.
5. De-activate the memory write signal. This ends the memory write operation.
For the 8086, the control signals for a write machine cycle is WR. Also the DT / R signal will
be high (for ‘data transmit’) for writing.
The write bus cycle also uses 4 T states normally.
Step-1: Address (where data is to be written) is

placed on Address bus
Step-2: Content of data to be written is placed on

Memory-chip
Microprocessor data bus Or output
device
Step-3: WR signal is sent to Memory chip/Output device
Timing Diagram for Memory Write machine cycle
❖ In T1, the address is placed on the lines AD0 to AD15 and
A16 to A19 .
❖ BHE’ is high or low depending on the type of data (byte /
word) to be accessed. ALE goes high.
❖ M / IO’ signal is high from T1 to T4.
❖ Also the DT/ R’ is high from T1 to T4 indicating that data is
to be ‘transmitted’ by the processor.
❖ In T2, the address information is removed from AD0 to
AD15. The address information is removed from A16 / S3
to A19 / S6 and BHE’ / S7 also, and these lines now carry
status information. In T2, the WR’ signal (which is the write
control signal) is made low. In T2, DEN’ goes low to enable
the data bus buffer outputs
❖ The clock cycle T3 is to allow ‘access time’ for bringing data
from the processor and putting it on the data bus. Thus,
after the data appears on the data bus, it is transferred to
the memory / IO of T3.
❖ In T4, all the bus signals are de-activated in preparation for
the next bus cycle. This machine cycle ends with T4, and
the next machine cycle is scheduled to start.
Maximum mode
❖ It is necessary to use the maximum mode if the processor is to be used in multiprocessor
configurations.
❖ The most important issues in a multiprocessor environment are inter-processor
communication and bus contention.
❖ In this mode, 8086 has special pins for resolving these issues.
❖ To use the maximum mode, pin No. 33 MN / MX must be connected to ground.
❖ This mode of operation was designed by Intel for allowing the 8086 to communicate
with other processors like the arithmetic co-processor (8087) and the input /output
processor 8089.
❖ It was also used to allow 8086 to be used in large loosely coupled multiprocessor
systems. This mode was dropped from Intel’s designs from 80286 onwards.
❖ Later processors (80486 onwards) had the arithmetic co-processor integrated on the
processor chip itself.
PIN description for Maximum mode
Min
mode (Max mode)
√
√
√
The functions of INTA , ALE, DT / R , M / IO , and WR are to

be generated externally by 8288 bus controller PIN diagram in Max mode
Maximum mode contd…
Control Signals Generated by the Bus Controller
Status signal Machine cycle Control signal
𝑆2 𝑆1 𝑆0 generated by
8288
√
0 0 0 Interrupt 𝐼𝑁𝑇𝐴
acknowledge √ √
0 0 1 I/O Read 𝐼𝑂𝑅𝐶
0 1 0 I/O Write 𝐼𝑂𝑊𝐶
0 1 1 Halt NONE
1 0 0 Instruction 𝑀𝑅𝐷𝐶
Fetch
1 0 1 Memory Read 𝑀𝐸𝑀𝑅
1 1 0 Memory write 𝑀𝐸𝑀𝑊
1 1 1 Inactive NONE
Pin diagram of the bus
controller IC 8288
Instruction Set of 8086
Instructions of 8086 are classified as
1. Data transfer instruction
2. Arithmetic Instruction
3. Logical Instruction
4. Flag manipulation instruction
5. Control transfer instruction
6. Shift/Rotate
7. String Instruction
8. Machine control instruction
92 Microprocessor 8086Architecture, Programming and Interfacing
MOD = 00
REG = 011
R/M = 101
The machine code is 0010 1011 0001 1101 = 2B1DH.
4.5 INSTRUCTION SET OF 8086
The instruction set of 8086 microprocessor can be broadly classified into eight groups depending
on the functions these instructions perform. The Data Transfer Instructions are used for transferring
data from source location to destination location. The Arithmetic Instructions are used to
perform arithmetic operations like addition, subtraction, multiplication and division. Logical
Instructions perform the logical operations like AND, OR, EXOR operations. Shift and Rotate
Instructions are used to perform the logical and arithmetic shift operations and left and right
shifting. String Instructions performs the string related operations. The Data Adjustment
Instructions are used to convert the binary data in ASCII or in BCD format. As the name
suggests the Flag Related Instructions are used to modify the flag bits. The Control Transfer
Instructions are used to transfer the control within the program or from main program to
subroutine program or from subroutine to main program. The Machine Control Instructions
are used to perform the machine control operations like halt.
4.5.1 Data Transfer Instructions

The data transfer instructions copy values from one location to another. These instructions
include MOV, XCHG, XLAT, LDS, LEA, LES, PUSH, PUSHF, POP, POPF, LAHF, SAHF,
IN, and OUT.
MOV destination, source Move source to destination
The MOV Instruction copies the second operand (source) to the first operand (destination)
without modifying the contents of the source. In true sense these are not the data transfer
instructions but data copy instruction because the source is not modified.
The source operand can be an immediate value, general-purpose register or memory location.
The destination register can be a general-purpose register, or memory location. Both operands
must be the same size, which can be a byte or a word.
The following types of operands are supported:
MOV REG, memory
MOV memory, REG
MOV REG, REG
MOV memory, immediate
MOV REG, immediate
Here the register may be any of the general purposes registers, i.e. AX, BX, CX, DX, AH,
AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, and SP. The memory may be specified by any
of the memory-related addressing modes. Immediate data can only be specified at the source
location.
Instructions Set of 8086 93
For segment registers only these types of MOV are supported:
MOV SREG, memory
MOV memory, SREG
MOV REG, SREG
MOV SREG, REG
A data cannot be transferred from a memory to another memory, from memory to an IO,
from an IO to another IO and from IO to memory. IO can communicate with Accumulator
only. The immediate data cannot be transferred into a segment register. The only instructions
that move data into or out of a segment register have mod-reg-r/m bytes associated with them;
there is no format that moves an immediate value into a segment register. Move to and from
segment registers are always 16-bits. Since we cannot load an immediate data directly into a
segment register so to initialize a segment register first we load the immediate data into a
general purpose data register and then transfer that data from the data register to the segment
register with the help of MOV instruction.
The MOV instruction cannot set the value of the CS and IP registers. Also it cannot copy
value of one segment register to another segment register. For example, if we want to initialize
the Data Segment by a memory location 02500H, then first we have to load the value 2500H
into AX register and then transferring the contents of AX to DS register with the help of the
following instructions.
Example MOV AX, 2500H,
MOV DS, AX
In MOV instruction the flag remain unchanged.
IN Input data from input port
Operands
AL, 8-bit port address
AL, DX
AX, 8-bit port address
AX, DX
This instruction transfers a byte or word from a port to the accumulator register. The port
address is specified by the source operand, which can be DX or an 8-bit constant. If the port
address is of 8-bit then direct addressing will be used.
Example
IN AX, 04H; Move the content of the port number 04H and 05H to AL and AH
IN AL, 70H; Move the content of the port number 70H to AL.
If the port number is of 16-bit, then indirect addressing will be used and DX will be the
default register to specify the port number. To note that the DX register is not enclosed in
square brackets like memory addressing.
Example
IN AX, DX; Move the content of the port number specified in DX and DX + 1 to AL and AH
IN AL, DX; Move the content of the port number specified in DX to AL.
OUT Output data to output port

Operands
AL, 8-bit port address
AL, DX
AX, 8-bit port address
AX, DX
This instruction transfers a byte or word to an output port from the accumulator register.
The port address is specified by the destination operand. Port number may be of 8-bit or 16-
bit. For 16-bit port address DX register will be used and for 8-bit port address an 8-bit
constant will be used.
Example
OUT 04H, AX; Transfer the content of the AX register to the port 04H and 05H.
OUT 70H, AL; Transfer the content of the AL register to the port 70H.
OUT DX, AX; Transfer the content of the AX register to the port specified by DX and
DX + 1.
OUT DX, AL; Transfer the content of the AL register to the port specified by DX.
The flag register remain unchanged.
LDS Rd, M: Load pointer using DS Load pointer and DS register
This instruction is used to load the double word stored in memory into specified register and
DS register. The general purpose register is loaded from the lower-order word of the memory
operand and the segment register DS from the higher-order word. The memory may be specified
by any of the memory-related addressing mode. This instruction is very useful in string
instructions where the source is always DS:SI. For example, the following instruction may be
used to initialize both the SI and DS registers.
LDS SI, [BX]; SI is set to [BX:BX + 1] and DS is set to [BX + 2:BX + 3].
Figure 4.17 shows the action taken by the processor in response to this instruction.
Figure 4.17 LDS SI, [BX].
The flag register remain unchanged.

LEA Rd, M: Load effective address Load effective address
This instruction is used to load the effective address (offset) of the source memory operand
into the specified destination register.
It loads the specified 16-bit register with the effective (offset) address of the specified
memory location. For example, LEA SI, DS:[4F00H] loads the destination register SI with the
value 4F00H. Here, in this example, the same operation can also be performed by the MOV
instruction, i.e. MOV AX, 4F00H.
But the LEA instruction also computes the effective address of the memory for a particular
addressing mode which a MOV instruction does not perform. For example, consider the
following LEA instruction:
LEA DI, 3[SI]
This instruction copies the address of the memory location 3[SI] into the DI register, i.e.
it adds three with the value in the SI register and moves the sum into DI. Now the MOV
instruction cannot add 3 to the content of SI before loading it to DI. So the LEA instruction
can be used to do a MOV operation and an addition with a single instruction.
In this instruction the flag remain unchanged.
LES Rd, M: Load pointer using ES Load effective address and ES register
This instruction is used to load the double word stored in memory into specified register and
ES register. The general purpose register is loaded from the lower-order word of the memory
operand and the segment register ES from the higher-order word. The source M can be
specified by any of the memory-related addressing modes. This single instruction can be used
to initialize the string destination ES: DI. For example:
LES DI, [BX + 15]; DI is set to [BX + 15:BX + 16] and ES is set to [BX + 17:BX + 18].
Figure 4.18 shows the action taken by the processor in response to this instruction.
Figure 4.18 LES DI, [BX + 15].
The flag remain unchanged.

XCHG Exchange
Operands Rd, M
M, Rs
Rd, Rs
Exchange values of two operands. The order of the XCHGs operands does not matter but both
operands should be of the same size. The flag register remain unchanged after this instruction.
For example, if BL = 15 and AH = 20, then after the instruction XCHG BL, AH the
content of BL will be 20 and AH will be 15.
PUSH Push content on to stack top
Operands REG
SREG
memory
Push instruction pushes the source operand onto the stack. After the PUSH instruction, the
content of SP is decreased by 2 and the source value is copied to SS:SP. The PUSH instruction
always operates on words. The operands in the PUSH instruction can be a memory location,
a general purpose 16-bit register, or a segment register. PUSH SP copies the value of SP after
the push.
For example, if the content of the AX register is 1234H, then after the PUSH AX instruction
the 12h is loaded on [SP] and 34H is loaded on [SP 1] and SP is further decremented by
1 and becomes SP = SP 2. The flag register remain unchanged after this instruction.
POP Pop-off contents from top of stack
Operands REG
SREG
memory
This instruction pops the top of the stack into the destination operand. This means that the
value at SS:SP is copied to the destination operand and SP is increased by 2. The destination
operand can be a memory location, a general purpose 16-bit register, or any segment register
except CS. For example, if the top of the stack contains 12H and 34H, then after the instruction
Figure 4.19 PUSH and POP instructions.

POP BX, the SP is increased by 1 and the content of that location is loaded into BL and SP
again is incremented by 1 and the content of that location is loaded into BH. The flag register
remain unchanged after this instruction.
PUSHF no operands Push flag on top of stack
The flag register is pushed onto the stack. The higher byte of the flag register is pushed at
[SP]. SP is then decremented by 1 and then lower byte of flag is pushed on the [SP]. The SP
is again decremented by 1. The flag register remain unchanged after this instruction.
POPF no operands Pop off flag from top of stack
This instruction pops the value on the top of the stack into the flags register. First the SP is
incremented by 1 then the byte of the top of the stack will be popped into the lower byte of
the flag register. Again the SP will increase by 1 and the next byte from the stack will be
loaded into the higher byte of the flag register. The flag register remain unchanged after this
instruction.
LAHF no operands Load flag
Load the AH register by the lower byte of the flag register which contains the status flag, i.e.
carry, parity, auxiliary carry, zero, and sign flags. By this instruction we can see the contents
of the status flag.
SAHF no operands Store flag
Store the AH register in the lower byte of the flag register which contains the status flag, i.e.
carry, parity, auxiliary carry, zero, and sign flags. By this instruction we can modify the
contents of the status flag.
XLAT Translate
This is the translate instruction which is used to translate a value from one coding system to
another with the help of a lookup table. In this instruction BX is by default one of the registers
which points to the starting location of the lookup table. This BX register must be initialized
before the XLAT instruction. AL is the second register used in this instruction and contains
the unsigned value which is to be translated from the table. The pointed table value will be
transferred in the AL register after the execution of the instruction. This instruction do not
required any operand. DS is the by default segment which can be override by segment override
prefix. The XLAT instruction will perform the operation AL = DS:[BX + unsigned AL].
For example, consider the program
LEA BX, 2000H
MOV AL, 20
XLAT
In this program AL will be loaded with the content of the memory location pointed by
[2000 + 20]. The flag register remain unchanged after this instruction.
4.5.2 Arithmetic Instructions

Microprocessor 8086/8088 may perform the arithmetic operations on four types of data, i.e.
signed binary, unsigned binary, unsigned unpacked BCD and unsigned packed BCD. The
binary numbers may be of 8-bit or of 16-bits, they may be signed or unsigned. The BCD
numbers are always unsigned and may be in packed BCD or unpacked BCD form.
The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication,
division/modulo (remainder), and comparing two values. The instructions that handle these
operations are ADD, ADC, SUB, SBB, MUL, IMUL, DIV, IDIV, NEG, INC, DEC, CBW and
CWD.
In the arithmetic instructions the flag register is modified.
ADD Add
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
These instructions add a data from source operand to a data from destination and save the
result in the destination operand. The source and destination must be of the same type, means
they must be a byte type or a word type. If a byte is to be added to a word, then the byte must
be converted to a word by extended the D7 bit of the byte in the upper byte of the word.
Segment registers cannot be used as an operand in ADD instruction. Memory to memory and
IO to memory addition is also not permitted.
The following example demonstrates how the ADD instruction can be used to perform the
operation F = X + Y + Z:
MOV AX, X
ADD AX, Y
ADD AX, Z
MOV F, AX
Flag bits are modified as per the result of the operation.
ADC Add with carry
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction adds the source operand to the destination operand along with the carry flag.
The result is stored in the destination operand. This instruction is used to add the data which
are of large in size, i.e. double word type. Both ADD and ADC instructions affect the flags
identically.
For example, the following example shows the addition of the two numbers 12345678H
and FEDB4321H with the help of ADC instruction.
MOV AX, 5678H
ADD AX, 4321H
MOV BX, 1234H
ADC BX, FEDBH
SUB Subtract
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction subtracts the source operand from the destination operand and stores the result
in the destination operand. Segment registers cannot be used as an operand in ADD instruction.
Memory to memory and IO to memory addition is also not permitted. Flag bits are modified
as per the result of the operation.
Example MOV AL, 05H SUB AL, 02H
After the execution of the SUB instruction AL will contain 03H.
SBB Subtract with borrow
memory, REG
REG, REG
memory, immediate
REG, immediate
Subtract with borrow. This instruction subtracts the source from the destination along with the
value of the carry flag. The result is stored in the destination. This instruction is used to
subtract the data which are of large in size, i.e. double word type.
The SBB instruction computes the value
DEST operand = DEST operand SRC operand Carry flag.
The carry flag will set if an unsigned overflow occurs during the SUB and SBB instructions.
For example, the following example shows the subtraction of FEDB4321H from 12345678H.
MOV AX, 5678H
SUB AX, 4321H
MOV BX, 1234H
SBB BX, FEDBH
INC Increment
Operands REG
memory
Increment the operand by 1. This instruction increment the destination operand by 1. This
instruction differs with the ADD by 1 instruction in the way that the INC instruction does not
affect the carry flag whereas the ADD instruction modifies the carry flag. The INC instruction
is more compact and often faster than the comparable ADD instruction because it is a one-
byte instruction.
In INC all flags, except the carry flag, changes as that of in ADD and ADC instructions.
DEC Decrement
Operands REG
memory
Decrement the operand by 1. This instruction decrement the destination operand by 1.
This instruction differs with the SUB by 1 instruction in the way that the DEC instruction does
not affect the carry flag whereas the SUB instruction modifies the carry flag. The DEC
instruction is more compact and often faster than the comparable ADD instruction because it
is a one-byte instruction. In DEC except the carry flag all other flag changes as that of in SUB
and SBB instructions.
DIV Unsigned division
Operands REG
memory
This instruction divides the contents of the AX or the DX:AX by a specified source operand.
The AX and the DX:AX is the implied destination operands for 16-bit and 32-bit division.
This is an unsigned operation and hence both operands are treated as unsigned operands. If
the divisor is 16-bits wide, then the dividend is the DX:AX register pair. After the division
the quotient will be stored into AX and the remainder into DX. When the divisor is of 8 bits,
the dividend is AX. And in this case the quotient will be stored in AL and the remainder in
AH. Figure 4.20 shows the pictorial representation of DIV. All the flag bits are undefined, i.e.
the value of all the flag bits may be either 0 or 1.
Figure 4.20 Pictorial representation of DIV and IDIV.
Example MOV AX, 00C8H

MOV CL, 06H
DIV CL
After this program the result is available in AL (= 21H) and the remainder is present in AH
(= 02H).
IDIV Signed division
Operands REG
memory
This instruction is exactly the same as that of DIV except that here both operands are signed
numbers. Figure 4.20 shows the pictorial representation of IDIV. In both DIV and IDIV
instructions, the source operand cannot be an immediate data or a segment register. All the
flag bits are undefined, i.e. the value of all the flag bits may be either 0 or 1.
Example MOV AX, 200; AX = 0FF38H
MOV CL, 6
IDIV CL
After this program the result is available in AL (= DFH = 33) and the remainder is
present in AH (= FEH = 02).
MUL Multiplication
Operands REG
memory
This instruction multiplies the contents of the AL or the AX by a specified source operand.
The AL and the AX are the implied destination operands for 8-bit and 16-bit multiplication.
This is an unsigned operation and hence both operands are treated as unsigned operands.
In this instruction both the implied operand and the source operand must be of the same size.
For a 16-bit multiplication, the implied operand will be the AX register. After the multiplication
the product, which is of 32-bits, will be stored into the DX:AX register pair. For an 8-bit
multiplication, the implied operand will be the AL register. After the multiplication the product,
which is of 16-bits, will be stored into the AX register. If after the multiplication DX is not
0 for 16-bit operands or AH is not zero for 8-bit operands, then the carry and overflow flags
will set. The A, P, S, and Z flags are undefined, i.e. the value of these flag bits may be either
0 or 1. Figure 4.21 shows the pictorial representation of MUL.
Figure 4.21 Pictorial representation of MUL and IMUL.
Example MOV AL, 0FDH

MOV CL, 05H
MUL CL; AX = 04F1H
CF = OF = 0 when high section of the result is zero.
IMUL Signed multiplication

Operands REG
memory
This instruction is exactly the same as that of MUL except that here both operands are signed
numbers. In both MUL and IMUL instructions, the source operand cannot be an immediate
data or a segment register. If the product is sign extended into DX for 16-bit operands, into
AH for 8-bit operands then the carry and overflow flags are set and the remaining flag bits,
i.e. the A, P, S, and Z flags are undefined, i.e. the value of these flag bits may be either 0 or
1. Figure 4.21 shows the pictorial representation of IMUL.
Example MOV AL, 03H
MOV CL, 05H
IMUL CL; AX = 000FH
CF = OF = 0 when result fits into operand of IMUL.
NEG Negate
Operands REG
memory
This instruction produces the twos complement of the specified operand and stored the result
in the same operand. Microprocessor performs the negate (NEG) operation by subtracting the
operand from 0. This is done to represent a negative number. All the flag bits are modified
as per the result. The carry flag will be set for a non-zero operand and for a zero operand it
will be reseted. If the operand contains the maximum possible negative value (128 for 8-bit
operands or 32768 for 16-bit operands), the value does not change, but the overflow and
carry flags are set.
Example MOV AL, 15H
NEG AL; AL = 0EBH (2s Complement of 15H)
CBW no operands Convert byte to word
CBW converts the signed value in the AL register into an equivalent 16-bit signed value in
the AX register by extending the sign bit to the left.
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to
be the sign extension of AL. The flags are not modified and remain unchanged.
MOV AX, 0; AH = 0, AL = 0
MOV AL, F5H
CBW; AX = 0FFF5H
In this example, F5H is equivalent to 11110101B, this means the sign bit is 1. After the CBW,
the sign bit (1 in this case) will be extended into AX register.
Similarly,
MOV AX, 0; AH = 0, AL = 0
MOV AL, 55H
CBW; AX = 0055H
In this example, 55H is equivalent to 01010101B, this means the sign bit is 0 hence after
the CBW the sign bit (0 in this case) will be extended into AX register (i.e. 0055H).
CWD no operands Convert word to double word
Convert word into double word. CWD converts the 16 bit signed value in the AX register into
an equivalent 32-bit signed value in DX:AX register pair by duplicating the sign bit to the left.
The CWD instruction sets all the bits in the DX register to the same sign bit of the AX
register. The effect is to create a 32-bit signed result that has the same integer value as the
original 16-bit operand. The flags are not modified and remain unchanged.
Example MOV DX, 0
MOV AX, 0
MOV AX, 14H; DX:AX = 0000H:0FFECH
CWD; DX:AX = 0FFFFH:0FFECH
4.5.3 Logical Instructions

The 8086 provides six logical instructions. The logical instructions are AND, OR, XOR,
TEST, NOT and CMP. These instructions can manipulate bits, convert values, do logical
operations, pack and unpack data operations.
AND Logically AND
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise Logical AND of destination operand and the source
operand. The result of the operation is stored in the destination operand. The AND operation
is performed as per Table 4.9. The Z, S, and P flag bits are modified as per the result. The
carry and overflow flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1).
Table 4.9 Truth table of the different logical operations

AND OR EXCLUSIVE OR NOT
A B A·B A B AB A B A()B A /A
0 0 0 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 1 0
1 0 0 1 0 1 1 0 1
1 1 1 1 1 1 1 1 0
Example MOV AL, 61H; AL = 01100001

AND AL, CFH; AL = 01000001
CMP Compare
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction compares the source operand with the destination operand. Microprocessor
executes this CMP instruction by subtracting the source operand from the destination operand
but none of the operands are modified. The result is reflected by the flag bits. Generally the
result (i.e. flag conditions) of this instruction is used for conditional control transfer instructions.
The comparison may be a signed comparison or an unsigned comparison. For unsigned
comparison, the result is reflected by the Carry and Zero flag bits whereas for signed comparison
the result is reflected by the Zero, Sign and the Overflow flag.
For unsigned comparison operation, consider instruction CMP AX, BX, the microprocessor
performs the AX BX operation.
Now if AX = BX, then the result will be zero and hence the zero flag will set. If AX is
greater than BX, the result will be non-zero and positive and hence both the Zero and Carry
are reset. Similarly, when BX is greater than AX, then to perform AX BX we require to take
borrow and hence the Zero flag is reset and the carry is set.
For signed comparison if the EX-OR operation of the Sign and Overflow flag is 1, then
the result is negative. It is to be noted that for signed comparisons, the sign flag doesnt show
the proper status. For example, CMP AX, BX.
Flag condition Result

Sign flag Overflow flag
0 1 AX < BX
1 0 AX < BX
0 0 AX > BX
1 1 AX > BX
The CMP instruction also affects the parity and auxiliary carry flags, but these two flags
are rarely tested after a compare operation.
NOT Logically NOT
Operands REG
memory
This instruction complements the individual bits of the operand and save the result in the same
operand. In other words, we can say that it generates the 1s complement or the NOT operation
of the operand. After this instruction the flag register remain unmodified. Table 4.8 shows the
logical NOT operation.
Example MOV AL, 39H
NOT AL; AL = C6H
OR Logically OR
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise logical OR operation between the source and destination
operands. The result is stored in the destination operand. Table 4.8 shows the logical OR
operation. After the operation, the Z, S, and P flag bits are modified whereas the carry and
overflow flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1).
TEST Test
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs logical AND between all bits of the source and destination operands.
In this instruction perform the logical AND operation but none of the operands is modified,
it is only the ZF, SF, PF flags are modified. The carry and the overflow flags are cleared.
This instruction is used to tests specified bits of an operand and sets the flags for a
subsequent conditional jump or set instruction. One of the operands contains the value to be
tested. The other contains a bit mask indicating the bits to be tested. TEST works by doing
a logical bitwise AND on the source and destination operands. The flags are modified according
to the result, but the destination operand is not changed. This instruction is the same as the
AND instruction, except that the result is not stored.
Example MOV AL, 25H
TEST AL, 05H; ZF = 0
TEST AL, 20H; ZF = 0
XOR Logically EX-OR
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise exclusive OR operation between the source and destination
operands. After the operation, the result is stored in the destination. Table 4.8 shows the
logical EX-OR operation. The Z, S, and P bits of the flag register are modified as per the
result whereas the carry and overflow flag bits are set to 0 and auxiliary carry is undefined
(i.e. may be 0 or 1).
4.5.4 Shift and Rotate Instructions

The 8086 provides four rotate instructions, and three shift instructions. This is the second set
of instructions which are used for bit manipulation. The 8086 supports three different shift
instructions (SHL and SAL are the same instruction), SHL (shift left), SAL (shift arithmetic
left), SHR (shift right), and SAR (shift arithmetic right). The shift instructions move bits
around in a register or memory location.
Rotate instructions are the third set (apart from Shift and Logical instructions) of instructions
which are used for bit manipulation. The rotate instructions shift the bits around, just like the
shift instructions, except the bits shifted out of the operand by the rotate instructions recirculate
through the operand. They include RCL (rotate through carry left), RCR (rotate through carry
right), ROL (rotate left), and ROR (rotate right).
These instructions can manipulate bits, convert values, do logical operations, pack and
unpack data, and do arithmetic operations.
RCL Rotate left through carry
Operands memory, immediate
REG, immediate
memory, CL
REG, CL
The RCL instruction is used to rotate the operand1 left through the Carry Flag. In this
instruction the second operand may be an immediate value or the counter register CL.
This second operand decides the number of times the rotation will take place.
The RCL instruction moves the D15 or D7 bit to the Carry Flag and the Carry Bit goes to
the D0 bit position and all other bits shift towards left, i.e. to the higher bit position in the
operand register. RCL sets the overflow flag if the sign changes as a result of the rotate when
the rotate count is one. If the count is not one, the overflow flag is undefined. Only carry and
overflow flags are modified, whereas, rest of the flag bits, i.e. zero, sign, parity or auxiliary
carry flags remain undefined, i.e. may be 0 or 1. Figure 4.22 shows the pictorial representation
of RCL.
Figure 4.22 Pictorial representation of RCL.
Example STC; set carry (CF = 1)

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
RCL AL, CL; AL = 11010101, CF = 0
ROL Rotate left
REG, immediate
memory, CL
REG, CL
The ROL instruction is used to rotate the operand 1 left. In this instruction the second operand
may be an immediate value or the counter register CL. This second operand decides the
number of times the rotation will take place.
The ROL instruction moves the D15 or D7 bit to the D0 bit position of the operand as well
as to the carry flag and all other bits shifts towards left, i.e. to the higher bit position in the
operand register. The ROL instruction is similar to the RCL instruction with a difference that
the carry flag bit is not part of the rotation. ROL sets the overflow flag if the sign changes
as a result of the rotate when the rotate count is one. If the count is not one, the overflow flag
is undefined. Only carry and overflow flags are modified whereas rest of the flag bits, i.e.
zero, sign, parity, or auxiliary carry flags remain undefined, i.e. may be 0 or 1. Figure 4.23
shows the pictorial representation of ROL.
Figure 4.23 Pictorial representation of ROL.

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
ROL AL, CL; AL = 11010010, CF = 0
RCR Rotate right through carry
REG, immediate
memory, CL
REG, CL
This instruction performs the rotation of the contents of operand1 right through the Carry Flag.
In this instruction the second operand may be an immediate value or the counter register CL.
This second operand decides the number of times the rotation will take place. This instruction
RCR is the complement to the RCL instruction. In this instruction the D 0 bit of the operand1
is shifted to the carry flag, the carry flag is shifted to the D15 or the D7 bit and all the other
bits are shifted towards the right, i.e. one bit down to itself. It shifts its bits right through the
carry flag and back into the MSB position.
After the execution only the carry and overflow flag bits are modified whereas rest of the
flag bits, i.e. zero, sign, parity, or auxiliary carry flags are undefined, i.e. they may be 0 or
1. However, if the count is not one, the value of the overflow flag is undefined. Figure 4.24
shows the pictorial representation of RCR.
Figure 4.24 Pictorial representation of RCR.

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
RCR AL, CL; AL = 10111010, CF = 0
ROR Rotate right
REG, immediate
memory, CL
REG, CL
Rotate operand1 right. This instruction is the same as that of RCR with a difference that the
LSB will go to the MSB position as well as to the carry. Only carry and overflow flags will
be modified rest will be undefined, i.e. may be 0 or 1. Figure 4.25 shows the pictorial
representation of ROR.
Figure 4.25 Pictorial representation of ROR.

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
ROR AL, CL; AL = 01011010, CF = 0
SAL/SHL Airthmatic/logical shift left
REG, immediate
memory, CL
REG, CL
The SHL (Shift Logically Left) and SAL (Shift Arithmetically Left) are used to shift the
content of the first operand towards left. The encoding of these two mnemonics is the same.
The second operand may be an immediate data or the counter register CL and represent the
number of times the shifting takes place. While each bit of the operand shifts to left, the zeros
fill vacated positions at the lower order bit.
As we know that the shifting towards left is equivalent to multiply by 2 hence the
SHL/SAL instruction multiplies both signed and unsigned values by two for each bit shift.
The carry and the overflow flags will set for the unsigned and signed numbers if the result
does not fit in the destination operand, i.e. MSB is one. The AC flag is undefined after the
SHL/SAL instruction. Figure 4.26 shows the pictorial representation of SAL/SHL.
Figure 4.26 Pictorial representation of SHL/SAL.
SAR Airthmatically shift right

REG, immediate
memory, CL
REG, CL
Shift arithmetically the content of the first operand right by the number of times specified by
the second operand. The second operand may be an immediate data or the counter register CL.
In SAR while each bit is shifted right and goes to the carry flag, the sign bit is inserted from
the MSB side as shown in Figure 4.27.
As we know that shifting a binary number towards right is equivalent to dividing that
number by two, hence the SAR instruction is used to perform a signed division. Each shift
to the right divides the value of the destination by two. In some way, the SAR is similar to
the IDIV instruction except a difference that the IDIV instruction always truncates towards
zero while SAR truncates results toward the smaller result. For positive results, an arithmetic
shift right by one position produces the same result as an integer division by two. However,
if the quotient is negative, IDIV truncates towards zero while SAR truncates towards negative
infinity.
After the execution of the SAR instruction, the carry, parity and zero flag modified as per
the result. The sign remain unchanged, overflow flag is always zero and the AC flag is
undefined.
Figure 4.27 Pictorial representation of SAR.

Example MOV AL, 8EH; AL = 10001110

MOV CL, 02H
SAR AL, CL; AL = 11100011; CF = 1.
SHR Logically shift right
REG, immediate
memory, CL
REG, CL
Shift, logically, the content of the first operand right by the number of times specified by the
second operand. The second operand may be an immediate data or the counter register CL.
In SHR while each bit is shifted right and goes to the carry flag, a zero bit is inserted from
the MSB side as shown in Figure 4.28. As the SHR performs division by two operations on
signed operand, similarly the SHR instruction performs division by two operations for unsigned
operands.
This instruction sets the overflow flag if the sign changes, i.e. if the shift count is one,
the overflow flag will contain the value of the higher order bit of the operand prior to the shift.
However, if the count is not one, the value of the overflow flag is undefined. The condition
of all other flag bits will be the same as in the case of SAR.
Figure 4.28 Pictorial representation of SHR.
Example MOV AL, 07H; AL = 00000111

MOV CL, 02H
SHR AL, CL; AL = 00000001; CF = 1
4.5.5 String Instructions

String instructions are the instructions used for manipulation of sequence of bytes or words
that contain the alphanumeric code for characters. These instructions are used for processing
the text. There are five types of string instructions in 8086. These instructions are for byte as
well as for words. The operands in string instructions may be an implied source or an implied
destination or both the source and destination may also be implied. The source string is always
in the data segment and the destination string is always in the extra segment. The source
location, i.e. data segment can be override but not the destination, i.e. extra segment.
The source index SI and the destination index DI will hold the offset of the source string and
the destination string respectively or in other words in string instructions DS:SI and ES:DI is
the default source and destination memory pointers. The SI and DI is auto updated after the
string instruction. The string instructions of 8086 are MOVS (move string), CMPS (compare
string), SCANS (scan string), LODS (load string) and STOS (store string).
CMPSB no operands Compare bytes string
CMPSW no operands Compare words string

These instructions are used to compare the two string bytes or string words stored in memory.
The source string is always pointed by SI in the data segment and the destination string is
pointed by the ES in the extra segment. To compare these two strings, the microprocessor
performs the subtraction operation. It subtracts the destination string from the source string.
After the operation, none of the operands is modified, only the flags are modified to reflect
the result. The SI and the DI registers are either incremented or decremented by one or two
depending on the status of the direction flag and according to the size of the operands.
They are increased if the direction flag is zero or decreased if the direction flag is one.
Though the source string is always present in the data segment but a segment override can
be used to other segment. The segment override cannot be used with the destination segment,
i.e. with extra segment. The compare instruction performs the comparison once for each CMP
instruction. If we wish to compare a series of string data stored in the source and destination
locations, then we use the REP instruction (to be discussed later in this section) as a prefix
to the CMP instruction.
LODSB no operands Load string byte
LODSW no operands Load string word

Load AL or AX by the string byte or string word pointed by SI in the Data Segment.
After the execution of the instruction, the SI is incremented by one (in case of string byte)
or two (in case of string word) if the direction flag is zero, otherwise the SI will be decremented
by the same value for byte and word string. The flag register will remain unmodified. A
segment override can be given to change the source segment DS.
MOVSB no operands Move string byte
MOVSW no operands Move string word

These instructions are used to transfer the string byte (MOVSB) or a word byte (MOVSW)
source pointed by DS:SI to the destination location pointed by ES:DI. After the execution of
the instruction, the SI and DI is incremented by one (in case of string byte) or two (in case
of string word) if the direction flag is zero, otherwise the SI and DI will be decremented by
the same value for byte and word string. The MOVS instruction is an excellent instruction
with the help of which we can transfer data directly from one memory location to another
memory location. If the source string is stored in a segment other than DS, then we can use
a segment override but it is not permissible for the destination segment, i.e. ES. For transferring
multiple string data the REP instruction is used as a suffix to MOVS. Before using the repeat
prefix the counter register CX must be initialize. The Flag register is not modified by the
MOVS instruction.
Example of MOVSB
LEA SI, 2000H
LEA DI, 3000H

MOV CL, 15H
REP MOVSB
This program transfers 15H string bytes from DS:2000H to ES:3000H.
SCASB no operands Scan string byte
SCASW no operands Scan string word

These instructions are used to scan a string stored in memory to find a value specified in the
accumulator register. These instructions actually compare the string present in AL or AX with
the string stored in memory pointed by ES:DI. The SCAS instruction is performed by subtracting
each element of the destination from the accumulator contents. After the operation the flags
are updated to show the comparison result. After the operation none of the operands is
modified. The DI register is either incremented or decremented by one or two depending on
the status of the direction flag and according to the size of the operands. The DI is increased
if the direction flag is zero or decreased if the direction flag is one. In case of SCAS instruction
segment override is not allowed.
Generally a repeat prefix is used with the SCAS instruction. REPNE (or REPNZ) is used
to find the first match of the accumulator value. REPE (or REPZ) is used to find the first non-
match. Before using the SCAS instruction, CX or CL must be initialized with the maximum
number of elements to be compared. After the comparison, CX will be 0 if no match or non-
match was found. Otherwise SI and DI will point to the element after the first match or non-
match. Flag will be modified as per the result.
STOSB no operands Store string byte
STOSW no operands Store string word

These two instructions are used to store the string data available in the AL or AX in the
memory specified location by ES:DI. After the operation the DI register is either incremented
or decremented by one or two depending on the status of the direction flag and according to
the size of the operands. DI is increased if the direction flag is zero or decreased if the
direction flag is one.
STOSB and STOSW are generally used with the REP prefix. The counter register CX or
CL must be initialized before the repeated instruction is executed. Flag register remain unchanged.
The following program shows how the STOSW instruction is used:
LEA DI, 2000H
MOV AX, 25FEH
MOV CX, 5
REP STOSW
In this program first DI is initialized to point to the memory location 2000H in the Data
segment, then AX is loaded with the string value and counter CX is initialized with 5.
The REP STOSW instruction will store the AX contents (25FEH) in the memory location
ES:2000H onwards till CX is zero.
REP (unconditionally) Repeat unconditionally
This is a prefix instruction to a string instruction. This instruction repeats the string instruction
by the number of times indicated by CX. The execution of the string instruction stops when
CX is decremented to 0. The REP instruction is generally used with MOVS and STOS string
instructions. Except zero all the other flag bits are undefined.
REP (conditionally) Repeat conditionally
The repeat conditionally instruction which is used as prefix to a string instruction is used to
repeat a string instruction as long as condition is true and the CX is not zero. There are two
conditional repeat instructions and four mnemonics. These are REPE/REPZ and REPNE/
REPNZ. Before executing any of these instructions, CX must be initialized with the maximum
allowable number of repetitions. For each string element, the string instruction is performed,
CX is decremented, and the zero flag is tested. Except zero, all the other flag bits are undefined.
(i) REPE/REPZ Repeat till equal/Repeat till zero
REPE (Repeat till equal) and REPZ (repeat till zero) instructions are used to repeat a
string instruction till the zero flag is set. As in these two instructions the zero flag is
tested so these instructions are used with the SCAS and CMPS instructions as these are
the only string instructions that modify the zero flag. For example,
Repeat CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1 (result is Equal)
or till CX reaches to.
(ii) REPNE/REPNZ Repeat till not equal/Repeat if no zero
REPNE (Repeat till not equal) or REPNZ (repeat if no zero) instructions are used to
repeat a string instruction till zero flag is not zero or till CX becomes zero. For
example,
Repeat CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 0 (result is Not
Equal) or till CX reaches zero.
4.5.6 Adjustment Instructions
AAA no operands ASCII adjustment after addition

AAA converts the result of the addition of two valid unpacked BCD digits to a valid packed
BCD number. AL register is the implied operand.
The decimal numbers in ASCII have a code from 30H (0) to 39H (9). When we add
two ASCII numbers, the result will not be in ASCII. The AAA instruction will adjust the result
of addition to a BCD digit. The instruction assumes that the add operands are proper ASCII
values.
If the addition produces carry (AF = 1), the AH register is incremented and the carry CF and
auxiliary carry AF flags are set to 1. If the addition did not produce a decimal carry, CF and AF
are cleared to 0 and AH is not altered. In both cases the higher 4-bits of AL are cleared to 0.
AAD no operands ASCII adjustment before division
AAD converts unpacked BCD digits in the AH and AL register into a single binary number
in the AX register in preparation for a division operation.
The most significant BCD digit is stored in the AH register and the last significant BCD
digit is stored in AL register before the execution of AAD. The two unpacked BCD digits are
combined into a single binary number by the AAD instruction by setting AL = (AH*10) + AL
and clearing AH to 0. The carry, auxiliary carry and overflow flag bits are modified as per the
result and all other flag bits are undefined.
AAM no operands ASCII adjustment after multiplication
AAM converts the result of the multiplication of two valid unpacked BCD digits into a valid
unpacked BCD number. AX is the implicit operand in AAM.
AAM unpacks the result by dividing AX by 10, placing the quotient (Most Significant
Digit) in AH and the remainder (Least Significant Digit) in AL. In AAM, except carry and
auxiliary carry flag bits, all the other flag bits are undefined.
AAS no operands ASCII adjustment after Subtraction
AAS converts the result of the subtraction of two valid unpacked BCD digits to a single valid
BCD number. AL register is an implicit operand.
The two operands of the subtraction must have its lower 4-bit contain number in the range
of 0 to 9. The AAS instruction then adjust AL so that it contains a correct BCD digit.
The AAS instruction operates on strings of ASCII numbers with one-decimal digit (in the
range of 0 to 9) per byte. This instruction can be used after a SUB or SBB instruction on the
ASCII value. Except carry and auxiliary flag bits, all other flag bits are undefined.
DAA no operands Decimal adjust after addition
The DAA instruction adjusts the result of an addition to a packed BCD number. DAA converts
this binary sum to packed BCD format. If the sum is greater than 99h after adjustment, then
the carry and auxiliary carry flags are set. Otherwise, the carry and auxiliary carry flags are
cleared.
For example, two BCD values are added as if they were binary numbers and the result will
be in binary and then to convert this binary sum the DAA instruction is executed to correct
the result in BCD. The DAA instruction functions like AAA except it handles packed BCD
(binary code decimal) values rather than unpacked. All flag bits are modified as per the result.
DAS no operands Decimal adjust after subtraction
The DAS instruction adjusts the result of a subtraction to a packed BCD number (less than
100 decimal). DAS converts the binary result of subtraction into packed BCD. If the sum is
greater than 99H after adjustment, then the carry and auxiliary carry flags are set. Otherwise,
carry and auxiliary carry flags are cleared. All flag bits are modified as per the result.
4.5.7 Flag Related Instructions
These instructions are used to set or reset the individual control flag bits and also the carry
flag. No operands are associated with these instructions.
CLC no operands Clear carry
CLC clear the carry flag (CF) to 0. This instruction has no effect on the processor, registers,
or other flags. It is often used to clear the CF before returning from a procedure to indicate
a successful termination. It is also use to clear the CF during rotate operation involving the
CF such as ADC, RCL, and RCR.
CLD no operands Clear direction flag
This instruction reset the designation flag to zero. This instruction has no effect on the
registers or other flags. When the direction flag is cleared/reset SI and DI will automatically
be incremented when one of the string instructions such as MOVS, CMPS, SCAS, MOVSB
and STOSB executes.
CLI no operands Clear interrupt enable flag
This instruction resets the interrupt flag to zero. No other flags are affected. If the interrupt
flag is reset, the 8086 will not respond to an interrupt signal on its INTR input. This CLI
instruction has no effect on the nonmaskable interrupt input, NMI.
CMC no operands Complement carry
If the carry flag CF is zero before this instruction, it will be set to one after the instruction.
If the carry flag is one before this instruction, it will be reset to zero after the instruction
executes. CMC has no effect on other flags.
STC no operands Set carry
This instruction sets the Carry flag.
STD no operands Set direction flag
This instruction sets the Direction flag. SI and DI will be decremented by chain instructions:
CMPSB, CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, and STOSW.
STI no operands Set interrupt enable flag
This instruction sets the Interrupt enable flag. When the interrupt flag is set, maskable interrupts
are enabled. If interrupts were disabled by a previous CLI instruction, pending interrupts will
not be executed immediately; they will be executed after the instruction following STI.
4.5.8 Control Transfer Instructions

The control transfer instructions are used to transfer the control from one memory location to
another location. In 8086 there are four types of control transfer instruction, i.e. jump, call,
return and interrupt. All these type of control transfer instructions may be conditional or
unconditional. In case of conditional control transfer instructions, the control will be transferred
only if the condition is true.
CALL Call subroutine/procedure
Operands procedure name
label
4-byte address
This instruction is used to transfer the control of execution to a subroutine or procedure.

There are two basic types of CALL instructions, the Near CALL and the Far CALL.
A CALL instruction is called Near CALL if the procedure is in the same code segment
as the main program.
When microprocessor executes the CALL instruction, the control is transferred to the
procedure but before it goes to the subroutine it saves the returning address on the top of
stack. The stack pointer is decremented by two and copies the offset of the next instruction
after the CALL on the stack.
The control is again transfer to the main program when microprocessor comes across RET
instruction at the end of the procedure. This is done by popping up the offset saved on the
stack back to IP.
When the procedure is stored in a code segment different from where the main program
is stored, the CALL instruction is called Far CALL. In this case also the returning address
which consists of CS:IP is stored at the top of stack. First the stack pointer is decremented
by two and stored the content of CS register to the stack top. Again stack pointer is decremented
by two and stored the IP contents on stack top.
When the procedure is completed, the control is again transferred to the main program by
executing the RET instruction at the end of procedure and by restoring saved CS and IP from
the stack.
RET no operands Return
This is the last instruction of a procedure. When microprocessor executes this instruction,
transfer the control from the subroutine to the main program, in doing so it popped the
returning address from the top of the stack. A near return is specified by the RETN and far
return is specified by RETF. A near return works by popping a word into IP. A far return works
by popping a word into IP and then popping a word into CS.
IRET no operands Interrupt return
The IRET (Return from Interrupt Service Routine) transferred the control from an interrupt
procedure to the main program. The IRET instruction pops IP, CS, and the flags (in that order)
and resumes execution.
INTn Interrupt
The INTn generates the software interrupts. Here in this instruction the subscript n may be
from 0 to 255 and is called type of interrupt. When microprocessor executes the software
interrupt INTn, the control is transferred to a predefined memory location called the vectored
location. From this vectored location, the address of the ISR is fetched by the microprocessor
and then the control is transferred to that ISR. When an interrupt is called, the flags CS and
IP are pushed onto the stack (in that order) and the trap and interrupt flags are cleared.
To return from an interrupt, use the IRET instruction.
INTO no operands Interrupt on overflow
Interrupt of overflow flag is 1. The control is transferred to the ISR if the overflow flag is set
after an arithmetic instruction. If overflow is not set, then the ISR will not be called.
JMP Jump unconditionally
Operands label
4-byte address
This is an unconditional jump instruction. By this instruction, the control is transferred
from one memory location to another location within the program. The 4-byte address specified
as 234h:5678H. Here the first value denotes the segment and the second value shows the
offset.
The jump instruction may be conditional also. There are 30 conditional jump instructions.
In these instructions the control will be transferred to the label or 4-byte address only when
the condition is true. The condition may be logical condition or may be arithmetical condition.
The arithmetical condition may further be either signed or unsigned. Table 4.10 shows the
interpretation of these conditional jumps.
Table 4.10 Interpretation of conditional jumps

Mnemonic Condition tested Jump it...
JA/JNBE (CF or ZF) = 0 above/not below nor equal
JAE/JNB CF = 0 above or equal/not below
JB/JNAE CF = 1 below/not above nor equal
JBE/JNA (CF or ZF) = 1 below or equal/not above
JC CF = 1 carry
JE/JZ ZF = 1 equal/zero
JG/JNLE ((SF XOR OF) or ZF) = 0 greater/not less nor equal
JGE/JNL (SF XOR OF) = 0 greater or equal/not less
JL/JNGE (SF XOR OF) = 1 less/not greater nor equal
JLE/JNG ((SF XOR OF) or ZF) = 1 less or equal/not greater
JNC CF = 0 not carry
JNE/JNZ ZF = 0 not equal/not zero
JNO OF = 0 not overflow
JNP/JPO PF = 0 not parity/parity odd
JNS SF = 0 not sign
JO OF = 1 overflow
JP/JPE PF = 1 parity/parity equal
JS SF = 1 sign
Note: above and below refer to the relationship of two unsigned values; greater and
less refer to the relationship of two signed values.
The different conditional jump instructions are:

(i) JAE label: Short jump if first operand is above or equal to second operand (as set by
CMP instruction). It is unsigned jump operation.
Algorithm:
if CF = 0, then jump
(ii) JB label: Short jump if first operand is below second operand (as set by CMP instruction).
It is unsigned jump operation.
Algorithm:
(iii) JBE label: Short jump if first operand is below or equal to second operand (as set by
CMP instruction). It is unsigned jump operation.
Algorithm:
if CF = 1 or ZF = 1, then jump
(iv) JC label: Short jump if carry flag is set to 1.
Algorithm:
(v) JCXZ label: Short jump if CX register is 0.
Algorithm:
if CX = 0, then jump
(vi) JE label: Short jump if first operand is equal to second operand (as set by CMP
instruction). It may be a signed or an unsigned jump operation.
Algorithm:
if ZF = 1, then jump
(vii) JG label: Short jump if first operand is greater than second operand (as set by CMP
instruction). It is a signed operation.
Algorithm:
if (ZF = 0) and (SF = OF), then jump
(viii) JGE label: Short jump if first operand is greater than or equal to second operand
(as set by CMP instruction). It is signed jump operation.
Algorithm:
if SF = OF, then jump
(ix) JL label: Short jump if first operand is less than second operand (as set by CMP
instruction). It is signed jump operation.
Algorithm:
if SF Å OF = 1, then jump
(x) JLE label: Short jump if first operand is less than or equal to second operand (as set
by CMP instruction). It is signed jump operation.
Algorithm:
if ((SF Å OF) + ZF) = 1, then jump
(xi) JNA label: Short jump if first operand is not above second operand (as set by CMP
instruction). It is unsigned jump operation.
Algorithm:
if CF = 1 or ZF = 1, then jump
(xii) JNAE label: Short jump if first operand is not above and not equal to second operand
(as set by CMP instruction). It is an unsigned operation.
Algorithm:
(xiii) JNB label: Short jump if first operand is not below second operand (as set by CMP
instruction). It is unsigned jump operation.
Algorithm:
(xiv) JNBE label: Short jump if first operand is not below and not equal to second operand
(as set by CMP instruction). It is unsigned jump operation.
Algorithm:
if (CF = 0) and (ZF = 0), then jump
(xv) JNC label: Short jump if carry flag is set to 0.
Algorithm:
(xvi) JNE label: Short jump if first operand is not equal to second operand (as set by CMP
instruction). It may be a signed or an unsigned jump operation.
Algorithm:
(xvii) JNG label: Short jump if first operand is not greater than second operand (as set by
CMP instruction). It is a signed jump operation.
Algorithm:
if ((SF Å OF) + ZF) = 1, then jump
(xviii) JNGE label: Short jump if first operand is not greater than and not equal to second
operand (as set by CMP instruction). It is a signed jump operation.
Algorithm:
if SF Å OF = 1, then jump
(xix) JNL label: Short jump if first operand is not less than second operand (as set by CMP
instruction). It is a signed jump operation.
Algorithm:
if SF = OF, then jump
(xx) JNLE label: Short jump if first operand is not less than and not equal to second
operand (as set by CMP instruction). It is a signed jump operation.
Algorithm:
if (SF = OF) and (ZF = 0), then jump
(xxi) JNO label: Short jump if not overflow.
Algorithm:
if OF = 0, then jump
(xxii) JNP label: Short jump if no parity (odd). only 8 low bits of result are checked. Set
by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if PF = 0, then jump
(xxiii) JNS label: Short jump if not signed (if positive). Set by CMP, SUB, ADD, TEST,
AND, OR, XOR instructions.
Algorithm:
if SF = 0, then jump
(xxiv) JNZ label: Short jump if not zero (not equal). Set by CMP, SUB, ADD, TEST,
AND, OR, XOR instructions.
Algorithm:
(xxv) JO label: Short jump if overflow.

Algorithm:
if OF = 1, then jump
(xxvi) JP label: Short jump if parity (even). Only 8 low bits of result are checked. Set by
CMP, SUB, ADD, TEST, AND, OR, XOR instructions.
Algorithm:
(xxvii) JPE label: Short jump if parity even. Only 8 low bits of result are checked. Set by
Algorithm:
(xxviii) JPO label: Short jump if parity odd. Only 8 low bits of result are checked. Set by
Algorithm:
(xxix) JS label: Short jump if signed (if negative). Set by CMP, SUB, ADD, TEST, AND,
OR, XOR instructions.
Algorithm:
if SF = 1, then jump
(xxx) JZ label: Short jump if zero (equal). Set by CMP, SUB, ADD, TEST, AND, OR,
XOR instructions.
Algorithm:
LOOP label LOOP unconditionally
Loop instruction is used to create a loop from the Loop instruction to a specified label. Loop
decrements CX without changing any flags and if the result is not 0, transfers execution to
the address specified by the operand. If CX is 0 after being decremented, execution continues
at the next instruction. The operand must specify a short label (between 128 and 127 bytes
from the instruction following the LOOP instruction).
LOOP conditional
Conditional Loop instruction is used to create a loop from the Loop instruction to a specified
label if condition is met and if CX is not 0. The instruction decrements CX without changing
any flags and tests to see if the zero flag was set by a previous instruction (such as CMP).
With LOOPE and LOOPZ, execution is transferred to the label if the zero flag is set and CX
is not 0. With LOOPNE and LOOPNZ, execution is transferred to the label if the zero flag
is cleared and CX is not 0. Execution continues at the next instruction if the condition is not
met. Before entering the loop, CX should be set to the maximum number of repetitions desired.
(i) LOOPE label: LOOP if equal decrease CX, jump to label if CX not zero and equal
(ZF = 1).
(ii) LOOPNE label: LOOP if not equal decrease CX, jump to label if CX not zero and
not equal (ZF = 0).
(iii) LOOPNZ label: LOOP if not zero decrease CX, jump to label if CX not zero and
ZF = 0.
(iv) LOOPZ label: LOOP if zero decrease CX, jump to label if CX not zero and ZF = 1.
4.5.9 Processor-control Instructions

This group of instructions (except for NOP) generally deals with interactions in multiprocessor
situations.
NOP No operation
No operation
This instruction performs no operation. NOP can be used for timing delays or alignment.
ESC Escape
There are certain instructions in the 8086 assembly language which are designed only for
coprocessor. These instructions are called ESCAPE instructions. In these ESCAPE instructions
the MSB 5-bits of the opcode is always 110011. This instruction allows a memory or register
operand to be used by a coprocessor instruction. This instruction is explained in detail in
Chapter 8.
WAIT Wait
The WAIT instruction suspends the microprocessor execution and the processor enters into the
wait state. The processor will remain in wait state until a signal (TEST ) is received which
indicates that the coprocessor has finished a simultaneous operation. This instruction is used
when the microprocessor is used in maximum mode configuration and specifically when a
math coprocessor is present in the multiprocessing environment system. This instruction prevents
the math coprocessor instruction from modifying a memory location that is being modified at
the same time by a processor instruction. FWAIT is an equivalent instruction in the math
coprocessors instruction set.
LOCK Lock
This instruction prevents the other processor from acquiring the buses during the execution of
an instruction. This instruction is used as a prefix. For example, suppose the microprocessor
is executing the instruction MOV AX, 1000H, and in the mean time the DMA controller sends
a request for the buses, then the microprocessor is forced to suspend the execution of the
MOV instruction and releases the buses for the DMA controller. But if the MOV instruction
is prefixed with the LOCK instruction like LOCK MOV AX, 1000H, then the processor will
not release the buses till the MOV instruction is complete. The processor will release the buses
after the execution of this instruction and before the execution of the next instruction.
The LOCK prefix will activate the LOCK pin of the microprocessor.
HLT Halt
This instruction stops the execution of the microprocessor and force the processor to enter into
the wait state. The processor comes out of this wait state only when an interrupt restarts
execution at the instruction following HLT or by the external RESET signal.

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Overview of 8086 Microprocessor

8086 Microprocessor is an enhanced version of 8085 Microprocessor that

MOV AX, 2001 D80120H=1101 1000 0000 0001 0010 0000

CS CODE SEGMENT REGISTER

conditional flag bits explanation

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Overflow flag bit: Parity flag bit:

✓ Pipelining greatly speeds up processing.

Pre-fetching of next opcode is done

Total 216=65,536=64K address

Data segment use to store data

✓ The effective address calculation depends on the mode of addressing.

Segment Offset Registers Function

The basic assumptions in this context are

MOV SI, BX ;copy the content of BX to SI

Multiplexed for data and address

18 INTR(See Interrupt Request – this is used by an external device to Input

Step-1: Address of instruction code is placed on

❖ In T1, the address is placed on the lines AD0 to AD15 and

Step-1: Address (where data is to be written) is

Step-2: Content of data to be written is placed on

The functions of INTA , ALE, DT / R , M / IO , and WR are to

4.5 INSTRUCTION SET OF 8086

4.5.1 Data Transfer Instructions

OUT Output data to output port

Figure 4.17 LDS SI, [BX].

The flag register remain unchanged.

Figure 4.18 LES DI, [BX + 15].

The flag remain unchanged.

Figure 4.19 PUSH and POP instructions.

4.5.2 Arithmetic Instructions

Figure 4.20 Pictorial representation of DIV and IDIV.

Example MOV AX, 00C8H

Figure 4.21 Pictorial representation of MUL and IMUL.

Example MOV AL, 0FDH

IMUL Signed multiplication

4.5.3 Logical Instructions

Table 4.9 Truth table of the different logical operations

Example MOV AL, 61H; AL = 01100001

Flag condition Result

4.5.4 Shift and Rotate Instructions

Figure 4.22 Pictorial representation of RCL.

Example STC; set carry (CF = 1)

Figure 4.23 Pictorial representation of ROL.

Example STC; set carry (CF = 1)

Figure 4.24 Pictorial representation of RCR.

Example STC; set carry (CF = 1)

Figure 4.25 Pictorial representation of ROR.

Example STC; set carry (CF = 1)

Figure 4.26 Pictorial representation of SHL/SAL.

SAR Airthmatically shift right

Figure 4.27 Pictorial representation of SAR.

Example MOV AL, 8EH; AL = 10001110

Figure 4.28 Pictorial representation of SHR.

Example MOV AL, 07H; AL = 00000111

4.5.5 String Instructions

CMPSW no operands Compare words string

LODSW no operands Load string word

MOVSW no operands Move string word

LEA DI, 3000H

SCASW no operands Scan string word

STOSW no operands Store string word

4.5.6 Adjustment Instructions