UNIVERSITY INSTITUTE OF

ENGINEERING
DEPARTMENT OF COMPUTER
SCIENCE AND ENGG.
Bachelor of Engineering (Computer Science & Engineering)
Microprocessor & Interfacing (CST-282/ITT-282)
Prepared by: Er. Virender Kumar

DISCOVER . LEARN . EMPOWER

 Introduction • https://www.tutorialspoint.com/
microprocessor/
microprocessor_8086_overview.htm

COURSE OUTCOMES
CO Title Level
Number

CO1 To understand basics of 8086 microprocessor, its Applying

architecture and addressing modes.

CO2 To learn and implement assembly language evaluating

programming  
CO3 To understand advanced microprocessors. Analyzing

CO1
 INTRODUCTION

In 1978 , Intel released its first 16 bit microprocessor i.e. 8086 which executes the
instructions at 2.5 MIPS(million /s) [1]
• The execution time is 400 ns.
• An 8086 has 20 bit address bus, so it can access 2^20 =66Kb of memory.
• Width of the data bus of 8086 is 8 bit.
 PIN DIAGRAM OF 8086

Figure: PIN DIAGRAM OF 8086 [1]

Signals
Internal Architecture of 8086 (cont..)
Internal Architecture of 8086 (cont..)
Internal Architecture of 8086 (cont..)
 Minimum & Maximum Mode Interface
8086 Works in 2modes [2]:

1. Minimum : All control signals for memory and I/O are generated by 8086.
It is a uniprocessor configuration.
2. Maximum : Some control signals are generated externally which requires
the addition of external bus controller such as 8288 to 8086. It is a
multiprocessor configuration.
Figure: Block Diagram of MIN mode OF 8086 [3]
Figure: Block Diagram of MAX mode OF 8086 [3]
 Various Pins of 8086
• Pins common to Minimum and Maximum modes:
• AD15-AD0
• A19/S6
• A18/S5
• A17/S4
• A16/S4
• BHE/S7
• RD
• READY
• INTR
• TEST
• CLK
• MN/MX
Pins for the minimum mode operation
• M/IO
• INTA
• ALE
• DT/R
• DEN
• HOLD/HLDA
Pins applicable for maximum mode operation
of 8086
• S2, S1, S0
• LOCK
• QS1, QS0QS1 QS0 Indication
0 0 No operation

0 1 First byte of the opcode

from the
queue
1 0 Empty queue
1 1 Subsequent byte from the
queue
 Architecture of 8086

It consists of two main section:

• EXECUTION UNIT- It consists of:

ALU
16 Bit General purpose registers- AX, BX, CX, DX, SP, BP, SI , DI
16 BIT Flag registers
Control Unit

17
• Bus Interface Unit : It consists of
• Adder for address calculations
• Four 16 bit segment registers
• A 16 bit Instruction pointer
• A 6 byte long instruction queue
• Control logic

BIU and EU has been shown in the block diagram in the next slide

18
Figure: Internal block diagram of 8086 [4]

19
 Internal architecture of 8086

EU consists of eight 16 bit General Purpose Registers [5]

AX : Accumulator register is divided into AH and AL

BX: Base Register is divided into BH and BL
CX: Count Register is divided into CH and CL
DX: Data Register is divided into DH and Dl
SP: Stack Pointer
BP: Base Pointer
SI: Stack Index
DI: Destination Index 20
OFFSET ADDRESS BASE ADDRESS

Stack Pointer Stack Segment

Base Pointer Stack Segment

Source Index Data Segment

Destination Index Extra Segment

21
INTRODUCTION

In 1978 , Intel released its first 16 bit microprocessor i.e. 8086 which executes the
instructions at 2.5 MIPS(million /s) [1]
• The execution time is 400 ns.
• An 8086 has 20 bit address bus, so it can access 2^20 =66Kb of memory.
• Width of the data bus of 8086 is 8 bit.
EXECUTION UNIT – General Purpose Registers
16 bits

8 bits 8 bits

AH AL Accumulator
AX

BX BH BL Base

CX CH CL Count

DX DH DL
Data
SP
Stack Pointer
Pointer BP Base Pointer
SI
Source Index
Index
DI
Destination Index
23
EXECUTION UNIT – General Purpose Registers

Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal arithmetic

AH Byte multiply, byte divide

BX Store address information

CX String operation, loops

CL Variable shift and rotate

DX Word multiply, word divide, indirect I/O

(Used to hold I/O address during I/O instructions. If the result is more than 16-bits,
the lower order 16-bits are stored in accumulator and higher order 16-bits are stored
in DX register)

24
 How to find base address?
• Base address of any segment can be obtained by adding four binary 0’s to the
right portion of the content of corresponding segment register

• It is like shifting the content of the segment registers to the right by 4 bits.

• E.g: If the value of CS is 2000H , base address of CS is obtained by adding 4

binary digits or 1 Hexadecimal zero to the content of CS : 20000H
• Formula : BA*10H

25
• The following examples shows the CS:IP scheme of address formation:

CS 34BA IP 8AB4 Code segment

Inserting a hexadecimal 0H (0000B) 34BA0
with the CSR or shifting the CSR
four binary digits left 8AB4 (offset)
3D645

34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F
26
 • Example For Address Calculation (segment: offset)
• If the data segment starts at location 2000h and a data reference contains
the address 48h where is the actual data?

Offset 0000 0000 0100 1000

Segment Address 0010 0000 0000 0000 0000

Required Address 0010 0000 0000 0100 1000

27
28
 Physical Memory

Physical Memory Organization in 00000

8086
Since 8086 has 20 address lines. It can
access 2^20=1 MB Code segment (64KB)

Data segment (64KB)

Memory address in 1 MB ranges from

1 MB
00000H to FFFFFH Extra segment (64KB)

Stack segment (64KB)

Memory is constructed using RAM,
ROM and EPROM chips

FFFFF

29
 MEMORY
00000

BIU
Segment Registers 34BA0
CODE (64k)
44B9F
CSR 34BA
44EB0
DATA (64K)

MB
1
44EB 54EAF
DSR
54EB0
ESR 54EB EXTRA (64K)
64EAF
695E 695E0
SSR
STACK (64K)
795DF

Each segment register store the upper 16 bit of the starting address
of the segments

30
Addressing modes
• Addressing modes : Addressing modes indicates the way in which the
operand (data/ address) for an instruction is accessed and the way in which
microprocessor calculated the branch address for jump or call or return
instruction [6]
I. Register addressing mode : Data presented in register is moved or
manipulated and result is stored in register.
MOV AL ,BL
MOV BX,AX

register register
II. Immediate addressing mode: The data ( 8 bit / 16 bit ) is directly given in
the instruction.
e.g: MOV AL, 50 H
MOV BX, 23A0 H
III. DATA ADDRESSING MODE : The term effective address means the offset
address of the data within the segment which is obtained by different
methods depending upon the mode
• Direct address mode
MOV AL,[1000]
MOV BX, [2000]
3F03 - 80x86 assembler
• Base addressing mode: In this mode EA is the content of BX or BP
• When BX register is present in the instruction, data is taken from
the data segment and when BP is present, data is taken from the
stack segment.

MOV AX,[BX]
• Base Relative Address:
MOV AX, [BX+5]
MOVCH,[BX-100]
• Base Relative plus Index Addressing mode :
MOV CX, [BX+SI+50H]

Effective address=BX+SI +50H

Memory address= DS*10 H +BX+SI+50

=30000+2000+1000+50
=33050 H
IV. Program Addressing mode
V. Stack Memory addressing mode
4. Relative addressing mode
• Register relative
• Relative based
• Relative Indexed
• Relative Based Indexed
5. String Addressing mode
6. I/O Addressing mode
1. Register addressing mode
ADD AX, BX
2. Register Indirect Addressing mode
MOV AX, [BX]
3. Based Addressing Mode
MOV AX,[BP]
4.Indexed Addressing Mode
MOV AX,[BP][SI]
5.Based Indexed Addressing Mode
MOV AX,[BP][SI]
6. Register Relative addressing mode
a) Relative Indexed: MOV AX, ABC [SI]
b) Relative Based : MOV AX, ABC[BP]
c) Relative Based Index: MOV AX, ABC,[BP],[SI]

7. String Addressing Mode

[ES]:[SI]
[DS]:[DI]
8. I/O Addressing Mode:
OUT DX
 Interrupts
The processor has the following interrupts [7]:
• INTR
• NMI
• Software Interrupts
• Processor Exceptions
References
[1] Gaonkar, Ramesh S., “Microprocessor Architecture, Programming & Applications
with 8085”,Wiley Eastern Ltd.
[2] Ayala, “The 8086 Microprocessor: Programming & Interfacing the PC” , Cengage
Learning.
[3] Bhurchandi, K.M , Ray, A.K , “Advanced microprocessors and peripherals”, TMH.
[4] Brey, “The Intel Microprocessors 8086- Pentium processor”, PHI.
[5] Triebel and Singh, Avtar , “The 8088 & 8086 Microprocessors-Programming,
interfacing, Hardware & Applications” , PHI .
[6] Liu,Yu-Chang & Gibson, Glenn A, “Microcomputer systems: The 8086/8088 Family:
architecture, Programming & Design”, PHI.
[7] Antonakos, James L., “The Pentium processor”, Pearson Education.
 THANK YOU

For queries
Email: virenderkumar.cse@cumail.in