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a.
Explain with a neat diagram, VHDL program structure. (06 Marks)
b. Construct SR gates latch using NAND gates and derive the charecternstiescquation for the
same. (08 Marks)
c. Explain T-fliplop with characteristics equation. (06 Marks)
OR
8 a. Explain with neat diagram, working ofJK flipflop and deriye its characteristic equation.
(08 Marks)
b. Write VHDL code for 4 bit adder. (06 Marks)
c. Explain the application of SR latch in switeh debouncing technique. (06 Marks)
Module-4
7 a. Explain the structure of VHDL program. Write VHDL code for 4-bit parallel adder using
full adder as component. (08 Marks)
b With necessary diagrams, Explain switch debouncing with an S-R latch. (06 Marks)
C. Explain D flip-flop with the help of timing diagram. (06 Marks)
OR
a
Give the implementation of T-flip-flop from D flip-fop. (04 Mars)
b. Explain master-slave J-K flip-flop operation. (08 Marks)
C. Derive the characteristic equations for the following flip-flops:
S-R flip-flop
ii) D-flip flop
ii) T-fip-flop
iv) J-K flip-flop. (08 Marks)
Module-4
7 What are the three different models for writing a module body in VHDL? Give example for
any one model. (06Mark)
b. Derive characteris tic cquation for JK, T, D and SR flip flop. (08 Mak)
Give VHDL code for 4:1 mutiplexer using conditional assign statement. 06 Marks)
OR
8 Using structural model, write VHDL code for Half Adder. (06 Marks)
b
Derive the excitation table for JK and SR flip flop. How SR flip flop is covorted to T flip
flop? (08 Marks)
With logic diagram, xplain JK flip flop. (06 Marks)
Module-4
7 a. What is VHDL? Show how to model the 4-to-l multiplexcr using a VHDL conditoat
assignment statcment. (06 VMarks)
Derive the characteristic cquat ion for S-R flip-flop and J-K flip-lop in product-of suns
form. 06 Mark
What is D flip-flop? lllustrate the opcration of the clear and preset inputs in D-ip-tiop i
timing diagram. (O8 Nlark)
OR
W6 Marks)
8 Show how to construct a VHDL module using an entity architecture pajt
b. Explain switch debouncing with an S-R latch. 6Marks)
What is T lip-flop? Show how to convert D-flip-flop into T-flip-flop (08 Marks)
Module-4
7 a Given that A - "00101101" and B ="10011". Determine the valuc of F
F<=not B&*01|" or A&"" and "1"&A (04 arks)
b Write the complete VHDL code for 4 bit binary adder. (08 Marks)
C. Explain how the VHDL code can be compiled simulated and synthesized ywt eNample
Q8 Marks)
OR
Explain T Flip Flop with truth table. (07 Marks)
b. Explain Master-Slave JK lip flop with neat diagram. (08 Marks)
Write short notes on switch debouncing with an SR Latch. (0S Marks)
Moduje-4
7 a
Write a VHDL module that implemcasa halfadder, a full adder, a half substractor and a
full substractor. (10 Marks)
b Write a VHDL module for 8 to IMUX (05 Marks)
C. Drawthc circuit represented by ahe followitg HDL statements.
F<=E and 1;
|<=G or H:
G<= A and B;
H<=not Cand D: (05 Marks)
OR
a
Explain the working oSR Leh withncat circuit diagram, truth table and timing diagram.
(10 Marks)
b
With a neat logie diagramm. truth table and timing diagram, cxplain the working of J-K
Master Skave
fhp-tlop. (10 Marks)
Module oy.
Explain aith a neat diagtom, VHDL Pavyfa
Strucfaee. OGmay
VHoL Proram sruchue
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brity
fhhitechuk chitecheee
mod-a mod .
mod
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memn.
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R n
4
Chanctejshe Rae.
oo
Chaiacteisic Squaton
Giplain oth neat diagans, soorki 3k fkp fig
Ond deive its chalacteiic quahv? cema.
mmony
c|k-, 3:1, keo, G: 4,8-0.
clk-, J=0, k= 1, Q0,g:4.
J=+, k- 1, ©,4,o|... 4,0, 5,0...
Truth table
chal actelinhic tabe
CiK Gnt}
chalacteiic q)
wite VHnL Code for 4 bit addes? osmaks.
Sioith
Swid
ata
Page
Palexonse,
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Do
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HDL
Fotmat d ADL
discápin anguage
HDL - Haxduens sped
L- Vexy hih
VHDL Cincu
hosdaaste deiptien language
Module Name o, the nAedule paxamelon uy
iabut vaiablo
Qutut vauxiable
End module;
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End ne&nle
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D
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