BIRLA INSTITUTE OF TECHNOLOGY &

SCIENCE, PILANI, GOA CAMPUS

GRAPHENE BASED FET

Course in charge
Prof. Ramesha C.K

Submitted by

K.N.D Chinni Krishna

(2023H1230136G)
ABSTRACT:
The silicon complementary metal-
oxide semiconductor (CMOS) technology
is the leading electronic industry. Today,
silicon CMOS technology has hit its basic
limits (physical and geometrical), which
for future technical nodes is the key
roadblock. The problem with silicon is its
poor stability below 10 nm, since it
decomposes, and migrates unpredictably.
Graphene field effect transistors (FETs)
are promising devices for the next
generation of electronic and photonic
devices. Graphene FETs have many
advantages over traditional silicon-based
Introduction:
In 2004, two pioneering papers on
graphene, a purely two-dimensional
carbon-based material, were published [1-
2]. The Geim-Novoselov group from the
University of Manchester reported on the
fabrication of graphene flakes by the
astonishingly simple exfoliation technique,
the observation of the field effect and high
mobilities in their samples [1]. This paper
ignited a revolution in condensed matter
physics and eventually led to the Nobel
Prize in Physics 2010 for Geim and
Novoselov. The second pioneering paper
came from the Berger-de Heer group from
Georgia Tech who explored epitaxial
graphene and observed the field effect as
well [2]. Since 2004, graphene has
attracted enormous attention in both basic
and applied research, and it did not take
long before the electron device community
showed strong interest in graphene. This
mainly arose from graphene's excellent
carrier transport properties. In particular
the high mobilities led with optimistic
evaluations of graphene's potential in the
field of electronics and the anticipation
that graphene-based transistors for high-
performance digital logic and ultra-fast RF
(radio frequency) circuits capable to rival
transistors, including higher electron
mobility, higher on/off ratio, and the
potential for high-speed operation. In
addition, graphene FETs have been
demonstrated to have excellent device
stability, low power operation, and low-
cost fabrication. This report is a
demonstration of the current state of
graphene FET technology, including
device physics, fabrication techniques, and
device performance. The potential of
graphene FETs in applications such as
high-speed computing, and energy
efficient electronics is also discussed.
the conventional Si and III-V transistors
could be realized. Indeed, already in their
2004 paper Novoselov and Geim reported
room-temperature mobilities of 10,000-
15,000 cm2 /Vs in graphene [1], and
meanwhile the measured record mobilities
in graphene exceed 100,000 cm2 /Vs at
room temperature and 1,000,000 cm2 /Vs
at 4 K [3-4]. Many groups started working
on graphene transistors with the main
focus on graphene MOSFETs. Although
the progress in this field was – and still is
– impressive, so far graphene could not
fulfil the high expectations yet. Meanwhile
part of the early excitement is gone and the
potential of graphene for electronic
applications is now assessed still
optimistic but much less enthusiastic
compared to the early days . This report
reviews graphene MOSFETs and
highlights the merits and drawbacks of
these transistors.
Graphene:
Graphene comprises carbon atoms
organized in a honeycomb structure,
creating a two-dimensional lattice. It has a
variety of unique properties, such as
incredibly high electrical and thermal
conductivity, flexibility, strength, and
transparency. The distance between two
adjacent carbon atoms in graphene is 1.42
Å and two front atoms are 2.46 Å.
Graphene has higher mobility than
silicon (more than 100 times) and, 30
times greater than Gallium arsenide
(GaAs). Is shows 2,00,000 cm2 /vs
mobility at room temperature," A physicist
Prof. Geim, university of Manchester, said
that graphene is a material in which
electron can travel thousands of inter
atomic distance without any scattering at a
room temperature [5]." The band gap of
pristine graphene is zero. This means that
electrons can move freely within the
material and that it acts as a zero-bandgap
semiconductor. This characteristic makes
it a highly attractive material for a wide
range of applications, such as electronics,
sensing, energy storage, and
optoelectronics. For example, it can be
used to create transistors, and field-effect
transistors. In addition, it can be used to
create ultra-thin, flexible, and transparent
electronic components such as switches
and displays. Device made with zero
bandgap material is very hard to control
(OFF state), which results loss of static
power consumption while used in CMOS
technology. The band gap of graphene is
adjustable by three methods:
1. Doping of hetero atoms.
2. Chemical modification
3. Tuning of the electrostatic field.
Band gap can be tuned, and fermi level can
be adjusted by the first two methods.
Fermi level of graphene can be changed
with the help of the gate voltage and
polarity during the process of electrostatic
field tuning. but it is unable to open the
bandgap of graphene. Electrostatic doping
is caused between metal gates, positioned
40 nanometers away from graphene
channels, through the electric field [6].
Band Structure of Graphene:
Conventional metals/semiconductor
materials, band structure is approximately
parabolic near the band gap. The Band
Structure for graphene Consists of the
conduction and valence bands forming
conic shapes and intersecting each other at
points known as the Dirac points. No band
gap means we cannot bring the OFF-state
current down to zero amperes. So, to
improve the band gap Bilayer Graphene,
Graphene Nanoribbons are being indulged
as the channel. Graphene lacks a band gap,
distinguishing it from insulators, and it
does not possess partially filled bands
characteristic of metals. Graphene is
therefore sometimes referred to as a semi-
metal.
Lack of Bandgap:
Because of its gapless structure,
graphene behaves like metal because the
valence and conduction bands collide at
zero volts. The two bands in
semiconductor materials like silicon are
separated by a gap that functions normally
like an insulator. Electrons typically need
extra energy to move from the valence
band to the conduction band. In FETs, a
bias voltage allows a current to flow across
the band, which otherwise serves as an
insulator. Unfortunately, since the GFET
cannot behave as an insulator because
there is no band gap, it is not easy to
switch off the transistor. A current ratio of
roughly 5, which is extremely low for
logic processes, derives from the inability
to shut it off entirely. As a result, it is
challenging to use GFETs in digital
circuits. The GFET is excellent for
amplifiers, mixed-signal circuits, and other
analog applications because this is not an
issue with analog circuits.
Graphene Transistors:
Graphene transistors consist of a
single layer of carbon atoms arranged in a
honeycomb lattice. Graphene transistors
offer several advantages over traditional
silicon transistors, including higher current
density, lower power consumption, and
faster switching speeds. Graphen e
transistors are also capable of operating at
much higher frequencies than silicon
transistors, making them ideal for high-
speed applications such as cell phones,
computers, and medical devices. Graphene
transistors are still in the research and
development phase, but they show great
potential for revolutionizing electronic
technology in the near future. Fujitsu has
manufactured graphene transistors directly
developed on insulating substrates with a
novel configuration that includes
beginning with an iron deposition The
process involves the deposition of a thin
film of graphene on a substrate and then
depositing a thin layer of iron onto the
graphene surface. The iron layer is then
heated to a high temperature in order to
fuse the iron and graphene together.it is
hard to form a transistor using a
conducting material but graphene can be
used to formed a transistor on a insulation
substrate . A method for shaping
transistors in which graphene is used as the
channel material has also been developed
by Fujitsu Laboratories. Conventional
photolithographic techniques are used to
form an iron catalyst, which is used to
formation of device channels. CVD
process is used to produce graphene with
the help of iron layer. Titanium-Gold film
is used to made electrodes (Source and
Drain) both the ends of graphene,
effectively trying to fix the graphene. Than
iron catalyst is removed (For source and
drain) using acid, by keeping graphene
layer is fixed. Atomic layer deposition
(ALD) to stabilize graphene a hafnium
oxide (HfO2) layer is grown on top of it,
which is a technique of forming thin films.
Finally, on top of the graphene a gate and
electrodes are created culminating in a
graphene transistor creation [9]. It is
important that graphene transistors should
be formed in such a way that it is
suspended in the air such that both sides of
the graphene can be washed to boost
efficiency of graphene transistors. The
ALD process used by Fujitsu Laboratories
allows insulator film to be formed to cover
the graphene suspended in the air.
Fabrication process of graphene
FET:
Fabrication of a graphene-based
FET (GFET) consists of several steps:
(1) formation of a single or a-few-
monolayer graphene on a desired
substrate,
(2) applying an out-of-plane electric field
through a gate insulator to invoke carriers
within the channel,
(3) application of an in-plane electric field
between source and drain contacts to drive
the induced carriers between the
electrodes.
The following summarizes the status of
these processes. Formation of graphene
Various methods exist to fabricate
graphene layers. Major methods include.
(1) mechanical exfoliation of graphite,
(2) epitaxial graphene formation on SiC
crystals, and
(3) CVD method using catalytic metals. In
the mechanical exfoliation method.
Graphene sheets are normally transferred
onto a Si substrate covered by a Si oxide
layer. For certain oxide layer thicknesses
(90 and 300 nm), the number of graphene
layers can easily be distinguished by the
contrast obtained in the optical
microscopy, which is one of the biggest
advantages of this method. To fabricate
graphene devices, however, one has to find
the right portion of the substrate that
contains graphene with a desired number
of layers. It is obvious that this method
cannot be industrially applicable. Epitaxial
graphene (EG) formation on SiC surfaces
[7] proceeds via sublimation of Si atoms at
high temperatures. Report on the
formation of graphene (a few layers
graphite) on SiC, after heating at 1200-
1600 °C in vacuum, dates back to 1975 by
the work of van Bommel et al Today, EG
method is intensively studied by using 4H
and 6H-SiC(0001) bulk crystals. Because
this method forms graphene directly on an
insulating substrate (SiC), there is no need
to transfer graphene onto substrates. The
high temperatures used in the process are
also beneficial because this gains the
reproducibility of the quality of graphene.
Issues of charge impurity at the surface of
the insulating substrate, which is quite
detrimental to the graphene performance,
can also be greatly minimized. A unique
and intriguing advantage about EG is the
ability to control the interfacial and
stacking structure of graphene. When one
utilizes a Si-face of a basal plane of
hexagonal SiC, there occurs an
intermediate layer between SiC and
graphene (the 0-th layer or the interface
layer). The stacking of graphene formed
thereon is AB-stacked (Bernal stacked).
As a result of presence of two non-
equivalent atoms in a unit cell, bilayer
graphene on Si-faced SiC opens a gap by
applying an electric field perpendicular to
the surface. On the C-face, in sharp
contrast, graphene formation causes no
interface layer in principle, therefore, EG
on Si-face is for digital applications while
EG on C-face is for analog and opto-
electronic applications. As we have seen,
graphene formation on SiC substrates (EG)
possesses a high applicability to industry.
However, the SiC substrates are still
expensive (~40 times than Si), and their
sizes are limited. In this situation, the
author and coworkers have developed a
method to grow EG on a 3C-SiC thin film
formed on a Si substrate. The advantage of
this graphene-on-silicon (GOS) technology
includes, in addition to its good
compatibility with the Si planar
technology, the controllability of the
structural (stacking) and electronic
properties of graphene by simply tuning
the orientation of the Si substrate. For
instance, we have developed a technology
to control the surface termination of
3C-SiC(111), i.e., 3C-SiC(111) and 3C-
SiC(-1-1-1), which yields EG layers on Si-
face and on C-face, respectively. For
formation of graphene in large area, CVD
method has a great advantage. In CVD
method, C atoms supplied by hydrocarbon
molecules either dissolve into the metal
(Ni, Ru) and precipitate at the surface or
chemisorb at the metal surface (Ir, Cu),
which yield graphene. CVD-grown
graphene must be transferred onto large-
sized insulating wafers, for which onset of
wrinkles and metal contamination should
`be cared.
Gate oxide formation:
To fabricate a top-gated graphene
FET (TG-GFET), we need a qualified
high-k gate insulator that is uniformly thin
enough with allowably low leakage current
and interface trap density. Gate insulators
can be formed by evaporation, natural
oxidation of deposited metals,28) and
atomic-layer deposition (ALD). While
ALD provides accurate control of the
thickness and high uniformity of the film,
the method cannot be applied directly onto
the hydrophobic graphene surface without
chemical functionalization of graphene by
NO2 and O3 or insertion of an interfacial
polymer layer [8] prior to ALD. Other
methods include deposition of metals (Al,
Hf) under oxidizing ambient. Quantum
capacitance Equally important to
formation of gate oxide formation is the
quantum capacitance. Because the density
of states of graphene vanishes at the Dirac
point, the energy required for a unit charge
to be transferred to graphene increases
with the total charge stored in graphene.
This leads to an onset of an effectively low
capacitance (Cq = dQ/dV) in graphene. As
a result, gate voltage induces channel
carriers via a series connection of both the
gate capacitance Cox and the quantum
capacitance Cq. As the EOT decreases to
~1 nm so as to become Cox > Cq, the
quantum capacitance begins to control the
total capacitance, which cancels out the
effort of further reduction of EOT.
Metal/graphene contacts:
In addition to the
graphene/substrate and graphene/gate-
oxide interfaces, the graphene/metal
interface forms the third important
interface in GFET devices. Being a
semimetal, graphene forms an Ohmic
contact with most of the metals. To realize
a low contact resistance Rc, metals with
high work function are normally used.
Metals to be used for GFET electrodes
include Ti/Au, Cr/Au, Cr/Pt, and Co.
While analog applications can tolerate
Rc~800 Ωμm, digital applications require
Rc values at or less than 80 Ωμm.
Configurations of Graphene FET:
The GFET comes in three different
gate configurations. It can have a top gate,
a global back gate, or both. The gate of a
GFET regulates the flow of electrons or
holes across its channel, just like in
conventional silicon FETs. The single-
atom transistor channel allows all current
to flow on its surface, which accounts for
the great sensitivity of graphene FETs.
Most of the current in silicon devices is
carried by electrons or holes. The GFET,
on the other hand, permits equal
conduction by electrons and holes. GFET
devices often exhibit ambipolar behaviour,
where in
hole carrier conduction is observed in the
channel region under a negative bias. A
positive bias, on the other hand, causes
electron carrier conduction. The Dirac or
charge neutrality point, which ideally
ought to be at zero voltage, is where the
two conduction curves converge. The
actual Dirac point, however, may change
in real life based on doping, the number of
impurities on the surface of graphene, the
surrounding environment, and other
factors. For instance, some p-doped
graphene FET devices typically have
values between 10 and 40 volts. The four-
terminal GFET uses both the top and back
gates and is suited for some applications,
while the rear gate GFET is the most
typical. The dual-gate GFET makes it
possible to bias the channel using two
distinct voltages.
Working of GFET:
GFET has an ambipolar curve when
the electric field effect is present. Charge
carriers in the graphene channel are
responsible for its conductivity. σ=nqv,
where σ is the conductance, n is the charge
carrier density, q is the charge per carrier,
and v is the mobility, the conductance of
graphene is proportional to both its mobility
and charge carrier density.As gate voltage
rises, GFET conductivity rises concurrently
with the electron (or hole) concentration
rise brought on by positive or negative gate
voltages. The Fermi level of graphene
controls the variations in the carrier
concentration of the graphene channel. As
gate voltage is provided, the Fermi level
will be constantly driven via the Dirac point
from the conduction band to the valence
band and vice versa. A considerable
number of holes are introduced into the
valence band when the Fermi level is below
the Dirac point. A good number of electrons
are introduced into the conduction band
when the Fermi level is above the Dirac
point. By applying a gate voltage, charge
carriers (electrons and holes) may be tuned
continuously up to (10^13) cm^2 and have
a room temperature mobility of about
100000 cm^2V/s, proving that graphene-
based FETs exhibit a strong ambipolar
electric effect. Despite charge carriers
disappearing at the Dirac point, an
experiment by Novoselov, K.S.A., et al.
demonstrates that graphene's conductivity
does not reach zero and stays finite at a
value of 4 e^2/h.
GFET Biasing (Vds = 0) :
Case 1 : Vgs< Vdirac
• In this case Ef is below Ed , Vch > 0
i.e. high concentration of holes.
• Decreased values of Vgs , Ef and Ed
move further away from each other
that increases the hole concentration
and conductivity of channel.
• When Vgs is increased, Ef and Ed
move together, there by
decreasing Vch
Case 2 : Vgs = Vdirac
• Ef goes through Ed , Vch = 0.
• Minimum charge density for
electrons and holes is reached.
• Conductivity in the channel is very
low.
Case 3 : Vgs > Vdirac
• Ef is above Ed , Vch < 0.
• Electron density is high.
• As Vgs is increased Ef and Ed move
further apart, decreasing Vch ,
increase electron concentration and
the conductivity of channel.
GFET Biasing (Vds >> 0) :
Case 1 : Vgs< Vdirac
• Ef is below Ed , Vch > 0 i.e., high
concentration of holes.
• Hole density is high and holes
travel from drain to source
generating a current in the same
direction.
• Holes are the majority carrier.
Case 2 : Vgs = Vdirac
• Ef goes through Ed , Vch = 0.
• Ef coincides with Ed at the source
end where Vch = 0.
• Ef is below Ed , in the rest of the
channel, Vch > 0 .
• Most of the voltage drops occur at
the source side where the local
carrier density is the lowest.

Case 3 : Vdirac < Vgs < Vdirac + Vds
• Ef is above Ed , Vch < 0, in part of
the channel, electron majority.
• Ef is below Ed , Vch > 0, in the
other part of the channel, hole
majority.
Case 4 : Vgs = Vdirac + Vds
• Ef and Ed coincide, Vch = 0, at the
drain side and in the rest of the
channel, Vch < 0
• Electron majority.
Case 5 : Vgs > Vdirac + Vds
• the voltage continues to increase Ef
and Ed move away from each other
everywhere in the channel, Vch < 0.
• The electron density and the
conductivity thereby continue to
increase.
Characteristic Curves:
From the below characteristic curve, we
observe the relation between drain current
(Ids) and drain voltage(Vds) of a graphene
field effect transistor with constant gate
voltage(Vgs=0.3V) for different channel
length(i.e.,3e-06m,5e-06m,7e-06m,) for
constant gate voltage and Dirac voltage ,
the Vds values range from 0.001 to 0.401
in increments of 0.05 and the Ids values are
given for each corresponding Vds value
and length. As Vds increase, the drain
current also increases for all lengths. The
longer the length, the larger the drain
current at any given Vds value. Thus, the
length is directly proportional to the drain
current.
From the curve below, we observe the
temperature characteristic against position
for the different lengths (i.e., 03×e-
06m,05×e-06m,07-06m) by keeping gate
voltage and Dirac voltage constant. For the
length (03×e-06m), the position begins at -
3.5 and temperature quickly rises to 501 &
temperature decreases as position
increases. For the length (05×e-06m), the
position begins at -4.5 and temperature
quickly rises to 600.403 & temperature
decreases as position increases. For the
length (07×e-06m), the position begins at -
5.5 and temperature quickly rises to
602.403 & temperature decreases as
position increases. By observing that as the
length increases, the position decreases
less. Temperature is inversely proportional
to length.
From the curve below, the graph between
electron density and position for different
channel lengths are maintained by keeping
the gate voltage and Dirac voltage
constant. For the length (03×e-.06 m), the
position starts at -3.5 and is kept constant
up to 2.37, and the electron density
increases linearly up to 7.9. Then, as the
position increases, the electron density
remains constant. For the length (05×e-06
m), the position starts at -4.5 and is kept
constant up to 2.4, and the electron density
increases linearly up to 7.9. Then, as the
position increases, the electron density
remains constant. For the length (07×e-06
m), the position starts at -5.5 and is kept
constant up to 2.5, and the electron density
increases linearly up to 7.9. Then, as the
position increases, the electron density
remains constant. By observing this, the
length increases, the position decreases,
and the electron density increases.
Issues for graphene FETs:
Despite the excellent properties
described above, graphene still needs to
wait until the realization of its commercial
devices. The following are the current
challenges for GFETs. The first challenge
is the opening of the band gap. From its
high mobility and high saturation velocity,
graphene, when it first appeared, was
considered a Si-substitute for CMOS logic
devices. However, FETs based on this
gapless material have found it difficult to
realize high enough on/Off ratios of the
drain current or which values as large as
104 ~107 are normally required. One of
the ways to open the band gap is to form
graphene nanoribbons (GNR). As we
shrink the GNR width to widen the gap,
however, contributions from the edge of
GNR to mobility begin to dominate, and
mobility decreases drastically. Out-of-
plane biasing of electric field on bilayer
graphene can also open the gap. Its effect
is limited, however, in that a field as large
as 2-3 V/nm can evoke a gap of only ~200
meV. The second challenge is to minimize
the graphene/substrate interaction. Top
data on graphene’s mobility have been
obtained by using air-suspended graphene
to avoid this interaction. Once the
graphene is contacted by a substrate, the
mobility is decreased by one order of
magnitude. The graphene’s mobility
degrades by several factors: charges on the
graphene, at the graphene/substrate
interface, phonons of the substrate, and at
the graphene/substrate interface. Elevation
in the dielectric constant of the gate
insulator is beneficial as it reduces the
Coulomb-scattering potential. The third
challenge is to realize a current saturation.
Current saturation is vitally important to
realize a high transconductance in FETs.
Because the lack of the band gap in
graphene inhibits the channel’s pinch-off
mechanism to be used for current
saturation, current saturation by velocity
saturation of carriers is critical in GFETs.
Velocity saturation is realized by using a
short-channel (~10 nm) device and by
applying a strong lateral field along its
channel. Carrier velocity is then saturated
by inelastic scatterings. In actual GFETs,
however, the high contact resistance of the
electrodes causes a high IR voltage to drop
and thereby reduces the effective lateral
field in the channel.
Conclusion:
The current status and outlook of
field-effect transistors based on graphene
(GFETs) have been assessed. To fabricate
GFETs, a graphene sheet must be
sandwiched from both sides: by a gate
insulator from the top and by a substrate
from the bottom. These two interfaces can
be a source of scatterings for carriers. High
contact resistance at source and drain
electrodes can impede the injection of
carriers to the channel and cancel out the
high voltage applied between source and
drain as well. To fully exploit the
exceptional transport properties of intrinsic
graphene, it is crucial to extensively
advance extrinsic technologies,
encompassing aspects such as the choice
of substrate and gate insulator and metal
electrodes. Future developments not only
on graphene itself but also on such
peripheral technologies will pave the way
to graphene-based devices.
References:
[1] K. S. Novoselov, A. K. Geim, S. V.
Morozov, D. Jiang, Y. Zhang, S. V. Dubonos,
I. V. Grigorieva, and A. A. Firsov, Science
306, 666, 2004.
[2] C. Berger, Z. Song, T. Li, X. Li, A. Y.
Ogbazghi, R. Feng, Z. Dai, A. N. Marchenkov,
E. H. Conrad, P. N. First, and W. A. de Heer,
J. Phys. Chem. B 108, 19912, 2004.
[3] A. S. Mayorov, R. V. Gorbachev, S. V.
Morozov, L. Britnell, R. Jalil, L. A.
Ponomarenko, P. Blake, K. S. Novoselov, K.
Watanabe, T. Taniguchi, and A. K. Geim,
Nano Lett. 11, 2396, 2011.
[4] E. V. Castro, H. Ochoa, M. I. Katsnelson,
R. V. Gorbachev, D. C. Elias, K. S.
Novoselov, A. K. Geim, and F. Guinea, Phys.
Rev. Lett. 105, 266601, 2010.
[5] G.P. Tang, J.C. Zhou, Z.H. Zhang, X.Q.
Deng, Z.Q. Fan, Altering regularities of
electronic transport properties in twisted
graphene nanoribbons, Appl. Phys. Lett. 101
(2012) 10–15,
https://doi.org/10.1063/1.4733618.
[6] S. Dutta, S.K. Pati, Novel properties of
graphene nanoribbons: a review, J. Mater.
Chem. 20 (2010) 8207–8223,
https://doi.org/10.1039/c0jm00261e.
[7] C. Berger, Z. Song, T. Li, X. Li, A. Y.
Ogbazghi, R. Feng, Z. Dai, A. N. Marchenkov,
E. H. Conrad, P. N. First, and W. A. de Heer,
J. Phys. Chem. B 108, (2004) 19 912.
[8] X. Wang, S. M. Tabakman, and H. Dai,
“Atomic layer deposition of metal oxides on
pristine and functionalized graphene,” J.
Amer. Chem. Soc., 130, (2008) 8152.
[9] F. Schwierz, Graphene transistors, Nat.
Nanotechnol. 5 (2010) 487–496, https://
doi.org/10.1038/nnano.2010.8