2022 SCHEME

ANALOG AND DIGITAL SYSTEMS DESIGN

LABORATORY (BECL305) MANUAL

LAB INCHARGE: SRINIVASAMURTHY R, Asst. Professor

STAFF INCHARGE: LEELA K P, Asst. Professor

III SEMESTER ELECTRONICS AND COMMUNICATION ENGG

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BANGALORE INSTITUTE OF TECHNOLOGY

BENGALURU
(Approved by AICTE, New Delhi & affiliated to VTU, Belagavi)
 DEPARTMENT OF ELECTRONICS
AND
COMMUNICATION ENGINEERING

VISION

Imparting Quality Education to achieve Academic

Excellence in Electronics and Communication
Engineering for Global Competent Engineers.

MISSION

 Create state of art infrastructure for quality education.

 Nurture innovative concepts and problem-solving skills.
 Delivering Professional Engineers to meet the societal
needs.
BANGALORE INSTITUTE OF TECHNOLOGY
BENGALURU

 Develop the Institute as a leader in Science,

Engineering, Technology and management, Research
and apply knowledge for the benefit of society.

 Establish mutual beneficial partnerships with industry,

alumni, local, state and central governments by public
service assistance and collaborative research.

 Inculcate personality development through sports,

cultural and extracurricular activities and engage in the
social, economic and professional challenges.

PROGRAMME EDUCATIONAL OBJECTIVES(PEOs)

01 Follow the schedule time, late comers will not be permitted.
02 Sign the Logbook available in the lab.
03 Compulsorily wear Footwear in the lab
04 Keep belongings in the specified place.
05 Students are expected to come prepared for experiments & VIVA
Show the completed observations book and submit record to the Teacher before the lab
06
session begins.
07 Cycle of experiments should be followed.

08 Don’t do the connections or remove the connections with power ON.

Check the circuit connections properly & get it checked, verified by staff
09
in – charge before switching it ON.
10 Follow all the safety measures as suggested by the Teachers / Lab Instructor.
Observe the instructions given by the Teacher / Lab Instructor and strictly follow
11
accordingly.
Report to the Teacher / Lab Instructor immediately in case of any Software / Hardware
12
/ Electrical failure during working. Never try to fixit manually / individually
Switch OFF the instruments, remove all connections & return components before
13
leaving the lab.
14 Get the observations verified / signed by the teacher before leaving the lab.
15 Maintain discipline & tidiness inside the lab. Attend the lab in formal attire.
Usage of Mobile phones, Pen Drive and Electronic Gadgets are restricted during the
16
lab session.

** You are Under CCTV Surveillance.

 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI

B.E: Electronics & Communication Engg / Electronics & Telecommunication Engg

NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS) (Effective
from the academic year 2023 – 22)

III Semester 2022 Scheme

Analog and Digital Systems Design Lab

Course Code BECL305 CIE Marks 50
Teaching Hours/Week (L: T:P: S) 0:0:2 SEE Marks 50
Credits 01 Exam Hours 3
Course objectives:
This laboratory course enables students to
 Understand the electronic circuit schematic and its working
 Realize and test amplifier and oscillator circuits for the given specifications
 Realize the op-amp circuits for the applications such as DAC, implement mathematical
functions and precision rectifiers.
 Study and test the RC triggering circuit.
 Design and test the combinational and sequential logic circuits for their functionalities.
 Use the suitable ICs based on the specifications and functions.

SL. Experiments (all the experiments has to be conducted using discrete

No components)
1 Design and set up the BJT common emitter voltage amplifier with and without
feedback and determine the gain- bandwidth product, input and output impedances.
2 Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator.
3 Design and set up the circuits using op-amp: i) Adder, ii) Integrator iii) Differentiator
and iv) Comparator
4 Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) for a 4-bit binary input
using toggle switches (ii) by generating digital inputs using mod-16 counter
5 Design and implement (a) Half Adder & Full Adder using basic gates and NAND
gates, (b) Half subtractor & Full subtractor using NAND gates, (c) 4-variable
function using IC74151(8:1MUX).
6 Realize (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to
Excess-3 code conversion and vice versa
7 a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and
iii) T Flip-Flop b) Realize the shift registers using IC7474/7495: (i) SISO (ii)
SIPO
b) (iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter.
8 Realize a) Design Mod – N Synchronous Up Counter & Down Counter using 7476
JK Flip-flop b) Mod-N Counter using IC7490 / 7476 c) Synchronous counter using
IC74192
Demonstration experiments (for CIE)
9 Design and test the second order Active Filters and plot the frequency response,
i) Low pass Filter
ii) High pass Filter
10 Design and test the following using 555 Timer
i) Monostable Multivibraator

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

ii) Astable Multivibrator

11 Design and Test a Regulated Power supply
12 Design and test an audio amplifier by connecting a microphone input and observe the
output using a loud speaker.

Course outcomes (Course Skill Set):

At the end of the course the student will be able to:

1. Design and analyze the BJT/FET amplifier and oscillator circuits.
2. Design and test R-2R DAC circuit using Op-amp.
3. Design and test the combinational logic circuits for the given specifications.
4. Test the sequential logic circuits for the given functionality.
5. Demonstrate the basic electronic circuit experiments using op-amp and 555 Timer.

Assessment Details (both CIE and SEE):

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End
Exam (SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum
marks (20 marks out of 50) and for the SEE minimum passing mark is 35% of the
maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student
secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together. Continuous

Continuous Internal Evaluation (CIE):

CIE marks for the practical course are 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment is to be evaluated for conduction with an observation sheet and
record write-up. Rubrics for the evaluation of the journal/write-up for
hardware/software experiments are designed by the faculty who is handling the
laboratory session and are made known to students at the beginning of the practical
session.
 Record should contain all the specified experiments in the syllabus and each
experiment write-up will be evaluated for 10 marks.
 Total marks scored by the students are scaled down to 30 marks (60% of maximum
marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct a test of 100 marks after the completion of all the
experiments listed in the syllabus.
 In a test, test write-up, conduction of experiment, acceptable result, and procedural
knowledge will carry a weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and
learning ability.
 The marks scored shall be scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and marks of a
test is the total CIE marks scored by the student.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Semester End Evaluation (SEE):

 SEE marks for the practical course are 50 Marks.

 SEE shall be conducted jointly by the two examiners of the same institute,
examiners are appointed by the Head of the Institute.
 The examination schedule and names of examiners are informed to the university
before the conduction of the examination. These practical examinations are to be
conducted between the schedule mentioned in the academic calendar of the
University.
 All laboratory experiments are to be included for practical examination.
 (Rubrics) Breakup of marks and the instructions printed on the cover page of the
answer script to be strictly adhered to by the examiners. OR based on the course
requirement evaluation rubrics shall be decided jointly by examiners.
 Students can pick one question (experiment) from the questions lot prepared by the
examiners jointly.
 Evaluation of test write-up/ conduction procedure and result/viva will be conducted
jointly by examiners. General rubrics suggested for SEE are mentioned here,
writeup-20%, Conduction procedure and result in -60%, Viva- voce 20% of
maximum marks. SEE for practical shall be evaluated for 100 marks and scored
marks shall be scaled down to 50 marks (however, based on course type, rubrics
shall be decided by the examiners)
 Change of experiment is allowed only once and 15% of Marks allotted to the
procedure part are to be made zero.
 The minimum duration of SEE is 03 hours

SL I CYCLE Experiments
No.
Design and setup the BJT Common Emitter voltage amplifier with and without feedback
1
and determine the gain bandwidth product, input and output impedances.
2 Design and set-up BJT i) Colpitts Oscillator, ii) Crystal Oscillator.
Design and implement (a) Half Adder & Full Adder using basic gates and NAND gates,
3 (b) Half subtractor & Full subtractor using NAND gates, (c) 4-variable function using
IC74151(8:1MUX).
Realize (i) Binary to Gray code conversion & vice-versa (IC74139) (ii) BCD to Excess-3
4
code conversion and vice versa

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

INTRODUCTION:

i) Analog part:
Study of equipments and components
Regulated DC Power supply:

Analog CRO:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Digital CRO:

Digital Signal Generator:

Digital Multimeter:

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ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Voltmeter:

Ammeter:

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ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Pin Diagram of IC uA 741 Op-Amp:

Pin Diagram of IC 555 timer:

Note: Draw the symbols and brief about the following

Resistors, capacitors, inductors, Potentiometers, Diodes, Transistors,
Transformer and SCR.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

ii) Digital part:

DIGITAL IC TRAINER KIT:

DIGITAL IC TRAINER KIT:

The equipment mainly used to test and set up digital circuits. Integrated circuits
can be fitted in sockets or bread board. There are built in voltage sources and
clock signals. Mono-pulse is used to apply clock manually. A number of select
switches are provided to obtain ‘0’ or ‘1’ state voltages as digital inputs. Green
and Red LEDs are provided to represent low and high states respectively to
visualize the digital outputs.

The following facilities are available in Digital IC trainer for conduction of

TTL/CMOS IC Experiments:

♦ Input Switch: Provides switch for Input AC Power.

♦ Power Indicator: Illuminates to indicate the presence of AC power.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

♦ Logic Output status Indicator: Individual LED Display Logic Output status
(High or Low).

♦ Input Logic Switches: Logic Input status Level (High or Low) with LED
Indicators.

♦ TTL Clocks: Frequency of 1Hz, 10Hz, 100Hz, 1 kHz and Mono-pulse.

♦ Connecting Sockets: 2mm/4mm Socket or terminals to connect patch cards.

♦ +5Volts Output: This delivers necessary VCC to all digital circuits.

♦Dual supply: +12V and -12V supply used for Op-Amp IC’s

♦GND: Common Ground.

♦16 pin Zero Insertion Force (ZIF) sockets and 40pin ZIF socket/ bread board

IC PACKAGES: 7404-Hex inverter gates, 7400-Quad two input NAND gates,

7402-Quad two input NOR gates, 7408-Quad two input AND gates, 7432-Quad
two input OR gates, 7486-Quad two input XOR gates,7410-3 Input Triple NAND
Gates,7420- 4 Input Dual NAND Gates.

PIN DIAGRAMS:

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ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Truth Table:

AND gate OR gate NOT gate

Y=A.B Y=A+B ̅
Y=𝑨
Input Output Input Output Input Output
A B Y A B Y A Y
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

NAND gate NOR gate, XOR gate XNOR gate

̅̅̅̅
Y=𝑨𝑩 Y=𝑨 ̅̅̅̅̅̅̅̅
+𝑩 Y=A ⊕ B Y=𝑨 ̅̅̅̅̅̅̅̅̅
⊕𝐁
Input Output Input Output Input Output Input Output
A B Y A B Y A B Y A B Y
0 0 0 0 0 1 0 0 0 0 0 1
0 1 0 0 1 0 0 1 1 0 1 0
1 0 0 1 0 0 1 0 1 1 0 0
1 1 1 1 1 0 1 1 0 1 1 1

Procedure:

1. Identify the IC required.

2. Check the components for their working.
3. Insert the appropriate IC into the IC base of the trainer kit such that the notch
of the IC is facing towards the Vcc, where the IC pin no. 7 and 14 are connected
to ground and VCC respectively.
4. Make connections as shown in the diagram. Switch ON the power supply.
5. Provide the input data via the input switches as per the truth table and observe
the output on-output LEDs.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

I Cycle Experiments:
EXPERIMENT NO - 1
AIM: Design and setup the BJT Common Emitter voltage amplifier with and
without feedback and determine the gain bandwidth product, input and output
impedances.

Components and Equipments Required: Transistor (BC107), resistors,

capacitors, DC power supply, signal generator, Multimeter, connecting wires and
Board, CRO, CRO probes.

Theory: In the circuit shown the NPN transistor is connected as a Common

emitter (CE) ac amplifier in which the voltage divider biasing (Voltage divider
network is formed by the resistors R1 and R2). For proper functioning of
transistor as an amplifier the transistor must be biased in the active region. Input
resistance of the amplifier Ri= R1|| R2||(1+hfe) re with the bypass capacitor CE
is connected and Ri = R1|| R2||(1+hfe) (re+ RE) with CE removed, where re= VT
/RE, where re is the internal emitter resistance of the transistor and V T = 26mV i.e
the equivalent thermal voltage at room temperature. The output resistance of the
amplifier R0 ≈ RC, where RC is the collector resistance. The purpose of the bypass
capacitor CE is to bypass signal current to the ground. the ac signal (feedback)
voltage developed across the emitter resistance R E is bypassed through CE. Since
bypassing increases the negative feedback the gain of the amplifier decreases.
This implies that when the bypass capacitor C E is connected the gain of the
amplifier increases and band width decreases and when disconnected the gain
falls and bandwidth increases. The purpose of the coupling capacitor C c1 and Cc2
is to block dc and to couple ac signal to the input and output of the amplifier
respectively. The coupling capacitors also determine the lowest frequency which
is to be amplified.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

CE amplifier without feed back

CIRCUIT DIAGRAM :

OUTPUTWAVE FORM:

DESIGN:

Given: Vcc =10V, Ic =2mA, hfe or β=100 to 150 choose BC 107

To find RE:
VRE =Vcc /10=1V
IE = I C = 2mA, RE = VRE/IE =1/2x10-3 = 500Ω (choose 470Ω)
To make the operating point in the middle of the load line take VCE =Vcc /2=5V

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

To find RC:
Applying KVL to output loop.
Vcc–VRC–VCE– VRE = 0
VRC = Vcc – VCE– VRE = 10 – 5 – 1 = 4V
RC = VRC/ I C = 4 / 2x10-3 = 2kΩ (choose 2.2kΩ)

To find R1 and R2

Assume Stability factor, S = 5 and β = 100

S = (1+β) (RE +RTh) / (1+β) RE +RTh
Where RTh = R1 R2 / (R1+ R2) = 2.1kΩ
VR2 = VBE + V RE = 0.7 + 1 =1.7V
VTh =VR2 = Vcc R2 / (R1+ R2)
R2/ (R1+ R2) = VTh / Vcc = 1.7 / 10 = 0.17V
RTh = R1 R2 / (R1 + R2), Solving R1 = 12.3KΩ, R2 = 2.5kΩ
Choose R1 = 12kΩ, R2 = 2.2 kΩ

To find CE :
X CE= 1/ (2πf CE)
As a thumb rule take XCE= (1 / 10) RE= 50 Ω
For fL= 100 Hz, (lower frequency) CE= 31.8µF (choose 47µF)
1
Choose the coupling capacitors Cc= where Ri = R1||R2|| (1+hfe) re
2𝜋 𝑋 𝑅𝑖 𝑓𝐿

re = 25mV/ IE = 12.5Ω, up to 1µF can be selected. Choose 0.47µFand RL= 10kΩ

PROCEDURE:

Find Q point (VCE, I C):

1. The Connections are made as per the circuit diagram.

2. Before applying AC input signal, without connecting capacitors the DC
conditions are checked by setting Vcc =10V. Check VCE = 1 / 2 Vcc ≈ 5V,
VRE≈ 1V, VBE ≈ 0.7V and VRC ≈ 4V using multimeter. Calculate I C =VRC / Rc.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

To determine Gain and Frequency Response: Connect the capacitors in the

circuit. Apply input sinusoidal signal Vin = 20 m V peak to peak to 50 m V peak
to peak using audio signal generator. Observe input and output wave forms
simultaneously on the CRO.

3. Keeping the input signal amplitude Vin constant at 20mVp-p, the frequency
of the input signal is varied from 100 Hz to 1 MHz in suitable steps measure
the output peak to peak voltage for different frequencies and enter it in a
tabular column. The gain of the amplifier is calculated from these values.
4. The gain in dB is calculated and tabulated. The graph of gain vs frequency is
plotted on a semi log graph sheet. Plot the frequency response characteristics
on a semi log graph sheet with gain in dB on Y-axis and frequency in Hz on
X-axis. Mark fL and fH corresponding to 3dB points. Bandwidth is calculated
from the frequency response using expression BW= fH - fL. Determine the
mid-band gain from graph, also Calculate Gain Band Width (GBW) product.
5. Remove the bypass capacitor CE from the circuit and repeat the steps 4 to 6.
Observe the increase in band width and decrease in gain in the absence of
CE

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Tabular column:

Vin = 20 mVp-p CE amplifier without feedback (with CE)

Frequency Vo (peak to peak) Gain Gain in DB

f (Hz) (Volts) AV = Vo / Vi AV= 20 log 10 (Vo / Vi)

100Hz
.
.
.
.
.
.
.
.
.
.
.
.
1MHz

Vin = 20 mV CE amplifier with feedback (without CE)

Frequency Vo (peak to peak) Gain Gain in DB
f (Hz) (Volts) AV = Vo / Vi AV = 20 log 10 (Vo / Vi)

100Hz
.
.
.
.
.
.
.
.
.
.

1MHz

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

FREQUENCY RESPONSE CURVE:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

To measure the input impedance Zi with feedback (Without CE) and without
feedback (With CE):

PROCEDURE:

1. Connect 5kΩ potentiometer in series with Signal Generator and CC1 as

shown in the above the circuit diagram.
2. Display the output wave form in mid band frequency i.e maximum output
voltage (Vomax).
3. Vary the potentiometer till output reduces to half of its maximum value.
4. Remove the potentiometer, measure the resistance using ohmmeter. This
is the value of input impedance Zi of the amplifier.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

To measure the output Impedance Zo With feedback (Without CE) and

Without feedback (With CE)

PROCEDURE:

1. Connect 10kΩ potentiometer across the RL as shown in above circuit diagram.

2. Display the output wave form in mid band frequency i.e maximum output
voltage (Vomax).

3.Vary the potentiometer till output reduces to half of its maximum value.

4.Remove the potentiometer, measure the resistance using ohmmeter. This is the
value of output impedance Zo of the amplifier.

RESULT:

Parameters Without feedback With feedback

Midband Gain (Av mid) = Amax -3dB
Band width BW = fH - fL in kHz
GBW in kHz (Av mid X BW)
Input Impedance in Ω
Output Impedance in Ω

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

EXPERIMENT NO - 2

AIM: To design and set up BJT i) Colpitts oscillator and ii) Crystal oscillator for
measuring frequency of oscillations and amplitude.
Components and Equipments Required: Transistor (BC107), resistors,
capacitors inductors, potentiometer, Crystal (1MHz), DC power supply, CRO,
CRO probes, multimeter, connecting wires and Board.

THEORY:

Colpitts Oscillator: The Colpitts oscillator uses a capacitive voltage divider

network as its feedback source. The emitter terminal of the transistor is effectively
connected to the junction of the two capacitors, C1 and C2 which are connected
in series and act as a simple voltage divider.

Crystal oscillator: As the name implies, they are made from quartz, a naturally
occurring form of silicon, although most of that used for electronics applications
is manufactured synthetically these days. The components rely on the remarkable
properties of quartz for their operation. When placed into an electronic circuit a
crystal acts as a very high-quality tuned circuit. In addition to this they are very
stable and their resonant frequency does not vary much with time or temperature.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Colpitts Oscillator:

DESIGN:

AMPLIFIER DESIGN

Given: Vcc =10V, Ic =2mA, hfe = 100 to 150, Choose BC 107

To find RE:

Vcc
VRE = =1V
10

VRE
IE = I C = 2mA, RE = = 1/2x10-3=500Ω (choose 470Ω)
IE

To find RC:

In order to make the operating point in the middle of the load line

Take VCE =Vcc /2=5V

Applying KVL to output loop.

VCC – VRC – VCE - VRE= 0

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

VRC = Vcc-VCE - VRE = 10 – 5 – 1 = 4V

RC = VRC / I C = 4 / 2x10-3 = 2kΩ(choose 2.2kΩ)

To find R1 and R2

Assume stability S = 5,

S = (1+β) (RE +RTh) / (1+β) RE +RTh

R1 R2
Where Rth = i.e Rth = 2.086kΩ (using above stability factor
(R1+ R2 )

equation)

VR2 = V BE +V RE = 0.7 + 1 =1.7V

Vcc R2
Vth = VR2 =
(R1+ R2 )

R2 Vth
= = 1.7 / 10 = 0.17V
(R1+ R2 ) Vcc

R1 R2
Rth = , Solving R1 = 12.27kΩ, R2 = 2.2kΩ
(R1+ R2 )

Choose R1 = 12kΩ, R2 = 2.2 kΩ

To find CE :

1
X CE = As a thumb rule take X CE= (1 / 10) RE = 50 Ω
(2π𝑓𝐿 𝐶𝐸 )

For fL= 100Hz, (lower frequency) CE = 31.8µF (choose 47µf)

1
Choose the coupling capacitors C c= , Ri = R1||R2|| (1+hfe) re
2𝜋 𝑋 𝑅𝑖 𝑓𝐿

re = 25mV/ IE = 12.5Ω, up to 1µF can be chosen Choose 0.47µF

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

FEED BACK CIRCUIT DESIGN:

Frequency of oscillations f = 100KHz

f = 1/2π√ LC --------- (1) where C = C1C2/C1+C2,

Let C1 = 4700pF, C2 = 2200pF then β = C2/C1= 0.46

On solving eq (1) we get L = 1.69mH, choose L = 1mH.

BJT CRYTAL OSCILLATOR:

AMPLIFIER DESIGN: Refer Colpitts Oscillator except feedback circuit design

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

PROCEDURE:

1. Without Connecting the feedback circuits of Colpitts Oscillator, Phase-

shift oscillator and crystal oscillator (i.e.,1MHz crystal and 0.01µFand
1000pF), the amplifier circuit is connected as per the circuit. The DC
conditions of the amplifier is checked by setting Vcc =10V, VCE must be
1
half of the Vcc ≈ 5V, VRE ≈ Vcc ≈ 1V, VBE ≈ 0.7V and check VRC = 4V,
10

using multi meter. Calculate IC = VRC/ Rc. Find Q point (VCE, I C).
2. Connect the feedback circuit, vary the potentiometer to get undistorted
sine wave output.
3. Measure the amplitude and frequency of oscillations for Colpitts
Oscillator, Phase-shift oscillator and crystal oscillator. Compare
theoretical and practical frequency.

OUTPUT WAVEFORM

RESULT:

Colpitts Crystal
Oscillator Oscillator
Theoretical Frequency (Hz)
Practical Frequency (Hz)

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

EXPERIMENT NO - 3

AIM: Design and implement (a) Half Adder & Full Adder using basic gates and
NAND gates, (b) Half subtractor & Full subtractor using NAND gates(c) 4-
variable function using IC74151(8:1MUX).

Components and Equipments Required:

IC 7400, 7404,7408, 7432, 7486, 74151, Patch Cards and Digital IC Trainer Kit.

Theory:

Half Adder: Half Adder is a binary adder which can add bits A, B and
generates 2 output bits S and Co representing sum and carry respectively.
Boolean expression for Sum, S = A ⊕ B, or 𝑨̅ 𝐁 + 𝐀 𝑩
̅ Boolean expression
for carry, Co = AB

Full Adder: Full adder is a binary adder which can add 3 input bits A, B and
Cin and generates 2 output bits sum ‘S’ and carry out ‘Cout’, Cin is the carry

input from the previous stage. Boolean expression for Sum, S = A ⊕ B ⊕ Cin
Boolean expression for carry, Co = AB + BCin + ACin

Half Subtractor: Half Subtractor is a binary Subtractor which has two input
bits A, B and generates 2 outputs, difference D and borrow out Bo.Boolean
expression for Difference, D= A ⊕ B
̅ B
Boolean expression for borrow out, Bo = 𝑨

Full Subtractor: Full Subtractor is a combinational logic circuit which has 3

input bits A, B and Bin (the Borrow input from the previous stage) and
generates 2 output bits difference D and borrow Bo Boolean expression for
Difference, D = A ⊕ B ⊕ Bin
Boolean expression for borrow out Bo = 𝑨̅ 𝐁𝐢𝐧 + 𝑨̅ B + B Bin

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

IC74151: is an 8 - Input Multiplexer 16 Pin IC. Data Selector/Multiplexer

contains full on-chip decoding to select one-of-eight data sources as a result of a
unique three binary code at select inputs. Two complementary outputs provide
both inverting and non-inverting buffer operation. Used for Boolean Function
Generator.

(a) Realization of Half Adder using Basic gates.

Truth Table
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

S = A ⊕ B or 𝑨̅ 𝐁 + 𝐀 𝑩
̅ Co = AB

Logic Diagram:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Half Adder using NAND gates:

Logic Diagram:

Realization of Full Adder using Basic gates:

Truth Table
A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S = ∑ (1,2,4,7) and Co = ∑ (3,5,6,7)

S = A ⊕ B ⊕ Cin, Co = AB + BCin + ACin

Simplify Sum S and Carry out Co expression using 3 variable K Map

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Logic Diagram:

Realization of Full Adder using NAND gates:

Logic Diagram:

(b) Realization of Half subtractor using basic gates:

Truth Table
A B D Bo
D = A ⊕ B or𝑨̅ 𝐁 + 𝐀 𝑩
̅,
0 0 0 0
0 1 1 1 Bo = 𝑨̅ B
1 0 1 0
1 1 0 0

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Logic Diagram:

Realization Half subtractor using NAND gates:

Logic Diagram:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Full subtractor using Basic gates:

Truth Table
A B Bin D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
D = ∑ (1,2,4,7) and Bo = ∑ (1,2,3,7)
D = A ⊕ B ⊕ Bin Bo = 𝑨̅ 𝐁𝐢𝐧 + 𝑨̅ B + B Bin
Simplify Difference D and Borrow out Bo using 3 variable K Map

Logic Diagram:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Full subtractor using NAND gates:

Logic Diagram:

c) REALIZATION OF THREE VARIABLE FUNCTION USING

IC74151(8:1MUX):

IC74151(8:1MUX) Details:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

i) Realize Y= f (A, B, C) = ∑ (0,2,4,7) using 8:1 MUX

Truth Table:

SL.No A B C Y
0 0 0 0 1
1 0 0 1 0
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1

Implementation:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

REALIZATION OF FOUR VARIABLE FUNCTION USING

IC74151(8:1MUX):

Realize Y = f (A, B, C, D) = Σ (1,2,4,5,8,12,13,14,15)

Implementation table:

̅
𝐷 D

I0 0 1 D

I1 2 3 ̅
𝐷

I2 4 5 1

I3 6 7 0

I4 8 9 ̅
𝐷

I5 10 11 0

I6 12 13 1

I7 14 15 1

Implementation:

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

PROCEDURE:
1. Test all the components required.
2. The connections are made as per the logic diagram using the pin diagram of
different ICs used.
3. Switch on the IC trainer kit. Apply the inputs and observe the outputs
corresponding to all the input combinations.
4. Verify all the logic diagram outputs using their truth table.

Result: verified the truth tables of all the logic diagrams.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

EXPERIMENT NO - 4

AIM: To Realize:
(i) Binary to Gray code conversion & vice-versa (IC74139).(ii) BCD to Excess-
3 code conversion and vice versa.

Components and Equipments Required: IC74139, IC7420, IC7404, Patch

Cards and Digital IC Trainer Kit and connecting wires.
Theory:

BINARY to GRAY Converter: The MSB of the gray code is equivalent to the
MSB of the binary code. Other bits of the gray code’s output can be got using
EX-OR the present binary code index as well as the next highest binary code
index. The below figure shows diagram for 3-bit conversion.

G2 = B2, G1 = B2 ⊕ B1, G0 = B1 ⊕ B0.

GRAY to BINARY Converter: The MSB of the binary code is equivalent to the
MSB of the gray code. To get the next binary bits perform EXOR operation
among the present gray code index and the next highest binary code. The below
figure shows diagram for 3-bit conversion.

B2 = G2, B1 = B2 ⊕ G1, B0 = B1 ⊕ G0.

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

BCD to Excess-3 code conversion and vice versa: Code converter is a

combinational circuit that translates the input code word into a new corresponding
word. The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder
feed BCD code to the 4-bit adder as the first operand and then feed constant 3 as
the second operand. The output is the corresponding excess-3 code. To make it
work as a excess-3 to BCD converter, we feed excess-3 code as the first operand
and then feed 2's complement of 3 as the second operand. The output is the BCD
code.

(i) Binary to Gray code conversion (IC74139):

Truth Table:
Binary Inputs Gray Outputs
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

Go = Σ (1,2,5,6), G1 = Σ (2,3,4,5).
Simplify above expression using 3 variable K Map
G2 = B2, G1 = B2 ⊕ B1, G0 = B1 ⊕ B0

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Implementation:

IC 74139

Gray to Binary code conversion (IC74139):

Gray Inputs Binary Outputs

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 0 0
1 1 1 1 0 1

Bo = Σ (1,2,4,7) B1 = Σ (2,3,4,5)

Simplify above expression using 3 variable K Map

B2 = G2 B1 = B2 ⊕ G1 B0 = B1 ⊕ G0

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Implementation:

(ii) BCD to Excess-3 code conversion:

Truth Table:
SL BCD INPUTS EXCESS-3 OUTPUTS
No B4 B3 B2 B1 E4 E3 E2 E1
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0

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ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Implementation:

BCD to Excess-3 code conversion logic diagram:

Excess-3 to BCD code conversion:

Truth Table:
SL EXCESS-3 INPUTS BCD OUTPUTS
No E4 E3 E2 E1 B4 B3 B2 B1
0 0 0 1 1 0 0 0 0
1 0 1 0 0 0 0 0 1
2 0 1 0 1 0 0 1 0
3 0 1 1 0 0 0 1 1
4 0 1 1 1 0 1 0 0
5 1 0 0 0 0 1 0 1
6 1 0 0 1 0 1 1 0
7 1 0 1 0 0 1 1 1
8 1 0 1 1 1 0 0 0
9 1 1 0 0 1 0 0 1

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 ANALOG AND DIGITAL SYSTEMS DESIGN LABORATORY(ECL305)

Implementation:

Excess-3 to BCD code conversion logic diagram:

PROCEDURE:
1. Test all the components required.
2. The connections are made as per the diagram.
3. Switch on the IC trainer kit. Apply the inputs and observe the outputs
corresponding to all the input combinations.
4. Verify all the logic diagram outputs using their truth table

RESULT: Verified the truth tables of all the logic diagrams.

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