Electronic Principles and Circuits Lab Manual - BEC303 - 18-11-2023

ELECTRONIC PRINCIPLES AND CIRCUITS LABORATORY
BEC303
CMR INSTITUTE OF TECHNOLOGY

132, AECS LAYOUT, ITPL MAIN ROAD, BANGALORE 560037
DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
ELECTRONIC
PRINCIPLES AND
CIRCUITS LABORATORY
MANUAL
SUBJECT CODE: BEC303
APPROVED BY: SIGNED BY:
Prof. Pappa M Dr. R Elumalai
Program Coordinator Head of Dept.
CONTRIBUTED BY :
1 . Dr. Meenakshi R Patil 3. Dr.Sridhar .N 5. Prof. Anju Das
2 . Dr. Naveen Kumar G.N. 4. Dr.Ananth Kumar M.S.
DEPARTMENT OF ECE, CMRIT 1

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Syllabus Contents
Syllabus Contents
Sl.NO Experiments
1 Design and Test
(i) Bridge Rectifier with Capacitor Input Filter
(ii) Zener voltage regulator
2 Design and Test

Biased Clippers – a)Positive, b) Negative , c) Positive-
Negative Positive and Negative Clampers with and without
Reference.
3 Plot the transfer and drain characteristics of a JFET and calculate its drain resistance, mutual conductance
and amplification factor.
4 Plot the transfer and drain characteristics of n-channel MOSFET and calculate its parameters, namely;
drain resistance, mutual conductance and amplification factor.
5
Design and test (i) Emitter Follower , (ii) Darlington Connection
6
Design and plot the frequency response of Common Source JFET/MOSFET amplifier
7
Test the Opamp Comparator with zero and non zero reference and obtain the Hysteresis curve.
8
Design and test Full wave Controlled rectifier using RC triggering circuit.
9 Design and test Precision Half wave and full wave rectifiers using Opamp
10 Design and test RC phase shift oscillator

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Expt.No.1 : Design and Test

(i) Bridge Rectifier with Capacitor Input Filter
(ii) Zener voltage regulator
BRIDGE RECTIFIER
Aim: Design and Testing of Full wave Bridge type rectifier circuit
with Capacitor filter. Determination of ripple factor, regulation
and efficiency.
OBJECTIVE :
To calculate the ripple factor, efficiency and regulation of the bridge rectifier at different loads, each
with filter.
COMPONENTS REQUIRED :
Sl. No. Components Details Specification Qty

1. Diode BY127 4
2. Capacitors 470µF 1
3. Decade resistance box 1
4. Step down transformer with centre-tap 12 V 1
5 CRO, Multimeter, Connecting Board, Connecting wires
THEORY :
Bridge rectifier circuit is a full wave rectifier consisting of a resistive load, four diodes forming the four
arms of a bridge and a source of ac voltage. The rectifying element i.e. the diode, conducts only during one
half cycle of the input ac supply when it is forward biased. Hence four diodes are connected such that two
in series are forward biased for one half of the cycle each. Hence output is obtained for both half cycles.
To one diagonal of the bridge, the ac voltage is applied through a transformer and the rectified DC voltage
is taken from the other diagonal of the bridge.
The DC output waveform is expected to be a straight line but the bridge rectifier gives output in the form
of only positive or negative sinusoidal pulses. Thus the output waveform is a pulsating DC waveform.
The main advantage of this circuit is that it does not require a center tap on the secondary winding of the
transformer, AC voltage can be directly applied to the bridge.
The ripple factor indicates the AC content (ripples) present in the output DC voltage. It is thus defined as
ratio of the RMS value to the average value of the output waveform. Ripples are reduced by using a
capacitor acting as a filter, resulting in a smoother waveform i.e. higher average value of the output DC
voltage.
Conversion efficiency is defined as ratio of the output power to the input power. Efficiency for a particular
load increases as ripple content is reduced using filters.
Regulation of the rectifier is defined as the drop in terminal voltage of the rectifier for a particular load
from that of no load expressed as a percentage of the no-load terminal voltage. This value indicates the
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load performance of the circuit.
CIRCUIT DIAGRAM :
BRIDGE RECTIFIER WITH FILTER CAPACITOR
PROCEDURE :
1. Connections are made as shown in the circuit diagram.

2. Switch on the AC power supply.
3. Observe the voltage waveform across the load resistor on the CRO and note down the output
amplitude and frequency.
4. Measure and note the following as per the given instructions for different load resistances :
5. Calculate the values of input RMS current, ripple factor, efficiency and regulation for each load
resistance using the formulae mentioned in the previous section.
OBSERVATION :
Amplitude : ……………
Frequency : ……………
VNL : ……………
TABULAR COLUMN :
Efficiency=
VAC= VRMS Ripple= Regulation=
RL (VNL-
VR(P-P) VDC VAC/ VDC
(Ω) =√(V2rms-V2 DC) VFL)/VFL
(%)
(%)

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WAVEFORMS :
VIN
20
0
t
- 20
VO
20
0 Vo (Without filter)
t
VC
Vo (With filter)
RESULT:
Output waveform of full wave rectifier using centre tapped transformer have been observed and
ripple factor, efficiency and regulation is calculated.
VIVA VOCE:
1. What is a rectifier ?
Rectifier is a circuit which converts AC waveform into DC.
2. What are the different types of rectifiers ? Explain their working.

HWR- one half of a cycle appears at the output, other half is eliminated
FWR- both halves of the cycle appears at the output, one half is inverted
BR - both halves of the cycle appears at the output, one half is inverted
3. List few differences between a bridge and full wave rectifier.

FWR BR
Uses 2 diodes Uses 4 diodes
PIV rating of diode is equal to peak value PIV rating of diode is half the peak value
Diode drops are less Diode drops are high
Needs centre tapped transformer Does not need a centre tapped transformer
4. Can a FWR be built without using a centre-tapped transformer ?

No.

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5. State some applications of rectifiers.

Mobile chargers. Torches, Radio, HVDC transmission, VFDs
6. What are ripples ? Define ripple factor and state its significance.
Ripples are the periodically alternating content present in the waveform. Ripple factor is defined as the ratio of
rms voltage of the measuring quantity to its average value. It indicates the amount of AC present in the DC
waveform.
7. State the standard values of ripple factor for each type of rectifier.
HWR-1.21
FWR and BR -0.48
8. Define conversion efficiency of a rectifier. What is its significance ?

Conversion efficiency is the ratio of DC output power to the AC input power. It indicates the performance of the
rectifier.
9. State the theoretical values of efficiency for each type of rectifier.

HWR-40.6 %
FWR and BR -81.2%
10. Define regulation of a rectifier. State its significance.

Regulation is defined as the drop in terminal voltage of the rectifier from no load to that on a particular load,
expressed as percentage of voltage on load. It indicates the load performance of the rectifier.
11. What is a filter used for in a rectifier ? Explain its working.

Filter is used to reduce ripples in the pulsating output waveform. While the supply waveform is increasing,
capacitor charges to the peak value of the supply voltage and while the waveform is reducing, the capacitor
discharges through the load resistor. Output voltage is the voltage across the capacitor.
12. State the design formula for filters for each type of rectifier.
HWR 1
C
2 3 frRL

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FWR and BR 1
C
4 3 frRL
13. How does the filter vary the average value, efficiency and ripple factor of the output voltage?
As the filter value increases, the ripple factor reduces, the average value of the output voltage and hence
efficiency increases.
14. State the average voltage values of the output under the following conditions (ignoring voltage drops across
components) :
a) HWR, with 12V centre-tapped transformer , without filter – 5.4 V
b) FWR, with 12V centre-tapped transformer, without filter – 10.8 V
c) BR, with 6V centre-tapped transformer, without filter – 10.8 V
15. What is a centre-tapped transformer? What is off nominal ratio ?

A transformer with tapping taken out at the centre of the windings. Voltage ratio of the tapping will be 1:1, called
the nominal ratio. If the tapping is taken away from centre, the ratio changes, and is called the off nominal ratio.
16. Define PIV rating of a diode.

The maximum voltage the diode can safely tolerate across its terminals when it is reverse biased.
17. Compare the PIV rating of the diodes in different types of rectifiers ?
HWR and FWR have PIV rating equal to peak supply voltage, while BR will have rating half the supply voltage.
18. What is the function of a coupling capacitor ?

Coupling capacitors are used to block DC and permit only AC across.
19. What is the voltage across the diode in each type of rectifier under the following situations :
a) Conducting period
b) Reverse biased period
Type of rectifier Conducting period Reverse biased period
HWR 0.7 Peak value of supply voltage
FWR 0.7 Peak value of supply voltage
BR 0.7 Half the peak value of supply voltage
20. What is the range of internal impedance of an ammeter and a voltmeter ?
Ammeter – very low impedance
Voltmeter – very high impedance
21. Why shouldn’t ammeters be connected in parallel to the supply in the circuit?
The internal impedance being very low, supply gets shorted, hence very high current flows through the ammeter
damaging the meter.
22. What do the following meters indicate ?

a) AC ammeter and voltmeter – RMS values of current and voltage
b) DC ammeter and voltmeter - Average values of current and voltage
23. What is the frequency of ripples obtained in the output waveform for each type of rectifier if the supply is 60 Hz?
HWR – 60Hz
FWR and BR – 120 Hz
24. State some advantages and disadvantages of a bridge or full wave rectifier over half wave rectifier.
a) The rectification efficiency of full-wave rectifier is double of that of a half-wave rectifier.
b) The ripple voltage is low and of higher frequency in case of full-wave rectifier so simple filtering circuit is
required.
c) Higher output voltage, higher output power and higher Transformer Utilization Factor (TUF) in case of a
full-wave rectifier.

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d) In a full-wave rectifier, there is no problem due to dc saturation of the core because the DC current in the two halves of the
two halves of the transformer secondary flow in opposite directions.
e) No centre tap is required in the transformer secondary so in case of a bridge rectifier the transformer required is simpler. If
stepping up or stepping down of voltage is not required, transformer can beeliminated even.
f) The PIV is one half that of centre-tap rectifier. Hence bridge rectifier is highly suited for high voltage applications.
g) Transformer utilization factor, in case of a bridge rectifier, is higher than that of a centre-tap rectifier.
h) For a given power output, power transformer of smaller size can be used in case of the bridge rectifier because current in
both (primary and secondary) windings of the supply transformer flow for the entire ac cycle.
25. Define transformer utilization factor of a transformer.

TUF is defined as ratio of DC power delivered to the load to AC rating of transformersecondary

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Zener Voltage Regulator

Aim: Conduct an experiment to draw the characteristics of Zener diode and design a Simple Zener voltage regulator. Determine
line and load regulation.
Apparatus Required :
Sl. No Components required Specification Quantity
1 Zener diode 20V, 1W 1
2 Resistors 1KΩ, 280Ω/1W 1
3 DRB 1
4 Bread board 1
5 Multimeter 2
6 DC regulated Power supply (0-30)V, 2A 1
Theory: The Zener diode is like a general-purpose signal diode. When biased in the forward direction it behaves just like a
normal signal diode, but when a reverse voltage is applied to it, the voltage across it remains constant for a wide range of
currents. The Zener Diode is used in its "reverse bias". From the I-V Characteristics curve we can study that the zener
diode has a region in its reverse bias characteristics of almost a constant negative voltage regardless of the value of the
current flowing through the diode and remains nearly constant even with large changes in current as long as the zener
diodes current remains between the breakdown current IZ(min) and the maximum current rating IZ(max).
This ability to control itself can be used to great effect to regulate or stabilise a voltage source against supply or load
variations. The fact that the voltage across the diode in the breakdown region is almost constant turns out to be an important
application of the zener diode as a voltage regulator.
Characteristics
Figure 1 shows the circuit diagram and current versus voltage curve for a Zener diode. Observe the nearly constant voltage in
the breakdown region.
Fig 1: Obtaining Zener diode characteristic curve

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Table1: To plot VI characteristics of Zener diode
Vin(V) Vz(V) Iz(mA)
Zener Diode as Voltage Regulators

Basically there are two type of regulations such as:
a) Line Regulation
In this type of regulation, series resistance and load resistance are fixed, only input voltage is changing. Output voltage remains
the same as long as the input voltage is maintained above a minimum value.
Percentage of line regulation can be calculated by
Where V0 is the output voltage and VIN is the input voltage and ΔV0 is the change inoutput voltage for a particular
change in input voltage ΔVIN.
b) Load Regulation
In this type of regulation, input voltage is fixed and the load resistance is varying. Output volt remains same, as long as the
load resistance is maintained above a minimum value.
Percentage of load regulation =
Where VNL is the null load resistor voltage (ie. remove the load resistance and measure thevoltage across the Zener Diode) and
VFL is the full load resistor voltage.
Design:
IZ(max) = PZ(max)/VZ
for a given Zener diode if VZ=15V and PZ(max)=1W, thenIZ(max)=66.67mA.
For safe operation select, IZ(max)= IZ(max)/2 = 33.335mA ≈ 35mA. Selecting IL=5mA, and IZ(min)=5mA
(from VI characteristic).
RL=VL/IL=VZ/IL= 3KΩ.

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Rs=(Vin(max)-VZ) / (IZ(max)+ IL)= (25-10)/(35mA+5mA)=250Ω ≈ select 280Ω/1W
Fig2. Circuit diagram to plot line and load regulation graph
Table2: Line regulation of Zener diode
Vin(V) V0(V) Iz(mA)
Table3: Load regulation of Zener diode
RL(Ω) V0(V) Iz(mA)

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Expt.No.2 : Design and Test

Biased Clippers – a)Positive, b) Negative , c) Positive-Negative. Positive and
Negative Clampers with and without Reference.
AIM OF THE EXPERIMENT: Conduct experiment to test diode clipping (single/double ended) and clamping circuits
(positive/negative).
COMPONENTS REQUIRED:
Sl. No. Component Details Specification Quantity

1 Diodes 1N4001/BY127 1
2 Resistor 10KΩ 1
3 Capacitor 0.1µf 1
4 DC Regulated power supply 1
5 Function Generator 1
6 CRO Probes 3
7 CRO 1
8 Bread Board 1
9 Connecting wire As per the requirement
THEORY:
CLIPPER CIRCUIT:
The process by which the shape of a signal is changed by passing the signal through a network consisting of
linear elements is called linear wave shaping. Most commonly used wave shaping circuit is clipper.
Clipping circuits are those, which cut off the unwanted portion of the waveform or signal without
distorting the remaining part of the signal. There are two types of clippers namely parallel and series. A
series clipper is one in which the diode is connected in series with the load and a parallel clipper is one in
which the diode is connected in parallel with the load.

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CIRCUIT DIAGRAM AND DESIGN:

a) SERIES NEGATIVE CLIPPER CIRCUIT:
In the positive half cycle D is forward biased

𝑉𝑂 = 𝑉𝑖 − 0.5 = 5 − 0.5𝑉
= 4.5𝑉 (0.5 𝑖𝑠 𝑡ℎ𝑒 𝑑𝑖𝑜𝑑𝑒 𝑑𝑟𝑜𝑝)
In the negative half cycle D is reverse biased
𝑉𝑂 = 0𝑉
b) SERIES POSITIVE CLIPPER CIRCUIT:
In the positive half cycle D is reverse biased
𝑉𝑂 = 0𝑉
In the negative half cycle D is forward biased
Applying KVL to the loop
𝑉𝑖 + 𝑉𝐷 − 𝑉𝑜 = 0
𝑉𝑜 = 𝑉𝑖 + 𝑉𝐷 => 𝑉𝑜 = −5 + 0.5 = −4.5𝑉
c) SERIES NEGATIVE CLIPPER CIRCUIT (WITH DC SUPPLY):

Applying KVL, we get
𝑉𝑖 = 𝑉𝐷 + 𝑉𝑅 + 𝑉𝑜
𝑉𝑜 = 𝑉𝑖 − 𝑉𝐷 − 𝑉𝑅
𝑉𝑜 = 5 − 0.5 − 2.5 => 𝑉𝑜 = 2𝑉
Otherwise ‘D’ is reverse biased, hence
𝑉𝑜 = 0𝑉

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In the positive half cycle

𝑊ℎ𝑒𝑛 |𝑉𝑖 | > |𝑉𝐷 + 𝑉𝑅 |, 𝐷 𝑖𝑠 𝑓𝑜𝑟𝑤𝑎𝑟𝑑 𝑏𝑖𝑎𝑠𝑒𝑑
In the negative half cycle
‘D’ is reverse biased, hence 𝑉𝑜 = 0
d) SERIES POSITIVE CLIPPER CIRCUIT (WITH DC SUPPLY):
In the negative half cycle

𝑉𝑖 = −𝑉𝐷 − 𝑉𝑅 + 𝑉𝑜
𝑉𝑜 = 𝑉𝑖 + 𝑉𝐷 + 𝑉𝑅
𝑉𝑜 = −5 + 0.5 + 2.5 => 𝑉𝑜 = −2𝑉
Otherwise ‘D’ is reverse biased, hence
𝑉𝑜 = 0𝑉
‘D’ is reverse biased, hence 𝑉𝑜 = 0𝑉
e) TWO SIDED SERIES CLIPPER:

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In the positive half cycle, D2 is reverse biased

𝑊ℎ𝑒𝑛 |𝑉𝑖 | > |𝑉𝐷1 + 𝑉𝑅1 | , 𝐷1𝑖𝑠 𝑓𝑜𝑟𝑤𝑎𝑟𝑑 𝑏𝑖𝑎𝑠𝑒𝑑
𝑉𝑖 = 𝑉𝐷1 + 𝑉𝑅1 + 𝑉𝑜
𝑉𝑜 = 5 − 0.5 − 2.5 => 𝑉𝑜 = 2𝑉
Otherwise 𝐷1𝑖𝑠 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑏𝑖𝑎𝑠𝑒𝑑, ℎ𝑒𝑛𝑐𝑒 𝑉𝑜 = 0𝑉
In the Negative half cycle, 𝐷1 is reverse biased
𝑉𝑖 = −𝑉𝐷2 − 𝑉𝑅2 + 𝑉𝑜
𝑉𝑜 = −5 + 0.5 + 2.5 => 𝑉𝑜 = −2𝑉
Otherwise 𝐷2𝑖𝑠 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑏𝑖𝑎𝑠𝑒𝑑, ℎ𝑒𝑛𝑐𝑒 𝑉𝑜 = 0𝑉
f) SHUNT POSITIVE CLIPPER:
In the positive half cycle, D is forward biased

𝑉𝑜 = 0.5𝑉
In the negative half cycle, D is reverse
biased
𝑉𝑜 = 𝑉𝑖

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g) SHUNT NEGATIVE CLIPPER:
In the positive half cycle, D is reverse

biased
𝑉𝑜 = 𝑉𝑖
In the negative half cycle, D is forward
biased
𝑉𝑜 = 0.5𝑉
h) SHUNT POSITIVE CLIPPER (WITH DC SUPPLY):
𝑉𝑜 = 𝑉𝐷 + 𝑉𝑅 = 0.5 + 2 => 𝑉𝑜 = 2.5𝑉
𝑂𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒, 𝐷 𝑖𝑠 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑏𝑖𝑎𝑠𝑒𝑑
𝑉𝑜 = 𝑉𝑖
During negative half cycle, D is reverse biased 𝑉𝑜 = 𝑉𝑖

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i) SHUNT NEGATIVE CLIPPER (WITH DC SUPPLY):
In the positive half cycle, D is reverse biased 𝑉𝑜 = 𝑉𝑖
During negative half cycle,
Applying KVL we get,
𝑉𝑜 = −𝑉𝐷 − 𝑉𝑅 = −0.5 − 2 => 𝑉𝑜 = −2.5𝑉

O𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒, 𝐷 𝑖𝑠 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑏𝑖𝑎𝑠𝑒𝑑, ℎ𝑒𝑛𝑐𝑒 𝑉𝑜 = 𝑉𝑖
j) TWO SIDED SHUNT CLIPPER:

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In the positive half cycle, 𝐷2 is reversed bias.

𝑉𝑜 = 𝑉𝐷1 + 𝑉𝑅1
𝑉𝑜 = 0.5 + 2 => 𝑉𝑜 = 2.5𝑉
Otherwise 𝐷1𝑖𝑠 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑏𝑖𝑎𝑠𝑒𝑑, ℎ𝑒𝑛𝑐𝑒 𝑜 = 𝑖
In the Negative half cycle, 𝐷1 is reverse biased

𝑉𝑜 = −𝑉𝐷2 − 𝑉𝑅2
𝑉𝑜 = −0.5 − 2 => 𝑉𝑜 = −2.5𝑉
Otherwise 𝐷2𝑖𝑠 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑏𝑖𝑎𝑠𝑒𝑑, ℎ𝑒𝑛𝑐𝑒 𝑉𝑜
CLAMPING CIRCUIT: A Clamper is a network constructed of a diode, a resistor and a capacitor that
shifts a waveform to a different DC level without changing the appearance of the applied signal. A
clamper is one, which provides a D.C shift to the input signal. The D.C shift can be positive or
negative. The clamper with positive D.C shift is called positive clamper and clamper with negative
shift is called negative clamper. The peak to peak voltage at the output of a clamper is the same as
that of the input.

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𝑊ℎ𝑒𝑛 𝑉𝑖 = 0; 𝑉𝑜 = 0— 4.5 = −4.5𝑉
𝑊ℎ𝑒𝑛 𝑉𝑖 = 5; 𝑉𝑜 = 5— 4.5 = 0.5𝑉
𝑊ℎ𝑒𝑛 𝑉𝑖 = −5; 𝑉𝑜 = −5— 4.5 = −9.5𝑉
The output shifts between 0.5V and -9.5V. Here the output has shifted down by 4.5V.
The peak to peak voltage at the output of a clamper is the same as that of the input.
Similarly analyze for all the clamper circuit.

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PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Give a sinusoidal input of 10V peak to peak to the clipper circuit and clamper circuit.
3. Check the output at the output terminal.
4. To plot the transfer characteristics for clipper circuits, connect channel X of the CRO to the input
and channel Y to the output and press the XY switch.
5. Adjust the grounds of both the channels to the centre.
6. Measure the designed values.
RESULT:
From the above experiment it has been observed that, with different value of the DC supply
voltage, the output waveform gets changed. In clamper circuit, for different values of DC voltage
the output waveform gets shifted without altering its peak to peak voltage.

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Expt.No.3 : Plot the transfer and drain characteristics of a JFET

and calculate its drain resistance, mutual conductance and
amplification factor.
Aim: Plot the input and output characteristics of a JFET. Calculate its
parameters, namely; drain dynamic resistance, mutual conductance and
amplification factor from the plot.
1. Transistor BFW10/BFW11 1 No.
2. Resistors 22 K 1 No
3. Digital Ammeters ( 0 - 200 mA) 1 NO
4. Digital Voltmeter (0 - 20V) 2 NO
5. Dual DC Regulated Power supply (0 - 30 V) 1 NO
THEORY:
A field effect transistor (FET) is a unipolar device, which
conducts current using only one kind of charge carriers. FET uses the
Gate voltage that is applied to input terminal to control the current
flowing through it resulting in the output current being proportional to
the input voltage. As their operation depends on an electric field (hence
the name field effect) generated by the input Gate voltage, this makes
the Field Effect Transistor a “VOLTAGE” operated device.
There are two main types of field effect transistor, the Junction
Field Effect Transistor (JFET) and Metal Oxide Semiconductor Field
Effect Transistor (MOSFET).
Junction Field Effect Transistor

There are two types of JFET namely n-channel and p-channel. N-
channel type means the carrier type in the conducting channel is
electron. Likewise, for p-channel type, the carrier type in conducting
channel is hole. JFET has three terminals, which are gate G, drain D and
source S. The gate is used to control the flow of carrier from source To

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drain. Source is the terminal that emits carrier and the drain is the
terminal that receives carrier.
In normal operation, the gate of JFET is always reverse-biased. Thus, in n-

channel type, the gate is biased with negative voltage i.e. gate voltage is less
than zero volt VG < 0, whilst for p channel type, the gate is biased with positive
voltage i.e. gate voltage is greater than zero voltage VG > 0. The source and
drain are biased according to the channel type or carrier type. If it is an nchannel
JFET (electron as carrier), the source is biased with negative voltage while the
drain is biased with positive voltage. Alternatively, it can be biased such that the
drain voltage VD is greater than the source voltage VS. i.e., VD > VS. If it is a p-
channel JFET (hole as carrier), the source is biased with positive voltage while
the drain is biased with negative voltage. Alternatively, it can be biased such
that the drain voltage VD is less than the source voltage VS. i.e., VD < VS
Circuit Diagram:
Expected Waveforms:

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Procedure:
a) Transfer Characteristics:
1. Connect the circuit as shown in the figure above.

2. Set voltage VDS = 5V (BFW10).
3. Varying VDD in steps of 0.5V until the current ID reduces to
minimum value.
4. Varying VGG gradually, note down both drain current ID and
gate-source voltage
(VGS).
5. Repeat above procedure (step 3) for VDS = 10V (BFW10).
b) Drain Characteristics:
1. Connect the circuit as shown in the figure above.

2. Keep VGS = 0V by varying VGG.
3. Varying VDD gradually in steps of 1V up to 10V note down
drain current ID and drain to source voltage (VDS).
4. Repeat above procedure for VGS = -1V, -2V, up to VGS = VP;
OBSERVATION:
Drain Characteristics:
SI.NO VGS=0V VGS= -1V VGS= -3V VGS= VP
(Constant) (Constant) (Constant) (Constant)
VDS ID VDS ID VDS ID VDS ID

(V) (mA) (V) (mA) (V) (mA) (V) (mA)
1
2
3

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Transfer Characteristics:
VDS = 1V VDS = 3V VDS = 5V

VGS(v) ID(mA) VGS(v) ID(mA) VGS(v) ID(mA)
1. Plot the drain characteristics by taking VDS on X-axis and

ID on Y-axis at a constant VGS.
2. Plot the transfer characteristics by taking VGS on X-axis and
taking ID on Y-axis at constant VDS.
Operation:
The circuit diagram for studying drain and transfer characteristics is
shown in the figure1.
1. Drain characteristics are obtained between the drain to

source voltage (VDS) and drain current (ID) taking gate to source
voltage (VGS) as the constant parameter.
2. Transfer characteristics are obtained between the gate to
source voltage (VGS) and drain current (ID) taking drain to source
voltage (VDS) as the constant parameter.
Calculations from Graph:
1. Drain Resistance (rd): It is given by the relation of

small change in drain to source voltage (∆VDS) to the corresponding
change in Drain current (∆ID) for a constant gate to source voltage (
VGS), when the JFET is operating in pinch-off region. at a

constant VGS (from drain characteristics)
2. Trans Conductance (gm): Ratio of small change in

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drain current (∆ID) to the corresponding change in gate to source

voltage (∆VGS) for a constant VDS. at constant VDS
(from transfer characteristics).
The value of gm is expressed in mho’s ( ) or Siemens (s).
3 Amplification factor (µ): It is given by the ratio of small

change in drain to source voltage ( VDS) to the corresponding change in
gate to source voltage ( VGS) for a constant drain current (ID).
RESULTS:
1. 𝒓𝒅 =
2. g𝒎 =
3. 𝝁 =
Viva Questions:
Q1. Why is JFET called as a unipolar device?

JFETs can be called UNIPOLAR devices because the charge carriers that carry the current
through the device are all of the same type i.e. either holes or electrons, but not both. This
distinguishes JFETs from the bipolar devices in which both holes and electrons are responsible
for current flow in any one device.
Q2. How JFET is a voltage controlled device?
A JFET is voltage controlled device because its output characteristics are determined by the
Field which depends on Voltage applied.
It is a voltage−controlled device in which current flows from the SOURCE terminal (equivalent
to the emitter in a bipolar transistor) to the DRAIN (equivalent to the collector). A voltage
applied between the source terminal and a GATE terminal (equivalent to the base) is used to
control the source − drain current.
Q3. What are the advantages of JFET?

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It is a unipolar device, depending only upon majority current flow. It is less

noisy. and is thus found in FM tuners and in low-noise amplifiers for VHF
and satellite receivers. It is relatively immune to radiation. It exhibits no
offset voltage at zero drain current and hence makes an excellent signal
chopper.
Q4. What is pinch-off voltage?
Pinch-off voltage is the drain to source voltage after which the drain to source current
becomes almost constant and JFET enters into saturation region and is defined only when gate
to source voltage is zero.
Q5. Which type of JFET biasing requires negative voltage supply?

Gate
Q6. What are the applications of JFET?
JFETs can be used for several applications including:
• High input impedance amplifier
• Low noise amplifier
• Differential amplifier
• Analog switch
• Voltage controlled resistor
Q7. What is trans conductance?
Trans conductance is an expression of the performance of a bipolar transistor or field-effect

transistor (FET). In general, the larger the Trans conductance figure for a device, the greater
the gain (amplification) it is capable of delivering, when all other factors are held constant. The
symbol for Trans conductance is gm.
Q8. When the JFET is no longer able to control the current, this point is called as? Breakdown
region
Q9. What is transfer characteristics? Give the relation between µ, 𝒈𝒎 and 𝒓𝒅?
The transfer characteristic for a JFET can be determined by keeping drain-source voltage, VDS
constant and determining drain current ID for various values of gate-source voltage VGS. The
curve is plotted between gate-source voltage VGS and drain current ID.
µ = 𝒈𝒎 × 𝒓𝒅

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Q10. Why do we get 180 degree phase shift in FET amplifier?
The reason for the phase shift can be seen easily by observing the operation of the N-
channel JFET. On the positive alternation of the input signal, the amount of reverse bias on
the P-type gate material is reduced, thus increasing the effective cross-sectional area of the
channel and decreasing source-to-drain resistance. When resistance decreases, current
flow through the JFET increases. This increase causes the voltage drop to increase, which in
turn causes the drain voltage to decrease. On the negative alternation of the cycle, the
amount of reverse bias on the gate of the JFET is increased and the action of the circuit is
reversed. The result is an output signal, which is an amplified 180-degree-out-of-phase
version of the input signal.
Q11. JFET amplifier provides a gain less than 1?
Common-drain
Q12. Why JFET apparatus must be handled with care while performing the experiment?
Because transistors are damaged by excess of heat while soldering or when there is a
sudden urge of current due to accidental shorting of leads while measuring voltages on
transistors, in operation.

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Expt.No.4 : Plot the transfer and drain characteristics of n-

channel MOSFET and calculate its parameters, namely; drain
resistance, mutual conductance and amplification factor.
Aim: To design and plot the input and output characteristics of n-

channel MOSFET and to
Calculate drain dynamic resistance, mutual conductance and
amplification factor
Sl. No. Components Details Specification Quantity

1. Transistor BS170 1 No.
2. Resistors 1K Each 2 No
3. DC Supply, Signal Generator, CRO with Probes
THEORY:
Metal Oxide Semiconductor Field Effect Transistor

(MOSFET) has three terminals source gate and drain. It uses a thin
layer of silicon dioxide as an insulator between the gate and the
channel. It is also known as Insulated Gate Field Effect Transistor.
There are two types of MOSFET, depletion and enhancement

types. Consider the N channel depletion type MOSFET. Heavily
doped two N- type regions are diffused on a lightly doped P-type
substrate to form source and drain. Between these two N type wells a

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lightly doped N type material forms a channel. A thin layer of SiO2

which is an insulating material is fabricated on the surface above the
channel and the gate terminal is attached to it. Source and Drain
terminals are attached to the heavily doped N type material with
metal contacts.
A positive voltage VDS is applied at the drain with respect to source

to establish drain current. When a negative voltage VGS is applied at
the gate with respect to the source, positive charges get induced in
the channel resulting the channel becoming Thinner. This reduces
the current flow through the channel. If the magnitude of VGS is
increased, the drain current decreases. If a positive voltage is applied
at the gate, drain
current increases.
Enhancement type MOSFET does not have a channel

fabricated in it. The applied positive voltage induces negative
charges between the source and drain and a channel forms. BS170 is
a low power enhancement type MOSFET. Some MOSFETS are able
to function in Enhancement and Depletion modes.
CIRCUIT DIAGRAM:
Fig 8.1. Enhancement Mode MOSFET and
Expected Graph:

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Fig 8.2: Transfer characteristics and Drain

characteristics
Procedure (Transfer characteristics):

1. Now vary the power supply V2 and set the VDS to 6v
2. Vary the power supply V1 in steps and note down the readings
of VGS and ID at each step and tabulate the readings in tabular
column 2.
3. Vary the power supply V2 and set the VDS to 12v
4. Vary the power supply V1 in steps and note down the readings
of VGS and ID at each step and tabulate the readings in tabular
column 2.
5. Determine trans conductance (gm) with the help of graph VGS
v/s ID.
Procedure (Drain characteristics):

1. Rig up the circuit as shown in fig 8.2 above and set VGS=0v.
2. Then vary the power supply V2 and note down VDS and ID
at each step and tabulate the reading in the tabular column 1.
3. Now set the gate voltage VGS to -0.5v with the help of
power supply V1.
4. Then vary the power supply V2 and note down VDS and ID
at each step and tabulate the readings in tabular column 1.
5. Repeat the same for VGS = +0.5v.

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6. Determine drain resistance (rd) with the help of graph VDS v/s ID.
Tabular column 1 (Transfer characteristics) :
VDS = 5V VDS = 10V
VGS(v) ID(mA) VGS(v) ID(mA)
Tabular column 2(Drain characteristics):
VGS = VGS = VGS =

VDS(v) ID(mA) VDS(v) ID(mA) VDS(v) ID(mA)
Calculations from Graph:

1. Trans Conductance (gm): Ratio of small change in drain

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current ( ID) to the corresponding change in gate to

source voltage ( VGS) for a constant VDS.
At constant VDS (from transfer characteristics).

The value of gm is expressed in mho’s ( ) or Siemens (s).
Result:
1. g𝒎 =
Viva Questions:
1. What is drift current?

Drift current is the current due to the movement of charge carriers
in a specific direction opposite to the applied electric field.
2. Expand MOSFET
Metal Oxide Semiconductor Field Effect Transistor
3. What is a MOSFET?
It is a special type of FET in which there is a thin layer of silicon
dioxide between
gate and the channel that works by electronically varying the width
of a channel along which charge carriers flow.
4. Mention the two types of MOSFETs

i)
Depletion - type
ii)
Enhancem
en t –type
5. Mention the applications of MOSFET.

a) It is used as an analog switch.
b) MOSFET is used as a transistor in integrated circuits.
c) It is used as an oscillator in radio system.
6. What is biasing?
Biasing is a method of applying a suitable potential across
any electronic equipment in order to make it operate as we require.

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7. What is the advantage of MOSFETs over JFETs?

MOSFETs have a very high input impedance. MOSFETs are
thermally very stable which make them extremely popular in computer
circuit design.
8. Mention the number of terminals that a MOSFET has.

MOSFET has four terminals:- source, gate, ,substrate.
9. What accounts for the high input impedance of a

MOSFET device?
The insulating layer of SiO2 accounts for the desirable high input
impedance.
10. Mention the parameters of a MOSFET.

Drain Resistance, Trans conductance, Amplification factor.
11. What is the basic difference in construction of a depletion

type MOSFET and an Enhancement type MOSFET?
The depletion type MOSFET consists of an n-channel
between the two n-doped regions while the enhancement type
MOSFET does not.
12. What does it mean “the channel is pinched off”?

For a MOSFET when VGS is greater than Vt, a channel is induced.
As we increase VDS current starts flowing from Drain to Source (triode
region). When we further increase VDS, till the voltage between gate and
channel at the drain end to become Vt, i.e. VGS – VDS = Vt, the channel
depth at Drain MOSFET end decreases almost to zero, and the channel is
said to be pinched off. This is where a MOSFET enters saturation region.
13. What is Forward Trans conductance?
It is the ratio of ID and (VGS – VGS(th)). In a MOSFET switching

circuit it determines the clamping voltage level of the gate – source voltage
and thus influences during turn on and turn off.
14. Explain the three regions of operation of a MOSFET.

Cut-off region: When VGS < VT, no channel is induced and the
MOSFET will be in cut-off region. No current flows.
Triode region: When VGS ≥ VT, a channel will be induced and
current starts flowing if VDS > 0. MOSFET will be in triode region as long

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as VDS < VGS – VT.

Saturation region: When VGS ≥ VT, and VDS ≥ VGS – VT, the
channel will be in saturation mode, where the current value saturates. There
will be little or no effect on MOSFET when VDS is further increased.

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Expt.No.5 : Design and test (i) Emitter Follower , (ii) Darlington

Connection.
EMITTER FOLLOWER
AIM
To construct an emitter follower circuit and
(i) Measure the gain

(ii) Plot its input and output waveforms
OBJECTIVES
On completion of the experiment students will be able to
Assemble an emitter follower circuit

Test the dc condition and ascertain the working condition of
the amplifier
Understand the characteristics of emitter follower circuit
EQUIPMENTS / COMPONENTS

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Sl. no. Name and Specification Quantity

1. Resistors 1 KΩ 1 no.
2.2 KΩ 1 no.
10 KΩ 1 no.
22 KΩ 1 no.
33 KΩ 1 no.
2. Capacitor 1 µF 2Nos
3. Transistor BC 107 1 no.
4. Function generator 0 to 1 MHz 1 no.
5. Oscilloscope 0 to 20 MHz 1 no.
6. Multimeter 1 no.
7. Breadboard 1 no.
8. Connecting wires
PRINCIPLE
Emitter follower is the popular name for common collector amplifier. Its voltage gain is approximately
unity (without RLvoltage gain is unity). It has high input impudence and lowoutput impedance. Thus emitter
follower has less loading effect and is suitable for impedance matching.
Since collector is directly connected to dc source, it appears to be grounded for ac signal. Output is
taken from the emitter terminal. The output voltage is in phase and is equal to the input signal.
Since the amplitude and phase of the output (emitter) follows the input (base), the circuit is called emitter
follower. In this circuit voltage divider biasing is used for base bias. RE acts as the load for signal at the
output circuit.RE also provides a negative feedback in the circuit.
PROCEDURE
1) Test the components

2) Assemble the circuit
3) Measure the dc condition using multimeter and verify whether the transistor is in active region
4) Apply 1Vpp,1 KHz sinusoidal signal as input
5) Observe the voltages at input point (Vin), at base, at emitter and at the output point(VO) without
RL
6) Measure the amplitudes and dc levels
7) Plot the waveforms
8) Observe and measure VO with RL = 10 KΩ and RL = 1KΩ

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9) Calculate the voltage gain for the above three conditions of RL
CIRCUIT DIAGRAM
OBSERVATIONS
1. DC Condition (multimeter)
VCC = VCE =
VBE =
Note : At proper biased condition, VBE should be 0.6V to 0.7V, VCE should be approximately half of VCC
2. Input Output waveforms

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Vin = 1V (pp), 1 KHz, without RL
3. Voltage gain
(i) Without load (RL = ∞)
VO = 1V
Gain = = 1
(ii) Voltage gain with 10 K load

VO =
Gain =
(iii) Voltage gain with 1 KΩ load
VO =
Gain =
RESULT:
INFERENCE:

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DARLINGTON EMITTER FOLLOWER
AIM:
To design and test a Darlington emitter follower circuit with and without boot strapping and
determine the gain, input and output impedance for both the circuits.

1. Transistor SL100 2 Nos.
10 f 1 No
2. Capacitors
0.47µf 2 Nos.
3. Resistors 1 M, 2.2 M, 1.5 K, 10 K, 47K Each 1 No
DC Supply, CRO with Probe, Signal generator, AC millivoltmeter
THEORY:
Normally transistors are used as amplifiers. But there are some applications in which, matching of
impedance is required between two circuits without any gain or attenuation. In such applications emitter
followers are used. Emitter followers have large input impedance and small output impedance. Darlington
emitter follower has two transistors connected in cascade such that the emitter of first transistor is connected
to the base of second transistor. The voltage gain of the darlington emitter follower is close to unity. The
major drawback of this circuit is that the second transistor amplifies leakage current of the first transistor and
overall leakage current becomes high. The output is observed at the emitter terminal of the second transistor.
Hence it is called an emitter follower.
CIRCUIT DIAGRAM:
Darlington emitter follower without bootstrapping

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Vcc = 12V
R1 1M
Cb = 0.47µf
Q1
QSL100
SL100
R2 2.2 M
Vin
CE = 0.47µf
RE
Vo
1.5 K
Darlington emitter follower with bootstrapping
DESIGN:
Given IC = 4mA, VCC = 12V, VBE = 0.6V, 1 = 2 = 100
To find RE:
Applying KVL to the output loop of the second transistor, we get
VCC = VCE + VRE
Therefore VRE = VCC – VCE = 12 – 6

Therefore VRE = 6V
W.K.T RE = VRE / IE2

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Here IE2 = IC2
Therefore RE = 6 / 4 x 10-3
RE = 1.5k

To find R1 & R2:
From the circuit we have
VA = VBE1 + VBE2 + VRE
= 0.6 + 0.6 + 6 = 7.2V
W.K.T. IC = IB
Therefore IB = (4 x 10-3)/ 100 = 40 A
Let 10IB be the current through R1 and 9IB be the current through R2.
From the fig. we see that

R1 = (VCC – VA) / 10IB
Therefore R1 = 12K
From the fig. R2 = VA / 9IB
Therefore R2 = 20 K  22K
W.K.T. CC = 10 / XRE = 10 / ( 2..f.RE)
Assume f = 50Hz
Therefore CC = 21.2F  47 F
W.K.T. Cb = 10 / XRB = 10 / ( 2..f.RB ) where RB = R1 || R2 = 7.5k


Therefore Cb = 4.2F  4.7F
Chose R3 = 10 K, CB = 10µf for bootstrapping
PROCEDURE:

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1. Rig up the circuit as shown in the fig.

2. Check the circuit for biasing, i.e. check VCE, VCC and VRE.
3. Give a sinusoidal input signal of 1KHz from a signal generator.
4. Set the input signal to a value such that the output doesn’t get clipped.
5. For different frequencies of the input signal, read the output on the voltmeter and verify thatthe
gain is 1.
6. To measure input impedance, connect a resistor of 47k in series with the signal generator.
7. Measure the voltage at the input point (VS) and at the point after the resistor (VIN).
8. Current through the resistor is given by the expression I = (VS - VIN) / 47K.
9. Input impedance is given by ZIN = VIN / 47 K
10. To measure output impedance, connect a DRB in parallel with the output.
11. Adjust all the knobs of the DRB to maximum.
12. Start reducing the resistance in the DRB from a large value until the output reduces to half.
13. The resistance in the DRB is the output impedance.
TABULAR COLUMN:
VIN = constant
Frequency
V0 (V) AV AV (dB)
(Hz)
WAVEFORM:

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Vin
Vin 0 t
V0
0 t
Vin

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Expt.No.6 : Design and plot the frequency response of Common

Source JFET/MOSFET amplifier.
Aim: Design, setup and plot the frequency response of Common Source JFET/MOSFET amplifier
and obtain the bandwidth.
Components and equipments required: JFET – BFW10, Resistors - 180 Ω, 1KΩ, 10KΩ and 1MΩ,
Capacitors 47μf, 0.1μf and 0.047μf, Power Supply, 10Hz – 3MHz Signal generator, CRO, Connecting
wiresand Bread board/Spring board with spring terminals.
Design:
For BFW10 Junction FET specifications are as below:

VDS max = 30 V, VGS off = -8 V, IDSS min = 8mA, IDSS max = 20mA
Choose IDSS (Min + Max)/2 = (8 + 20)/2= 14 mA,
VP = Max/2 = - 4 V and gm = 3.5 to 6.5
m-mhosQuiscent-Conditions: IDQ =
IDSS/2 = 7mA,
Let IDQ = 5 mA. VDD=12V, VDSQ=VDD / 2=6V
Using these values, we get
let Rs = 330Ω
With this choice of Rs, VS = RSIDQ = 1.65 V
Let RD=1.0 KΩ
RG may be chosen arbitrarily but should be large enough such that overall input impedance is not
affectedmuch. Let RG=1.0 MΩ
CC1 = 1/2лf1Ri will be very small because of large Ri and chosen to be much larger so that it
does notdecide f1. Thus CC1=0.1μF
Let RL=10KΩ and f1=300Hz
Typical value of output admittance for BFW10, gd =85μ
MhosThat is, rd =1/ gd = 12KΩ. Therefore RD||rd
≈RD=1KΩ

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Now, CC2=1/2лf1 (RD+RL) =0.0482μF Thus select CC2=0.047μF

Choosing XCs=RS/10 = 18Ω at f1/2=150Hz, we get CS=58.9μF let CS=47μF or CS= 100 μF
Circuit Diagram:
Procedure:
1. Switch on the D.C. power supply and check the D.C. conditions without any input signal and
record in table below:
2.Select sine wave

input and set the input signal frequency ≥10f1 (Say = 10 KHz.

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This will be a convenient ‘Mid – frequency’).

3. Observe the input wave form and output wave form on a dual
channel CRO.
4. Adjust the input amplitude such that the output waveform is just
undistorted (or in the verge of becoming distorted). Measure the
amplitude of the Input Signal now. This amplitude is the
Maximum Signal Handling Capacity of your amplifier.
5. Decrease the input voltage to a convenient value such that the
output is undistorted. Say 100mV. Measure the corresponding
o/p voltage. Calculate mid-band gain, AM = Vo (p-p) / Vin (p-p).
6. Keeping the input voltage constant, go on reducing the
frequency until the output voltage reduces to 0.707 times its
value at 10 KHz. The frequency at which this happens gives you
the Lower Cut-off frequency (f1).
7. Keeping the input voltage constant, go on increasing the
frequency until the output voltage decreases to 0.707 times its
value at 10 KHz. The frequency at which this happens gives you
the Upper Cut-off frequency (f2).
8. Thus you have pre-determined f1 and f2. Find the amplifier
band width, BW = f2 – f1
9. Determine Gain Bandwidth product (GBW product) which is a
Figure of Merit of your amplifier as GBW= AM x BW.
10. Now repeat the experiment by recording values of output
voltage versus frequency keeping the input voltage at a constant
value convenient to you. You should take at least five readings
below f1 and 5 readings above f1, at least 5 readings in the mid
band, at least 5 readings below f2 and 5 readings above f2.
11. Plot graphs of AV versus Frequency, f and /or M, dB versus
Frequency, f on a semi-log graph paper. From the graph
determine: Mid –band - gain, Lower and Upper Cut-off
frequencies and Band width. Compute the GBW product and
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verify with answer obtained earlier.Vin (P-P) = Volts

(Constant)

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Plot of Voltage Gain AV versus frequency
Result:
Thus the frequency response analysis of JFET and MOSFET amplifier are analysed.

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Expt.No.7 : Test the Opamp Comparator with zero and non

zero reference and obtain the Hysteresis curve.
Voltage Comparator :
POSITIVE AND NEGATIVE VOLTAGE COMPARATORS:
THEORY:
Positive voltage comparator:
In fig 7.6, a positive reference voltage Vref is applied to one of the op-amp’s inputs. This means that
the op-amp is set up as a comparator to detect a positive voltage. The voltage to be sensed Vi ,is
applied to the op-amp’s (-) input, therefore this circuit is a inverting positive level detector. When Vi is
above Vref , Vo equals - Vsat ,When Vi is below Vref , Vo equals + Vsat
Negative voltage comparator:

In fig 7.7, a negative reference voltage Vref is applied to one of the op-amp’s inputs. This means that
the op-amp is set up as a comparator to detect a negative voltage. The voltage to be sensed Vi ,is
applied to the op-amp’s(-) input, therefore this circuit is a inverting negative level detector. When Vi is
above - Vref , Vo equals +Vsat ,When Vi is below - Vref , Vo equals - Vsat
CIRCUIT DIAGRAM:
Fig 7.6 Inverting positive voltage comparator Fig 7.7 Inverting Negative voltage Comparator

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TRANSFER CHARACTERISTICS:
Fig 7.8 Transfer Characteristics of positive and negative voltage comparators
PSPICE Schematic Diagram :

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Figure 7.10 : Pspice schematic diagram and output waveform of Inverting negative voltage comparator.

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RESULT: Inverting positive voltage comparator:

When Vi is below Vref , Vo equals + Vsat
Vo  MVd  M (VP VN )  M[Vref Vi ]  Vsat
When Vi is above Vref , Vo equals - Vsat
Vo  MVd  M (VP VN )  M[Vref Vi ]  Vsat
Inverting negative voltage comparator:

When Vi is below - Vref , Vo equals - Vsat
Vo  MVd  M (VP VN )  M[Vref Vi ]  Vsat
When Vi is above - Vref , Vo equals +Vsat
Vo  MVd  M (VP VN )  M[Vref (Vi )]  Vsat
VIVA QUESTION:
1. What is a voltage comparator?
2. What is a zero-crossing detector?
3. What is the difference between voltage comparator and zero crossing detector?
4. What is the difference between inverting and non-inverting ZCD?
5. What is the difference between inverting and non-inverting voltage comparator?
6. What is the drawback in zero crossing detectors?
a) Low frequency signal and noise at output terminal
b) High frequency signal and noise at input terminal
c) Low frequency signal and noise at input terminal
d) High frequency signal and noise at output terminal
7. State a method to overcome the drawback of zero crossing detectors?
a) Increasing input voltage
b) Use of positive feedback
c) Connect a compensating network
d) None of the mentioned
8. How the op-amp comparator should be chosen to get higher speed of operation?
a) Large gain
b) High slew rate
c) Wider bandwidth

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Expt.No.8 : Design and test Full wave Controlled rectifier

using RC triggering circuit.
AIM: To study RC Triggering for FWR.
APPARATUS REQUIRED :
1. RC TRIGGERING MODULE
2. Multimeter -1NO.
3. LAMP 100W – 1NO.
4. FUSE UNIT – 1NO.
5. CRO with PROBE – 1NO.
THEORY :
R and RC firing circuits are simple and economical. They can be used to
trigger SCRs in rectifiers and AC voltage controllers. But they are not used commercially
because the turn on angle of the SCR realized using these circuits is not thermally stable.
In the RC firing circuit the firing angle can be varied from nearly 0o to almost 180o
by varying the pot. During each negative half cycle of the input voltage, the capacitor
charges to the peak supply voltage through D1 is provided in order to by pass R1 and R2
during each negative half cycle of the supply voltage so that the capacitor charges fast to
the negative peak value of the supply . When the SCR anode voltage becomes positive, the
capacitor starts charging through the pot so as to make the top plate positive with respect
to the bottom plate. When the positive capacitor voltage becomes equal to Vgt the SCR
turns ON. The time taken for the capacitor to charge up to Vgt can be increased by
increasing the pot resistance. Then, the firing angle increases. If the pot resistance is
decreased, then, the capacitor voltage reaches the value Vgt earlier during the half cycle,
and the firing angle will be lower. Diode D2 is provided to prevent breakdown of
cathode gate junction during negative half cycles.
When the SCR turns ON, the voltage drop across C during conduction of SCR
keeps it almost discharged till the beginning of the next half cycle of the supply
voltage.

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CIRCUIT DIAGRAM :
PROCEDURE :
1. Observe and study the module.
2. Connect the circuit as shown in the circuit diagram
3. Vary the pot meter R1 to get minimum alpha and note down the corresponding
average value of the voltage and wave form across the load.
4. Repeat the steps 1 to 3 for different values of alpha by varying the pot
meter Resistance.
5. Switch off the power.
TABULAR COLUMN :
Delay angle Conduction angle voltage

Time (ms)
α β (v)

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EXPECTED GRAPH :

BEC303
Expt.No.9: Design and test Precision Half wave and full wave
rectifiers using Opamp.
AIM
To design and set up precision rectifier using op-amp and check its performance.
EQUIPMENT AND COMPONENTS REQUIRED
Dual power supply, CRO, function generator, bread board, op-amp, diodes, and resistors.
THEORY
In a normal diode rectifier, the cut in voltage across the diode will result in reduction
of output voltage and inaccuracy of rectification. If ideal rectifier is needed in an
application,a precision rectifier as shown Fig. 1 may be used.
In the circuit, when the input is greater than zero, D1 will conduct and D2 is OFF, so the
output is zero because the other end of R2 is connected to the virtual ground and there is no
current through R2. When the input is less than zero, D2 is on, and D1 is off, and the output
is
Fig 1. Circuit diagram of Precision Rectifier

BEC303
R2
similar to that of an inverting amplifier with gain  .
R1
The value of R1 and R2 are selected in such a way that the circuit has reasonable level of
input impedance and the gain is unity. Diode D1 and D2 are signal diodes.
PROCEDURE
1. Set up the circuit as shown in figure. Give a sine wave of ±5V peak magnitude
and 1 kHz frequency at the input and observe the input and output simultaneously on
CRO.
2. Put the CRO into X-Y mode and connect input signal to X and output signal to Y.
Select suitable volt per division in both channels and observe the characteristics. The
display should look similar to Fig 3.
R2

R1
Fig. 2. Input and output waveforms Fig. 3. Transfer characteristics

BEC303
Full wave Rectifier

Aim : Design and Analysis of full wave rectifier and determine its performance
parameters.
Apparatus Required: PC, Simulation package- Orcad family release 9.2 lite edition.
Learning Objectives :
1. To learn the designing of Precision full wave rectifier Opamp circuit.
2. To simulate Precision full wave rectifier opamp circuits using PSPICE software.
THEORY:
AC and DC are two frequent terms that you encounter while studying the flow of electrical
charge. Alternating Current (AC) has the property to change its state continuously. For example, if we
consider a sine wave, the current flows in one direction for positive half cycle and in the opposite
directionfor negative half cycle. On the other hand, Direct Current (DC) flows only in one direction.
An electronic circuit, which produces either DC signal or a pulsated DC signal, when an AC signal is
applied to it is called as a rectifier.
A full wave rectifier produces positive half cycles at the output for both half cycles of the
input.The circuit diagram of a full wave rectifier is shown in the following figure –

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Figure 2.1 : Circuit diagram of full wave rectifier
The above circuit diagram consists of two op-amps, two diodes, D1 & D2 and five resistors, R1 to R5.

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The working of the full wave rectifier circuit shown above is explained below −
 For the positive half cycle of a sinusoidal input, the output of the first op-amp will be
negative.Hence, diodes D1 and D2 will be forward biased and reverse biased respectively.
the output of the first op-amp is connected to a resistor R4, which is connected to the inverting terminal
of the second op-amp. The voltage present at the non-inverting terminal of second op-amp is 0 V. So, the
second op-amp with resistors, R4 and R4 acts as an inverting amplifier.
Therefore, the output of a full wave rectifier will be a positive half cycle for the positive half cycle of
a sinusoidal input.
 For the negative half cycle of a sinusoidal input, the output of the first op-amp will be
positive.Hence, diodes D1 and D2 will be reverse biased and forward biased respectively.
The output of the first op-amp is directly connected to the non-inverting terminal of the second op-
amp.Now, the second op-amp with resistors, R4 and R5 acts as a non-inverting amplifier.
The input and output waveforms of a full wave rectifier are shown in the following figure

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Fig 2.3 Full wave rectifier

BEC303

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CIRCUIT DIAGRAM:
R2 R4
R5
10k 10k
10k
0 0
V4
V2 12Vdc
12Vdc
D1
D1N4002
U2
U1
4
1 uA741
4
R1 2
V-
2 1uA741 - OS1
V-
- OS1
6
10k OUT
V 6
OUT 3 5
V+
V1 V
VOFF = 0 3 5 + OS2
VAMPL = 2 + OS2
FREQ = 1k
V3 V5
0 12Vdc D2 12Vdc
D1N4002
0
0
R3
10k

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Figure 2.6 : Pspice schematic diagram of full wave rectifier
Figure 2.7: Output waveform for full wave rectifier
RESULT
A sinusoidally varying input signal with an amplitude of less than 1V is rectified with the help of a
precision rectifier.
For 𝑉𝑖 = 0.6𝑉 𝑝𝑒𝑎𝑘 𝑡𝑜 𝑝𝑒𝑎𝑘, 𝑉0 = ⋯ … . 𝑉𝑝𝑒𝑎𝑘 𝑡𝑜 𝑝𝑒𝑎𝑘
VIVA QUESTIONS
1. What is a rectifier?
2. What is a precision rectifier?
3. What are the applications of precision rectifiers?
4. Draw the circuit diagram for half wave saturating precision rectifier?
5. What are the advantages of precision rectifiers over diode rectifiers?
6. What are the disadvantages of saturating precision rectifiers?
7. What are non-saturating precision rectifiers?
8. What are the steps to be followed in designing non-saturating precision rectfiers?

BEC303
Expt.No.10: Design and test RC phase shift oscillator.
Aim: To design RC phase shift oscillator circuit using op-amps for a frequency of 200
Hz and hence to simulate using pspice.
Learning Objectives :
1. To understand the operation of an RC-phase shift oscillator.

2. To learn the designing of an RC-phase shift oscillator circuit.
To simulate the inverting and non-inverting opamp circuits using PSPICE software.
Apparatus Required :PC, Simulation package- Orcad family release 9.2 lite edition.
Theory :
The phase shift oscillator shown in fig 4.1. consists of an inverting amplifier and an RC phase shift
network. The RC network feeds a portion of the amplifier ac output back to the amplifier input. The
amplifier has an internal phase shift of -1800 and each pair of RC network designed to provide phase
shift of 600 summing upto +1800 , thus satisfying barkhausen criteria of phase shift 00.
The frequency of the oscillator output depends upon the capacitor and resistor values employed in the
feedback network. If three equal value resistors and three equal value capacitors are used the RC
circuit can be analyzed to show that the network phase shift is 1800 , when
𝑿𝑪 = 𝑹√𝟔
This gives an oscillation frequency of, 𝒇 = 𝟏/(𝟐𝝅𝑹𝑪√𝟔 ) 𝑯𝒛
In addition to providing network phase shift, the RC network attenuates the amplifier output. Network
analysis shows that at the required 1800 phase shift, the RC network has an attenuation factor of 29.
This means the amplifier must have voltage gain of 29 for loop gain to be equal to 1.

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If the amplifier gain is less than 29, circuit will not oscillate and when the gain is much higher than
29, oscillator output waveform will be distorted, thus design of resistor values in an amplifier circuit
must be in such a way that the ratio
𝑹𝒇 ⁄ 𝑹𝟏 = 𝟐𝟗

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DESIGN :
Design a RC phase shift oscillator generating sine wave of frequency 1 kHz

The frequency of oscillation of an RC phase shift oscillator is given by
𝑓𝑜 = 1/(2𝜋𝑅𝐶√6) Hz (1)
Let C = 0.1 µF
𝑅 = 1/2𝜋𝑓𝑜 𝐶√6 = ½𝜋 ∗ 1 ∗ 103 ∗ 0.1 ∗ 10−6 ∗ √6 = 3250.38 Ω =3.3 kΩ
To prevent loading of the amplifier by RC network, 𝑅𝑖 ≥ 10 𝑅 ; 𝑅𝑖 = 10 ∗ 3.3 𝑘Ω = 33 𝑘Ω

For sustained oscillation, amplifier gain must be 29 and feed back gain must be 1/29 .
𝐴𝑚𝑝𝑙𝑖𝑓𝑖𝑒𝑟 𝐺𝑎𝑖𝑛; 𝐴 𝑐𝑙 = 29, 𝑓𝑒𝑒𝑑𝑏𝑎𝑐𝑘 𝑔𝑎𝑖𝑛 ; 𝛽 = 1 ⁄ 29
𝑇ℎ𝑢𝑠, 𝑅𝐹 = 29 𝑅𝑖 = 29 ∗ 33 𝑘Ω = 957 𝑘Ω = 1 𝑀Ω
PROCEDURE:
1. Create a blank project.
2. Draw the circuit diagram by selecting the parts from parts menu (active
sources fromsource library and analog components and dependent sources
from analog library)
3. Select new simulation setting from the simulation tool option.
4. In the simulation setting window select Transient analysis.
5. Enter suitable value for run time of 20 ms and maximum step size 1 ms and skip initial
transients.
6. Run the simulation and verify the results.

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PSPICE SIMULATION CIRCUIT :
Fig 4.3. RC Phase shift Oscillator Output

BEC303
Viva Questions:
1. State Barkhausen’s criteria for sustained oscillations

2. What is the value of attenuation factor of feedback network of an RC phase shift oscillator?
3. Explain how phase shift criteria is satisfied in an RC phase shift oscillator
4. Explain how capacitor and resistor values are designed in feedback network of an RC phase
shift oscillator
5. Write the expression of oscillation frequency of an RC Phase shift oscillator.
6. Explain how amplitude stabilization is achieved for an RC pahse shift oscillator
7. An RC phase shift oscillator is to be designed to have output frequency of 1 kHz. Value
of capacitors in feedback network is 0.01 µF. Determine the value of resistors of RC pair
network.
8. What should be the value of amplifier gain in RC phase shift oscillator for sustained oscillation

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ELECTRONIC PRINCIPLES AND CIRCUITS LABORATORY

CMR INSTITUTE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS & COMMUNICATION

1 . Dr. Meenakshi R Patil 3. Dr.Sridhar .N 5. Prof. Anju Das

2 . Dr. Naveen Kumar G.N. 4. Dr.Ananth Kumar M.S.

DEPARTMENT OF ECE, CMRIT 1

2 Design and Test

10 Design and test RC phase shift oscillator

DEPARTMENT OF ECE, CMRIT 2

Expt.No.1 : Design and Test

Sl. No. Components Details Specification Qty

load performance of the circuit.

BRIDGE RECTIFIER WITH FILTER CAPACITOR

1. Connections are made as shown in the circuit diagram.

DEPARTMENT OF ECE, CMRIT 4

2. What are the different types of rectifiers ? Explain their working.

3. List few differences between a bridge and full wave rectifier.

4. Can a FWR be built without using a centre-tapped transformer ?

DEPARTMENT OF ECE, CMRIT 5

5. State some applications of rectifiers.

8. Define conversion efficiency of a rectifier. What is its significance ?

9. State the theoretical values of efficiency for each type of rectifier.

10. Define regulation of a rectifier. State its significance.

11. What is a filter used for in a rectifier ? Explain its working.

DEPARTMENT OF ECE, CMRIT 6

15. What is a centre-tapped transformer? What is off nominal ratio ?

16. Define PIV rating of a diode.

18. What is the function of a coupling capacitor ?

22. What do the following meters indicate ?

DEPARTMENT OF ECE, CMRIT 7

25. Define transformer utilization factor of a transformer.

DEPARTMENT OF ECE, CMRIT 8

Zener Voltage Regulator

Fig 1: Obtaining Zener diode characteristic curve

DEPARTMENT OF ECE, CMRIT 9

Table1: To plot VI characteristics of Zener diode

Vin(V) Vz(V) Iz(mA)

Zener Diode as Voltage Regulators

DEPARTMENT OF ECE, CMRIT 10

Rs=(Vin(max)-VZ) / (IZ(max)+ IL)= (25-10)/(35mA+5mA)=250Ω ≈ select 280Ω/1W

Fig2. Circuit diagram to plot line and load regulation graph

Table2: Line regulation of Zener diode

Vin(V) V0(V) Iz(mA)

Table3: Load regulation of Zener diode

RL(Ω) V0(V) Iz(mA)

DEPARTMENT OF ECE, CMRIT 11

Expt.No.2 : Design and Test

Sl. No. Component Details Specification Quantity

DEPARTMENT OF ECE, CMRIT 12

CIRCUIT DIAGRAM AND DESIGN:

In the positive half cycle D is forward biased

b) SERIES POSITIVE CLIPPER CIRCUIT:

In the positive half cycle D is reverse biased

𝑉𝑜 = 𝑉𝑖 + 𝑉𝐷 => 𝑉𝑜 = −5 + 0.5 = −4.5𝑉

c) SERIES NEGATIVE CLIPPER CIRCUIT (WITH DC SUPPLY):

DEPARTMENT OF ECE, CMRIT 13

In the positive half cycle

In the negative half cycle

‘D’ is reverse biased, hence 𝑉𝑜 = 0

d) SERIES POSITIVE CLIPPER CIRCUIT (WITH DC SUPPLY):

In the negative half cycle

e) TWO SIDED SERIES CLIPPER: