Electronic Devices and Circuits Lab New

ELECTRONIC DEVICES AND CIRCUITS LAB
Dept. Of ECE, SBCE Page 1

LIST OF EXPERIMENTS
Sl.No Name of Experiment Page No.
1 VI Characteristics of rectifier and zener diodes
2 RC integrating and differentiating circuits
3 Clipping and clamping circuits
4 Fullwave Rectifier -with and without filter
5 Simple Zener voltage regulator
6 Characteristics of BJT in CE configuration and

evaluation of parameters
7 RC coupled CE amplifier
8 Cascade amplifier
9 Feedback amplifiers (current series, voltage series)
10 RC phase shift Oscillator
11 Wien bridge Oscillator
12 Bootstrap sweep circuit
13 Astable Multivibrator
14 Monostable Multivibrator
15 Schmitt trigger

Expt. No: 1
Date:
V-I CHARACTERISTICS OF RECTIFIER AND ZENER

DIODES
Aim: To plot the characteristics of rectifier and zener diode.
Components Required:
Components Specification Quantity
Silicon diode 1N4001 1
Germanium Diode OA79 1
Zener Diode 5.6v 1
Rheostat 1K 1
Voltmeter (0-1)V,(0-30)V 1 each
Ammeter (0-100)mA 1
Theory:
A PN Junction Diode is one of the simplest semiconductor devices around, and
which has the characteristic of passing current in only one direction.
When a diode is connected in a Forward Bias condition, a negative voltage is
applied to the N-type material and a positive voltage is applied to the P-type
material. If this external voltage becomes greater than the value of the
potential barrier, approx. 0.7 volts for silicon and 0.3 volts for germanium, the
potential barriers opposition will be overcome and current will start to flow.
This is because the negative voltage pushes or repels electrons towards the
junction giving them the energy to cross over and combine with the holes
being pushed in the opposite direction towards the junction by the positive
voltage. This results in a characteristics curve of zero current flowing up to this
voltage point, called the “knee” on the static curves and then a high current
flow through the diode with little increase in the external voltage.
When a diode is connected in a Reverse Bias condition, a positive voltage is
applied to the N-type material and a negative voltage is applied to the P-type
material. If the reverse bias voltage applied to the diode is increased to a
sufficiently high enough value, it will cause the diode’s PN junction to overheat

and fail due to the avalanche effect around the junction. This may cause the
diode to become shorted and will result in the flow of maximum circuit
current.
The Zener diode is like a general-purpose signal diode consisting of a silicon PN
junction. When biased in the forward direction it behaves just like a normal
signal diode passing the rated current, but as soon as a reverse voltage applied
across the zener diode, exceeds the rated voltage of the device, the diode’s
breakdown voltage is reached at which point a process called Avalanche
Breakdown occurs in the semiconductor depletion layer and a current starts to
flow through the diode to limit this increase in voltage.
The current now flowing through the zener diode increases dramatically to the
maximum circuit value (which is usually limited by a series resistor) and once
achieved this, reverse saturation current remains fairly constant over a wide
range of applied voltages. The voltage point at which the voltage across the
zener diode becomes stable is called the “zener voltage”. For zener diodes this
voltage can range from less than one volt to hundreds of volts.
Procedure:
1. Wire the circuit as shown in the figure after testing the components.
2. Vary the input voltage by adjusting the rheostat and note down the
ammeter and voltmeter readings and enter it in the tabular column.
3. Plot the characteristics on a graph sheet with voltage and current along the
x and y axis respectively. (Forward characteristics for Silicon and Germanium
diodes and the reverse characteristics of Zener diode.)
4. Calculate the static and dynamic resistances.

Result:
For Silicon
Cut in voltage:
Static Resistance:
Dynamic Resistance:
For Germanium
Cut in voltage:
Static Resistance:
Dynamic Resistance:
For Zener diode
Break down voltage:
Static Resistance:
Dynamic Resistance:

Circuit Diagram:

Design:
Design for rectifier
To assure the safety of the diode, take current =10 mA .

Vmax−0.7
R= = 1K where Vmax=10 V
10 mA
Design for Zener:

Vmax−5.6
R= =470Ω where Vmax=10 V
10 mA
Tabular column:
Forward Characteristics - Silicon
V(volts) I(mA)
Forward Characteristics - Germanium

V(volts) I(mA)
Reverse Characteristics - Zener

V(volts) I(mA)

Expt. No: 2
Date:
RC INTEGRATOR AND DIFFERENTIATOR

Aim: To design and set up an RC integrator and Differentiator and study its
response to pulse and square waves.
Capacitor 3.3µF,220pF 1 each
Resistor 5.6K 1
Theory:
A differentiator gives the derivative of input voltage as output. A differentiator
using passive components resistors and capacitors is a high pass filter. It acts as
a differentiator only when the time constant is too small. The voltage at output
is proportional to the current through the capacitor. The current through the
capacitor can be expressed as Cdv /dt .The output is taking across the resistor.
So output will be RC dv /dt . Thus differentiation of input takes place.
When a square wave is applied at the input, during the positive half cycle,
capacitor charges. So initially the voltage across the resistor will be the applied
voltage. As the capacitor charges, the voltage across resistor decreases.
Consider the case of integrator. It is a low pass filter. Here the time
constant of the circuit should be very large. Here output is taking across the
capacitor. As the input square wave is applied, during the positive half cycle
the voltage across capacitor increases from zero to the maximum (peak value
of applied voltage). During the negative half cycle, the capacitor starts to
discharge and comes to zero. This process repeats for the remaining cycles and
a triangular wave is obtained.

Procedure:

2. Note down the output waveforms for the following conditions using a
potentiometer. (i) RC =T (ii) RC ≪T (iii) RC ≫T
3. Repeat the above steps for a 10Vpp, 1 kHz pulse wave input.

Result:

Circuit Diagram:
RC Integrator
RC Differentiator

Design:
Design of Integrator:
Let the input be pulse train of 1kHz. Then T=1ms.
For an Integrator RC ≥16 T
To avoid loading select R=10× output impedance of the signal generator
The output impedance of the signal generator = 600Ω
Then R= 6000Ω
Use 5.6 k std
We get C= 2.857 µF. Use 3.3µF std.
Design of Differentiator:
Let the input be pulse train of 1kHz. Then T=1ms.
For an Integrator RC ≤ 0.0016T
To avoid loading select R=10× output impedance of the signal generator
The output impedance of the signal generator = 600Ω
Then R= 6000Ω
Use 5.6 k std
We get C= 285pF. Use 220pF std.

Expt. No: 3
Date:
CLIPPING AND CLAMPING CIRCUITS

Aim: To design, setup and study various shunt clipping and clamping circuits
using diodes.
Diodes IN4001 2
Resistor 3.3k 2
Theory:
The Diode Clipper, also known as a Diode Limiter, is a wave shaping circuit that
takes an input waveform and clips or cuts off its top half, bottom half or both
halves together to produce an output waveform that resembles a flattened
version of the input.
Positive Diode Clipping Circuits
In this diode clipping circuit, the diode is forward biased (anode more positive
than cathode) during the positive half cycle of the sinusoidal input waveform.
For the diode to become forward biased, it must have the input voltage
magnitude greater than +0.7 volts (0.3 volts for a germanium diode).
When this happens the diodes begins to conduct and holds the voltage across
itself constant at 0.7V until the sinusoidal waveform falls below this value.
Thus the output voltage which is taken across the diode can never exceed 0.7
volts during the positive half cycle.
During the negative half cycle, the diode is reverse biased (cathode more
positive than anode) blocking current flow through itself and as a result has no
effect on the negative half of the sinusoidal voltage which passes to the load
unaltered. Then the diode limits the positive half of the input waveform and is
known as a positive clipper circuit.

Negative Diode Clipping Circuits

Here the reverse is true. The diode is forward biased during the negative half
cycle of the sinusoidal waveform and limits or clips it to -0.7 volts while
allowing the positive half cycle to pass unaltered when reverse biased. As the
diode limits the negative half cycle of the input voltage it is therefore called a
negative clipper circuit.
Positive clipping at +3 V
Till the input becomes greater than +3V, diode is reversing biased and the
input appears at the output. When input is greater than +3V.diode becomes
forward biased and cell voltage appease at the output. Since the voltage drop
across the diode develops in series with the cell, actual clipping level is at
+3.6V
Positive clipper clipping at -3V
Diode becomes reverse biased when the input voltage is less than -3V and the
input appear at the output. When the input is above-3V, diode becomes
forward biased and the cell voltage is available at the output. Since the voltage
drop across the diode develops in series and opposite with the cell, actual
clipping level is at -2.4V.
Negative clipper with clipping level at -3V
When the input voltage becomes less than -3V, diode becomes forward biased
and the cell voltage becomes available at the output. When the input is greater
than -3V, diode is reverse biased and the input appears at the output. Actual
clipping level is at -3.6V, due to the voltage drop across the diode
Negative clipper clipping at +3V
Diode becomes reverse biased when the input voltage is greater than the +3V,
diode become forward biased and the cell voltage is available at the output.
Since the voltage drops across the diode develops in series and opposite with
the cell, actual clipping level is at +2.4V.

In some situation it is necessary to add or subtract a dc voltage to a given

waveform without changing its shape. Circuits used for this purpose are cell
clamping circuits. This can be achieved by connecting a dc source in series with
the input. DC sources are very expensive and bulky equipments. A capacitor
which is charged to a voltage and subsequently prevented from discharging
can serve as a suitable replacement for a dc source. This principle is utilized in
clamping circuits. The clamping level can be made at any voltage level by
biasing the diode. Such a clamping circuit is called a biased clamper.
Positive clamper clamping at 0V
Suppose the input voltage is represented by the expression VM sin ωt.

During one negative half cycle of the input sine wave, the diode conducts and
capacitor charges to vm with positive polarity at right side of the capacitor.
During the positive half cycle of the input sin wave, the capacitor cannot
discharge since the diode does not conduct. Thus capacitor act as a dc source
of VM volts connected in series with input signal source. The output voltage
than can be expressed as V0 =VM+VMsinωt.
Negative clamper clamping at 0V
During one positive half cycle of the input sine wave, the diode conducts and
capacitor charges to vm with negative polarity at right side of the capacitor.
During the negative half cycle of the input sine wave, the capacitor cannot
discharge since the diode does not conduct. Thus capacitor acts as a dc source
of vm volts connected in series with input signal source .The output voltage
then can be expressed as V0=-VM+VMsinωt.
Positive clamper clamping at +3V
During one negative half cycle of the input sine wave, capacitor charge through
the dc source and diode till (VM+3) vots with positive polarity of the capacitor
at the right side .The charging of the capacitor is limited to (VM+3) volts due to
the presence of the dc source .The output is then expressed as V 0= (VM+3) + VM
sin ωt.
Positive clamper clamping at-3V

During one negative half cycle of the input sine wave, capacitor charge
through dc source and diode till (VM-3) vots with positive polarity of the
capacitor at the right side. The charging of the capacitor is limited to (VM-3)
volts due to the presence of the dc source. The output is then expressed as V 0=
(VM-3) + VM sin ωt.
Negative clamper clamping at +3V
During one positive half cycle of the input sine wave, capacitor charge through
the dc source and diode till (VM - 3) vots with negative polarity of the capacitor
at the right side .The charging of the capacitor is extended up to (VM-3) volts
due to the presence of the dc source .The output is then expressed as V 0= -
(VM-3) + VM sin ωt.
Negative clamper clamping at -3V
During one positive half cycle of the input sine wave, capacitor charge through
the dc source and diode till (VM+3) vots with positive polarity of the capacitor
at the right side .The charging of the capacitor is extended up to (VM+3) volts
due to the presence of the dc source .The output is then expressed as V 0=-
(VM+3) + VM sin ωt.
Procedure:
1. Wire the circuit as shown in the figure after testing the components
2. Apply 20V peak to peak sine wave at the input.
3. Observe the input and output waveforms on the CRO simultaneously.
4. To observe transfer characteristics on the CRO screen, feed Vin to
channel-X and Vo to channel and set the CRO in transfer characteristics
mode.

Result:

Circuit Diagram:



Design:
Select 1N4001 diodes
The series resistance used for current limiting R=√ R f × Rr
Typical values of R f = 30 Ω and of Rr = 300k
We get R=√ 30 Ω ×300 k = 3k
Use 3.3k
For clamping circuits, use C=1 µF or more since the capacitor acts a voltage
source.
Expt. No: 4
Date:
FULL WAVE RECTIFIER WITH AND WITHOUT FILTER

Aim: To study the characteristics of full wave rectifier with and without filter
and to find its percentage regulation, ripple factor and efficiency.
Diodes IN4001 4
Resistor 1K 2
Capacitor 100 µF 1
Transformer 230V/6V 1
Theory:
The conversion of AC into pulsating DC is called Rectification.The full-wave
rectifier consists of a center-tapped transformer, which results in equal
voltages above and below the center-tap. During the positive half cycle, a
positive voltage appears at the anode of D1 while a negative voltage appears
at the anode of D2. Due to this diode D1 is forward biased. It results a current I
through the load R.
During the negative half cycle, a positive voltage appears at the anode of D2
and hence it is forward biased, resulting a current through the load. At the
same instant a negative voltage appears at the anode of D1, reverse biasing it
and hence it doesn’t conduct.
Electronic filters perform signal processing functions, specifically to remove
unwanted frequency components from the signal. Capacitor allows AC and
blocks DC signal. Capacitor is placed in parallel with the output. If capacitance
value increases its capacity also increases which increases efficiency of rectifier .
Procedure:

1. Wire the circuit of full wave rectifier without filter as shown in the figure
after testing the components.
2. Switch on the mains supply. Observe the transformer secondary voltage
waveform and output voltage waveform across the load resistor. Note
down Vm and calculate Vrms and Vdc.
3. Calculate the ripple factor, percentage regulation and efficiency using
the expression.
4. Connect the capacitor filter and observe the waveforms.
Result:

Circuit Diagram:

Design:
Select 230V/6V-0-6V,100 mA center-tapped transformer and diodes 1N4001.
Design of load resistor RL
Load resistor RL should be high enough to make the capacitor discharge slowly.
Same time it should limit the current through the diodes.
Assume a current of 5 mA should flow through the diodes.
Then
6 √ 2−1.4
R L= = 920 Ω
5 mA
Since the voltage drop across the two diodes together is 1.4 V.
Select R L=1k
Design of Capacitor C
The required ripple factor of capacitor input filter is 3%.

1
r=
4 √ 3 f RL C
Power supply frequency f= 50 Hz.

Assume R L=1k
Then C ≈ 100µF.
Tabular column:
Vm Vrms Vdc Ripple factor
FWR without
filter
FWR with filter
Expt. No: 5

Date:
ZENER VOLTAGE REGULATOR

Aim: To setup and study a zener diode regulator and to plot the line and
load regulation characteristics.
Zener Diode 5.6v 1
Rheostat 1K 1
Resistor 100Ω 1
Voltmeter (0-10)V,(0-30)V 1 each
Ammeter (0-100)mA 1
Theory:
The function of a regulator is to provide a constant output voltage to a load
connected in parallel with it, in spite of the ripples in the supply voltage or the
variation in the load current. The zener diode will continue to regulate the
voltage until the diodes current falls below the minimum I Z(min) value in the
reverse breakdown region. It permits current to flow in the forward direction
as normal, but will also allow it to flow in the reverse direction when the
voltage is above a certain value - the breakdown voltage known as the Zener
voltage. The Zener diode specially made to have a reverse voltage breakdown
at a specific voltage. Its characteristics are otherwise very similar to common
diodes. During breakdown, the voltage across the Zener diode is close to
constant over a wide range of currents thus making it useful as a shunt voltage
regulator.
The resistor is selected so that when the input voltage is at V IN(min) and the
load current is at IL(max) that the current through the Zener diode is at least
Iz(min). Then for all other combinations of input voltage and load current the
Zener diode conducts the excess current thus maintaining a constant voltage
across the load. The Zener conducts the least current when the load current is
the highest and it conducts the most current when the load current is the
lowest.
If there is no load resistance, shunt regulators can be used to dissipate total
power through the series resistance and the Zener diode. Shunt regulators

have an inherent current limiting advantage under load fault conditions

because the series resistor limits excess current.
A Zener diode of break down voltage Vz is reverse connected to an input
voltage source Vi across a load resistance RL and a series resistor RS. The
voltage across the zener will remain steady at its break down voltage V Z for all
the values of zener current IZ as long as the current remains in the break down
region. Hence a regulated DC output voltage V 0 = VZ is obtained across RL,
whenever the input voltage remains within a minimum and maximum voltage.
Basically there are two type of regulations such as:
a. Line Regulation: In this type of regulation, series resistance and load

resistance are fixed, only input voltage is changing. Output voltage
remains the same as long as the input voltage is maintained above a
minimum value.
b. Load Regulation: In this type of regulation, input voltage is fixed and the
load resistance is varying. Output volt remains same, as long as the load
resistance is maintained above a minimum value.
Procedure:
1. Wire the circuit as shown in the figure after testing the components
2. Note down the output voltage varying from 7 V to 10 V in steps of
1V.Plot the line regulation graph with Vin along the x-axis and Vo along
y-axis.
3. Calculate the percentage line regulation with expression (∆Vo/∆Vin)×
100%.
4. Keep the input voltage constant and note down output voltage for
various values of load current starting from 0 to 10 mA, by varying R L
using a pot. Plot the load regulation graph with IL along the x-axis and Vo
along y-axis.
5. To calculate percentage load regulation, mark VNL and VFL on y-axis on the
load regulation graph. VNL is the output voltage in the absence of load
resistor and VFL is the output voltage corresponds to rated IL.
6. Calculate the percentage load regulation VR using the expression.

V NL −V FL
V R= × 100 %
V NL

Result:
The percentage load regulation VR =
V NL −V FL
V R= × 100 %
V NL
The percentage line regulation = (∆Vo/∆Vin)× 100%.

Circuit Diagram:
Design:
Select 5.6 V zener
R L=V o /I L
But Vo=Vz
5.6 V
Then R L= 5 mA = 1.12k.
Use 1.2k pot

Design of series resistance Rs
RS max > RS > RS min
V i max−V z 13−5.6
R Smax= = V =493Ω
IS 15 mA
V i min −V z 7−5.6
R Smin= = V =93 Ω
IS 15 mA
Since I S=I L + I z =5 mA+10 mA=15 mA

Select Rs =100Ω

Tabular column:
Line Regulation
Vin Vo
Load Regulation
IL Vo

Expt. No:6
Date:
CHARACTERISTICS OF BJT IN CE CONFIGURATION AND

EVALUATION OF PARAMETERS
Aim: To Plot the input and output characteristics of an NPN transistor in
common emitter configuration and to find out its parameters.
Transistor BC107 1
Resistor 47k, 1k I each
Rheostat 1K 2
Micro ammeter 0-100 µA 1
voltmeter 0-1v,0-30V 1 each
Milli ammeter 0-100mA 1
Theory:
The input is applied between base and emitter and the output is taken
between collector and emitter. Here emitter of the transistor is common to
both input and output and hence the name Common Emitter Configuration.
Input characteristics are obtained between the input current and input voltage
at constant output voltage. It is plotted between VBE and IB at constant VCE in CE
configuration.
Output characteristics are obtained between the output voltage and output
current at constant input current. It is plotted between VCE and IC at constant IB
in CE configuration.
Procedure:
2. Switch on the power supplies keeping the rheostat in minimum voltage

position.

3. Note down the base current for different values of base to emitter potential
by keeping VCE constant(repeat this step for at least 3 values of V CE) to plot the
i/p characteristics.
4. Note down the collector current for different values of collector to emitter
potential by keeping IB constant(repeat this step for at least 3 values of I B)to
plot the o/p characteristics.
Result:
Dynamic input resistance ri = ΔVBE/ΔIB=…………..Ω
Dynamic output resistance ro= ΔVCE/ΔIC=…………..Ω
Common emitter current gain β= ΔIC/ΔIB =……………..
Circuit Diagram:

Design:
BC 107 is a low power npn transistor.
Maximum ratings: VCB=50V,VCE=45V,VEB=6V, IC=100mA
Normal ratings: Vce=5V, Ic=2mA, hFE=100 to 500.
RB=(5v-Vbe)/IB = 5V-0.6V/100 µA = 47K
RC= (30v-VCEsat)/IC=30v-0.3V/30mA= 1K
Tabular column:
Input Characteristics
VBB (Volts)8 VCE = 0V VCE = 5V
VBE (Volts) IB (µA) VBE (Volts) IB (µA)


Output Characteristics
VCC (Volts) IB = 0 µA IB = 20 µA IB = 40 µA
VCE (Volts) IC (mA) VCE (Volts) IC (mA) VCE (Volts) IC (mA)


Expt. No:7
Date:
RC COUPLED CE AMPLIFIER
Aim:
To design and set up an RC-coupled CE amplifier using bipolar junction
transistor and to plot its frequency response.
Transistor BC107 1
Resistor 47K,2.2K,10K 1 each
680Ω,820Ω
Capacitor 10µF 2
22µF 1
Theory:
RC-coupled CE amplifier is widely used in audio frequency applications in radio
and TV receivers. It provides current, voltage and power gains. Base current
controls the collector current of a common emitter amplifier. A small increase
in base current results in a relatively large increase in collector current.
Similarly, a small decrease in base current causes large decrease in collector
current. The emitter-base junction must be forward biased and the collector
base junction must be reverse biased for the proper functioning of an
amplifier. In the circuit diagram, an NPN transistor is connected as a common
emitter ac amplifier. R1 and R2 are employed for the voltage divider bias of the
transistor. Voltage divider bias provides good stabilisation independent of the
variations of β. The input signal Vin is coupled through CC1 to the base and
output voltage is coupled from collector through the capacitor C C2. The input
impedance of the amplifier is expressed as Z in = R1||R2||(1 +hFEre) and output
impedance as Zout = RC||RL , where re is the internal emitter resistance of the
transistor given by the expression = 25 mV/I E, where 25 mV is temperature
equivalent voltage at room temperature.

Selection of transistor
Transistor is selected according to the frequency of operation and power
requirements. The hFE of the transistor is another aspect we should be careful
about. Voltage gain Av = −hFE RL Ri .
Therefore a transistor must be selected such that its minimum guaranteed h FE
is greater than or equal to Av required.
Selection of supply voltage VCC
For a distortion less output from an audio amplifier, the operating point must
be kept at the middle of the load line selecting V CEQ = 50% VCC(= 0.5VCC). This
means that the output voltage swing in either positive or negative direction
and is half of VCC. However, VCC is selected 20% more than the required voltage
swing. For example, if the required output swing is 10 V, VCC is selected 12 V.
Selection of collector current IC
The nominal value of IC can be selected from the data sheet. Usually it will be
given corresponding to hFE bias. It is the bias current at which h FE is measured.
For BC107 it is 2 mA, for SL100 it is 150 mA, and for power transistor 2N3055 it
is 4 A.
Design of emitter resistor RE:
Current series feedback is used in this circuit using R E. It stabilizes the
operating point against temperature variation. Voltage across R E must be as
high as possible. But, higher drop across R E will reduce the output voltage
swing. So, as a rule of thumb, 10% of VCC is fixed across RE.
RE = VRE/ IE = VRE/ IC since IE ≈ IC, RE = 0.1 VCC/ IC
Design of RC
Value of RC can be obtained from the relation RC = 0.4VCC/IC since remaining
40% of VCC is dropped across RC.
Design of potential divider R1 and R2
Value of IB is obtained by using the expression I B = IC/hFE min. At least 10IB
should be allowed to flow through R1 and R2 for the better stability of bias
voltages. If the current through R 1 and R2 is near to IB , slight variation in IB will
affect the voltage across R1 and R2. In other words, the base current will load
the voltage divider. When IB gets branched into the base of transistor, 9IB flows

through R2. Values of R1 and R2 can be calculated from the dc potentials

created by the respective currents.
Design of bypass capacitor CE
The purpose of the bypass capacitor is to bypass signal current to ground. To
bypass the frequency of interest, reactance of the capacitor X CE computed at
that frequency should be much less than the emitter resistance. As a rule of
thumb, it is taken XCE ≤ RE/10.
Design of coupling capacitor CC
The purpose of the coupling capacitor is to couple the ac signal to the input of
the amplifier and block dc. It also determines the lowest frequency that to be
amplified. Value of the coupling capacitor CC is obtained such that its reactance
XC at the lowest frequency (say 100 Hz or so for an audio amplifier), should be
less than the input impedance of the amplifier. That means X≤ Ri n/10. Here Rin
= R1||R2||(1 + hFEre) where re is the internal emitter resistance of the
transistor.
Procedure:
1.Test all the components using a multimeter. Set up the circuit and verify
dc bias conditions. To check dc bias conditions, remove input signal and
capacitors in the circuit.
2. Connect the capacitors in the circuit. Apply a 100 mV peak to peak
sinusoidal signal from the function generator to the circuit input. Observe
the input and output waveforms on the CRO screen simultaneously.
3. Keep the input voltage constant at 100 mV, vary the frequency of the
input signal from 0 to 1 MHz or highest frequency available in the generator.
Measure the output amplitude corresponding to different frequencies and
enter it in tabular column.
4. Plot the frequency response characteristics on a graph sheet with gain in
dB on y-axis and log f on x-axis. Mark log f L and log fH corresponding to 3 dB
points.
5. Calculate the bandwidth of the amplifier using the expression
BW= fH − fL.

Result:
With CE:
Mid-band gain of the amplifier =. . . . . .
Bandwidth of the amplifier =. . . . . . Hz

Circuit Diagram:
Design:
Output requirements: Mid-band voltage gain of the amplifier = 50 and required
output voltage swing = 10 V.
Selection of transistor
Select transistor BC107 since its minimum guaranteed hFE(= 100) is more than
the required gain (=50) of the amplifier.
Quick Reference data of BC107
Type: NPN-Silicon, Application: In audio frequency
Maximum rating: VCB = 50 V, VCE = 45 V, VEB = 6 V, IC = 100 mA.
Nominal rating: VCE = 5 V, IC = 2 mA, hF E = 100 to 500.
DC biasing conditions
VCC is taken as 20% more than required output swing.
Hence VCC = 12 V.
IC = 2 mA, because hFE is guaranteed 100 at that current as per data sheet.
In order to make the operating point at the middle of the load line, assume the
dc conditions VRC = 40% of VCC = 4.8 V, VRE = 10% of VCC = 1.2 V and VCE = 50%of
VCC = 6 V .

Design of RC
VRC = IC × RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k.
Design of RE
VRE = IE × RE = 1.2 V. From this, we get RE = 600 Ω because IE ≈ IC. Use 680 Ω std.
Design of voltage divider R1 and R2
Assume the current through R1 = 10IB and that through R2 = 9IB for a stable
voltage across R1 and R2 independent of the variations of the base current.
VR2 = Voltage drop across R2 = VBE + VRE.
i.e., VR2 = VBE + VRE = 0.6 + 1.2 = 1.8 V. Also, VR2 = 9IBR2 = 1.8 V
But IB = IC/hFE = 2 mA/100 = 20 µA. Then R2 =10.6K,Use 10 k.
VR1 = voltage across R1 = VCC − VR2 = 12 V − 1.8 V = 10.2 V
Also, VR1 = 10IBR1 = 10.1 V. Then R1 =10.210×20×10−6 = 50 k. Select 47 k std.
Design of RL
Gain of the common emitter amplifier is given by the expression
AV = −(rc/re). Where rc = RC||RL and re = 25 mV /IE = 25 mV /2 mA = 12.5 Ω.
Since the required gain = 50, substituting it in the expression we get, R L = 845Ω.
Use 820 Ω std.
Design of coupling capacitors CC1 and CC2
XC1 should be less than the input impedance of the transistor. Here, R in is the
series impedance.
Then XC1 ≤= Rin/10. Here Rin = R1||R2||(1 + hFEre) because is RE bypassed.
We get Rin = 1.1 k. Then XC1 ≤ 110 Ω.
So, CC1 ≥ 1/2πfL × 110 = 14 µF. Use 15 µF std.
Similarly, XC2 ≤ Rout/10, where Rout = RC. Then XCE ≤ 240 Ω.
So, CC2 ≥ 1/2π × 240 = 6.6 µF. Use 10 µF std.
Design of bypass capacitors CE
To bypass the lowest frequency (say 100Hz), XCE should be less than or equal to
the resistance RE.
i.e., XCE ≤ RE/10 Then, CE ≥ 1/(2π × 100 × 68) = 23 µF. Use 22 µF.
Tabular column:
Frequency Gain 20log(gain)

Expt. No:8
Date:
CASCADE AMPLIFIER
Aim:
To design, set up and study a two stage RC coupled CE amplifier using BJT.
Transistor BC107 1
Resistor 47K,2.2K,10K,470Ω 2each
680Ω,180Ω 1each
Capacitor 33µF 2
22µF 3
Theory:
Multistage amplifiers are used in cascade to improve parameters such as
voltage gain, current gain, input impedance and output impedance etc.
Common emitter stages are cascaded to increase the voltage gain. A two stage
amplifier provides an overall voltage gain of A1A2, where A1 and A2 are the gains
of first and second stages respectively. Since each stage provides a phase
inversion, the final output signal is in phase with the input signal.
The input impedance of the second stage is in parallel with R C1 of the first
stage. The ac voltage gain of the first stage is A 1 = RC1||Rin2/(re + Re) where Rin2 is
the input resistance of the second stage. R in2 = R12||R22||(1 + hFEre) The ac
voltage gain of the second stage is A2 = (RC2||RL)/r. Care must be taken while
selecting A1 and A2. If A1 is large, the input to the second stage will become too
high. This may pull out the transistor of the second stage from active region.
For example, if we need an overall voltage gain of 100, select A1 = 4 and A2 =
25. Gain of the first stage can be controlled by a negative feedback in series
with the emitter. This is achieved by the bypassed resistor RE.

Procedure:
1.Test all the components using a multimeter. Set up the circuit and verify
dc bias conditions. To check dc bias conditions, remove input signal and
capacitors in the circuit.
2. Connect the capacitors in the circuit. Apply a 100 mV peak to peak
sinusoidal signal from the function generator to the circuit input. Observe
the input and output waveforms on the CRO screen simultaneously.
3. Keep the input voltage constant at 100 mV, vary the frequency of the
input signal from 0 to 1 MHz or highest frequency available in the generator.
Measure the output amplitude corresponding to different frequencies and
enter it in tabular column.
4. Plot the frequency response characteristics on a graph sheet with gain in
dB on y-axis and log f on x-axis. Mark log fL and log fH corresponding to 3 dB
points. (If a semi-log graph sheet is used instead of ordinary graph sheet,
mark f along x-axis instead of logf).
5. Calculate the bandwidth of the amplifier using the expression BW= fH − fL.

Result:
Gain of the first stage = …………………
Gain of the first stage = …………………
Bandwidth of the amplifier = …………………..Hz

Circuit Diagram:
Design:
Assume the gains A1=4 and A2=25 since A= A1A2 and A1 should be a lower value
to avoid high input voltage to second stage.
VCC is taken as 20% more than the required output swing.
Hence VCC = 12 V.
In order to make the operating point at the middle of the load line, assume the
dc conditions VRC = 40% of VCC = 4.8 V, VRE = 10% of VCC = 1.2 V and VCE = 50% of
VCC = 6V.
Design of RC1 and RC2
Take RC1=RC2=RC
Design of RE

But IB = IC/hF E = 2 mA/100 = 20 µA.
Then R2 = 1.8×20×10−6 = 10.6 k. Use 10 k.
Also, VR1 = 10IBR1 = 10.1 V. Then R1 = 10.2×20×10−6 = 50 k. Select 47 k std.
Design of Re and Re’
Gain of the first stage is given by the expression
RC ∨¿ R ¿2
A1=
re+ R e
Where Re = R E + Re ' and R¿ 2= R1∨¿ R2 ∨¿(1+h ¿ ¿ FE r e )=1.1 Ω¿

25 mV
Here r e = I =12.5 Ω
E
We get Re =173 Ω
Re ' =R E−R e=470 Ω
Design of RL:
Gain of the second stage is given by the expression
A2 = RC||RL) /re = 25.
substituting it in the expression we get, RL = 470 Ω.
series impedance.
Then XC1 ≤= Rin/10. Here Rin = R1||R2||(1 + hFEre)=1.1K
We get Rin = 1.1 k. Then XC1 ≤ 110 Ω.

So, CC1 ≥ 1/2πfL × 110 = 14 µF. Use 22µF std.

Take CC2=CC3=CC1=22µF
To bypass the lowest frequency (say 100Hz), X CE should be less than or equal to
the resistance RE.
i.e., XCE ≤ RE/10.
Then, CE ≥ 1/(2π × 100 × 68) = 23 µF. Use 33µF
Tabular column:
Frequency V0 in volts Gain (db)
in Hz

Expt. No:9
Date:
FEEDBACK AMPLIFIERS
Aim:
To design, setup and study various feedback amplifiers.
Transistor BC107 1
Resistor 47K,2.2K,10K, 680Ω 1 each
Capacitor 10µF 2
1µF 2
Theory:
An open loop amplifiers suffers from many limitations such as frequency and
phase distortions, noise. These limitations can be rectified in a feedback
amplifier. Though the gain will be reduced in the feedback amplifiers,
bandwidth of operation will be greater.
Current series feedback amplifier
A common emitter RC Coupled amplifier without emitter bypass capacitor C E is
an example of current series amplifier. Sampled signal is current and feedback
signal is voltage. Emitter resistance sample the output current and feed a
voltage back to the input side as a voltage.
Voltage series feedback amplifier
Emitter follower is a good example of voltage series feedback. Here sampled
signal is voltage and feedback signal is current.
Its feedback factor is 1.

Procedure:
1. Set up the circuit after testing all the components using a multimeter .
2. Feed the input signal and note down o/p amplitude by varying their
frequency.
3. Plot the frequency response characteristics on a graph sheet with gain in dB
on y-axis and log f on x-axis. Mark log f L and log fH corresponding to 3 dB
points.
4. Calculate the bandwidth of the amplifier using the expression BW= f H − fL.

Result:
Gain of the current series feedback amplifier = ……………….
Bandwidth of current series feedback amplifier = …………………….
Gain of voltage series feedback amplifier = …………………..
Bandwidth of voltage series feedback amplifier = ………………….

Circuit Diagram:
Design:

Hence VCC = 12 V.
In order to make the operating point at the middle of the load line,

assume the dc conditions VRC = 40% of VCC = 4.8 V, VRE = 10% of VCC = 1.2 V and
VCE = 50% of VCC = 6 V .
Design of RC

Design of RE
VRE = IE × RE = 1.2 V. From this, we get RE = 600 Ω because
IE ≈ IC. Use 680 Ω std.
But IB = IC/hFE = 2 mA/100 = 20 µA. Then R2 = 1.8×20×10−6 = 10.6 k. Use 10 k.
Also, VR1 = 10IBR1 = 10.1 V. Then R1 =10×20×10−6 = 50 k. Select 47 k std.
series impedance.
Then XC1 ≤= Rin/10. Here Rin = R1||R2||(1 + hFEre) because is RE bypassed.
We get Rin = 1.1 k. Then X= ≤ 110 Ω.
So, CC1 ≥ 1/2πfL × 110 = 14 µF. Use 15 µF std.
Similarly, XC2 ≤ Rout/10, where Rout = RC.
Then XCE ≤ 240 Ω.
So, CC2 ≥ 1/2π × 240 = 6.6 µF. Use 10 µF std.
Design of bypass capacitor C
Use C=10µF

Design of feedback resistor Rf

β= RE2/ (RE2+RF) Take β = 0.5. Then RF= 680Ω
Tabular column:
Frequency V0 in volts Gain (db)
in Hz
Expt. No:10
Date:
RC PHASE SHIFT OSCILLATOR

Aim: To design and set up an RC Phase shift oscillator
Transistor BC107 1
Resistor 47K, 2.2K, 10K,680E 1each

4.7k 2
POT 4.7K 1
Capacitor 0.01µF 3
22µF, 1µF 1 each
Theory:
An oscillator is an electronic circuit for generating an ac signal voltage with a dc
supply as the only input requirement. The frequency of the generated signal is
decided by the circuit elements. An oscillator requires an amplifier, a
frequency selective network, and a positive feedback from the output to the
input. The Barkhausen criterion for sustained oscillation is Aβ = 1 where A is
the gain of the amplifier and β is the feedback factor. The unity gain means
signal is in phase. (If the signal is 180◦ out of phase, gain will be −1.)
If a common emitter amplifier is used, with a resistive collector load, there is a
180◦ phase shift between the voltages at the base and the collector. Feedback
network between the collector and the base must introduce an additional 180◦
phase shift at a particular frequency.
Three sections of phase shift networks are used so that each section introduces
approximately 60◦ phase shift at resonant frequency. By analysis, resonant
frequency f can be expressed by the equation,
1
F=
2 πRC √ 6+4 Rc/ R
The three section RC network offers a β of 1/29. Hence the gain of the
amplifier should be 29. For this, the requirement on the h FE of the transistor is
found to be

hFE ≥ 23 + 29(R/RC) + 4(RC/R).

The phase shift oscillator is particularly useful in the audio frequency range.
Procedure:
1. Connections are made as per circuit diagram.
2. Connect CRO output terminals and observe the waveform at the base and
collector of the transistor simultaneously.
Result:
Amplitude of the sine wave = ………………..V

Frequency of the sine wave = ……………Hz
Circuit Diagram:

Design:
Output requirements
Sine wave with amplitude 10 VPP and frequency 1 kHz.
Design of the amplifier
Select transistor BC107.
It can provide a gain more than 29 because its minimum hFE is 100.
VCC = 12 V, IC = 2 mA, VRC = 40% of VCC = 4.8 V,
VRE = 10% of VCC = 1.2 V and VCE = 50% of VCC = 6 V.
VCC is taken as 20% additional to the required output peak amplitude.
Design of RC
Design of RE
Voltage drop across R2 = VBE + VRE = 0.7+1.2 = 1.9V

Also VR2= 9IBR2= 1.9V

Then R2 =10K
VR1 = Vcc-VR2 = 12-1.9 = 10.1V
Then R1= 47K
Design of frequency selective network
1
F= =1KHz
2 πRC √ 6+4 Rc/ R
Take R= 4.7K to avoid loading of RC by the RC network. Then C =0.01µF. Use

4.7K pot in the last RC network.
To bypass the lowest frequency (say 100Hz), X CE should be less than or equal to
the resistance RE.
i.e., XCE ≤ RE/10 Then, CE ≥ 1/(2π × 100 × 68) = 23 µF. Use 22 µF.
Expt. No:11
Date:
WEIN BRIDGE OSCILLATOR

Aim: To design and set up a wein bridge oscillator
Transistor BC107 1
Resistor 680E 1
4.7K, 47K, 2.2K, 10K, 2 each
POT 4.7K 1
Capacitor 0.033 µF 2
1µF 2
Theory:
The wein bridge oscillator is a standard circuit for generating low frequencies
in the range of 10 Hz to about 1MHz.The method used for getting positive
feedback in wein bridge oscillator is to use two stages of an RC-coupled
amplifier. Since one stage of the RC-coupled amplifier introduces a phase shift
of 180 degree, two stages will introduces a phase shift of 360 degree. At the
frequency of oscillations f, the positive feedback network makes the input &
output in the phase. The frequency of oscillations is given as:
f =1/2π√R 1C1R2C2
Procedure:
1. Connections are made as per the circuit diagram
2. Feed the output of the oscillator to a C.R.O by making adjustments in the

Potentiometer connected in the positive feedback loop, try to obtain a stable
sine wave.

3. Measure the time period of the waveform obtained on CRO and calculate
the frequency of oscillations.
Result:
Amplitude and frequency of the sine wave = ………………….V ………….Hz

Circuit Diagram:

Design:
Quick Reference data of BC107
Type: NPN-Silicon, Application: In audio frequency
Maximum rating: VCB = 50 V, VCE = 45 V, VEB = 6 V, IC = 100 mA.
Nominal rating: VCE = 5 V, IC = 2 mA, hFE = 100 to 500.
Hence VCC = 12 V.
In order to make the operating point at the middle of the load line, assume
the dc conditions VRC = 40% of VCC = 4.8 V, VRE = 10% of VCC = 1.2 V and VCE = 50%
of VCC = 6 V .
Design of RC
Design of RE

But IB = IC/hF E = 2 mA/100 = 20 µA.
Then R2 =1.8×20×10−6 = 10.6 k. Use 10 k.
Also, VR1 = 10IBR1 = 10.1 V. Then R1 =10.210×20×10−6 = 50 k. Select 47 k std.
Design of CC
F= 1/2 πCC( R1||R2||hFERE)=1.1K, we get CC= 1µF
Design of feedback network

1
The required frequency of oscillation is f0 = 2 πRC = 1KHz
Take R= 4.7K, C=0.033µF, The gain of the amplifier must be 3
Negative feedback factor is given by R E/(RE+R3)= 3 ,then we get R3=2RE=1.2K use

4.7K pot.
Expt. No: 12
Date:
SCHMITT TRIGGER
Aim: To set up a Schmitt trigger circuit for a UTP of 6V and LTP of 4V.
Transistor BC107 2
Resistors 47k,4.7k,10k,3.3k,33k,1.5k 1 each
Capacitor 4.7pF 1
Theory:
Schmitt trigger is a Bistable circuit and the existence of only two stable states
results from the fact that positive feedback is incorporated into the circuit and
from the further fact that the loop gain of the circuit is greater than unity.
There are several ways to adjust the loop gain. One way of adjusting the loop
gain is by varying Rc1. Under quiescent conditions Q1 is OFF and Q2 is ON
because it gets the required base drive from Vcc through R c1 and R1. So the
output voltage is Vo=Vcc-Ic2Rc2 is at its lower level. Until then the output
remains at its lower level.
Procedure:
1. Set up the circuit after testing the components.
2. Switch on the power supply and observe Vc1 and Vc2 .Verify whether Vc2 is
low and Vc1 is high.
3. Feed 20 Vpp, 1kHz sine wave at the input and observe the output
waveform.
4. Observe the hysteresis curve on the CRO
Result:
Circuit Diagram:
Design:
Design of RE
UTP= VBE +IE2RE= 6 V
LTP= VBE +IE1RE= 4 V
Assume IE1= 1mA and IE2= 1.5mA.
We get RE=3.3k
Design of RB
Current limiting resistor RB= (Vin- VB)/ IB
Where Vin= peak input voltage= 10V
VB= max. voltage at the base of Q1
IB min= Ic/hFE= 20 µA
To ensure that Q1 goes to saturation actual IB should be greater than IBmin.
We get RB = (10 V- 6 V)/ 100 µA= 40k
Use 47k std.
Design of Rc1 and Rc2

When Q1 is ON:
R¿
Rc 1=V cc −I E 1 =4.4 k ¿
I E1
Use 4.7k std.
When Q2 is ON:
R¿
Rc 2=V cc −I E 2 =1.5 k ¿
I E2
IB flows through Q2= IC/hFE= 2 mA/100= 20 µA

Assume 10IB flows through R1 and 9IB flows through R2
9IBR2= V BE + I E 2 R E❑
R2= 33k
10 IB R1=V cc −I E 2 R ¿ ¿
R1= 10 k
Design of speed up capacitor C1
C1R2 = CπR1, where Cπ is base emitter capacitance of the transistor and it is
12pF.
We get C1= 5.5pF
Use 4.7 pF
Expt. No: 13
Date:
BOOTSTRAP SWEEP CIRCUIT

Aim: To set up and study a Bootstrap sweep circuit.
Transistor BC107 2
Resistors 100k,5.6k , 4.7k 1 each
Capacitor 10µF,47 µF,0.1 µF 1 each
Diode 1N4001 1
Theory:
Bootstrap sweep circuit generates a linear sweep waveform. If the charging
current of a capacitor is made constant, the voltage across the capacitor will
rise linearly. Bootstrap circuit achieves constant current through the capacitor.
The input to Q1 is the gating waveform. Before the application of the gating
waveform, at t = 0, transistor Q1 is in saturation. The voltage across the
capacitor C and at the base of Q2 is VCE(sat). To ensure Q1 to be in saturation for t
= 0, it is necessary that its current be at least equal to ICE / hFE so that Rb < hfeR.
With the application of the gating waveform at t = 0, Q 1 is driven OFF. The
current IC1 now flow into C and assuming unity gain in the emitter follower V 0.
When the sweep starts, the diode is reverse biased, as already explained
above, the current through R is supplied by C1. The current VCC / R through C
and R now flows from base to emitter of Q2.if the output V0 reaches the voltage
VCC in a time TS / Tg, then from above we have TS = RC.
Procedure:
2. Switch on the input square wave keeping at 10 Vpp,500Hz.
3. Observe the input and output waveforms on the CRO screen
4. Vary the input frequency and observe the changes in the output
waveform.

Result:

Circuit Diagram:

Design:
Design of C2
V=(I/C)T.
IT=CV
Here T= half of the time period of the input signal .i.e 0.5ms
2×10-3 ×0.5×10-3=C2×10.
Then C2=0.1µF
Use 0.1µF std
Design of R
Since the voltage across the resistor R is always constant
R=Vcc/I= 10/2×10-3=5k
Use 5.6kstd
Design of C1
Take C1>100C2 since C1 is acting as a voltage source.
Take 47 µF
Design of RB

RB provides sufficient base current to the transistor.

IB= IC/hFE= 2mA/100=20µA
Since the transistor functions as a switch ,base current should be more than
IC/hFE.
Let the actual IB be 5 times IB.
Then IB = 0.1mA
V cc −V BEsat
R B= =93 k
IB
Use 100k std.

Design of RE
R= V/RE= 10V/2mA= 5k
Use 4.7k std
Select coupling capacitor C=10µF
Expt. No: 14
Date:

ASTABLE MULTIVIBRATOR
Aim: To design and set up an astable multivibrator using transistors.
Transistor BC107 2
Resistors 82k,4.7k 2 each
Capacitor 0.1 µF,0.022 µF 1 each
Theory:
When the circuit is switched on, one transistor will drive to saturation (ON)
and the other will drive to cut off (OFF). Consider Q1 is ON and Q2 is OFF.
During this time capacitor C2 is charging to Vcc through resistor R2. Q2 is
OFF due to the negative voltage from the discharging capacitor C1 which is
charged during the previous cycle. So the OFF time of Q2 is determined by
R1C1 time constant.
After a time period determined by R1C1, the capacitor C2 discharges

completely and C1 starts charging through R1. When the Capacitor C1
charges to a voltage sufficient to provide base emitter voltage of 0.7V to the
transistor Q2, it turns ON and capacitor C2 starts discharging.
The negative voltage from the capacitor C2 turns off the transistor Q1 and
the capacitor C1 starts charging from Vcc through resistor R2 and base
emitter of transistor Q2. Thus the transistor Q2 remains in ON state. As in
the previous state, when the capacitor C2 discharges completely it starts
charging towards opposite direction through R2.
When the voltage across the capacitor C2 is sufficient to turn ON transistor

Q1, Q1 will turn ON and capacitor C1 starts discharging.This process
continuous and produces rectangular waves at the collector of each
transistors. Charging time is very less compared to discharging time.
Procedure:

2. Observe the collector and base waveforms of both transistors.
Result:

Circuit Diagram:

Design:
Output requirements
A square wave of amplitude 9V, frequency 1kHz and duty cycle =1/3.
Choose transistor BC107.
Take VCC=9V since the required amplitude of the output square wave is 9V.
V cc−V CEsat
R C 1= =4.35 k
IC1
With IC1= 2 mA
Use 4.7 k std.
Also RC1=RC2=4.7k
Design of R1 and R2
The resistors R1 and R2 must be able to provide base current enough to keep
the transistors in saturation.
IBmin- IC/ hFE= 20 µA
Actual base current IB=0.1mA

V cc−V BEsat
R 1= =83 k
0.1 mA
Take R1=R2
R1 and R2 should be less than hFERC.
Design of C1 and C2
Given that T=T1 and T2=1ms and dutycycle= T1/(T1+T2)=1/3
From T1≈0.33ms and T2≈0.66ms
T1≈0.33ms=0.69 R1C1.
Then C1=0.006µF. Use 0.01µF std.
T2≈0.66ms=0.69R2C2
Then C2= 0.011 µF
Use C2=0.022µF to make C2= 2C1
Expt. No: 15
Date:
MONOSTABLE MULTIVIBRATOR
Aim: To setup and study a monostable multivibrator using transistors
Transistor BC107 2
Resistors 6.8k,100k,56k,47k,1k 1 No. each
4.7k 2
Capacitor 1.1 µF 2
4.7pF 1
Diode 1N4001 1
Theory:
A monostable multivibrator, on the other hand compared to astable and
bistable, has only one stable state, the other state being quasi stable state.
Normally the multivibrator is in stable state and when an external triggering
pulse is applied, it switches from the stable to the quasi stable state. It remains
in the quasi stable state for a short duration, but automatically reverse
switches back to its original stable state without any triggering pulse. The
monostable multivibrator is also referred as ‘one shot’ or ‘uni-vibrator’ since
only one triggering signal is required to reverse the original stable state. The
duration of quasi stable state is termed as delay time (or) pulse width (or) gate
time. It is denoted as ‘t’.
Procedure:


2. Apply 20V, 500 Hz square wave at the trigger input.
3. Observe the collector and base waveforms for both transistors.
Result:

Circuit Diagram:
Design:
Output requirements: amplitude= 12V, pulse width =1.5ms
Selection of transistor and diode

Select transistor BC107 and diode 1N4007.

Hence VCC = 12 V, IC = 2 mA, VRE = 2V.
Take RC1= RC2 = RC
Vcc−Vc
RC = Icsat =4.7k
Design of RE
VRE = IE × RE = 2 V. From this, we get RE = 1K because IE ≈ IC.
Design of R
R must be able to provide enough base current to keep the transistor Q 2 in
saturation
IBmin = Ic/hFE=2mA/ hFE = 20µA
Consider an over-driving factor of 5, so that transistor will be indeed in
saturation.
Base current IB= 5IBmin=0.1mA
R=(Vcc- VRE- VBEsat)/0.1mA= (12-2-0.6)/0.1mA=100K
Consider the stable state(Q1 is off and Q2 is on)
Assume VBE1 =-1V assure that the transistor Q1 is in the cut off state
Then VB1=VR1= -1+2=1V
Since IB= 0, current flowing through R2 = current flowing through R1
Vc 2 R 1 2.3V ∗R 1
VB1 = R 1+ R 2 = R 1+ R 2 because VC2=VCE+VRE from this R2=1.3R1
Consider the quasi-stable state(Q1 is on and Q2 off): Vc2=12V because Q2 is off

VB1 = VBEsat + VRE =2.7V
Also IR2 = IB1+IR1
Vcc−VB 1
= IB1 + VB1/R1
R2
(12V-2.7V)/R2 =IB1+ 2.7V/R1

R1=44.5K
Design of C
We have T= 0.69 RC., T=1.5ms
Therefore C=0.02µF
Design of speedup capacitor C1
C1R2=CπR1, where Cπ is base-emitter capacitance of the transistor and it is 12pF
as per data sheet of BC107.
Substituting the values
we get C1=5.5 pF. Use 4.7 PF.
Design of differentiator circuit.
The condition is RdCd<0.0016Tt Where Tt=time period of trigger signal=2ms.
Take Rd= 608k (ten times of the output resistance of the signal generator)to
Avoid the loading of the signal generator by the differentiator.
Then Cd=0.47nf.Use0.01 µF std.


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ELECTRONIC DEVICES AND CIRCUITS LAB

ELECTRONIC DEVICES AND CIRCUITS LAB

Dept. Of ECE, SBCE Page 1

1 VI Characteristics of rectifier and zener diodes

2 RC integrating and differentiating circuits

3 Clipping and clamping circuits

4 Fullwave Rectifier -with and without filter

5 Simple Zener voltage regulator

6 Characteristics of BJT in CE configuration and

9 Feedback amplifiers (current series, voltage series)

10 RC phase shift Oscillator

11 Wien bridge Oscillator

12 Bootstrap sweep circuit

Dept. Of ECE, SBCE Page 2

V-I CHARACTERISTICS OF RECTIFIER AND ZENER

Dept. Of ECE, SBCE Page 3

Dept. Of ECE, SBCE Page 4

For Zener diode

Break down voltage:

Dept. Of ECE, SBCE Page 5

Dept. Of ECE, SBCE Page 6

To assure the safety of the diode, take current =10 mA .

Design for Zener:

Forward Characteristics - Germanium

Reverse Characteristics - Zener

Dept. Of ECE, SBCE Page 7

RC INTEGRATOR AND DIFFERENTIATOR

Dept. Of ECE, SBCE Page 8

Dept. Of ECE, SBCE Page 9

Dept. Of ECE, SBCE Page 10

Dept. Of ECE, SBCE Page 11

Dept. Of ECE, SBCE Page 12

CLIPPING AND CLAMPING CIRCUITS

Dept. Of ECE, SBCE Page 13

Negative Diode Clipping Circuits

Positive clipper clipping at -3V

Negative clipper with clipping level at -3V

Negative clipper clipping at +3V

Dept. Of ECE, SBCE Page 14

In some situation it is necessary to add or subtract a dc voltage to a given

Positive clamper clamping at 0V

Suppose the input voltage is represented by the expression VM sin ωt.

Negative clamper clamping at 0V

Positive clamper clamping at +3V

Positive clamper clamping at-3V

Dept. Of ECE, SBCE Page 15

Negative clamper clamping at +3V

Negative clamper clamping at -3V

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The series resistance used for current limiting R=√ R f × Rr

Typical values of R f = 30 Ω and of Rr = 300k

We get R=√ 30 Ω ×300 k = 3k

FULL WAVE RECTIFIER WITH AND WITHOUT FILTER

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Power supply frequency f= 50 Hz.

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ZENER VOLTAGE REGULATOR