PTPPT

i-1
PrimeTime: Introduction
to Static Timing Analysis
Workshop
Synopsys Customer Education Services

© 2002 Synopsys, Inc. All Rights Reserved
Welcome
Synopsys 34000-000-S16 34000-000-S16
PrimeTime: Introduction to Static Timing Analysis
PrimeTime: Introduction to Static Timing Analysis i-1 Unit i: Welcome

First Things First i-2
Welcome and Introductions
Materials you should have:

Student Guide
Lab Guide
PrimeTime Quick Reference
Synopsys Online Documentation (SOLD) CD
Breaks
Facilities
Welcome
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

Workshop Goal i-3
Use
UsePrimeTime
PrimeTimeto
toperform
performStatic
StaticTiming
TimingAnalysis
Analysis(STA)
(STA)
on
onaa“Functional
“FunctionalCore”
Core”prior
priorto
toPlace
Placeand
andRoute
Route(P&R).
(P&R).
Obtain
Obtainthe
theprerequisite
prerequisiteknowledge
knowledgeto
toattend
attendthe
the
“PrimeTime:
“PrimeTime:Chip
ChipLevel
LevelSTA”
STA”workshop.
workshop.
A/D DSP CODEC
Processor_CORE
MPEG
USB RAM
Functional Core Core Clock

Welcome
Design Assumptions:
1. STA is performed on the Functional core only; Block level STA has been done in DC. (See Flow
Diagram)
2. No scan chains yet (Flow diagram in PT:Chip level STA workshop)
3. Functional Core routing parasitic RCs (detailed SPEF) and sub block WLMs are available from
early design planning (Chip level floor plan)
4. No clock tree synthesis yet (Flow diagram in PT:Chip level STA workshop)
5. Blocks may be either synthesized netlist or QTMs (will be covered if class time permits)
6. Functional Core has Logical hierarchical partitions (blocks)
7. No I/O pads, no BSD, no clock generation logic yet (Definition of Functional Core)
8. Chip specification is available (in Constraints modules)
9. Multiple Synch/Asynch clocks (in Constraints modules)
10. Multicycle paths (in Constraints modules)
11. Hold Time analysis is performed using Worst case PVT (as opposed to Best case PVT) (in
Constraints modules)
12. No case analysis (absence of scan chains); no functional modes (Flow diagram in PT:Chip level
STA workshop -- although it may apply to Functional CORE but is not discussed in this PT: ISTA)

Workshop Target Audience i-4
Design or Verification engineers who perform STA at the

“functional core” level
Little or no formal experience with PrimeTime
Little or no formal experience with Design Compiler
Planning to take the “PrimeTime: Chip level STA” workshop
You are here PrimeTime:

ISTA
PrimeTime:
CHIP Level
CHIP Synthesis
(Design Compiler)
Welcome
Design or Verification engineers who perform STA at the “functional core” level.
In addition to block level STA, you will handle functional core integration.
Little or no formal experience with Design Compiler.

If you have taken “CHIP Synthesis” or have experience using Design Compiler, do not attend this
workshop: Take “PrimeTime: Chip Level STA”
If your expectation is to learn DC as you’re expanding your portfolio to include synthesis, you should
take the CHIP Synthesis workshop next and then PrimeTime: Chip Level STA.
“PT:Chip Level STA Workshop” focuses on final, full chip, post route STA in order to achieve Timing
closure.

What is Functional Core on a CHIP? i-5
TOP
MID
CLOCK-GEN
PLL FUNC_CORE
Synthesized Synthesized
JTAG/BSD
Block1(wlm) Block2
Logic
ASYNCH Synthesized RAM (Timing

LOGIC Block3 model)
Functional CORE constitutes “most” of the CHIP containing:

Synthesized logic blocks (Gate level netlist) and Models (RAMs)
Functional core constraints are derived from Chip-level constraints
Functional core level parasitics are extracted
Extraction is done after a CHIP level floorplan and global routing
Welcome
Parasitics are supplied in SPEF (Standard Parasitic Extraction Format).
At the full-chip level one must consider the following issues:

Model clock generation circuitry
Analyze latch-based versus flip-flop design styles
Functional vs. Test modes (Case analysis)
Analyze PVT corners
These issues are addressed in the “PrimeTime: Chip level STA” workshop.

Functional Core Integration – Pre-Layout i-6
Fully synthesized
Functional Core.
Write Top-Level
Chip-Level floorplan
constraints and
and constraints. Units 4-6 exceptions
Functional core inter-
block RC parasitics Design Compiler
Read required files
extracted. Resynthesis
Unit 3
Errors/
Fix data
yes Warnings?
no
Generate STA Timing

Units 1,8 Reports violations
Place&Route
Welcome
After synthesis of all sub-blocks, perform Chip level floorplan, global routing and extract the parasitic
RCs between blocks within the Functional core.
QTMs (or Timing models) may be used for the blocks for which synthesized gate level netlist is not
available.
Day-1: Objective: Using the basic 5 step STA flow, constrain all the Register to Register (Internal)
timing paths within the functional core
Day-2: Objectives:Using the 5 step STA flow, constrain all the I/O (interface) timing paths within the
functional core and apply the necessary single clock cycle timing exceptions

PT Compatibility with other Tools i-7
Design Compiler Physical Compiler
Mapped netlist Placed netlist

(using WLM)
PrimeTime CHIP Architect
STAMP Parasitics, SDF
PathMill 3rd Party Layout
Welcome

What Will Be Covered i-8
Performing basic 5 step Static Timing Analysis (STA) flow

on a functional core prior to P&R using PrimeTime GUI
and shell (Units 1-3)
Applying required constraints and exceptions and

checking for missing constraints and ignored exceptions
(Units 4-6)
Creating a Quick Timing Model (Unit 7)
Analyzing in detail for timing, design rules and timing

bottlenecks (Unit 8)
Welcome

Workshop Prerequisites i-9
Understanding of digital IC design
Familiarity with UNIX, X-Windows and Unix-based

text editor
Welcome

Agenda: Day One i-10
DAY
1 Unit Register to Register Paths Lab
0i Welcome
1 Introduction to Static Timing Analysis
2 Writing Basic Tcl Constructs in PT
3 Reading Data
4 Constraining Internal Reg-Reg Paths
Welcome
Unit 1 Objective:
Is to introduce Static Timing Analysis in PrimeTime by: Defining the 2 steps performed by a Static
Timing Analyzer; Understanding under the hood calculation of cell and net delays based on NLDM
(Non-Linear Delay Model) and WLM (Wire Load Model); Listing 4 types of timing paths; Identifying
the path with the WNS (worst negative slack) or longest delay using the report_timing command;
Interpreting results of the report_delay_calculation command and for cell and net timing arcs and
Finding specific topics in SOLD using key word search.
Unit 2 Objective:
Is to find Tcl syntax errors using the Tcl Syntax checker, to fix these errors and to obtain command and
variable syntax information.
Unit 3 Objective:
Is to create a basic PT setup file, read all the required files for STA and resolve errors and warnings
associated with reading the files.
Unit 4 Objective:
Is to create a Tcl script, which fully constrains internal Register-to-Register paths by Applying clock
constraints and design environmental attributes; Modeling multiple synchronous/asynchronous clocks,
Modeling pre-layout non ideal clocks, Invoking appropriate report commands to verify the correctness
of constraints and Invoking a report to verify the completeness of constraints.

Agenda: Day Two i-11
DAY Unit I/O Paths and Exceptions Lab

2
5 Constraining I/O Interface Paths
6 Specifying Timing Exceptions
7 Introduction to Timing Models (QTM)
8 Performing STA
9 Summary
10 Customer Support
Welcome
Unit 5 Objective:
Is to create a Tcl script which fully constrains the Input/Output interface paths by applying port constraints and
environmental attributes, modeling I/O data paths between multiple synchronous and asynchronous clock domains,
modeling pre-layout non ideal clock effects, Invoking appropriate report commands to verify the correctness of constraints,
Invoking a report to ensure the completeness of constraints and Identifying the effect of constraints on the path reported by a
timing report.
Unit 6 Objective:
Is to Efficiently constrain a design for non-single-clock cycle behavior by Defining Timing exceptions, Modeling multi cycle
path, Modeling logically false paths, Writing efficient constraints to model the above and Identifying any ignored exceptions
and remove them.
Unit 7 Objective:
Is to Create a Quick Timing model using a given specification for use in PT by Defining what QTM is, Writing a QTM script
to create a QTM library cell for the given specification and Modifying the link_path to use the QTM just created.
Unit 8 Objective:
Is to Apply three techniques in a systematic approach to analyze timing and design rule violations by Listing the 3 techniques
in the appropriate order, Obtaining summary reports of all constraint violations and determining the next course of action,
Identifying timing bottleneck blocks for re-synthesis. Enabling generation of Divide and conquer Timing reports to
investigate what types of timing paths are causing violations (group_path) and Generating timing reports for setup check,
hold check and showing the fanout, capacitance and transition time along the path.
Unit 9 Objective:
Is to list ways to improve the runtime and memory when using the STA flow in PT and summarize the workshop.
Unit 10 Objective:
Is to introduce you to our Customer Support Services.

Test For Understanding i-12
In this class, what are the 2 types of blocks which you assume are
contained within the floor-planned Functional Core?
_____________________
_____________________
In this class, how are the net parasitics (RC values) within
Functional Core modeled prior to Place and Route?
Nets within a block __________________________
Nets between blocks __________________________
After attending this class, you will be able to perform Static Timing Analysis on:
(Circle all that apply)
a. Block (Module) level design that is either a mapped netlist or a timing model
b. Functional CORE level design containing synthesized gate level blocks
c. Functional CORE level design with some blocks described as an RTL
verilog/VHDL file
d. CHIP level design that has been placed and routed (P&R)
Welcome

Abbreviations and Acronyms i-13
Acronym
Acronym Meaning
Meaning Acronym
Acronym Meaning
Meaning
STA
STA PVT
PVT
DC
DC WLM
WLM
PT
PT WNS
WNS
GUI
GUI SPEF
SPEF
Tcl
Tcl DRC
DRC
SOLD
SOLD NLDM
NLDM
QTM
QTM --
Welcome

Appendix i-14
Icons used in this workshop

Conventions used in this workshop
The Synopsys “Physical Synthesis
Hierarchical Design Flow”
Welcome

Icons Used in This Workshop (1/2) i-15
Lab Exercise Group Exercise
Acronyms
Recommendation
For further reference
Welcome

Icons Used in This Workshop (2/2) i-16
Question Remember
Checklist Caution
Hint, Tip or Suggestion Note
Welcome

Conventions Used in this Workshop i-17
Convention Description
Courier Indicates command syntax.
Courier italic Indicates a user-defined value in Synopsys.
Courier bold Indicates user input—text you type verbatim—in Synopsys syntax and
examples. (User input that is not Synopsys syntax, such as a user name
or password you enter in a GUI, is indicated by regular text font bold.)
[ ] Denotes optional parameters, such as pin1 [pin2 ... pinN]
| Indicates a choice among alternatives, such as low | medium | high

(This example indicates that you can enter one of three possible values for
an option: low, medium, or high.)
Control-c Indicates a keyboard combination, such as holding down the Control key
and pressing c.
\ Indicates a continuation of a command line.
/ Indicates levels of directory structure or design’s hierarchy.
Edit > Copy Indicates a path to a menu command, such as opening the Edit menu and
choosing Copy.
Welcome

The Synopsys Physical Synthesis Flow i-18
START
START Objectives
RTLand
RTL and Develop a realizable floorplan for the chip
Chip
Chip and realistic design budgets for blocks
Constraints
Constraints
Design
Planning
Create a placed design which passes STA.
Perform an initial detail route of chip
Design
Implementation
Design
Refinement and ECO the P&R until it meets required
Chip Finishing performance specs for tapeout
END
END
Welcome
RTL (Register Transfer Level)
The Synopsys Physical Synthesis hierarchical design flow was created by the Synopsys Design Flow
Group to help promote and ease the adoption of Synopsys design tools, as well as to provide feedback
and drive enhancements of product performance and usability. The Synopsys Design Flow Group
engages in customer partnerships from RTL to tapeout to drive success for multi-million gate designs.
The flow encourages top-level floorplanning, power planning and global routing early in the flow
followed by successive refinement of data and design until timing closure (i.e. the Design Planning,
Design Implementation, and Design Refinement phases).

An Overview of Design Planning i-19
START
START RTL,
chip constraints
RTL, PP Power
PowerAnalysis
Analysis
RTL,
Chip
Chip VCS RTL
RTLverification
verification
constraints
constraints CoverMeter Obtain
Obtaintarget
targetRTL
RTL
CA Power
PowerPlanning
Planning
and
andtoggle
togglecoverage
coverage
Vera
ILM
CA
Initial
Initial pin
pin
Design compile assignment
MC, compiledatapath
datapath FV assignment
Planning ACS
synthesis
synthesiswith
withscan
scan
Top-level
Top-level ILM
JTAG CA
BSDC JTAGinsertion
insertion global routing and
global routing and
Design congestion
congestionanalysis
analysis
Implementation Die
CA DieInitialization
Initialization CA Top-level
Top-level ILM
IO repeater
repeaterinsertion
CA IOPad
Pad
Assignment
insertion
Design Assignment
FR Top-level
Top-levelroute
route
Refinement estimation
estimation
Floor-planning,
Floor-planning,
and Chip CA
Finishing A hierarchy manipulation
hierarchy manipulation Initial
Initialblock
block
reshaping
reshaping timing
timingbudget
budget
END
END
New in 2.2
Welcome
VCS VCS Verilog Simulator

CA Chip Architect
PP PrimePower
FR Flex Route
BSDC BSD Compiler, Boundary Scan Synthesis
FV Formal Verification (FM Formality)
MC Module Compiler
ACS Automatic Chip Synthesis
ILM Interface Logic Model

An Overview of Design Implementation i-20
A
START Block
BlockLevel Block
START
physical
Level
synthesis BlockLevel
LevelCTS
CTS CTC
physical synthesis
RTL, Low
RTL, LowPower
Power Block
Chip Optimization BlockLevel
Level Detail
Chip PC
Optimization FV Detail
DetailRouting
Routing Router Detail
constraints One
OnePass
PassScan
Scan
constraints Arcadia
Router
Placement
Placement Block
BlockLevel
Level ECO
ECO
RC
RCExtraction
Extraction Route
Route
Design PT ILM
ILM
Generation
Planning PC Generation
PT
Block
BlockLevel
Level
STA
STAand
and
Top
TopLevel
Level ILM ILM
ILMcreation
creation RC- FV
RC-
correlation
Design physical synthesis correlation
physical synthesis Block
Implementation Low
LowPower
Power FV Block
level
levelIPO
IPO
Optimization
Optimization timing OK ?
PC
no
One
OnePass
PassScan
Scan
PC
yes
Placement
Placement ATPG
Chip Finishing Chip
CA ChipIntegration
Integration ILM
and Design
Full Top
TopLevel
LevelCTS
Refinement
PT FullChip
ChipSTA
STA ILM CTS CTC,
Placement
Placementhandoff
handoff STAMP
END
END FV Top
TopLevel
Level
Detail
DetailRoute
Route
Detail
Router
timing OK
no yes
New in 2.2
Welcome
CTS Clock Tree Synthesis

ECO Engineering Change Order
PC Physical Compiler
CTC ClockTree Compiler
ATPG Automatic Test Pattern Generation
IPO In-Place Optimization

An Overview of Design Refinement i-21
Top
TopLevel
Level Blocks/Top
Arcadia
Extraction Blocks/Top
START
START Extraction Arcadia RC
RCExtraction
Extraction
ILM
ILMGeneration
RTL,
RTL, PT Full
FullChip
ChipSTA
STA
PT Generation
Chip Full
FullChip
ChipSTA
Chip ILM PT STA ILM
constraints
constraints
no
yes timing OK
timing OK
yes
Design
Planning
PP Final
FinalPower
Power
Capture
Capture Analysis
Analysis
PT
Block
BlockLevel
Level
Constraints Crosstalk
Crosstalk
Design Constraints PT-SI
Analysis
Analysis
Implementation
Block Crosstalk
Blocklevel Top
Toplevel
ILM Detail Crosstalk
PC level level Repair
IPO,
IPO,hold
holdfix
fix IPO, hold fix
IPO, hold fix
Router Repair
Design PC
GDSII
SLE
GDSIIMerge
Merge
Refinement and
Chip Finishing Block Level
BlockRoute
Level Top
TopLevel
Level DRC
Detail
ECO ECO Calibre DRC
Router ECO Route ECORoute
Route
END Detail
Calibre LVS
LVS
END Router
New in 2.2 SLE Chip

ChipFinishing
Finishing
Welcome
SLE Synopsys Layout Editor

LVS Layout vs. Schematic
DRC Design Rule Checker
GDSII Graphics Design Standard Format II

Agenda: Day One 1-1
DAY
0i Welcome
2 Writing basic Tcl constructs in PT
3 Reading Data
4 Constraining Internal Reg-Reg paths
Introduction to STA
PrimeTime: Introduction to Static Timing Analysis 1-1 Unit 1: Introduction to STA

Unit Objectives 1-2
After completing this unit, you should be able to:

n Define setup and hold time constraint
n Explain how cell and net delays are calculated in PT
n State the two steps performed by a static timing analyzer
n List the 4 types of timing paths and their valid start and
end points
n State what design rules are
Introduction to STA

$1M Qn: Does my Circuit Meet Timing? 1-3
C
B
FF3
D
CLK
What
Whatmust
mustbe
bechecked
checkedto
toverify
verifythe
thedesign
designmet
mettiming?
timing?
Introduction to STA
To verify this design for timing, you need to perform timing verification to ensure that FF3’s setup
and hold time requirements are satisfied.

Timing Verification Is? 1-4
Verification that every flip -flop in the design meets its

setup and hold time requirements.
Setup/Hold
D Q Z
Capture Flip-Flop
CLK FF3
FF3/CLK Setup check Hold check
FF3/D UNKNOWN VALID UNKNOWN
FF3/Q VALID UNKNOWN
Clk2Q
D changes too close to clock edge, Q becomes unknown.

Introduction to STA
In order for a design to function correctly at a specified clock frequency, it must meet both setup and
hold time requirements. Data should not change during the setup and hold time intervals.

Setup Definition 1-5
Verification that data becomes valid and stable for a minimum

time before being captured by flip-flop. (Setup Check)
A D Q
FF1
D Q Z
B D Q FF3
FF2
CLK
FF1/CLK
FF1/D
FF1/Q
FF3/CLK
FF3/D VALID VALID
Setup check
Introduction to STA
To verify a design for timing, setup is checked each time a flip-flop captures data.
Setup check: Data must be stable and valid for a specified amount of time before the capture clock
edge.
FF1.clk captures FF1.D into FF1.Q then propagate through logic cloud “XOR” to have data stable and
valid ready to be captured by FF3. (Setup check)
The scenario described here is referred to as single-cycle behavior, where FF3 captures data from FF1
within a single clock cycle.

Setup Slack Calculation 1-6
EQN 1 Slacksetup = Data Required Time – Data Arrival Time ≥ 0
EQN 2 Tcapture – tFF2setup ≥ Tlaunch + t FF1clk2Q + tM

Clk Spec Library Clk Spec Library Cell + Net
FF1/CLK
FF3/CLK
FF3/D VALID VALID
Data Arrival Time

Data Required Time
Slack
Introduction to STA
To meet setup time, Setup’s slack must be ≥ 0 (EQN 1).

Hold Definition 1-7
Verify that data remains stable for a minimum time as

required by capture flip-flop. (Hold Check)
A D Q
FF1
D Q Z
B D Q FF3
FF2
CLK
FF1/CLK
FF1/D
FF1/Q
FF3/CLK
FF3/D VALID VALID
Hold check
Introduction to STA
To verify a design for timing, hold is checked each time a flip-flop captures a data.
Hold check: Data must remain stable (unchanged) for a specified amount of time after capture clock
edge arrived.
During FF3 captures data from FF3.D into FF3.Q, data on FF3.D must remain stable so that FF3
captures it correctly. (Hold check)
The scenario described here is referred as “single-cycle” behavior where FF3 captures data from FF1
in the same clock cycle.

Hold Slack Calculation 1-8
EQN 1 Slackhold = Data Arrival Time – Data Required Time ≥ 0
EQN 2 Tlaunch + t FF1clk2Q + tM ≥ Tcapture + tFF2hold

Clk Spec Library Cell + Net Clk Spec Library
FF1/CLK
FF3/CLK
FF3/D VALID VALID
Data Arrival Time

Data Required Time
Slack
Does
Doesthe
thehold
holdcheck
checkdepend
dependon
onyour
yourclock
clockperiod?
period?
Introduction to STA
To meet hold time, Hold slack must be ≥ 0 (EQN 1).

One Method of Timing Verification 1-9
SPICE can be used to accurately verify circuit’s timing.
A D Q
FF1
D Q Z
B D Q FF3
FF2
CLK
FF1.clk
FF1.D
FF2.D
FF1.Q
FF2.Q
FF3.clk
FF3.D Valid Valid
Data Arrival Time Hold check

Setup check
What
Whatdesign
designformat
formatis
isrequired
requiredby
bySPICE?
SPICE?
Introduction to STA

Transistor Level Verification using SPICE 1-10
A D Q
FF1 D Q
D Q
Z
B FF3
CLK FF2
How
Howlong
longwould
woulditittake
takeSPICE
SPICEto
torun?
run?
Introduction to STA
It would take a while for SPICE to verify setup and hold checks for this transistor level design (FFs-
XOR-FF). You DON’T want SPICE to verify your multi million gates design.

What is Static Timing Analysis? 1-11
n Static Timing Analysis uses SPICE characterized data

stored in a technology library to verify circuit’s timing
n The traditional method of verifying timing, is to simulate

your circuit using SPICE
1.4
Characteristic Curves
.30
(XOR)
Output Load (pF)

1.2
Cell Delay (ns)

C 1.0
.20
0.8 .10
0.6
.01
0.4
0.2
Delay 0.0
0.0 1.0 2.0
SPICE Characterization Input Transition (ns)
How
Howdo
doyou
youget
getRRnet and C pre-layout?
net and Cnet
net pre-layout?
Introduction to STA
SPICE characterized data is stored in the technology library as a lookup table. Data in the lookup table
represent gate delay as a function of input transition and output load. Timing verification done in STA
includes setup/hold and recovery/removal check.

Estimating Rnet and Cnet Pre-layout 1-12
n Extraction data from already routed designs are used to

build a lookup table known as the wire load model (WLM)
n WLM is based on the statistical estimates of R and C based

on “Net Fanout”
Net Resistance Capacitance

Fanout KΩ pF
1 0.00498 0.00312
0.00498 KΩ
2 0.01295 0.00812 Cpin

0.00312 pF
3 0.02092 0.01312
4 0.02888 0.01811 From Library
Wire Load Model (RC)
Estimated
EstimatedRCs
RCsare
arerepresented
representedas
aswire
wireload
loadmodel
model(WLM)
(WLM)
Introduction to STA
For fanouts greater than those specified in a wire load table, a “slope factor” is specified for linear
extrapolation.
wire_load (“5KGATES”) {
resistance : 0.000271 ----------> R per unit length
capacitance : 0.00017 ----------> C per unit length
slope : 29.4005 ----------> Used for linear extrapolation
fanout_length (1, 18.38) ----------> (fanout = 1, length = 18.38)
fanout_length (2, 47.78)
}
Fanout = 7
Net length = 135.98 + 2 x 29.4005 (slope) = 194.78 ----------> length of net with fanout of 7
Resistance = 194.78 x 0.000271 = 0.05279 units
Capacitance = 194.78 x 0.00017 = 0.03311 units

Cell Delay Calculation 1-13
Cell Delay = f (Input Transition Time, Output Load)
n Cell delays are calculated from a Non Linear Delay Model

(NLDM) table in the technology library
n Tables are indexed by input transition and total output
load for each gate
Output Load (pF)
0.5 ns .005 .05 .10 .15
Input Trans (ns)

0.005 pF 0.0 .1 .15 .2 .25
0.045 pF
Cell Delay = .23 ns 0.5 .15 . 23 .3 .38
From Library
1.0 .25 .4 .55 .75
From Wire Load Model
Cell Delay (ns)
Introduction to STA
Cell delay is calculated using NLDM before and after layout, but the values before and after layout
may differ. This is due to differences in input transition time and/or output load value before and after
layout.
The nonlinear delay model stores vendor-specific delay information inside the technology library in
the form of lookup tables.
The delay is a function of the input transition time of the cell (TInput) [also called slew], the driving
strength of the cell (RCell), the wire capacitance (CNet) and the pin capacitance of the receivers (CPin).
A slow input transition time will slow the rate at which the two transistors can change state (from
“on” to “off”). So will a large output load.
Input transition time = input slew rate.
Output load = Cnet + Cpin.

Output Transition Calculation 1-14
Output Transition = f (Input Transition Time, Output Load)

n There is another NLDM table in the library to calculate
output transition
n Output transition of a cell becomes the input
transition of the next cell down the chain
Output Load (pF)

Output Trans = 0.30 ns
0.5 ns .005 . 05 .10 .15
Input Trans (ns)

0.005 pF 0.00 0.10 0.20 0.37 0.60
0.045 pF
0.50 0.18 0.30 0.49 0.80

From Library
1.00 0.25 0.40 0.62 1.00
From Wire Load Model
Output Transition (ns)
Introduction to STA
Output transition of a cell becomes input transition time for the next cell.

Net Delay Calculation 1-15
n Net delay is the “time-of-flight” due to the net’s RC
n Net’s RC is obtained from wire load model for pre-layout design
Net delay
Cpin
Rnet Cnet
Net Delay = f (Rnet, Cnet + Cpin)
Post-layout:
Post-layout:Known
KnownRs
Rsand
andCs
Csare
areextracted
extractedinto
intoparasitics
parasiticsfile.
file.
Introduction to STA
Net delay is calculated using Rs and Cs.

There are several factors which affect net parasitics:
Net Length
Net cross-sectional area
Resistively of material used for metal layers (Aluminum vs. copper)
Number of vias traversed by the net
Proximity to other nets (crosstalk)
more….
Post-layout design is annotated with RCs extracted from layout for better accuracy. Annotated RCs
override information from WLM.

Test For Understanding 1-16
What is used as index to calculate R and C from a WLM?

l Length
l Fanout
l Cell location
l Weather report
In a Non-Linear Delay Model (NLDM), cell delay is a function

of:
a) _________________ and
b) _________________
Using the 300KGATES WLM provided in the notes below,

estimate R and C for this circuit.
a) R: _________________
b) C: _________________
Cpin
Introduction to STA
wire_load (“300KGATES”) {
resistance : 0.00025
capacitance : 0.00015
slope : 29.4005
fanout_length (1, 30)
}

Summary: STA Delay Calculation 1-17
Factors affecting STA delay calculations:
n Cell delay based on NLDM

n Net delay using RC estimation from WLM
Output Load (pF)

Net Resistance Capacitance
Fanout KΩ pF
.005 .05 .10 .15
1 0.00498 0.00312
Input Trans (ns)
0.0 .1 .15 .2 .25

2 0.01295 0.00812
0.5 .15 . 23 .3 .38
3 0.02092 0.01312
1.0 .25 .4 .55 .75 4 0.02888 0.01811
Cell Delay (ns) Net RC
Introduction to STA

Two Steps in Static Timing Analysis 1-18
Path 1 Path 2
A D Q Z
CLK
Path 3
Two main steps in Static Timing Analysis:
n The delay of each path is calculated (Data Arrival Time)
n All path delays are checked to see if setup and hold

(timing constraints) have been met (Slack >= 0)
Introduction to STA

Timing Paths 1-19
MY_DESIGN
A D Q D Q Y
FF1 FF2
QB QB
CLK
B Z
Each timing path has a startpoint and an endpoint:
n Startpoints:
l Input ports
Draw
Drawall
allthe
thetiming
timing
l Clock pins of Flip-Flops or registers
paths
pathscontained
containedin in
n Endpoints: MY_DESIGN.
MY_DESIGN.
l Output ports
l Data input pins of sequential devices
Introduction to STA

Net and Cell Timing Arcs 1-20
The actual path delay (Data Arrival Time) is the sum

of net and cell delays along the timing path.
Net Arc
Cell Arc
Introduction to STA
A timing arc is a delay from the beginning to the end of a net or from the input pin of a cell in the
library, to a corresponding output pin. For the combinational gates in the circuit above (AND gates,
OR gates, etc), a timing arc is simply from one input pin to the output pin.
Note that for sequential cells (such as flip-flops), the timing arc is specified only from the clock input
pin to the output. This is because a change in the output can only be caused by a change in the clock
pin for a simple flip-flop.

STA Setup and Hold Checks 1-21
Using defined timing constraints, STA

Define Launch
performs setup and hold checks on and Capture
Clocks
every timing path in the entire design.
D Q Per Timing Path, Calculate

A
Data Arrival Time Using
FF1 D Q Clocklaunch, NLDM, WLM
Z
B D Q
FF3
CLK Calculate Data Required
FF2 Time Using Clockcapture,
NLDM
FF1/CLK
FF1/D
FF2/D
FF1/Q
FF2/Q Slacksetup and
FF3/CLK Slackhold
FF3/D
Positive?
Valid Valid
Data Arrival Time Hold check
Setup check
Introduction to STA
To meet setup time, Setup’s slack must be >= 0 (Recall setup definition)

Other Design Checks 1-22
n Capacitance:
l Maximum allowed node capacitance (max_capacitance)
l Minimum allowed node capacitance (min_capacitance)
n Transition:
l Maximum allowed signal transition (max_transition)
l Minimum allowed signal transition (min_transition)
n Fanout:
l Maximum allowed fanout load (max_fanout)
l Minimum allowed fanout load (min_fanout)
These design rule checks are specified by your vendor.
Introduction to STA

Two main steps in Static Timing Analysis are:

l ________________________________________________
l ________________________________________________
What is more probable to fail (setup or hold) at the

following temperatures?
l 125 °C : _____________
l -40 °C : _____________
Are the following equations correct/incorrect to

meet setup and hold requirements respectively?
l Path Delay <= Clock period – Setup time
l Path Delay >= Hold Time
Introduction to STA

Lab Overview 1-24
LAB
n Search information using SOLD
n Explain GUI features
60 min n Invoke PrimeTime, and execute Pre-written script

files to perform the static timing flow:
l READ, CONSTRAIN, CHECK and ANALYZE
n Use “report_timing -input pins” to create timing

report and interpret the report
n Use “report_delay_calculation” on cell and net to

see how cell and net delays are calculated
Introduction to STA
Use the Lab Guide for detailed instructions.

Use the Instructor provided login information.

Agenda: Day One 2-1
DAY
0i Welcome
3 Reading Data
Writing Basic Tcl Constructs in PT

PrimeTime: Introduction to Static Timing Analysis 2-1 Unit 2: Writing Basic Tcl Constructs in PT
Unit Objectives 2-2
Use PT-Tcl variables
Embed PT-Tcl commands
Describe basic control structures
Define a simple Tcl procedure
Describe how to use the Tcl Syntax Checker

What is PT Tcl? 2-3
Tcl = Tool Command Language (tickle):

PT-Tcl is the command interface to PrimeTime
Built on the “open” industry-standard shell

programming language Tcl
PT-Tcl an interpreted, fully programmable and fully

scriptable language

Tcl was originally developed by John K. Ousterhout at UCA Berkeley.

There are many books on the topic of Tcl programming, here a few:
Tcl and the Tk Toolkit, John K. Ousterhout
Practical Programming in Tcl and Tk, Brent B. Welch
Visual Tcl, David Young
Running PT Tcl Commands 2-4
Commands can be typed interactively in PT Tcl:
pt_shell>
pt_shell> echo
echo "Running
"Running my.tcl..."
my.tcl..."
pt_shell>
pt_shell> source
source my.tcl
my.tcl
Or executed in batch mode
UNIX%
UNIX% pt_shell
pt_shell -f
-f my.tcl
my.tcl || tee
tee my.log
my.log

Tcl Basics 2-5
Commands:
One or more words separated by white space
First word is command name, others are arguments
Returns string result
Script:
Sequence of commands
Commands separated by newlines and/or semi-colons
Examples:
set a 22 set the variable ‘a’ to 22
echo "Hello, World!" world’s shortest program

Arguments 2-6
Parser assigns no meaning to arguments:

C: x = 4; y = x+10 y is 14
Tcl: set x 4; set y x+10 y is "x+10"
Different commands assign different meanings to their

arguments
“Type-checking” must be done by commands themselves
set
set aa 122
122
expr 24/3.2
expr 24/3.2
read_file
read_file –format
–format verilog
verilog foo.v
foo.v
string
string length
length Abracadabra
Abracadabra

“Type-checking” means that the command itself, not the “Tcl Parser”, has to figure out whether the
arguments passed to it are of the correct type, e.g. the expr function would make sure it is receiving
numbers and arithmetic operators.
set a 122
Assigns the string “122” to the variable named “a”
expr 24/3.2
The Tcl parser calls the expr function with the “string” “24/3.2”. The command expr
(mathematical expression calculator) interprets/type-checks “24/3.2”, calculates and returns the result,
in this case the string “7.5”. The result is a “floating point” number because one of the arguments was
a floating point as well. Division of two “integers” yields an integer result,
e.g. [expr 10/3] would return 3, not 3.333!
read_file –format verilog foo.v
This is a DC/PT-command that reads the verilog file foo.v. The Tcl parser just passes the arguments to
the command “read_file” without interpreting the arguments.
string length Abracadabra
The string function can perform many operations on strings. In this example the function will
return the length (again as a string), here “11”.
Variable Substitution 2-7
Syntax: $varName:
Variable name is:
letters
digits
underscores *
May occur anywhere in a word
Sample
Samplecommand
command Result
Result
set
set bb 66
66 66
66
set a
set a bb bb
set
set aa $b
$b 66
66
set
set aa $b+$b+$b
$b+$b+$b 66+66+66
66+66+66
set
set aa $b.3
$b.3 66.3
66.3
set a $b4
set a $b4 no
no such
such variable
variable
Variables do not need to be declared:

All are type “string” and of arbitrary length
* Actually, Variables in Tcl can have any shape and form, e.g.:
set {*&#2$3rdt} 333
333
puts ${*&#2$3rdt}
333
Using a combination of letters, digits and underscores is recommended; this will make variable
substitution a lot easier.
To remove a variable, use the command unset e.g.:
unset b
Variables can be concatenated with strings in many ways, e.g. to get the contents of the variable b
concatenated with the string “test”, you type:
set a ${b}test -> “66test”
Variables do not need declaration as in languages like C, Pascal, etc., since there is only one “type” of
variable – a string.
Command Substitution 2-8
Syntax: [script]:
Evaluate script, substitute result
May occur anywhere in a word
Sample
Samplecommand
command Result
Result
set
set bb 88 88
set
set aa [expr
[expr $b+2]
$b+2] 10
10
set
set a "b-3 is [expr
a "b-3 is [expr $b-3]"
$b-3]" b-3
b-3 is
is 55

“expr” is a Tcl function that performs math operations.
Controlling Word Structure 2-9
Words end or break at white space and semi-colons, except:
Double-quotes prevent breaks:

set a "x is $x; y is $y"
Curly braces prevent breaks and substitutions:

set a {[expr $b*$c]}
Backslashes quote special characters:

set a word\ with\ \$\ and\ space
Backslashes can escape newline (line-continuation):

report_constraint \
-all_violators

set a “x is $x; y is $y”

Sets the variable a to “x is 3; y is 5”
set a {[expr $b*$c]}

Sets the variable a to “[expr $b*$c]”
set a word\ with\ \$\ and\ space

Sets the variable a to “word with $ and space.”
report_constraint \
all_violators
Make sure that there is no space after the backslash.
“Line-continuation” means “backslash – newline.”
Notes on Substitution and Parsing 2-10
Tcl substitution rules are simple and absolute.
Example comments:
set
set aa 22;
22; set
set bb 33
33 OK
OK
## this
this is a comment
is a comment OK
OK
set
set aa 22
22 ## same
same thing?
thing? Wrong!
Wrong!
set a 22 ;# same thing
set a 22 ;# same thing OK
OK
Parser looks at a command just once!

set
set aa 77
set
set bb aa
echo
echo $b
$b aa
echo
echo $$b
$$b $a
$a
expr
expr $$b+5
$$b+5 12
12
echo $$b
This command returns “$a”. The Tcl parser looks at the command only once, it substitutes $b by its
contents “a”
expr $$b+5
Here, the Tcl parser does the first substitution, replacing $b with “a”. The expr command performs a
second round of substitution, replacing $a with its contents “7”
Tcl Lists 2-11
Data can be arranged as lists

Example: set colors {red green blue}
Lists are accessed through special commands
Example:
llength
llength $colors
$colors
33
lappend
lappend colors
colors white
white yellow
yellow
red
red green blue white yellow
green blue white yellow
set
set colors
colors [lsort
[lsort $colors]
$colors]
blue
blue green red white yellow
green red white yellow

Other list manipulation commands include:

lindex list index Returns value of element at index in list
linsert list index element [element…] Returns new list formed by inserting given new
elements at index in list
lrange list first last Returns new list from slice of list at indices first
through last inclusive
lsearch list pattern Returns index of first element in list that matches
pattern (-1 for no match)
join list [joinString] Returns string created by joining all elements of list
with joinString
split string [splitChars] Returns a list formed by splitting string at each
character in splitChars
Note: List indices start at 0 and the word end may be used to reference the last element in the list. To
echo the first and last element of a list you would use:
echo “First: [lindex $colors 0], Last: [lindex $colors end]”
Control Flow 2-12
There are many commands to control the flow of a Tcl script.
Example:
if
if [file
[file exists
exists postlayout_design.db]
postlayout_design.db] {{
read_db
read_db postlayout_design.db
postlayout_design.db
}} elseif
elseif [file exists
[file exists prelayout_design.db]
prelayout_design.db] {{
read_db prelayout_design.db
read_db prelayout_design.db
}} else
else {{
echo
echo "Could
"Could not
not read
read design!"
design!"
}}

Other file command options are:

executable returns a 1 if file is executable by current user
exists returns a 1 if file name exists
extension returns characters after and including the last dot
isdirectory returns a 1 if file name is a directory
isfile returns a 1 if file name is a file
mtime returns time the file was last modified
owned returns a 1 if file name is owned by the current user
readable returns a 1 if the file name is readable
size returns the size of file name
type returns a string giving the type of the file name
writable returns 1 if file name is writable
For a complete description of the options see the man page of file.
Looping Constructs 2-13
A foreach loop iterates through members of a list:
set
set aa "red
"red green
green blue"
blue"
foreach
foreach color
color $a
$a {{
set
set ss "$color
"$color is
is aa nice
nice color..."
color..."
echo $s
echo $s
}}
Other looping commands:

for
while

for {set i 1} {$i <= 10} {incr i} {

echo “$i potato”
}
The following example reverses a list:

set a "red green blue"
set b ""
set i [expr [llength $a] – 1]
while {$i >= 0} {
lappend b [lindex $a $i]
incr i –1
}
Procedures 2-14
proc command defines a procedure:

proc sub1 {x} {expr $x-1}
name body
list of argument names
Procedures behave just like built-in commands:

sub1 3 2
Arguments can have default values:

proc decr {x {y 1}} {
expr $x-$y
}

In a procedure, the last command’s return value is the procedure’s return value as well. For more
control over what is returned, use “return” and have a look at the example below.
As stated earlier, brackets {} can be used to control word structure. This means that if the procedure
body is multiple lines, the opening bracket still needs to be on the first line, since the command proc
requires 3 arguments.
A procedure can also have a variable number of arguments.
Here is an example procedure:
proc add args { the argument name “args” is FIXED – you cannot use a different name!
set result 0
foreach value $args {
incr result $value
}
return $result
}
Now the procedure can be called in these ways:

add 1 2 3 4 10
add 7 8 15
Procedures and Scope 2-15
Scoping: local and global variables:

Interpreter knows variables by their name and scope
Each procedure introduces a new scope
global procedure makes a global variable local:
> set x 10
> proc DELTAX {d} {
set x [expr $x-$d]
}
> DELTAX 1 can't read "x": no such variable
> proc DELTAX {d} {
global x
set x [expr $x-$d]
}
> DELTAX 1 9

You can use the command info to get information on procedures created in PT memory.
pt_shell> info procs; # Returns all procedures defined in current session.
(By using UPPERCASE letters for the procedure names, it is easier to locate the procedure name
as returned by “info procs”).
pt_shell> info args DELTAX

d
pt_shell> info body DELTAX
global x
set x [expr $x-$d]
Recommendations 2-16
Use procedures to simplify scripts

Prefer UPPER case letters for procedure
names and user defined variable names
Avoid using aliases and abbreviating
sy s command names in scripts
op
S yn e nds Use common extensions:
comm my_script.pt or foo.tcl
R e
Use full option names in commands:
create_clock –period 5 clk
Avoid “snake scripts”

Perform syntax checking

“Snake scripts” are scripts that call scripts that call scripts: Very hard to debug.
Avoid sourcing scripts from your .synopsys_pt.setup file, since these scripts will be executed
automatically every time you start the tool. This of course excludes scripts that only define procedures
for later use.
Syntax Checking 2-17
Check your script in PrimeTime
pt_shell> package require snpsTclPro

1.0
pt_shell> check_script my_script.tcl
Synopsys Tcl Syntax Checker - Version 1.0
Loading snps_tcl.pcx...
Loading primetime.pcx...
scanning: /home/.../my_script.tcl
checking: /home/.../my_script.tcl
my_script.tcl:6 (warnUndefProc) undefined procedure: set_ouput_delay
set_ouput_delay 4 -clock clk [all_outputs]

The Syntax checker has some limitations:

• Cannot check abbreviated command names
• Cannot understand aliased command name
• Does not use PT's search_path variable to find a script file
Need Help? 2-18
Help on PT Tcl Commands:
help
help create*
create*
help
help –verbose
–verbose create_clock
create_clock
create_clock
create_clock –help
–help
man
man create_clock
create_clock
Help on PT variables:
printvar
printvar *_path
*_path
echo
echo $link_path
$link_path
man
man link_path
link_path

Lab Overview and Review 2-19
During this lab, you will:

LAB
Use the “transcript” program to translate a
given specification (in DC shell format) into
PT Tcl format
45 min
Write a Tcl procedure to convert a given
frequency (in MHz) into a clock period (in ns)
Use the Syntax checker to debug your Tcl
script
Find any reusable information from the
command log file

Review 2-20
The command needed to display the value of all “*_path”

variables is?
a) help *_path
b) help –verbose *_path
c) printvar *_path
d) echo $*_path
e) C and D
The result of the command “echo 25 divided by 3 is [expr

{25/3}]” is?
a) 25 divided by 3 is 8.333
b) 25 divided by 3 is 8
c) 25 divided by 3 is 25/3
d) 25 divided by 3 is [expr 25/3]
Is the following Tcl statement for PrimeTime correct?

lappend link_path “CORE.db RAMS.db”
Agenda: Day One 3-1
DAY
0i Welcome
3 Reading Data
4 Constraining Internal Reg-Reg paths
Reading Data
PrimeTime: Introduction to Static Timing Analysis 3-1 Unit 3: Reading Data

Unit Objectives 3-2

n Use a 3 step flow to read design(s) into PT memory
n Resolve errors and warnings associated with reading
and linking a design
n Access design objects after a design has been read
into PT memory
Reading Data

The Inputs and Outputs of PrimeTime 3-3
Gate-Level Exceptions
Constraints
Netlist
read_db source
Setup read_verilog source Technology
File read_vhdl Libraries
Loaded at linking
Read at PT
invocation
PrimeTime
Constraint
Reports Script
Log
File Reading Data
The PrimeTime setup file is .synopsys_pt.setup.

Constraints and Exceptions are usually placed in “script(s)”.

Five Step Static Timing Analysis Flow 3-4
READ
READ
CONSTRAIN
CONSTRAIN
EXCEPTIONS
EXCEPTIONS
CHECK
CHECK
ANALYZE
ANALYZE
Our Focus
Reading Data

PRIMETIME Interfaces 3-5
Two ways to interface to PrimeTime (PT)

primetime
PT GUI
Command line shell
PRIMETIME
(PT)
Engine
pt_shell
Reading Data
Primetime only accepts Tcl mode.

Three Steps to Read Your Data into PT 3-6
Three steps to read in the required design(s):

n Set Variables:
l search_path
l link_path
n Read Design
n Resolve References (Link design)
Reading Data

1: Set the search_path Variable 3-7
Synonymous with UNIX path variable
ProjectX/
db/ vlog/ Tom/ scripts/

tech_lib.db blockA.db top.v top.pt
uart.db
projectX.log blockB.db blockD.v proc1.pt
blockC.db blockE.v proc2.pt
set search_path ”$search_path db vlog scripts”
printvar search_path
Reading Data
What is a search_path?
search_path contains a list of paths used to locate the designs, libraries and other files needed to
perform STA.
search_path variable usually includes paths to:

Design Database(s)
Timing Model(s)
Technology Library
Constraint files
These two commands have the same effect:

set search_path “$search_path db vlog scripts”.
# lappend search_path “db vlog scripts”
lappend search_path db vlog scripts
The default value of search_path is empty string “”.

1: Set the link_path variable 3-8
n The Link Path specifies where PT searches for designs and

library files when linking the design:
set link_path {* tech_lib.db rams.db}
Link PT Memory Technology Custom IP

= + + +
Path “*” Library Conditions Cores
n During linking, PT will search (in sequence) the:

l PT Memory (*)
l Library file tech_lib.db
l IP core rams.db
printvar link_path
Reading Data
link_library = link_path.
Design Compiler uses link_library, PrimeTime uses link_path.
These two commands are equivalent:

set link_path {* core_slow.db rams.db}
lappend link_path core_slow.db rams.db

2: Manually Read Design(s) into PT 3-9
top
U33
blockA
U4
U21
INV blockB
pt_shell> read_db top.db

pt_shell> read_db blockA.db
pt_shell> read_db blockB.db
OR
pt_shell> read_db “blockA.db blockB.db top.db”
What is the current_design in each case?

Reading Data
The last design read is the current design by default. You can make another design current with the
current_design command.
In the above example of 2 cases, the current designs are blockB and top respectively.

2: Read Sub Designs Automatically 3-10
ProjectX/

uart.db
pt_shell> read_verilog top.v

pt_shell> link_design TOP
What should the search_path be?
Reading Data
Top.v is in the vlog directory, search_path should have this directory.

Designs blockA.db AND blockB.db are in the DB directory; search_path should also have this
directory.
set search_path “./vlog ./db”

2: Read Designs in Different Formats 3-11
top
U33
blockA
U4
U21
INV blockB

pt_shell> read_vhd blockB.vhd
Can you mix netlist formats?

How does it work?
Reading Data

Example 1: Read Problem 3-12

set link_path “* tech_lib.db”
ProjectX/

uart.db
pt_shell> read_db uart.db Error !

Error: Cannot read file ‘uart.db’
Error: Problem in read_db: No designs were read.
How would you fix this read problem?

Reading Data

Example 2: Read Problem 3-13

ProjectX/

uart.db
pt_shell> pwd
/…../ISTA/ProjectX
pt_shell> cd scripts
Error !
Error: Cannot read file ‘blockA.db’
How would you fix this read problem?

Reading Data

3: What is Resolving References? 3-14
U33 RISC_CORE
What is INV?
Where is BLOCKB?
BLOCKA
U4
U21
INV BLOCKB
How will PrimeTime know what each instance in

RISC_CORE design netlist refers to?
Reading Data
Resolving references (aka link) means finding and replacing the space holders with the actual library
cells or sub designs referenced.

3: Link the Design to Resolve References 3-15
The link_design command:
n Resolves all references in a design using the link_path variable:

l If it fails, it will use the search_path variable to resolve references
n Reads the technology library if not already read in
What are blockA,

blockB, and INV? top
U33
blockA
U4
U21
INV blockB
Reading Data
link = link_design.
Design Compiler (DC) uses link while PrimeTime (PT) uses link_design command to link a
design.
For convenience, PT has built-in alias link for link_design.
Q: What happens if you accidentally try to link the same design that has been previously linked?
A: If you originally used “-remove_sub_designs” then, black boxes will be resulted since sub
design references could not be found in the memory (*).
Solution: - Use the link -incr option (OR)
- Remove the (corrupted) design in memory and start over from read again
(Recommended).

Example: Linking a Design 3-16

ProjectX/

uart.db
top pt_shell> read_db “blockA.db blockB.db”

U33
blockA
pt_shell> current_design top
U21 U4
pt_shell> link_design
INV blockB
Where are the references found during linking?

Reading Data
PT found blockA.db and blockB.db in its memory and INV in the library.
After linking, if current_design is set to a different design, all the previously established link
information will be gone.
PT automatically reads in Library file(s) when link_design is executed.

Example: Link Warning 3-17
pt_shell> read_db CLOCK_GEN.db
pt_shell> link
Linking
Linking design
design CLOCK_GEN...
CLOCK_GEN...
Warning:
Warning: Unable
Unable to
to resolve
resolve reference
reference to
to 'MUX21L'
'MUX21L' inin 'CLOCK_GEN'.
'CLOCK_GEN'. (LNK-005)
(LNK-005)
Warning:
Warning: Unable to resolve reference to 'IVI' in 'CLOCK_GEN'. (LNK-005)
Unable to resolve reference to 'IVI' in 'CLOCK_GEN'. (LNK-005)
Warning:
Warning: Unable
Unable to
to resolve
resolve reference
reference to
to 'FD2'
'FD2' in
in 'CLOCK_GEN'.
'CLOCK_GEN'. (LNK-005)
(LNK-005)
Creating black box for U31/MUX21L...
Creating black box for U31/MUX21L...
Creating
Creating black
black box
box for
for U32/MUX21L...
U32/MUX21L...
Creating
Creating black box for U34/IVI...
black box for U34/IVI...
Creating
Creating black
black box
box for
for U35/IVI...
U35/IVI...
Creating
Creating black
black box
box for
for CLK_BY_2_reg/FD2...
CLK_BY_2_reg/FD2...
Designs
Designs used
used to
to link
link CLOCK_GEN:
CLOCK_GEN:
<None>
<None>
Libraries
Libraries used
used to
to link
link CLOCK_GEN:
CLOCK_GEN:
<None>
<None> WHAT!
Design
Design 'CLOCK_GEN'
'CLOCK_GEN' was
was successfully
successfully linked.
linked.
11
Verify link_path and search_path
Reading Data
Primetime create black boxes for unresolved references.

This is because the link_create_black_boxes variable is set to true by default.

Black Boxes with link_design 3-18
If link_design could not resolve a particular reference,

PT will create black boxes
A black box is an empty cell with no timing arcs
n The variable link_create_black_boxes is true by default:

l Substitute unresolved references with black boxes
l Design is linked and timing analysis can be performed
n Set the variable link_create_black_boxes to false:

l Unresolved references, cause a design to remain unlinked
l Most timing analysis commands will not function
l Fix any problems and re-link the design
What command would you use to set this variable to false?

Reading Data
set link_create_black_boxes false

Name three design netlist formats that PrimeTime

accept?
l ___
l ___
l ___
Linking a design involves the use of:

a) _________________ and b) _________________ variables
What is the purpose of linking a design?

____________________________________________
What does “*” in the link_path mean?

____________________________________________
Reading Data

Do You need to Set Variables Every Time? 3-20
Can you have search_path and link_path variables
set automatically when you invoke PT?
Reading Data

Create a .synopsys_pt.setup File 3-21

set sh_enable_page_mode true

set sh_command_log_file projectX.log
alias h history
alias rc “report_constraint -all_violators”
history keep 200
Within the setup file, you can:

n Create commands you want to execute every time PrimeTime is
invoked, i.e. “set search_path or set link_path”
n Define aliases for interactive use
n Change log file name from its default pt_shell_command.log

Reading Data
history keep 200 specifies:

the number of commands (200) to be retained in the history list. By default, only 20 commands are
retained.
You can control the naming of the Log file (default: pt_shell_command.log) via the variable:
sh_command_log_file, but, it should appear inside the setup file (.synopsys_pt.setup)
Example: set sh_command_log_file ./projectX.log.
Do not source any script file in the setup file since it will increase invocation time and will make
debugging difficult.

PrimeTime Setup Files 3-22
2
User’s General
Setup
~user $SYNOPSYS/admin/setup
~/.synopsys_pt.setup .synopsys_pt.setup
1
3
Standard
User’s Specific Setup
Project Setup
Project_Directory
./.synopsys_pt.setup
Reading Data
PrimeTime will read the .synopsys_pt.setup files from three directories (in the following order):
1. The “primetime root” directory, which contains the PrimeTime files. For example, if PrimeTime
was installed under /tools/synopsys/PT, standard installation would include a setup file under
/tools/synopsys/PT/admin/setup.
2. Once the “standard” setup file has been read in and executed, PrimeTime then searches for a setup
file in the user’s login directory. If a setup file exists in this directory, it will be read in and
executed.
-- Warning: During project archiving (using tar -cvf) you need to think about it!
3. Last, PrimeTime will read in and execute the .synopsys_pt.setup file from the directory under
which it was invoked.
-- It makes life easier if this project specific setup file contains everything including the contents of
your home directory setup file, if you have one -- recall the Warning above.

Read/Link Problem Debug Check List 3-23
n Is PT invoked in the correct directory? Correct setup file?
n Is the design fully mapped to gate level instances?

l No high level HDL constructs (such as if, case,...)
n Are search_path and link_path variables set correctly?

l printvar *_path
n Are Black Boxes created for unresolved references?

l set link_create_black_boxes false
n Check Libraries in Memory & Library used:

l list_libraries
l list_libraries -used
There can be only one linked design in PT memory
Reading Data
Q: What happens if you accidentally try to link the same design that has been previously linked?
A: If you originally used “-remove_sub_designs” , the result will be black boxes since sub design
references could not be found in the memory (*).
Solution: - Use the link -incr option (OR)
- Remove the (corrupted) design in memory and start over from read again (Recommended).

How does PT Store My Design Netlist? 3-24
Vocabulary of Design Objects
Design Cell Net
TOP
U1 U4
Port A U2
A AIN BUS0 INV0 OUT[1:0]
B Q0 INV D0 Q[1:0]
B BIN
C C U3
CIN BUS1
INV
INV1 D1 Pin
D D
Q1
DIN
Clock CLK
ENCODER
CLK REGFILE
CLK
Reference and Design

Reading Data
Here are some commands to access your design stored in PT memory:

get_cells # Create a collection of cells
get_clocks # Create a collection of clocks
get_nets # Create a collection of nets
get_pins # Create a collection of pins
...
all_clocks # Create a collection of all clocks in design
all_inputs # Create a collection of all input ports in design
all_outputs # Create a collection of all output ports in design
all_registers # Create a collection of register cells or pins
…..

What Information Is Found in the Library? 3-25
n Units for time, capacitance, resistance
n List of library cells
n Cell Timing (propagation delay, setup, hold ...)
n Operating conditions
n Wire load model
n Design rules (max_capacitance, max_fanout ...)
list_libraries
report_lib LIB_NAME
Reading Data
pt_shell> list_libraries
Library Registry:
* ssc_core_slow …./core_slow.db::ssc_core_slow
pt_shell> report_lib ssc_core_slow
****************************************
Report : library
Library: ssc_core_slow
Version: 2002.03
****************************************
Time Unit : 1 ns
Capacitance Unit : 1 pF
Usually, library file is read in during link_design. You can also explicitly read in a library file using
the read_db command:
Example: read_db ssc_core_slow.db
To remove all the designs and libraries from the memory:

remove_design –all
remove_lib –all
NOTE: PT cannot remove a library if it is used by a design residing in memory.

Lab Overview 3-26
n Given a set of design and library files, you will

LAB need to successfully read them into PrimeTime
memory and access the design objects
n You will set the search_path and link_path

variables correctly such that you can read:
45 min l A Top level Verilog/VHDL netlist and link using
Verilog/VHDL sub blocks and the library
l A top level Verilog/VHDL netlist and link using DB sub
blocks and the library
l A complete netlist in VHDL/Verilog/DB and library, link
efficiently and access sevaral objects within the design
Reading Data

Review 3-27
Write 3 variable names that are used to read and link a

design in PT:
________________________________________________
________________________________________________
________________________________________________
Write 3 command names that are used to read and link a

design in Verilog format into PT:
________________________________________________
________________________________________________
________________________________________________
Reading Data

Agenda: Day One 4-1
DAY
0i Welcome
3 Reading Data
Constraining Internal Reg-Reg Paths

PrimeTime: Introduction to Static Timing Analysis 4-1 Unit 4: Constraining Internal Reg-Reg Paths
Unit Objectives 4-2
Create a TCL script which fully constrains internal

register-to-register paths for timing and environment
Correlate the applied constraints from timing reports
Model Pre layout non ideal clocks
Constrain multiple synchronous clocks

Gate-Level
Constraints Exceptions
Netlist
Technology
Setup
Libraries
File
Timing
SDF PrimeTime Models in
.db format
Log,
Reports Script
Files
Our Focus
READ
READ
CONSTRAIN
CONSTRAIN
EXCEPTIONS
EXCEPTIONS
CHECK
CHECK
ANALYZE
ANALYZE
Our Focus
Timing Goals: Synchronous Designs 4-5
Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
Clock
Clock Clk u1 u4
source
source
Source latency Network latency
Synchronous Designs:
Data arrives from a clocked device
Data goes to a clocked device
Objective:
Define the timing constraints for all paths within a design:
All input paths
The internal (register to register) paths
All output paths

In this unit you will focus on the register-to-register paths (reg-to-reg). The discussion will cover input
logic paths and output paths in the following unit.
Reg-Reg Paths 4-6
Assuming ideal clock
Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
Clk
u1 u4
What is the max

Clku1 allowable delay for
Du4 reg-reg path?
Clku4
Setup time = 0.21
0 0.72 9.79 10
Data arrival time Required time

Report: Reg-Reg Paths w/ Ideal Clock 4-7
create_clock -period 10 [get_ports CLK]
Point Incr Path

---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00 Data Launch
u1/CLK (fdef1a15) 0.00 0.00 r
u1/Q (fdef1a15) 0.50 0.50 r
u2/Y (buf1a27) 0.11 0.61 r
u3/Y (buf1a27) 0.11 0.72 r
u4/D (fdef1a15) 0.00 0.72 r
data arrival time 0.72 Data arrival time
clock Clk (rise edge) 10.00 10.00 Period = 10

clock network delay (ideal) 0.00 10.00
u4/CLK (fdef1a15) 10.00 r
library setup time -0.21 9.79
data required time 9.79 Data Required Time
---------------------------------------------------------------
data required time 9.79
data arrival time -0.72
---------------------------------------------------------------
slack (MET) 9.07

Tclk = clock period

Tu = clock uncertainty
Tsl = source latency
Tnl = network latenty
Tsu = flip-flop setup time
Σ Tcn = sum of all cell and net delay in the path
Data arrival time = Σ Tcn

Data required time = Tclk - (Tsu)
Data arrival time <= Data required time
Specifying Constraint: Reg-Reg Paths 4-8
Current_Design
a N D Q D Q y
FF1 FF2
S 0 5 10
u2 u3 Default 50% duty cycle
Clk
u1 u4
1 Clock Cycle
pt_shell> create_clock -period 10 [get_ports Clk]
MUST Define: period and clock source (port/pin)
Optional :
-name clk_A (to assign clock name)
-waveform {0, 6} (to define duty cycle and or offset/skew)
pt_shell> report_clock
Creating a clock constrains all internal register to register timing paths.

By default, duty cycle is assumed to be 50%. Therefore, if your duty cycle is other than 50% you
would specify it using the “-waveform” option to the “create_clock” command. For example, to
specify 40% duty cycle:
create_clock -period 10 -waveform {0 4} [get_ports Clk]
Use report_clock to see defined clocks and their attributes.
When the create clock command is used as shown above, the port that is specified in the get_ports
command (Clk in this example) will be designated as a clock object. If however, the –name switch is
used, the clock object will be whatever name was specified in the –name switch.
Example 1: create_clock -period 10 –name Mary [get_ports Clk]
clock object is named Mary.
Example 2: create_clock -period 10 [get_ports Clk]
clock object is named Clk.
This is important because there are some commands which require the clock object be specified
(set_input_delay, set_output_delay) to be discussed in a subsequent unit.
Reg-Reg Paths w/ Clock Skew 4-9
Anticipate skew between launch and capture after layout

Current_Design
a N D Q
FF1 After layout
u1
u2 u3
D Q S y
Longer delay FF2
Clk u4
Clku1 PrimeTime applies

skew/uncertainty to
Du4 the capture edge.
Clku4
0 0.72
FF2 setup = 0.21 ns
9.29 10
Skew = 0.5 ns
9.5
PT always applies clock uncertainty to the capture clock edge.

setup check = (clock_edge - uncertainty - lib_setup)
Report: Reg-Reg Paths With Clock Skew 4-10
set_clock_uncertainty 0.5 [get_clocks CLK]
Point Incr Path

---------------------------------------------------------------
u1/CLK (fdef1a15) 0.00 0.00 r
u1/Q (fdef1a15) 0.50 0.50 r
u2/Y (buf1a27) 0.11 0.61 r
u3/Y (buf1a27) 0.11 0.72 r
u4/D (fdef1a15) 0.00 0.72 r
data arrival time 0.72
clock uncertainty -0.50 9.50 Skew = 0.5
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 8.57

Assume launch flop and capture flop are on opposite diagonals of the block.
Assume launch flop clock path has largest possible delay with respect to capture flop clock path.
Difference is called the setup uncertainty.
Obtain uncertainty value (Tu) from vendor or layout person.
PT always applies uncertainty to the capture flop.
Tclk = clock period

Data arrival time = Σ Tcn

Data required time = Tclk - Tu - Tsu
Notice that PrimeTime always applies uncertainty to the capture edge.
Reg-Reg Paths w/ Latency 4-11
Taking into account the delay due to clock tree insertion

Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
u1 u4
Clk
Network latency
Clk
Clku1
Du4
Clku4
1 10.29 11 Skew= 0.5

1.72
Network latency = 1 Setup = 0.21

Report: Reg-Reg Path w/ Network Latency 4-12
create_clock -per 10 [get_ports CLK]
set_clock_latency 1 [get_clocks CLK]
Point Incr Path

---------------------------------------------------------------
clock network delay (ideal) 1.00 1.00 Network latency = 1
u1/CLK (fdef1a15) 0.00 1.00 r
u1/Q (fdef1a15) 0.50 1.50 r
u2/Y (buf1a27) 0.11 1.61 r
u3/Y (buf1a27) 0.11 1.72 r
u4/D (fdef1a15) 0.00 1.72 r
clock uncertainty -0.50 10.50
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 8.57

Tclk = clock period

Data arrival time = Tnl + Σ Tcn

Data required time = Tclk + Tnl - Tu - Tsu
Reg-Reg Path with Source Latency 4-13
Taking into account clock source latency

Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
Clock
Clock Clk u1 u4
source
source
Clock source
Clk
Clku1
Du4
Clku4
Source latency = 3 4 4.72 13.29 14 Skew = 0.5

Network latency = 1 Setup = 0.21

Report: Reg-Reg Path w/ Source Latency 4-14
create_clock -per 10 [get_ports CLK]
set_clock_latency -source 3 [get_clocks CLK]
Point Incr Path

---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00 Network latency = 1
clock network delay (ideal) 4.00 4.00 source latency = 3
u1/CLK (fdef1a15) 0.00 4.00 r
u1/Q (fdef1a15) 0.50 4.50 r
u2/Y (buf1a27) 0.11 4.61 r
u3/Y (buf1a27) 0.11 4.72 r
u4/D (fdef1a15) 0.00 4.72 r
Network latency = 1
clock uncertainty -0.50 13.50 source latency = 3
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 8.57

Tclk = clock period

Data arrival time = Tsl + Tnl + Σ Tcn

Data required time = Tclk + Tsl + Tnl - Tu - Tsu
Reg-Reg Paths w/ Jitter 4-15
Taking into account clock jitter
Current_Design
a N D Q D Q S y
FF1 FF2
Jitter = +/- 0.5 ns u2 u3
Clock
Clock Clk u1 u4
source
source
Clock source early latency = 2.5

late latency = 3.5
Clkearly early
Clk
Clklate late
0 3.5
2.5
3.0

J = jitter
Jitter is the variation of clock period from edge to edge. The period of the clock can vary by +/- j.
Specifying Jitter 4-16

set_clock_latency 2.5 -source -early [get_clocks CLK]
set_clock_latency 3.5 -source -late [get_clocks CLK]
0 5 10
CLK Ideal
Late
LateLatency
Latency Early
EarlyLatency
Latency
2.5 3.5 12.5 13.5

CLK with
source latency
and jitter
Under worst case
conditions the jitter shortens the
effective clock period as shown.
How do you specify jitter using set_clock_latency -source -early/-late?

For late latency, the value is 3.5 - 0 = 3.5 (see the above timing diagram).
For early latency, the value is 12.5 - 10 = 2.5 (see the above timing diagram).
It is possible to get a negative values for early and late latency. For example: if the source latency +
the network latency is less than the jitter value, you can get a negative early latency.
Report: Reg-Reg Paths w/ Clock Jitter 4-17
set_clock_uncertainty –setup 0.5 [get_clocks CLK]
Point Incr Path
---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00 Network latency = 1
u1/CLK (fdef1a15) 0.00 4.50 r
late source latency = 3.5
u1/Q (fdef1a15) 0.50 5.00 r
u2/Y (buf1a27) 0.11 5.11 r
u3/Y (buf1a27) 0.11 5.22 r
u4/D (fdef1a15) 0.00 5.22 r
Network latency = 1
clock uncertainty -0.50 13.00 early source latency = 2.5
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 7.57

Tclk = clock period

Data arrival time = Tsl(late) + Tnl + Σ Tcn

Data required time = Tclk + Tsl(early) + Tnl - Tu - Tsu
Reg-Reg Paths w/ Clock Transition time 4-18
Taking into account clock transition time
Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
Clock
Clock Clk u1 u4
source
source
Ideal Clock: transition time is zero
Non-Ideal Clock: transition time is not zero
How
Howdo
doyou
youknow
knowbefore
beforeP&R,
P&R,what
whatvalue
valuetotouse
usefor
forclock_transition?
clock_transition?
What timings are affected by clock transition?
What timings are affected by clock transition?

If you do not know what cell is likely to drive your design’s clock port, pick the weakest buffer out of
the library. Once you picked the driving cell, look for any max_transition design rule that has been
placed on its output pin.
Clock transition affects clock-to-q delay and setup time values. Clock-to-q delay value increases as
clock transition value increases. The setup time for the capture flip-flop gets smaller as clock
transition increases.
Report: Reg-Reg w/ Clock Transition 4-19
set_clock_uncertainty –setup 0.5 [get_clocks CLK]
set_clock_transition 0.3 [all_clocks]
Point Incr Path
--------------------------------------------------------------- Clock transition = 0.3
u1/CLK (fdef1a15) 0.00 4.50 r late source latency = 3.5
u1/Q (fdef1a15) 0.56 5.06 r
u2/Y (buf1a27) 0.11 5.18 r Larger Clk2Q : 0.56 vs.
u3/Y (buf1a27) 0.11 5.28 r 0.50 ns
u4/D (fdef1a15) 0.00 5.28 r
clock uncertainty -0.50 13.00 early source latency = 2.5
library setup time -0.18 12.82 Smaller Tsetup : 0.18 vs.
data required time 12.82 0.21 ns
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 7.53
Reporting Clock Information 4-20
report_clock –skew -attribute
Rise Fall Hold Setup

Object Delay Delay Uncertainty Uncertainty
-------------------------------------------------------------------------------- Latency = 1.00 ns
Clk 1.00 1.00 0.50 0.50
Uncertainty = 0.50 ns
Source Latency
Object Early Rise Early Fall Late Rise Late fall
--------------------------------------------------------------------------------
Source early latency = 2.5 ns
Clk 2.50 2.50 3.50 3.50
Source late latency = 3.5 ns
Rise Fall
Object Transition Transition
--------------------------------------------------------------------------------
Clk 0.30 0.30 Clock Transition = 0.30 ns
Clock Period Waveform Attrs Sources

-------------------------------------------------------------------------------
Clk 10.00 {0 5} {Clk} Clock Period = 10 ns
Duty Cycle = 50%
Which of the following is (are) normally used to add pessimism

(or margin)?
a) Network latency
b) Source latency with –early and –late (jitter)
c) Setup uncertainty
d) Clock transition
e) All of the above
Using what report can you find the clock transition amount specified?
__________________________
What is the effect of clock transition: (Circle all that apply)

a) Increases (or decreases) the network latency (insertion delay)
b) Increases (or decreases) the source latency
c) Increases (or decreases) the register propagation delay and setup time
d) All of the above

Multiple Synchronous Clocks 4-22
Current_Design
a N D Q D Q S y
Clk1 FF1 FF2
300 MHz ÷9 u2 u3
Clk2 u1 u4
÷6
Clk1
Clk2
0 10 20 30 40 50 60
10 ns
Clk1
Clk2 Setup
= 0.21
30 40
Du4
30.72 39.79
The common base for Clk1 and Clk2 is 60ns.

There are two possible scenarios:
1) Clk1 launches at 0ns, Clk2 captures at 20ns.
2) Clk1 launches at 30ns, Clk2 captures at 40ns.
Scenario 2 is the tightest time wise. PrimeTime uses scenario 2 to check setup violation.
Report: Multiple Synchronous Clocks 4-23
create_clock -period 30 [get_ports Clk1]

create_clock -period 20 [get_ports Clk2]
Point Incr Path

---------------------------------------------------------------
clock Clk1 (rise edge) 30.00 30.00 Launch Edge = 30 ns
u1/CLK (fdef1a15) 0.00 30.00 r
u1/Q (fdef1a15) 0.50 30.50 r
u2/Y (buf1a27) 0.11 30.61 r
u3/Y (buf1a27) 0.11 30.72 r
u4/D (fdef1a15) 0.00 30.72 r
clock Clk2 (rise edge) 40.00 40.00 Capture Edge = 40 ns

library setup time -0.21 39.79 LaunchTime
Setup Edge
==0.21
30 ns
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 9.07

Uncertainties with Multiple Clocks 4-24
Current_Design
a N D Q D Q S y
Clk1 FF1 FF2
300 MHz ÷9 u2 u3
Clk2 u1 u4
÷6
Clk1 uncertainty = 0.15 ns

Clk1
Clk2 uncertainty = 0.20 ns
Clk2
0 10 20 30 40 50 60
10 ns
skew = 0.15 (?)

What uncertainty does
Clk1 skew = 0.20
PT use for the path
between registers?
Clk2 Setup
= 0.21
30 40
Du4
30.72 39.59
Report: Multi-synch. Clocks w/ Uncertainty 4-25
create_clock -p 30 [get_ports Clk1]
set_clock_uncertainty –setup 0.15 [get_clocks Clk1]

set_clock_uncertainty –setup 0.20 [get_clocks Clk2]
Point Incr Path
---------------------------------------------------------------
clock Clk1 (rise edge) 30.00 30.00 Launch Edge = 30 ns
clock network delay (ideal) 0.00 30.00 No uncertainty at launch
u1/CLK (fdef1a15) 0.00 30.00 r
u1/Q (fdef1a15) 0.50 30.50 r
u2/Y (buf1a27) 0.11 30.61 r
u3/Y (buf1a27) 0.11 30.72 r
u4/D (fdef1a15) 0.00 30.72 r
clock Clk2 (rise edge) 40.00 40.00
Launch Edge
Capture Edge== 30
40ns
ns
clock network delay (ideal) 0.00 40.00 Clock uncertainty = 0.20
library setup time -0.21 39.59 LaunchTime
Setup Edge
==0.21
30 ns
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 8.87

Uncertainties Between Sync. Clocks 4-26
set_clock_uncertainty 0.35 -setup \

-from [get_clocks Clk1] -to [get_clocks Clk2]
Point Incr Path
--------------------------------------------------------------- Launch Edge = 30 ns
clock network delay (ideal) 0.00 30.00 No uncertainty at launch
u1/CLK (fdef1a15) 0.00 30.00 r
u1/Q (fdef1a15) 0.50 30.50 r
u2/Y (buf1a27) 0.11 30.61 r
u3/Y (buf1a27) 0.11 30.72 r
u4/D (fdef1a15) 0.00 30.72 r
Launch Edge
Capture Edge== 30
40ns
ns
clock network delay (ideal) 0.00 40.00 Clock uncertainty = 0.35
u4/CLK (fdef1a15) 39.65 r LaunchTime
Setup Edge
==0.21
30 ns
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 8.72

Summary of Modeling Non-ideal Clocks 4-27
set_clock_latency
Models network delay (insertion delay) encountered within
current_design
set_clock_latency -source
Models delay before reaching clock port of current_design
set_clock_latency –source –early -late
Models delay including external jitter before reaching clock
port of current_design
set_clock_uncertainty
Models uncertainty (skew) between clock tree branches
set_clock_transition
Models clock transition time (slew)

Where to get numbers for the above spec?

- Ask for recommendations from the Clock Tree Synthesis Vendor/Tool for information on network
delay and the maximum guaranteed skew between clock branches.
- Ask your System Engineer about Source Latency. How far is the clock source (crystal/PLL) going
to placed on the chip from your design’s Clock port. Is Top Level Floor plan available?
- Ask the Layout Engineer if he/she expects any Timing margin so that you can include it as part of
the skew specification in order to be more pessimistic
Environmental Attributes? 4-28
Which wire load model

will PT use to estimate
the pre-layout net
parasitic data?
D Q M N D Q X D Q S T D Q
FF1 FF2 FF3 FF4
Clk The_Current_Design
Under what process,

voltage, and temperature
conditions will PT
calculate the path
delays?
Specifying Wire Load Model 4-29
U1
MY_DES
SUBDES_A
U33
SUBDES_B
50KGATES
To specify a single WLM for all the nets in the design:
set_wire_load_model -name 40KGATES [current_design]
To specify a “larger” WLM for the boundary nets:
set_wire_load_model -name 80KGATES [get_ports *]

Recall from Unit-1 that a wire load model is a table for estimating the capacitance, resistance and area
of a net. It is based on a statistical correlation between net fanout and net parasitics.
R1
C1
R2 C2
Use report_lib libname to list the vendor-supplied wire load models.
Automatic Selection of Wire Load Model 4-30
Name
----------------------------------
5KGATES
10KGATES
20KGATES
40KGATES
80KGATES
….
AreaBasedWireLoadSelection
Turn off automatic wire load model selection with:
pt_shell> printvar *wire*

pt_shell> set auto_wire_load_selection false

By default the variable auto_wire_load_selection is true.
Specifying Wire Load Mode 4-31
U1
MY_DES
SUBDES_A
U33
SUBDES_B
20KGATES
40KGATES 20KGATES
set_wire_load_model -name 40KGATES [current_design]

set_wire_load_model -name 20KGATES [get_cell U1]
set_wire_load_model -name 20KGATES [get_cell U33]
set_wire_load_mode enclosed
With the mode enclosed, the wire load model which fully
encloses each net is used
With the mode top used on the top level design, all nets in
the design use the Top level WLM
The default WLM mode is “top”

If the library has a default wire load mode, then the default mode is used if user does not specify
one.
Operating Condition Models 4-32
Library cells are usually characterized using “nominal”

voltage and temperature.
What if the circuit is to operate at a voltage

and/or temperature OTHER than nominal?
How is the delay through the net or cell

affected?
worst
worst nominal worst
Delay best Delay
nominal Delay nominal
best
best
Temperature Voltage Process

Specifying Operating Conditions 4-33
Operating Conditions specify:

A scaling (K) factor for the nominal cell, net delays and
A Tree Type representing the RC distribution or Interconnect
model of the nets, used in the net delay calculation
K = f (Process, Voltage, Temp)

Operating Conditions:
Name Process Temp Voltage Tree Type

---------------------------------------------------------------------
slow_125_1.62 1.00 125.00 1.62 balanced_case
slow_125_1.62_WCT 1.00 125.00 1.62 worst_case
pt_shell> set_operating_conditions -max slow_125_1.62

If the library has a default operating conditions and user does not specify one, the default in the library
will be used.
Reporting Environmental Information 4-34
report_design
Design Attribute Value

---------------------------------------------------------------------------
Operating Conditions:
analysis_type single Operating Condition
operating_condition_max_name slow_125_1.62 name = slow_125_1.62
process_max 1
temperature_max 125
voltage_max 1.62 Tree Type
Launch Edge
= = 30 ns
tree_type_max balanced_case balanced_case
Wire Load: (use report_wire_load for more information)

wire_load_mode top WLM Mode = top
wire_load_model_max 40KGATES
WLM = 40KGATES
wire_load_model_library_max ssc_core_slow
wire_load_selection_type_max user-specified
wire_load_selection_group_max AreaBasedWireLoadSelection
wire_load_min_block_size 0

Summary of Reg-Reg Path Constraints 4-35
create_clock -period 4.0 [get_ports Clk]

set_clock_latency 0.3 [get_clocks Clk]
set_clock_uncertainty 0.25 [get_clocks Clk]
set_clock_latency -source 0.5 [get_clocks Clk]
set_clock_transition 0.4 [get_clocks Clk]
set_wire_load_model -name 5KGATES
set_wire_load_mode TOP
set_operating_conditions -max slow_125_1.62
redirect reg2reg.rpt {report_clock -skew -attr}
redirect -append reg2reg.rpt {report_design}

Lab Overview 4-36
Given a specification (clock definitions, latencies,

LAB
uncertainties), write a script file that constrains
all the register to register paths in a design
Generate several pre STA reports (such as the
library report, clock report, design report) to
45 min ensure you’ve specified the constraints
Discover the incompleteness of constraints
(using check_timing) and generate timing report
for the longest register to register path
Experiment the effect of clock transition on the
register propagation delay (Clk2Q), setup time
and the amount of slack

Review 4-37
1. Between what clock edges you expect the setup time to be checked
between synchronous Clk1 (launch) and Clk2(capture) given the
following specifications (Draw the waveform and answer this question).
create_clock –period 10.0 [get_ports Clk1]
create_clock –period 15.0 –waveform {1 9} [get_ports Clk2]
Between what clock edges you expect the setup time to be checked
between synchronous Clk1 (launch) and Clk2(capture) given the
following specifications (Draw the waveform and answer this question).
set_clock_latency –rise 1.0 –fall 1.5 [get_clocks Clk2]
3. With what command can you check the name of the library operating conditions set on
your current_design? Use Quick Reference and your notes. (Circle all that apply).
a. report_lib
b. report_design
c. report_operating_conditions
d. report_clock
Appendix 4-38
Reporting Hold Time violations

Setup Time Is Met; What Next? 4-39
Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
Clk
u1 u4
Data meets setup requirement.

Clku1
Does it meet hold requirement?
Du4
setup
Clku4
Data required time What is hold time?

Reg-Reg Path Hold Requirement 4-40
Assuming ideal clock
Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
Clk
u1 u4
Hold time is an amount of time from the capture edge within

which data has to remain stable.
Assume FF2 hold time

Clku1
requirement is 0.23 ns.
Du4
Hold = 0.23 What is the minimum
delay requirement
Clku4
from FF1 to FF2?
0 0.75
Minimum delay from FF1 to FF2 must be equal to the hold time.
Report: Reg-Reg Path Hold Requirement 4-41
Point Incr Path

---------------------------------------------------------------
u1/CLK (fdef1a15) 0.00 0.00 r
u1/Q (fdef1a15) 0.48 0.48 f
u2/Y (buf1a27) 0.14 0.62 f
u3/Y (buf1a27) 0.14 0.75 f
u4/D (fdef1a15) 0.00 0.75 f
data arrival time 0.75 Σ Tcell = 0.75

library hold time 0.23 0.23
data required time 0.23 Hold requirement = 0.23
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 0.53

Tclk = clock period

Th = flip-flop hold time
For hold:
Data arrival time (Σ Tcn ) => Th
Why Check Hold Before Layout? 4-42
Usually hold is checked after layout under the best

case conditions
Prior to layout, hold may be checked under the worst

case conditions to catch any large hold time violations
Hold time requirements are affected by:

Skew on the clock tree network
Operating Conditions (discussed later in this unit)
FF Hold Time

Hold Requirement w/ Latencies 4-43
Non-ideal clock w/ source and network latencies

Current_Design
a N D Q D Q S y
FF1 FF2
u2 u3
Network latency
Clock
Clock Clk u1 u4
source
source
Source latency
Network latency = 1
Clku1 early latency = 2.5
late latency = 3.5
Du4
skew = +/- 0.5
Hold = 0.29
Clku4 Does this design
meet the hold time
3.5 4.5 5.29 skew = 0.5ns requirement?
4.31 5.0 If not, how big is
the violation?
PT always applies clock uncertainty to the capture clock edge.
Report: Reg-to-Reg Hold w/ Latencies 4-44
Point Incr Path
---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00 early source latency = 2.5
u1/CLK (fdef1a15) 0.00 3.50 r
Network latency = 1
u1/Q (fdef1a15) 0.54 4.04 f
u2/Y (buf1a27) 0.14 4.18 f
u3/Y (buf1a27) 0.14 4.31 f
u4/D (fdef1a15) 0.00 4.31 f
late source latency = 3.5
clock uncertainty 0.50 5.00
library hold time 0.29 5.29
---------------------------------------------------------------
---------------------------------------------------------------
slack (VIOLATED) -0.97

When performing timing report for hold time in a single clock domain environment with jitter, you
will get a pessimism equal to the jitter. In this example, you get a pessimism of 1 ns, so you have a
positive slack of 0.03ns.
In general, jitter is a very small percentage of clock period, therefore the pessimism can be ignored for
most designs.
In very high speed designs, the jitter may be a significant portion of the clock period.
Under single clock environment and under best case condition, if early and late source latency are
used to model jitter for register-to-register path timing analysis, you will get extra pessimism.
Agenda: Day Two 5-1

2
8 Performing STA
9 Summary
10 Customer Support
Constraining I/O paths

PrimeTime: Introduction to Static Timing Analysis 5-1 Unit 5: Constraining I/O Paths
Unit Objectives 5-2

Constrain the input and output (I/O) timing paths for
single and multiple non-ideal clocks
Determine when and how to use a Virtual clock
Define common base period of synchronous
multiple clocks

Gate-Level
Netlist
Technology
Setup
Libraries
File
Timing
.db format
Log,
Reports Script
Files
Our Focus
READ
READ
CONSTRAIN
CONSTRAIN
EXCEPTIONS
EXCEPTIONS
CHECK
CHECK
ANALYZE
ANALYZE
Our Focus

Constrain Input and Output Timing Paths 5-5
In Unit-4, Path X was

D Q M constrained by
FF3
create_clock
Current_Design
A N D Q D Q S B
FF1 FF2
u2 u3
Clock
Clock Clk u1 u4
source
source Network latency
Source latency
I/O Paths N & S are

still unconstrained!
T D Q
FF4

Input Arrival Time 5-6
External Logic The_Current_Design

Launch edge M A N
triggers D Q D Q
data
Clk
Clk Next edge
captures data
TClk-q TM TN TSETUP
Clk
Valid new data

A
(TClk-q + TM) (TN + TSETUP)

(Input Delay)

To meet the setup time of our flop:

Tclk-q + Tm + Tn + Tsetup < Clock period
Constraining Input Paths 5-7
pt_shell> set_input_delay -max 1.5 -clock Clk [get_ports A]
set_input_delay -max
Describes the maximum arrival time of external data with
respect to a launching clock and an input port
Launch Edge Capture Edge
1.5
You specify PT calculates
how much time how much time
is used by is left for the
external logic. internal logic.
delay of time left
external for
logic internal
logic

Exercise:: Constraining Input Paths 5-8
Clk latency: 0.8 ns EXTERNAL CIRCUIT
The_Current_Design
A
Skew: 0.25 ns CLK-OUTPUT
1.5 ns N D Q
Clk (worst)
(250 MHz) Clk U1
create_clock _______________________________________
set_clock_latency ___________________________________
set_clock_uncertainty _______________________________
set_input_delay ____________________________________
0.0 2.0 4.0
If U1 has a 0.37 ns Clk 1.5

setup time, what is
the maximum A
delay for N?
Constraint of
YOUR input path
Points to remember:
1. Set_input_delay is specified w.r.t the launch clock.
2. Set_input_delay amount specified is measured from the launch clock edge.
Timing Report:: Constraining Input Paths 5-9
create_clock -period 4.0 [get_ports Clk]
set_input_delay -max 1.5 –clock Clk [get_ports A]

report_timing –from [all_inputs]
Point Incr Path
---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00 Latency = 0.80
input external delay 1.50 2.30 f Input delay = 1.50
A (in) 0.00 2.30 f
…..

Period = 4.0
clock network delay (ideal) 0.80 4.80 Latency = 0.80
clock uncertainty -0.25 4.55 r
library setup time -0.37 4.18 Skew = 0.25
---------------------------------------------------------------
---------------------------------------------------------------
slack (VIOLATED) -0.07 Slack violation

Input Delay May Include Latency 5-10
In the previous timing report, would slack be different if you

changed the clock latency?
What if the latency amount is already part of the input delay?

Would you see a different slack?
Clk latency: 0.8 ns EXTERNAL CIRCUIT

The_Current_Design
A
Skew: 0.25 ns CLK-OUTPUT
1.5 ns N D Q
Clk (worst)
(250 MHz) Clk U1
Includes latency

Timing Report:: Constraining Input Paths 5-11
create_clock -p 4 [get_ports Clk]
set_input_delay -network_latency_included -max 1.5 \
–clock Clk [get_ports A]
report_timing –from [all_inputs]
Point Incr Path
---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00 Latency = 0.00
input external delay 1.50 1.50 f Input delay = 1.50
A (in) 0.00 1.50 f
…..
clock Clk (rise edge) 4.00 4.00 Period = 4.0

clock network delay (ideal) 0.80 4.80 Latency = 0.80
clock uncertainty -0.25 4.55 r
library setup time -0.37 4.18 Skew = 0.25
---------------------------------------------------------------
---------------------------------------------------------------
slack (MET) 0.73 Slack MET
Specifying Input Driving Cell 5-12
In order to accurately calculate the timing of input boundary

cells, PT also needs to know the driving cell
set_driving_cell allows the user to specify the external
driving cell (thus transition time or slew rate) for input ports:
The default drive on input ports is 0; Transition time is zero.
The driving cell also imposes its design rules (max_transition etc) on
the input port (and slows down the data)
You may also specify max and min driving cells; for setup and hold.
buf1
IN1
set_driving_cell -lib_cell buf1 [get_ports IN1]

You will experiment the effect of applying driving cell in the lab.
Output Setup Time 5-13
The_Current_Design External Logic External

U3
Launches U3 B
Flip-Flop
S T
Data D Q D Q captures
data
Clk
TClk-q Ts TT TSETUP
Launch Edge Capture Edge
Clk
B Valid new data
TClk-q + TS TT + TSETUP
(Output Delay)

To meet the external flop’s setup time:

Tclk-q + Ts + Tt + Tsetup < clock period
Constraining Output Paths 5-14
pt_shell>set_output_delay -max 1.75 -clock Clk [get_ports B]
set_output_delay -max
Describes the setup time of an output port with respect to a
capture clock
Launch Capture
Edge Edge
You specify PT calculates
how much time how much time
is needed by is left for
external logic. internal logic.
1.75
Constraint for
YOUR output path

Exercise:: Constraining Output Paths 5-15
Source latency: 0.5 ns The_Current_Design

EXTERNAL CIRCUIT
Network latency: 0.3 U3 S B
Setup
D Q
Skew: 0.25 ns Requirement:
1.75 ns
Clock Clk
(250 MHz)
Use Clock period and skew constraints from the previous exercise
set_clock_latency ___________________________________
set_clock_latency -source ___________________________
set_output_delay ___________________________________
0.0 2.0 4.0

What is the
maximum Clk
delay for the 1.75
timing path B
through S?
Must be valid
Data launch here
Points to remember:
1.set_output_delay is specified w.r.t the capture clock.
2.set_output_delay amount specified is measured from the capture clock edge, towards the
launch clock, (in the negative time direction).
Timing Report:: Constraining Output Paths 5-16
set_clock_latency –source 0.5 [get_clocks Clk]
set_output_delay -max 1.75 –clock Clk [all_outputs]
report_timing –to [all_outputs]
Point Incr Path

---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00 Source Lat : 0.50
….. Network Lat: 0.30
B (out) 0.00 2.60 r

Period = 4.0
clock network delay (ideal) 0.80 4.80 Source Lat : 0.50
clock uncertainty -0.25 4.55 Network Lat: 0.30
output external delay -1.75 2.80
data required time 2.80 Skew = 0.25
---------------------------------------------------------------
data required time 2.80 Output delay: 1.75
---------------------------------------------------------------
slack (MET) 0.20 Slack MET
Output Delay May Include Latency 5-17
In the previous timing report, would slack be different if you

changed the clock source or network latencies?
What if the latency amount is already part of the input delay?

Would you see a different slack?
Source latency: 0.5 ns The_Current_Design

EXTERNAL CIRCUIT
Network latency: 0.3 U3 S B
Setup
D Q
Skew: 0.25 ns Requirement:
1.75 ns
Clock Clk
(250 MHz) Includes source,
network latencies

Timing Report:: Constraining Output Paths 5-18
set_clock_latency –source 0.5 [get_clocks Clk]
set_output_delay -source_latency \
–network_latency -max 1.75 –clock Clk [all_outputs]
report_timing –to [all_outputs]
Point Incr Path
---------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00 Source Lat : 0.50
….. Network Lat: 0.30
B (out) 0.00 2.60 r
data arrival time 2.60 Period = 4.0

clock Clk (rise edge) 4.00 4.00 source latency (incl)
clock uncertainty -0.25 3.75 network latency (inc)
output external delay -1.75 2.00
data required time 2.00 Skew = 0.25
--------------------------------------------------------------- Output delay: 1.75
---------------------------------------------------------------
slack (VIOLATED) -0.60 Slack VIOLATION
Is this Output Path Fully Constrained? 5-19
External Logic
T
D Q
Clk
The_Current_Design External Logic
U3 S B T
D Q D Q
Clk buf1 Clk
External Logic
T
D Q
Clk
How many output delay constraints are specified on Port B?

What is the effect of connecting another 10 External logic to B?
Specifying Output Capacitance (fixed) 5-20
OUT1
5 pt_shell>set_load 5 [get_ports OUT1]
In order to accurately calculate the timing of boundary cells,

PT needs to know the external capacitate loading
set_load allows the user to specify the external capacitive
load on ports:
By default, the external load on ports is 0
You may also specify different min and max numbers

Useful at the very top level of the CHIP where the driving cell is an I/O buffer.
Specifying Output Capacitance (Derived) 5-21
Use load_of lib/cell/pin to return the pin capacitance of a

specific gate from the technology library.
set_load [load_of ssc_core_slow/AN2/A] [get_ports OUT1]
OUT1 A
AN2
B
set LOAD [expr [load_of ssc_core_slow/IVA/A] * 3]

set_load $LOAD [get_ports OUT1]
A
Required BLANK spaces
OUT1
A around the *
A

Suitable for sub blocks within the chip.
Test for Understanding 5-22
EXTERNAL
Board PATH
CHIP1 CHIP2 DELAY = 2
tu = 0.35
CHIP1_CORE Port Out1 CHIP2_CORE
tsl1 = 0.5 tn1 = 0.25 BLOCK2A
tsu
Clk
INTERNAL
PATH DELAY
J = .1
tn2 = 0.5
tsl2 = 0.7 CLOCK NETWORK DELAY2
Your task is to constrain the input timing path(s) in CHIP2_CORE in the context
shown above.
Use the legend for the terms and the command template provided to you in the
Notes section.
There is a single clock Clk that controls 2 chips on a board. Your focus is on
CHIP2_CORE.
Legend:
Clk is 200 MHz Clock with a Jitter (J) = 0.1 and a maximum skew within each chip (tu) = 0.35
CHIP1_CORE: Source Latency (tsl1) = 0.5, Network latency (tn1) = 0.25
CHIP2_CORE: Source latency (tsl2) = 0.7, Network latency (tn2) = 0.5, Cell name driving
CHIP2_CORE is is mux007
NOTE1: Make reasonable assumptions for parameters not supplied
NOTE2: You do not have to use all the constraints below. You can, however, use additional
constraints.
create_clock ______________________________________________________________
set_clock_latency __________________________________________________________
set_clock_latency –source –early _____________________________________________
set_clock_latency –source -late ______________________________________________
set_clock_uncertainty ______________________________________________________
set_input_delay __________________________________________________________
set_driving_cell __________________________________________________________
Verify or Remove I/O Constraints 5-23
report_port -verbose:
Returns all constraints and environment placed on all the
input and output ports (delay, load, driving cell).
remove_capacitance:
Removes capacitance load placed by set_load command
remove_driving_cell:
Removes driving cell placed by set_driving_cell
remove_input_delay:
Removes input delay constraints from specified ports
remove_output_delay:
Removes output delay constraints from specified ports

Note that to remove the capacitance placed by the set_load command you should use the
remove_capacitance command.
Synchronous Multiple Clock Designs 5-24
The_Current_Design
CLKD
CLKA
N D Q X D Q S
FF2 FF3
CLKB CLKC
CLKE
What is different?
A: Multiple clock sources
All derived from the same clock source
Some clocks do not have a corresponding clock port
on our design
Multiple constraints on a single port
What do you do now?

Clocks are said to be synchronous if they are derived from the SAME clock source.
Answer: Use Virtual Clocks! 5-25
What are virtual clocks?
A: Clocks in the environment of the design that:

Are defined as clock objects
Do not clock any sequential devices within the
current_design
Serve as references for input or output delays

Creating a Virtual Clock 5-26
How do you create a virtual clock?
A: It is the same as defining a clock, but you

do not specify a clock pin or port:
You must name your virtual clock, since there is
no clock port for the virtual clock
create_clock -name VCLK -period 5.00
Must be named No source pin or port!

Method for Synchronous Multiple Clocks 5-27
÷9 CLKA
÷6 CLKC
300 MHz ÷4 CLKD
÷3 CLKE
The_Current_Design
CLKD
N D Q X D Q S (75 Mhz)
CLKA
FF2 FF3
(33 Mhz)
CLKC
(50 Mhz) CLKE
(100 Mhz)
Method is the same as that for single clock designs:

1. Define the clock(s), using virtual clocks if necessary
2. Specify I/O delays relative to the clock(s):
• PrimeTime will determine which clock imposes the most
restrictive constraint on the design by finding Base Period

Base Period is the Lowest Common Multiple (LCM) of all the clock periods involved. In the above
example there are 2 base periods:
For the Input paths: Base period = LCM (20, 30) = 60 ns

For the output paths: Base period = LCM (20, 1000/75, 10) = 40 ns
Example: Multiple Clocks on Input Ports 5-28
create_clock
create_clock -period
-period 30
30 -name
-name CLKA
CLKA
create_clock
-period 20
20 [get_ports
[get_ports CLKC]
CLKC]
set_input_delay
set_input_delay 5.5
5.5 -clock
-clock CLKA
CLKA -max
-max [get_ports
[get_ports IN1]
IN1]
5.5 ns
The_Current_Design
IN1
0.5 ns 5 ns N
300 CLKA
MHz
CLK-Q tN
÷9 CLKC
÷6
CLKC

Example Waveforms 5-29
÷6 CLKC
What is the Base period? 300 MHz
÷9 CLKA
CLKA
CLKC
0 10 20 30 40 50 60
10 ns
For the example shown, input logic cloud of

The_Current_Design must meet:
tN < 10 - 5.5 - tsetup

Example: Multiple Clocks Output Ports 5-30
create_clock -period [expr 1000.0/75] -name CLKD
create_clock -period 10 -name CLKE
create_clock -period 20 [get_ports CLKC]
set_output_delay -max 2.5 -clock CLKD [get_ports OUT1]

set_output_delay -max 4.5 -clock CLKE -add_delay [get_ports OUT1]
2.5 ns
The_Current_Design 2ns 0.5 ns
OUT1 SETUP
S CLKD
tS
CLKC 4 ns 0.5 ns
SETUP
CLKE
4.5 ns

NOTE: Do NOT use “13.3” as the clock period for CLKD when you cannot correctly represent it
using finite decimals. Use “1000.0/75”. Also, do NOT use “1000/75”, the result will be truncated to
integer 13.
Example Waveforms 5-31
÷4 CLKD
What is the Base period? 300
÷6 CLKC
MHz
÷3 CLKE
6.6
CLKD 13.3 26.6
CLKC
CLKE
0 10 20 30 40
10
For the example shown, output logic cloud of

The_Current_Design must meet:
tS < 10 - 4.5 AND tS < 6.6 - 2.5
Hints for Multiple Clock Designs 5-32
By definition, all clocks used with PT are synchronous:

You can not create asynchronous clocks with create_clock
PT will determine every possible data launch/data capture
time, and perform STA to the most conservative constraint
This can be very time consuming, when
difference in periods between multiple clocks is large
base period is too large
Recommendation:
Keep the base period smaller than 10 *
(the smallest clock period) whenever possible.

1. Given 4 synchronous clock periods of: 3, 5, 20, 25 ns:
A) What is the Base period? ______________________________
B) Does this Base period follow our Recommendation,

i.e. Tbase < 10 * min (periods)? ___________________________
C) How would this affect the runtime for PT? _______________________________
2. Does it make sense to specify source and network latency for a

virtual clock?

Summary of I/O Path Constraints 5-34
set IN_EX_CLK [remove_from_collection \
[all_inputs] [get_ports Clk]]
set LOAD [load_of ssc_core_slow/AN2/A]
set_input_delay -max 1.0 -clock Clk $IN_EX_CLK
set_driving_cell -lib_cell FD2 -pin Q $IN_EX_CLK
set_output_delay -max 2.0 -clock Clk [all_outp]
set_load $LOAD [all_outputs]
redirect io.rpt {report_lib ssc_core_slow}
redirect -append io.rpt {report_port -verbose}

Lab Overview 5-35
LAB
Given a design specification you will
constrain all the I/O paths in the design
You will ensure that all timing paths in the
design have been constrained using
60 min check_timing
You will generate timing reports for the
longest I/O paths and interpret the effects of
your applied I/O constraints
You will vary the input driving cell, output
load and observe their effects on the timing
paths

Appendix 5-36
Constraining I/O for Hold Time check

When to Check for Hold Violations 5-37
My design has met setup requirements.

Is it a good time to check for hold?
Small Violations:
Post layout: Check all hold-time violations using best case
operating conditions post-layout because
The clock tree is not in place until after layout
They often disappear when net parasitics are annotated
Large Violations:
Pre-Layouit: Check only using the worst case operating
conditions for any large hold-time violations pre-layout

Constrain for Hold Time: Input Paths 5-38
min 0.3ns
TO_BE_SYNTHESIZED
FF1 FF2 FF3 FF4
QB QB
Clk
set_input_delay -min describes the fastest arrival

time of the external logic on the input ports.
create_clock
-period 10
10 [get_ports
[get_ports Clk]
Clk]
set_input_delay
set_input_delay -min
-min 0.3
0.3 -clock Clk $all_in_ex_clk
-clock Clk $all_in_ex_clk
If FF2 has THOLD = 1ns:

What is the min delay allowed for N?

Constrain for Hold Time: Output Paths 5-39
0.3ns 0.5ns
Hold Time
Requirement
TO_BE_SYNTHESIZED
FF1 FF2 FF3 FF4
QB QB
Clk
set_output_delay -min :
Describes the hold time requirement of the external logic on the
output ports
If FF has THOLD = 0.5ns and TT = 0.3ns:

What is the min output delay?

If logic cloud T uses 0.3 ns, you need to have a minimum delay for FF3 (Clk->Q) plus logic cloud S
of 0.2 ns in order not to violate the hold time requirement on FF4.
Calculation of Output Hold Time 5-40
Tmin
0.3ns
setup = 0.8
hold = 0.5
D Q S T D Q
FF3 FF4
QB
Clk
set_output_delay -max (Tmax + FF4setup)

set_output_delay -min (Tmin - FF4hold)
create_clock -period 5 [get_ports Clk]

set_output_delay -min (0.3-0.5) -clock Clk [all_outputs]
-0.2

Agenda: Day Two 6-1

2
8 Performing STA
9 Summary
10 Customer Support
Specifying Timing Exceptions
PrimeTime: Introduction to Static Timing Analysis 6-1 Unit 6: Specifying Timing Exceptions
Unit Objectives 6-2
List 4 timing exception commands and state their

legal start and end points
Specify false path exception in 3 design examples
Write down the relationship between the Setup
and Hold Multipliers when applying a multicycle
path exception
State the command to look for ignored exceptions
Give 2 recommendations to specify timing
exceptions effectively

Gate-Level
Netlist
Technology
Setup
Libraries
File
Timing
.db format
Log,
Reports Script
Files
Our Focus
READ
READ
CONSTRAIN
CONSTRAIN
EXCEPTIONS
EXCEPTIONS
CHECK
CHECK
ANALYZE
ANALYZE
Our Focus
What are Timing Exceptions? 6-5
F1 F2
single clock cycle
Timing
Timingexceptions
exceptionsare
areused
usedto
tooverride
override
the
thedefault
defaultsingle-cycle
single-cycleconstraints
constraints
described
describedbybycreate_clock,
create_clock,
set_input_delay,and
set_input_delay, and
set_output_delay.
set_output_delay.

Timing Exception Commands 6-6
Timing
Timingexceptions
exceptionscan
canbe
beapplied
appliedto
toany
anytiming
timingpath:
path:
set_false_path Removes timing constraints from a timing path
set_multicycle_path Allows more than one clock cycle for a timing path
set_max_delay
Specifies max and min delays on paths
set_min_delay
report_exceptions Reports current timing exceptions
reset_path Restores the default timing constraints on

specified paths
Applying Exceptions 1/2 6-7
When using –from and –to options, you need to specify

legal path start and end points:
Start End Start & End
Input Ports and Output Ports

Clock Objects,
Clock Pins and Data Pins
Registers
of Registers of Registers
A D Q D Q
R1 R2
clk1
clk2
pt_shell> set_false_path –from A –to R1/D

pt_shell> set_false_path –from clk1 –to clk2

The complete commands for the example shown above should be:
set_false_path –from [get_pins A] –to [get_pins R1/D]
set_false_path –from [get_clocks clk1] –to [get_clocks clk2]
When specifying register cell names for the start and end points, (under the hood) PrimeTime will look
for the actual start and end pins of the register cell and apply the timing exception correctly for you.
You can be very specific with timing exceptions with -to/-from/-through options by specifying rise or
fall edges.
New options include:
-rise_from
-fall_from
-rise_to
-fall_to
-rise_through
-fall_through
Applying Exceptions 2/2 6-8
When using the –through option, any pin can be

used to describe the path:
D Q D Q
U12
Z
R1 R2
clk
pt_shell> set_false_path –through U12/Z
The path from R1/CP to R2/D will be false

Assumption: No fanin/fanout

When using the –through option, multiple –through arguments mean AND, multiple pins in one
–through are an OR.
Example:
set_false_path –through A –through B –through {C D}
means set a false path through the path that goes through “A and B and (C or D).”
Multiple Paths 6-9
pt_shell>
pt_shell> set_multicycle_path
set_multicycle_path 22 -from
-from FFA/CP
FFA/CP \\
-through
-through Multiply/Out
Multiply/Out -to
-to FFB/D
FFB/D
Two-Cycle Path -through
-from -to
In Multiply
Out
FFB
FFA
D
CP
sel
Add
One-Cycle Path

In this example, it is sufficient to specify Multiply/Out using the –through option, without the -from and
–to.
Logically False Paths 6-10
A
0 A
B 1 0
B 1
mux1
mux2
The paths through both A’s and both B’s cannot happen:
They are logical false paths!
Use the -through option:
set_false_path –through mux1/A –through mux2/A

set_false_path –through mux1/B –through mux2/B

You can find logical false paths with the “report_timing –true/-false/-justify”
command. This command will apply input combinations and trace through the netlist to find whether
the reported path is logically correct. Consult the PrimeTime User Guide for a detailed explanation.
Generally, you would only set this path as a false path if it appears in the timing reports with a violation.
Paths Between Asynchronous Clocks 6-11
FUNC_CORE
Des_A Des_B
CLKA
(100 Mhz N D Q D Q X D Q
from OSC1)
CLKB
(100 Mhz
from OSC2)
current_design FUNC_CORE
/* Make sure register-register paths meet timing */

create_clock -period 10 [get_ports CLKA]
create_clock -period 10 [get_ports CLKB]
/* Don’t optimize logic crossing clock domains */

set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]
set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]

CLKA and CLKB are asynchronous to each other.

To exclude Timing analysis between these 2 clock domains, specify the path(s) as false paths.
Constrain Tri-states at the Top-Level 6-12
Tri-states can be the cause of many false paths.

set_false_path -through [get_pins U1/DATA_BUS_OUT[1]] \
-through [get_pins U1/DATA_BUS_IN[1]]
U1 U2
UART TIMER
DATA_BUS_OUT DATA_BUS_IN
DATA_BUS
U3
CPU
TOP_BLOCK
Multi-cycle Paths 6-13
Clock
Clockperiod
periodis
is10
10ns.
ns.Per
PerSpecification,
Specification,the
the
adder
addertakes
takes66clock
clockcycles.
cycles.
How
Howdodoyou
youconstrain
constrainthe
thedesign?
design?
A D Q
64
A < 60 ns
E
C_reg
B D Q
+ D Q
64
Y
64
E
B
E
D Q
0 0 0 0 0 1
Clk
shift_reg

Timing with Multi-cycle Constraints 6-14
create_clock
-period 10
10 [get_ports
[get_ports CLK]
CLK]
set_multicycle_path
set_multicycle_path 66 –setup
–setup -to
-to [get_pins
[get_pins C_reg[*]/D]
C_reg[*]/D]
Launch Capture
CLK
-10 0ns 10 20 30 40 50 60
C_reg/D IDEAL: TH < Adder_Delay < (60 - TSU)
C_reg/D
PT assumes change could occur near any clock edge causing metastability!
Where does PT perform hold analysis?

TSU = setup time

TH = hold time
PT will perform the setup analysis on edge 6, i.e. at 60 ns. This will allow the adder’s logic to have a
delay of (60 – setup_time – uncertainty).
Default Hold Check 6-15
set_multicycle_path
set_multicycle_path -setup
-setup 66 -to
-to [get_pins
C_reg[*]/D]
IMPLICIT! set_multicycle_path
set_multicycle_path -hold
-hold 00 -to
-to [get_pins
C_reg[*]/D]
Default
Hold
Check Capture
Launch
CLK
-10 0ns 10 20 30 40 50 60
C_reg/D (50 + TH) < Combo_Logic < (60 - TSU)
Why is hold check performed at 50 ns?

The default Hold check is always performed one edge before the setup check.
PT assumes that the clock edges at 10-50 ns can cause metastability if they occur at the same time the
data changes. Putting the hold check at 50 ns is the safest.
Set the Proper Hold Constraint 6-16
set_multicycle_path
set_multicycle_path -setup
-setup 66 -to
-to [get_pins
C_reg[*]/D]
OVERRIDE! set_multicycle_path
set_multicycle_path -hold
-hold 55 -to
-to [get_pins
C_reg[*]/D]
M H = MS - 1
Setup Check
Hold checks for : MH = 5 MH = 4 MH = 3 MH = 2 MH = 1 MH = 0
with MS = 6
CLK
-10 0ns 10 20 30 40 50 60
C_reg/D Now allows change between TH and (60 - TSU)
C_reg
D Q + D Q
E E
DESIRED RESULT: ALLOW 60ns for ADDER

MH stands for Hold Multiplier, MS for Setup Multiplier. The Setup multiplier counts up with
increasing clock cycles, the Hold multiplier counts up with decreasing cycles. The origin (0) for the
Hold Multiplier is always at the Setup Multiplier – 1 position.
Precedence of Timing Exceptions 6-17
F1 F2
More than one exception set

on the path from F1 to F2.
set_false_path has higher
precedence!
(see student notes)
clk1
clk2
set_false_path
set_false_path –from
–from clk1
clk1 –to
–to clk2
clk2
set_max_delay
set_max_delay 77 –from
–from F1
F1 –to
–to F2
F2
PrimeTime uses the following general precedence rules, when applying multiple exceptions to the same
path:
• set_false_path > set_max_delay or set_min_delay > set_multicycle_path
• pin > clock
• -from > -to > -through
• tighter constraint > looser constraint
For more detailed information refer to the PrimeTime User Guide: Advanced Timing Analysis.
Ignored Timing Exceptions 6-18
PrimeTime will warn you when invalid exceptions are applied.
pt_shell> set_false_path -from FF1/Q

Warning: Object 'FF1/Q' is not a valid
startpoint. (UITE-216)
How would you correct this exception?

set_false_path -from FF1/Q -- Invalid because this is an INVALID start point.

The exception needs the CLK pin of the flip-flop, so the correct syntax would be:
set_false_path -from FF1/CLK
Always Check for Invalid Exceptions 6-19
pt_shell> check_timing
Warning:
Warning: There
There are
are timing
timing exceptions
exceptions which
which are
are ignored.
ignored.
pt_shell> check_timing -verbose -ignored

Warning:
Warning: There
There are
are timing
timing exceptions
exceptions which
which are
are ignored.
ignored.
From
From To
To Setup
Setup Hold
Hold
---------------------------------------------------------
---------------------------------------------------------
FF1/Q
FF1/Q ** FALSE
FALSE FALSE
FALSE

To remove any unwanted exceptions, use the reset_path command, e.g.:

reset_path –from FF1/Q
You may also use the command report_exceptions –ignored to view ignored exceptions.
Reduce Number of Timing Exceptions 6-20
To reduce the run-time for timing analysis, minimize the total

number of exceptions!
The paths from F1_reg to F2_reg are false.

How many exceptions do each of the following commands generate?
32
F1 F2 F3
clk1
clk2
set_false_path
set_false_path -from
-from F1_reg[*]/CP
F1_reg[*]/CP -to
-to F2_reg[*]/D
F2_reg[*]/D 1
for
for {set
{set ii 1}
1} {$i
{$i <=
<= 32}
32} {incr
{incr i}
i} {{
set_false_path
set_false_path -from F1_reg[$i]/CP -to
-from F1_reg[$i]/CP -to F2_reg[$i]/D
F2_reg[$i]/D
2
}}
set_false_path
-from F1_reg[*]/CP
F1_reg[*]/CP 3
set_false_path
-from [get_clocks
[get_clocks clk1]
clk1] -to
-to [get_clocks
[get_clocks clk2]
clk2] 4
The most efficient way to specify timing exceptions is between clock domains!
Optimizing Analysis Time 1/2 6-21
The -through option requires more CPU for large designs

Do not use -through unless it is necessary
Sub-Optimal:
Sub-Optimal:
set_multicycle_path
set_multicycle_path 22 -from
-from U1/CP
U1/CP -through
-through U2/A
U2/A
-through
-through U3/B -through U4/A
U3/B -through U4/A
-through U5/C -to U6/D
-through U5/C -to U6/D
Optimal:
Optimal:
set_multicycle_path
set_multicycle_path 22 -to
-to U6/D
U6/D
To help PT’s run time, use -to option when possible.

Optimizing Analysis Time 2/2 6-22
Use set_disable_timing instead of set_false_path -through

when there is one pin.
Sub-Optimal:
Sub-Optimal:
ow
set_false_path
set_false_path -through
-through [get_pins
[get_pins ADDER/CI]
ADDER/CI]
Sl
Optimal:
Optimal:
st
Fa
set_disable_timing
set_disable_timing [get_pins
[get_pins ADDER/CI]
ADDER/CI]

Lab Overview and Review 6-23
LAB
Apply Multicycle and false path exceptions

on a complex design
60 min
Lab Review
How do you know where in a design to apply

a multicycle path constraint?
After applying a multicycle path constraint,

how can you verify the constraint has been
applied correctly?

Answers will follow.
A path between 2 flops are controlled by a 200 MHz clock.

The path delay is 13 ns worst case. Clock has a network
delay of 3 ns, and an uncertainty of 1 ns. Assume both
setup and hold time are 0.5 ns. The best case delay of
this path is known to be 6 ns. Write down the exceptions
such that there will not be any setup or hold violations:
______________________________________________
______________________________________________
How can you constrain a path from an asynchronous

Reset input port to the Rst pin of a flop? The worst case
absolute delay is 3 ns and the best case absolute delay is
0.9 ns.
______________________________________________
______________________________________________

Agenda: Day Two 7-1
DAY
Unit I/O Paths and Exceptions Lab
2
8 Performing STA
9 Summary
10 Customer Support
Creating Timing Models (QTM)
PrimeTime: Introduction to Static Timing Analysis 7-1 Unit 7: Creating Timing Models (QTM)
Unit Objectives 7-2
Create a quick timing model (QTM) of a block

given a block specification

Gate-Level
Netlist
Technology
Setup
Libraries
File
Timing
.db format
Log,
Reports Script
Files
Our Focus
Functional Core Integration – Pre-Layout 7-4
DSP CODEC
A/D
(WLM 4) (WLM 1)
RISC_CORE
(WLM 3)
MPEG
(WLM 2)
USB RAM
Functional Core
Core Clock(s)
Blocks synthesized using Timing Models

Wire Load Models (Gates) (QTM)

QTM is typically used as a place holder when some blocks are not yet available in the form of
synthesized gates, but you still want to perform STA on the Functional Core for early estimation.
Here are some other Timing Models supported by PT:

ILM: Interface Logic Model (requires Gate level netlist).
ETM: Extracted Timing Model (requires Gate level netlist).
These 2 models (created more accurately using Post Layout data) are covered in the PrimeTime: Chip
Level Timing Analysis workshop.
Quick Timing Models (QTM) 7-5
A QTM is typically used to create a timing model for a block

in which the gate level netlist does not yet exist
Normally used for early floorplanning and top-level timing
analysis:
Before HDL has been written
Before 3rd party macros (or their timing models) have been
obtained
A QTM is a “library cell” with setup, hold and delay arcs:

Created using a PrimeTime script of QTM commands
A QTM is as accurate as your description of the interface

timing specification of the design
help *qtm*
To create QTM, you need to write a PT script containing QTM commands. Fortunately, all qtm
commands contain the “qtm” string in them, thus you can obtain a list of all the QTM commands with
the “help *qtm*” command.
QTMs in the Early Chip Planning Flow 7-6
QTM PrimeTime
PrimeTime design_lib.db
Scripts for Blocks for Blocks at
at Top-Level Top-Level
Chip
ChipArchitect/
Architect/
FlexRoute
FlexRoute
Top-Level Top-Level
Net
Netlist
Parasitics
PrimeTime
PrimeTimeor
or
Design Compiler
Design Compiler
The flow shows a role of QTM in the early floor planning stage when no blocks have been realized
into gates. PT is used to create block level QTMs, which are used by a Top level Floor planner (CHIP
Architect) to estimate the placement (and extract the net parasitics between them).
FlexRoute is used as the Top level router in this flow. Once you have the DB files for the block level
QTMs and the Top level net parasitics between them, PT can perform STA and help derive block
level constraints. Block level synthesis, (using DC) therefore, has a better starting point with more
accurate block constraints because it took into account top level net parasitics.
Creating QTMs 7-7
A QTM is created by writing a PrimeTime script containing

QTM commands
Commands will indicate:

Port name, directions and input to output delays
Input Port
setup and hold constraints
capacitive loading
Output Port
Clock-to-output delays
Drive Strength
Delay, load and drive are specified in technology library units
Setup, hold, clk_to_output parameters can be specified as a

constant value or derived from a library flip flop
Simple QTM Example 7-8
Your job is to design a 4-bit synchronous

adder/subtractor
add_subN Add/Sub Y / Y
4
A / A
4 Carry/Borrow carry_borrow
B / B
4
Clk Clk
ADDSUB
Before writing HDL code, a QTM will be written to:

Formalize the design’s specification
Allow the system engineer(s) to perform top-level routing and
timing analysis

Specification for ADDSUB 7-9
The block-level specification is as follows:

Clock Frequency = 250 Mhz
Inputs shall perform desired mathematical operation within 2 ns
Input pin capacitance shall not be more than 0.05 fF
Clock-to-output delay shall be less than 0.5ns
Output drive resistance shall be less than 0.05 mΩ
ADDSUB
add_subN / Y
4
A /
4 carry_borrow
B /
4
2
Clk
0.5

Basic QTM Flow - Define Ports 7-10
State the model name
Declare name & direction of IO ports
# Tell PT we’re defining a QTM

create_qtm_model ADDSUB
# Define IO Ports
create_qtm_port {Clk} -type clock
create_qtm_port {A[3:0] B[3:0] add_subN} -type input
create_qtm_port {Y[3:0] carry_borrow} -type output

Basic QTM Flow - Specify Input Ports 7-11
Define input port characteristics:

Timing
Capacitive Loading
# Define input port setup time

set_qtm_global_parameter -param setup -value 0.0
create_qtm_constraint_arc -setup -from Clk \
-to {A[3:0] B[3:0] add_subN} -value 2.0 -edge rise
# Define input port capacitive loading

set_qtm_port_load {Clk A[3:0] B[3:0] add_subN} \
-value 0.05

set_qtm_global_parameter specifies one of the 3 global parameters: setup, hold or clk_to_output. The
value specified (in this case 0.00) is added to the arcs (in this case setup). Consider this as a way of
adding a known setup time from library flop, (OR) you can combine the setup time altogether with the
constraint arc.
You can set a global parameter extracted from your library flip-flop, for example:
Set_qtm_global_parameter –param setup –lib_cell fd1fa1 –pin D.
Constraint arc is defined (in reverse) from the Clk to data as in the create_qtm_constraint_arc, since it
is a setup check as opposed to propagation delay.
Basic QTM Flow - Specify Output Ports 7-12
Define output port characteristics:

Timing
Drive Strengths
# Define output port clock-to-output timing

set_qtm_global_parameter -param clk_to_output \
-value 0.0
create_qtm_delay_arc -from Clk \
-to {Y[3:0] carry_borrow} -value 0.5 -edge rise
# Define output port drive strengths

set_qtm_port_drive {Y[3:0] carry_borrow} -value 0.05

In this case, the global parameter clk_to_output value (0.00) is added to the delay arc. “clk_to_output”
can be specified as a fixed value (in this case, 0.00) or can be derived from that of a library flip-flop.
Example: set_qtm_global_parameter –param clk_to_output –lib_cell fd1fa1 –pin QN.
Basic QTM Flow - Reporting & Saving 7-13
Issue a QTM model report to ensure the model was

entered correctly
Save the model in “.db” format for use by Synopsys tools
# Before saving, report model & check results

redirect qtm.rpt report_qtm_model
# Save timing model

save_qtm_model

Saving QTM 7-14
save_qtm_model
ADDSUB
QTM
PrimeTime
PrimeTime ADDSUB_lib.db
pt_shell> report_lib ADDSUB_lib
Library Cells:
Attributes:
b - black box (function unknown)
….other attributes...
Q - Quick timing model (QTM)
Lib Cell Attributes

-------------------- ---------------
ADDSUB b,Q

By default, the base name (or design name) for the QTM files are specified to the create_qtm_model
command (ADDSUB).
save_qtm_model creates a library DB file, i.e., basename_lib.db (in our case, ADDSUB_lib.db).
You can use the “-output” option with save_qtm_model to change the name of the file.
Using QTM 7-15
pt_shell> lappend link_path ADDSUB_lib.db

pt_shell> current_design TOP
TOP
TOP
U1
U1
add_subN / Y
4
A /
4 carry_borrow
B /
4
Clk ADDSUB
ADDSUB

Reporting QTM 7-16
pt_shell> report_cell
Attributes:
n - noncombinational
…other attributes...
E - extracted timing model
S - Stamp timing model
Q - Quick timing model (QTM)
Cell Reference Library Area Attributes

-------------------------------------------------------------
U1 ADDSUB ADDSUB_lib 0.00 n,Q
-------------------------------------------------------------
Total 1 cells 0.00
Zero Area

QTM Parameters in the Timing Report 7-17
pt_shell> report_timing –from [all_inputs]

U1/Clk (ADDSUB) 9.90 r
----------------------------------------------------------
----------------------------------------------------------
slack (MET) 0.65

create_qtm_constraint_arc –setup –edge rise –from Clk –to {A[3:0] B[3:0] add_subN} –value 6.
Which of the following is (are) NOT specified when creating a QTM:

a) Design input, output port names
b) Timing from an input to output
c) Functionality of an output in terms of input(s)
d) Input port load, output port drive
Under what circumstance(s) is a QTM used? Circle all that apply:

a) The gate level netlist of a block is too large for PrimeTime
b) The gate level netlist of a block has been verified for timing and stable
c) Inter block net parasitics are to be extracted for a more accurate block
synthesis
d) RTL code for one of the blocks in Functional core is not yet available
e) 3rd party IP is not yet available
Circle whichever is (are) correct:

a) A QTM library file can be read into PrimeTime memory using read_verilog
b) A QTM library file is specified in the link_path variable

Unit Review 7-19
You will be given a design specification,

from which you will create a quick timing
model

Agenda: Day Two 8-1

2
8 Performing STA
9 Summary
10 Customer Support
Performing Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 8-1 Unit 8: Performing Static Timing Analysis
MOTIVATIONS 8-2
EFFICIENCY: report_timing is NOT the most efficient

report to uncover and direct solution efforts towards
obtaining zero violations in the design
COMPLETENESS: report_timing only uncovers

timing violations. DRC, Pulse width and Max skew
violations are NOT uncovered by the report_timing

Unit Objectives 8-3
Quickly find out the scope of violations (5 vs. 5000

violations in the design)
Do a complete analysis to identify Timing and DRC
violations
Identify bottleneck blocks in the design as candidates for
re-synthesis
Provide “Info Reports” for the largest violations on input
paths, reg-to-reg paths and output paths

Gate-Level
Netlist
Technology
Setup
Libraries
File
Timing
.db format
Log,
Reports Script
Files
Our Focus
Having applied all the inputs to PT, the goal is to generate various STA reports to analyze for Timing
and Constraint violations.
READ
READ
CONSTRAIN
CONSTRAIN
EXCEPTIONS
EXCEPTIONS
CHECK
CHECK
STA: Any Violations?
Our Focus ANALYZE

ANALYZE

Three Analysis Techniques 8-6
report_constraint –all report_bottleneck
1 Violations 2
Constraint Report Bottleneck Report
s
ion
lat
O
K
Vio
3
Timing Report
report_timing

NOTE: The arrows are only a recommended sequence of generating reports. All 3 reports can be
generated without following the indicated sequence. Bottleneck report can be generated only if there
are violations.
Given a floor planned Functional Core, you need to identify if there are any Timing/DRC violations
and provide information to guide the iterative design decision. The goal of Analyze is to generate
Timing and Constraint violation reports. In this unit, you will invoke 3 PT reports in the appropriate
order.
You will find answers to the following scenarios:
If I had started with a Timing Report that indicated no violations, Would I be done?
If I had started with a Constraint Report that indicated no violations, Would I be Done?
What is the magnitude and percentage of violations between registers and at the interface?
You will investigate causes for the violations due to: poor partitioning, excessive net fanout, larger
capacitance load, slower transition time and so on.
You will identify bottleneck block(s) for design budgeting and re-synthesis.
CHECK Before you Analyze 8-7
Check the design to assure it is fully constrained
To identify problems with design constraints:

check_timing [-verbose]
✔ Missing clock definitions?

✔ Ports with missing input delay?
✔ Unconstrained endpoints for setup?
✔ Input /Output delay set without a
reference clock?
✔ Combinational feedback loops?
✔ And more …

Example:
Use “check_timing –no_clock” to quickly determine if all the Register to Register paths have been
constrained.
ANALYZE Step1: Constraint Report 8-8
“report_constraints” shows all types of violations in the design:

Setup
Hold
DRC
Pulse Width …
The default is to show the longest violation of each type:

max_delay/setup 0.61 (VIOLATED)
min_delay/hold 0.00
sequential_clock_pulse_width 0.00
max_capacitance 2.16 (VIOLATED)
max_transition 41.18 (VIOLATED)
How many are the design rules in the above report?

Constraint Report: All Violations 8-9
“report_constraints –all_violators” shows all the violations

in the design and where the violations are:
max_delay/setup ('Clk' group) Timing Violations
Endpoint Slack
I_ALU/Zro_Flag_reg/D0 -0.28 (VIOLATED)
I_STACK_TOP/TOS_int_reg[0]/D0 -0.22 (VIOLATED)
max_capacitance DRC Violations
Required Actual
Pin Capacitance Capacitance Slack
Clk 0.00 0.03 -0.03 (VIOLATED)
Reset 0.00 0.01 -0.01 (VIOLATED)
If the report is empty, there are no violations.

The “-all_violators” shows the summary of all violations, one line per violation. If the report is
empty, then there are no violations. You need to generate a timing report to understand the longest
path (with constraints) that has the smallest amount of positive slack.
Constraint Report: Things to Investigate 8-10
How many end points violate Timing?
pt_shell> redirect vio.rpt \

{report_constraint -all -max_delay -min_delay}
unix% grep “VIOLATED” vio.rpt | wc -l
What is the largest violation?
How serious is it compared to the Clock Period?
Are the end points registers or output ports?

Are there any design rule constraint (DRC) violations?
report_constraint -all -max_capacitance -max_fanout
Are the DRC violations real?

Are max_capacitance violations in the previous page real?

Each violation in the “vio.rpt” contains the pattern “VIOLATED”.

An example of the output of the command:
grep “VIOLATED” vio.rpt | wc –l
67
max_delay/setup ('Clk' group)
Endpoint Slack
I_ALU/Zro_Flag_reg/D0 -0.28 (VIOLATED)
I_STACK_TOP/TOS_int_reg[0]/D0 -0.22 (VIOLATED)
max_capacitance
Pin Req. Capacitance Actual Capacitance Slack
Clk 0.00 0.03 -0.03 (VIOLATED)
Reset 0.00 0.01 -0.01 (VIOLATED)
Are the DRC violations real?

For example: The previous page shows that a max_capacitance of 0 was applied to the Clk
and Reset ports – this is not realistic and points to a potential problem with constraints
1 Violations 2
s
ion
lat
O
K
Vio
3
Timing Report
report_timing
Constraint report showed a lot of timing violations. What next?

Control the temptation of invoking “report_timing” when you have a lot of violations. It is useful to
determine if the violations have anything in common, for example: a heavily loaded cell (or) a poorly
synthesized subblock.
ANALYZE Step-2: Bottleneck Analysis 8-12
Bottleneck analysis identifies the cells (or blocks) which are involved
in multiple violations
Bottleneck
Cell List
Bottleneck
Histogram
report_bottleneck -cost_type path_count:

path_count (the default cost_type) uses the number of violating paths
through the cell as the bottleneck cost

pt_shell> report_bottleneck
****************************************
Report : bottleneck
-cost_type path_count
-max_cells 20
-nworst_paths 100
****************************************
Bottleneck Cost = Number of violating paths through cell
Bottleneck Cell Reference Cost
------------------------------------------------------------
U2/U104 EO 100.00
U2/U70 AN2 100.00
…...
U4/core Y_core 100.00
U3/U106 OR3 99.00
U5/U210 ND2 93.00
U5/U207 ND2I 56.00
There are 2 other cost types (in addition to path_count).
•path_cost uses the total cost of violating paths through the cell as the
bottleneck cost.
•endpoint_cost uses the total cost of violating endpoints in the fanout of the
cell as the bottleneck cost.
What can I do with Bottleneck Analysis? 8-13
Identify subblock(s) containing bottleneck cells:
Refine subblock(s) by resynthesizing them
Replace the subblock with a newly synthesized one:
read_db ALU1.db
current_design RISC_CORE
swap_cell U1_ALU ALU1.db:ALU
A/D DSP CODEC
RISC_CORE U1_ALU
ALU1.db
MPEG
USB RAM
Functional Core
Core Clock
Re-generate Constraints report (“What if” analysis)

NOTE that PrimeTime only identifies what blocks are causing violations. PT cannot fix the problem.
This is only a “What-if” analysis. To fix the problem, perform Design budgeting in Design Compiler
and resynthesize the block using the constraints obtained after design budgeting.
NOTE that only the filename of the new design is changed to ALU1.db (example), the design name is
still the same, ALU.
1 Violations 2
s
ion
lat
O
K
Vio
3
Timing Report
report_timing
Bottleneck report identified a subblock to be fixed. What else?

Before asking a synthesis engineer to resynthesize the bottleneck block, you can now provide him/her
with more information regarding the context of block being used and where to find the violations.
For example:
Are the violations found at the I/O interface?
Between registers?
Between specific start and end points within the design?
Analyze Step 3: Timing Reports 8-15
Timing report (report_timing) command finds all the

individual timing paths in the design for analysis
Each path is analyzed for timing twice:

Once for a rising edge input
Once with a falling edge input
The critical path (worst violator) for each clock group is

found and reported (default)
Constrained w.r.t CLK3
A path1 D Q path2 D Q path3 Z

FF2 FF3
CLK1 QB QB
CLK2
MY_DESIGN
By default, how many paths of MY_DESIGN would be reported?

MY_DESIGN
Constrained w.r.t CLK
A path1 D Q path2 D Q path3 Z

FF2 FF3
CLK QB QB
CLK Constrained w.r.t CLK
path4
Timing Paths
Which path will be reported by default, given the following?

O Path Delays : 2 ns (path1), 3 ns (path2), 2.5 ns (path3), 2 ns (path4)
O CLK period = 5 ns
O Input delay (ref. CLK) on A = 1.5 ns, output delay (ref CLK) on Z = 1 ns
O Setup (FF2, FF3) = 0.5 ns, Clk-Q (FF2, FF3) = 0.5 ns
O Assume zero net delays

Grouping the Timing Paths 8-17
MY_DESIGN
MY_DESIGN
CLK1
A path1 D Q path2 D Q path3 Z path1
FF2 FF3
CLK1 QB QB
CLK2 CLK2 default
path2 path3
path4 path4
Timing Paths Path Groups
Timing paths are grouped into path groups by the clocks

controlling their endpoints:
The “default” group contains paths not captured by a clock (OR)
not belonging to any user defined path group
PrimeTime organizes its timing reports by path groups

Creating User Defined Path Groups 8-18
MY_DESIGN
MY_DESIGN
IN OUT
A path1 D Q path2 D Q path3 Z path1 path3
FF2 FF3
CLK QB QB
CLK CLK COMBO
path4 path2 path4
Timing Paths Path Groups

A Timing path can ONLY belong to a one path group
Always create groups to organize the timing paths meaningfully
group_path -name IN -from [all_inputs]

group_path -name OUT -to [all_outputs]
group_path -name COMBO -from [all_inputs] \
-to [all_outputs]
group_path command can be invoked from pt_shell or the command window of PT GUI. There is no
menu option in the GUI for group_path.
Once you have created the groups, you can generate grouped timing reports as follows:
report_timing -group CLK
report_timing -group IN
report_timing -group OUT
report_timing -group COMBO
Edge Sensitivity in Path Delays 8-19
What are the longest and shortest paths through these two
inverters?
library: pin(Z) library: pin(Z)

intrinsic_rise : 1.8; intrinsic_rise : 1.5;
intrinsic_fall : 0.5; intrinsic_fall : 0.7;
U1 U2
There is an “edge sensitivity” (called unateness) in a cell’s

timing arc.
PT applies the appropriate unateness to each cell in a timing path.

Example Timing Report: Circuit Diagram 8-20
D Q U2
U12
Z U23
INV Z presum_reg[1]
data1 ND2 Z
ND2 D Q
FD1
clk1
RISC_CORE
current_design RISC_CORE
report_timing -from data1 -to presum_reg[1]/D

Timing Report: Path Information Section 8-21
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : RISC_CORE
****************************************
Startpoint: data1
(input port clocked by clk1)
Endpoint: presum_reg[1]/D
(rising edge-triggered Flip-Flop clocked by clk1)
Path Group: clk1
Path Type: max
A timing report consists of four sections:

1.Path Information section
2.Path Delay section
3.Path Requirement section
4.Summary section
Path information section provides you with answers to several questions:

-What type of path is being reported (input, reg-reg, output, combo?)
-What path group does path belong to?
-Is it a setup or hold time report?
Timing Report: Path Delay Section 8-22
Individual Contribution Running Total of

to Path Delay the Path Delay
Point Incr Path

----------------------------------------------
Cells input external delay 2.00 2.00
in data1 (in) 0.00 2.00 r
Path U2/Z (INV) 1.54 3.54 f
U12/Z (ND2) 0.98 4.52 r
U23/Z (ND2) 0.66 5.18 f
presum_reg[1]/D (FD1) 0.81 5.99 f
Net & Cell Delays Total Delay

Are Combined for the Path Unateness
0.54
1.0

Path Delay section provides you with answers to several questions:

What is the delay through each cell on the path?
What cells have been used from the library?
What is the path delay (or data arrival time)?
What unateness (or edge sensitivity) has chosen for STA on this path?
Does the path go through several (and how many) combinational hierarchies (snake path)?
In the default timing report, the cell delay is combined with the delay of the preceding net.
You can show the net and cell delays separately by using: report_timing –input_pins.
Timing Report: Spot the Whales 8-23
Spot the whales in the timing report: Where are they? What are they? And why?
Point Incr Path

clock (input port clock) (rise edge) 0.00 0.00
input external delay 22.40 22.40 f
addr31 (in) 0.00 22.40 f
u_proc/address31 (proc) 1.08 23.48 f Rather late arrival for
u_proc/u_dcl/int_add[7] (dcl)
u_proc/u_dcl/U159/Q (NAND3H)
0.00
0.62
23.48
24.10
f
r a 30 ns period!
u_proc/u_dcl/U160/Q (NOR3F) 0.75 24.85 f
u_proc/u_dcl/U186/Q (AND3F) 1.33 26.18 f
u_proc/u_dcl/U86/Q (INVF) 0.64
1.36
26.82
28.17
r
f
Six buffers back
u_proc/u_dcl/U135/Q (NOR3B)
u_proc/u_dcl/U136/Q (INVF) 0.49 28.67 r to back?!
u_proc/u_dcl/U100/Q (NBF) 0.87 29.54 r
u_proc/u_dcl/U95/Q (BF) 0.44 29.98 f
u_proc/u_dcl/U96/Q (BF) 0.45 30.43 r
u_proc/u_dcl/ctl_rs_N (dcl) 0.00 32.21 r
u_proc/u_ctl/ctl_rs_N (ctl) 0.00 32.21 r
u_proc/u_ctl/U126/Q (NOR3B)
u_proc/u_ctl/U120/Q (NAND2B)
1.78
1.07
33.98
35.06
f
r 11 ns delay for an OR
u_proc/u_ctl/U99/Q (NBF)
u_proc/u_ctl/U122/Q (OR2B)
0.88
10.72
35.94
46.67
r
r
gate is not good
u_proc/u_ctl/read_int_N (ctl) 0.00 46.67 r
u_proc/int_cs (proc) 0.00 46.67 r
u_int/readN (int) 0.00 46.67 r
u_int/U39/Q (NBF) 1.29 47.95 r Four hierarchical
u_int/U17/Q (INVB) 1.76 49.71 f
u_int/U16/Q (AOI21F) 2.49 52.20 r partitions
u_int/U60/Q (AOI22B) 1.43 53.63 f
u_int/U68/Q (INVB) 1.81 55.44 r
u_int/int_flop_0/D (DFF) 0.00 55.44 r

Timing Report Exercise 1/2 8-24
Point
Point Incr
Incr Path
Path How
Howmany
many
--------------------------------------------------
-------------------------------------------------- hierarchical
hierarchical
clock
clock CLOCK
CLOCK (rise
(rise edge) 0.00 0.00
clock network delay
edge)
(ideal)
0.00
0.00
0.00
0.00 boundaries
boundariesdoes
doesthis
this
U3/OUTPUT_reg[12]/CP
U3/OUTPUT_reg[12]/CP (FD1) (FD1) 0.00
0.00 0.00
0.00 rr path traverse?
path traverse?
U3/OUTPUT_reg[12]/Q
U3/OUTPUT_reg[12]/Q (FD1)(FD1) 3.97
3.97 3.97
3.97 ff
.. .. .. .. .. .. .. .. .. ..
U3/U148/Z
U3/U148/Z (IV)
(IV) 2.90
2.90 17.25
17.25 rr
U3/ZERO (REGCNT)
U3/ZERO (REGCNT) 0.00
0.00 17.25
17.25 rr
U5/REGCNT_ZERO (CONTROL)
U5/REGCNT_ZERO (CONTROL) 0.00
0.00 17.25
17.25 rr Do
Doany
anycells
cellsappear
appear
U5/U232/Z (ND2) 0.64 17.88
17.88 ff
U5/U232/Z (ND2)
U5/U232/Z (XOR2)
0.64
2.77 19.65 to have a relatively
to have a relatively
U5/U232/Z (XOR2) 2.77 19.65 ff
U5/U236/Z
U5/U236/Z (IVA)
(IVA) 1.75
1.75 21.15
21.15 rr large
largedelay?
delay?
U5/U193/Z (ND4)
U5/U193/Z (ND4) 1.38
1.38 22.53
22.53 ff
U5/Y_CONTROL[1] (CONTROL)
U5/Y_CONTROL[1] (CONTROL) 0.00
0.00 22.53
22.53 ff
U4/OPERATION[1]
U4/OPERATION[1] (Y) (Y) 0.00
0.00 22.53
22.53 ff
U4/core/MUXOUT[1] (Y_core)
U4/core/MUXOUT[1] (Y_core) 7.24
7.24 29.77
29.77 rr
U4/MUXOUT[1]
U4/MUXOUT[1] (Y)(Y) 0.00
0.00 29.77
29.77 rr
U2/DATA[12] (UPC)
U2/DATA[12] (UPC) 0.00
0.00 29.77
29.77 rr
U2/U73/Z (ND2)
U2/U73/Z (ND2) 0.74
0.74 30.51
30.51 ff
.. .. .. .. .. .. .. .. .. ..
U2/U62/Z
U2/U62/Z (AN2)
(AN2) 1.92
1.92 38.90
38.90 ff
U2/OUTPUT_reg[2]/D
U2/OUTPUT_reg[2]/D (FD1)(FD1) 0.00
0.00 38.90
38.90 ff
data arrival time
38.90
Timing Report Exercise 2/2 8-25
Does
Doesthe
thepath
pathmeet
meettiming?
timing?
What
Whatis
isthe
thepercentage
percentageviolation?
violation?
clock
clock CLOCK
CLOCK (rise
(rise edge)
edge) 30.00
30.00 30.00
30.00
clock network delay (ideal)
clock network delay (ideal) 0.00
0.00 30.00
30.00
clock
clock uncertainty
uncertainty 0.00
0.00 30.00
30.00
U2/OUTPUT_reg[2]/CP
U2/OUTPUT_reg[2]/CP (FD1)
(FD1) 30.00
30.00 rr
library
library setup
setup time
time -0.80
-0.80 29.20
29.20
data required time
29.20
---------------------------------------------------------------
---------------------------------------------------------------
data
data required
required time
time 29.20
29.20
data arrival time
-38.91
---------------------------------------------------------------
---------------------------------------------------------------
slack
slack (VIOLATED)
(VIOLATED) -9.71
-9.71

Timing Report for Setup and Hold Checks 8-26
Setup Check Report (default) Analysis is performed to identify

report_timing -delay max The slowest paths using setup time,
worst case Cell delays, WLM and OC.
Hold Check Report
report_timing -delay min Analysis is performed to identify
the fastest paths using library
Hold time.
Setup and Hold Check Reports
report_timing -delay min_max The report contains the analysis of
2 paths: slowest and the fastest.
Multiple Timing Reports
report_timing -max_paths 10 The report contains the analysis of
report_timing -nworst 10 at most 10 slowest paths.
report_timing by default reports ONE path with the

worst slack within each path group.
Using large numbers for -nworst and -max_paths can lead to longer run times.
-nworst paths_per_endpoint
Specifies the number of paths to be reported per endpoint. Allowed values are 1 to 2000000; default
is 1.
-max_paths count
Specifies the number of paths to be reported per path group. Allowed values are 1 to 2000000;
default is 1.
You can also generate non default timing reports by specifying the start or end or both start and end
points:
report_timing -from [all_inputs]
report_timing -to [all_outputs]
report_timing -from [all_inputs] -to [all_outputs]
Example -nworst vs. -max_paths 8-27
WNS = -0.3
WNS = -0.25
WNS = -0.15
WNS = -0.05
How many timing paths are in this picture?

Which paths will be reported with report_timing -max_paths 2
What changes with report_timing -nworst 2 -max_paths 2

There are at least 4 timing paths in this picture.
report_timing -max_paths 2 will generate two reports considering only one path per endpoint. So in
this example it will give you the paths with WNS = -0.3 and WNS = -0.15.
report_timing -max_paths 2 -nworst 2 will generate two reports considering at least two paths per
endpoint. So in this example it will give you the paths with WNS = -0.3 and WNS = -0.25.
Timing Report: Displaying path details 8-28
report_timing -input_pins -nets \
-capacitance –transition_time
Point Fanout Cap Trans Incr Path

-----------------------------------------------------------------------------
-input_pins Net delay: Actually 0.004
…...
I_ALU/U1099/A (inv1a3) 0.31 0.00 0.61 r
I_ALU/U1099/Y (inv1a3) 0.24 0.18 0.79 f
I_ALU/N6422 (net) 3 0.04
…..
-nets -capa -tran Cell delay

-input_pins: Shows the net and cell delays by showing the timing to a cell’s input pins in addition
(default) to the output pins.
-nets: Show net fanout
-capacitance: Show capacitance
-transition_time: Show Transition time
report_timing -input_pins –significant_digits 3
Point Incr Path
--------------------------------------------------------------------
I_PRGRM_DECODE/Crnt_Instrn[25] (PRGRM_DECODE) 0.000 2.040 f
I_PRGRM_DECODE/U362/A (buf1a2) 0.030 2.070 f
I_PRGRM_DECODE/U362/Y (buf1a2) 0.450 2.530 f
report_timing -nets
---------------------------------------------------------------
I_PRGRM_DECODE/Crnt_Instrn[25] (PRGRM_DECODE) 0.000 2.04 f
I_PRGRM_DECODE/Crnt_Instrn[25] (net) 0.000 2.040 f
I_PRGRM_DECODE/U362/Y (buf1a2) 0.480 2.530 f
I_PRGRM_DECODE/n984 (net) 4 0.000 2.530 f
I_PRGRM_DECODE/U371/Y (xor2a0) 0.560 3.090 f
Lab Overview 8-29
You are provided with a design netlist that

LAB
does not meet timing. Another set of
subblocks that were improved for timing
possibly at the expense of area are also
provided.
45 min You are in charge of providing STA reports
to the synthesis engineer and find if you
can meet timing using some or all of the
improved blocks.

Review (1/2) 8-30
State 3 techniques in the correct order for analyzing

constraint violations in a design.
____________________________
____________________________
____________________________
List 2 types of violations detected by the constraint report.

_____________________
_____________________
After a bottleneck analysis, using what command can you

replace a violating block (or cell) with another?
____________________

Review (2/2) 8-31
How can you generate a single report containing one setup

and one hold violations.
____________________
How do you obtain the following details from a Timing report:

Cell and net delays: _____________________
Net fanout: _____________________
Net capacitance: _____________________
Cell input transition time: _____________________
Cell output transition time: _____________________
Name 2 methods by which you can obtain timing report of a

path that starts at an input port and ends at an output port of
a design. (Hint: Use of –from and –to options)
_____________________
_____________________

8-32
APPENDIX: Reporting via PT GUI

Constraint Report 8-33
1
Reports-> OK
All Violators
2 3
Analysis->
Constraint

Bottleneck Report 8-34
1
Reports->
Histograms 2
Timing
Bottleneck

Timing Report 8-35
1
Reports->
Analysis->
Timing path
2
OK

Agenda: Day Two 9-1
DAY Unit I/O paths and Exceptions Lab

2
8 Performing STA
9 Summary
10 Customer Support
Conclusion
PrimeTime: Introduction to Static Timing Analysis 9-1 Unit 9: Conclusion

Gate-Level Exceptions
Constraints
Netlist
Technology
Setup
Libraries
File
Timing
PrimeTime Models (QTM)
Constraint
Reports Script
Log
File Conclusion

What information would you obtain from the following

timing report?
report_timing -input -nets -sign 3 -path full_clock
________________
________________
________________
Which one of the following is an odd man out, why?

read_db ____________
link_design ____________
link_path ____________
create_clock ____________
Conclusion

Checklist before invoking PrimeTime 9-4
n .synopsys_pt.setup file:
l Search_path and link_path set?
l What will be my Log file name?
n Directory Structure (Ex: Libs, DB, Scripts, Reports)
n Gate Level Netlist:

l Format of the netlist (DB, VHDL, Verilog)
n Technology Library (Same as used with DC)
n Constraints (Same as used by DC)
n Timing Exceptions (same as used with DC)
n Quick Timing Models (QTMs as needed)
Conclusion

What Constraints READ

READ How do I READ my design
do I need? into PT memory?
CONSTRAIN
CONSTRAIN
How can I check if my

EXCEPTIONS
EXCEPTIONS Constraints & Exceptions
are Correct?
Are there any
Timing Exceptions? CHECK
CHECK
STA: Any Violations?

ANALYZE
ANALYZE
Conclusion

Identify the following commands as belonging to which of the

5 steps in the STA flow.
l check_timing _____________________
l link_design _____________________
l create_clock _____________________
l report_constraint _____________________
l set_false_path _____________________
Write 2 Timing Constraints that DO NOT affect timing of

internal Register to Register paths.
________________________________________
________________________________________
Write down the 3 Timing constraints whose absence could be

detected by the check_timing command.
________________________________________
________________________________________
Conclusion

Hints on Improving Runtime/Memory 9-7
n Read only the “Netlist” from a DB file:

l read_db -netlist_only design.db
l source -echo -verbose design_constraints.pt
n Remove sub designs when linking a large design:

l link_design -remove_sub_designs
l Caution: Cannot access subdesigns anymore
n Avoid using multiple wild cards with exceptions:

l set_false_path -to my_reg[*]/* ; # NO
l set_false_path -to my_reg[1]/*; # OK
n Remove unused timing exceptions from memory:

l reset_path -from I_ALU/FF3/Q
n Use Timing models (QTM):

l ILM and ETM are covered in PrimeTime: Chip level class
Conclusion

Synopsys Online Documentation 9-8
%SOLD
acroread \
$SYNOPSYS/doc/online/top.pdf
Conclusion

Related Workshops 9-9
n PrimeTime CHIP Level Synthesis Workshop
n PrimeTime Signal Integrity Workshop
Conclusion

Congratulations! 9-10
PrimeTime
Ready
n You can download Labs from our Web site
n Try an online Quiz once you are back at work:

l www.synopsys.com/services/education/pt_test.html
Conclusion
To download the labs go to: www.synopsys.com

-> then follow the link: Education & Training
-> Look for Download Labs
You will need to provide your SolvNET ID and Password (See the Customer Support slides
that follow).

Job Name PrimeTime: Intro to Static Timing Analysis Lab Guide
Part Numbers 34000-000-S36
Synopsys Contact Barbara Zimmerman 650 584-4021
Collating Sequence Comments

Double sided copies
White Wire-0 binding
Synopsys Covers
Number of Pages
Cover 1 Pre-printed Die Cut Cover
PrimeTime ISTA Cove 2 White Stock

Lab 1 22 Title on light blue body on white stock
Rear Cover 1 Pre-printed Rear Cover
Total page count 113

Double sided print 57

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i-1

Synopsys Customer Education Services

PrimeTime: Introduction to Static Timing Analysis i-1 Unit i: Welcome

Welcome and Introductions

Materials you should have:

PrimeTime: Introduction to Static Timing Analysis i-2 Unit i: Welcome

A/D DSP CODEC

Functional Core Core Clock

PrimeTime: Introduction to Static Timing Analysis i-3 Unit i: Welcome

Design or Verification engineers who perform STA at the

Little or no formal experience with PrimeTime

Little or no formal experience with Design Compiler

Planning to take the “PrimeTime: Chip level STA” workshop

You are here PrimeTime:

Little or no formal experience with Design Compiler.

PrimeTime: Introduction to Static Timing Analysis i-4 Unit i: Welcome

ASYNCH Synthesized RAM (Timing

Functional CORE constitutes “most” of the CHIP containing:

Parasitics are supplied in SPEF (Standard Parasitic Extraction Format).

At the full-chip level one must consider the following issues:

PrimeTime: Introduction to Static Timing Analysis i-5 Unit i: Welcome

Generate STA Timing

PrimeTime: Introduction to Static Timing Analysis i-6 Unit i: Welcome

Design Compiler Physical Compiler

Mapped netlist Placed netlist

PrimeTime CHIP Architect

STAMP Parasitics, SDF

PathMill 3rd Party Layout

PrimeTime: Introduction to Static Timing Analysis i-7 Unit i: Welcome

Performing basic 5 step Static Timing Analysis (STA) flow

Applying required constraints and exceptions and

Creating a Quick Timing Model (Unit 7)

Analyzing in detail for timing, design rules and timing

PrimeTime: Introduction to Static Timing Analysis i-8 Unit i: Welcome

Understanding of digital IC design

Familiarity with UNIX, X-Windows and Unix-based

PrimeTime: Introduction to Static Timing Analysis i-9 Unit i: Welcome

1 Introduction to Static Timing Analysis

2 Writing Basic Tcl Constructs in PT

4 Constraining Internal Reg-Reg Paths

PrimeTime: Introduction to Static Timing Analysis i-10 Unit i: Welcome

DAY Unit I/O Paths and Exceptions Lab

5 Constraining I/O Interface Paths

6 Specifying Timing Exceptions

7 Introduction to Timing Models (QTM)

PrimeTime: Introduction to Static Timing Analysis i-11 Unit i: Welcome

PrimeTime: Introduction to Static Timing Analysis i-12 Unit i: Welcome

PrimeTime: Introduction to Static Timing Analysis i-13 Unit i: Welcome

Icons used in this workshop

PrimeTime: Introduction to Static Timing Analysis i-14 Unit i: Welcome

Lab Exercise Group Exercise

For further reference

PrimeTime: Introduction to Static Timing Analysis i-15 Unit i: Welcome

Hint, Tip or Suggestion Note

PrimeTime: Introduction to Static Timing Analysis i-16 Unit i: Welcome

| Indicates a choice among alternatives, such as low | medium | high

PrimeTime: Introduction to Static Timing Analysis i-17 Unit i: Welcome

RTL (Register Transfer Level)

PrimeTime: Introduction to Static Timing Analysis i-18 Unit i: Welcome

VCS VCS Verilog Simulator

PrimeTime: Introduction to Static Timing Analysis i-19 Unit i: Welcome

CTS Clock Tree Synthesis

PrimeTime: Introduction to Static Timing Analysis i-20 Unit i: Welcome

New in 2.2 SLE Chip

What is used as index to calculate R and C from a WLM?

In a Non-Linear Delay Model (NLDM), cell delay is a function

Using the 300KGATES WLM provided in the notes below,