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ELECTRONICS ENGINEERING
“CENTRE OF
EXCELLENC
E”
Bengaluru-560059
Bachelor of Engineering in
Electronics and
Electronics
Engineering2022-2023
RV COLLEGE OF ENGINEERING®, BENGALURU-59
(Autonomous Institution Affiliated to VTU, Belagavi)
CERTIFICATE
Certified that the internship work titled “VLSI Design” is carried out by Kedar
Bhandarkar(1RV21EE031), a bonafide student of RV College of Engineering®,
Bengaluru, in partial fulfillment for the award of degree of Bachelor of Engineering
in Electrical and Electronics Engineering of the Visvesvaraya Technological
University, Belagavi during the year 2022-2023. It is certified that all
corrections/suggestions indicated for the Internal Assessment have been incorporated
in the internship report deposited in the departmental library. The internship report
has been approved as it satisfies the academic requirements in respect of internship
work prescribed by the institution for the said degree.
External Viva
2
INTERNSHIP CERTIFICATE
III
RV COLLEGE OF ENGINEERING®, BENGALURU-59
(Autonomous Institution Affiliated to VTU, Belagavi)
DECLARATION
Place: Bengaluru
Date:
Name Signature
VIJAY KIRAN U.R (RVCE22BEE401)
IV
ACKNOWLEDGEMENT
Gratitude & Appreciation are two important facets of life and while words are
seldom warm & tender enough to express one’s appreciation. We will try our best to
extend our gratitude to everyone, whom this achievement is owed.
I also thank our panel members C Sunanda, Assistant Professor, Dr. Madhu B R,
Assistant Professor and Prof Raja Vidya, Assistant Professor, Department of
Electrical and Electronics Engineering for their valuable comments and suggestions
during the phase evaluations.
Our sincere thanks to Dr. S G Srivani, Professor and Head, Department of Electrical
and Electronics Engineering, RVCE for the support and encouragement.
I express sincere gratitude to our beloved Principal, Dr. K. N. Subramanya for the
appreciation towards this project work.
I thank all the teaching staff and technical staff of Electrical and Electronics
Engineering department, RVCE for their help.
I take this opportunity to thank our family members and friends who provided all the
backup support throughout the project work.
V
ABSTRACT
A substation is an integral part of an electrical power system that is used to transmit and
distribute electric power. It functions as a hub for connecting various high-voltage
transmission lines and transforming the voltage to a lower level for distribution to homes and
businesses. Substations are usually equipped with transformers, circuit breakers, disconnect
switches, and other equipment necessary to control and protect the power system. Substations
can be classified into different types based on their location, voltage level, and purpose. They
play a crucial role in ensuring the reliability, stability, and security of the electrical grid.
VI
LIST OF FIGURES
3.1 IC Evolution 20
3.3 Y- Chart 21
6.1 FPGA 40
VI
I
TABLE OF
CONTENTS
Page no
Internship Certificate I
Declaration II
Acknowledgement III
Abstract IV
List of figures V
Chapter 1
Profile of the Organization 10
1.1 About of the company 11
1.2 History of the Organization 12
Chapter 2
Activities of the Organization 14
2.1 Internshala 15
2.2 Training 15
2.3 Internship 16
2.4 Partnerships 16
2.5 Awards and Achievements 17
2.6 Freshers Jobs 17
Chapter 3
Tasks Performed 18
3.1 Introduction to VLSI (WEEK-1) 19
3.1.1 History 20
3.1.2 Evolution 20
3.1.3 VLSI Design Flow 21
3.1.4 Types of Digital Systems/Circuits 23
8
3.1.5 Software Used 24
3.2 Verilog (WEEK-2) 24
3.2.1 Structure 24
3.2.2 Datatype 24
3.2.3 Operators 25
3.2.4 Coding Styles 26
3.3 Combinational Circuits using Verilog (WEEK-3) 27
3.4 Sequential Circuits using Verilog (WEEK-4) 32
3.5 Finite State Machines (WEEK-5) 38
3.6 System Design using FPGA (WEEK-6) 39
3.7 Final Project (WEEK-7) 42
Chapter 4
Reflections 43
4.1 Final Project 44
4.2 Applications of VLSI
4.3 Technical skills acquired
9
VLSI Design
CHAPTER 1
PROFILE OF THE
ORGANIZATION
CHAPTER 1
PROFILE OF THE ORGANIZATION
The internship was carried out for 7 weeks on INTERNSHALA on the topic VLSI
Design, which is a process of creating an integrated circuit (IC) by combining thousands
of transistors into a single chip.
Internshala is an internship and online training platform, based in Gurgaon, India.
Founded by Sarvesh Agrawal, an IIT Madras alumnus, in 2011, the website helps
students find internships with organizations in India.
It is a private, employment website.
This is a technology company on a mission to equip students with relevant skills and
practical exposure through internships and online training. The practical – based online
training comes with 100% placement assistance and 1:1 doubt solving.
Internshala concentrates on helping students in learning, training, and garnering on-field
experience.
Services
The website helps students find internship with organization in India. It is
India’s no. 1 internship and training platform with 40000+ paid internships in
engineering, MBA, media, laws, arts and other streams.
CHAPTER 2
ACTIVITIES OF THE ORGANIZATION
CHAPTER 2
ACTIVITIES OF THE ORGANIZATION
This chapter focuses on the activities of the organization, Internshala. It puts forward the
activities like training, placement guarantee courses, fresher jobs, internships which help
many students and people searching for part time and full-time jobs, and other activities.
2.1 Internshala
The tagline of Internshala is ‘internships that matter’; it means that the company provides
you a platform for seeking meaningful and helpful internships. Internshala's mission is to equip
every student with practical skills and exposure so that they can build their dream careers. A
world where you do not have to wait till 21 to taste your first work experience Internshala
trainings certificate is recognized by over 1.8 lakh companies. The website helps students find
internship with organization in India. It is India’s no. 1 internship and training platform with
40000+ paid internships in engineering, MBA, media, laws, arts and other streams.
Internshala courses are largely divided into Summer Training and Winter Training.
Internshala offers different kinds of internships—full time, part-time, and work from home. The
top Internshala competitors are StuMagz, twenty19, Letsintern and Interworld. In 2011, the
website became a part of NASSCOM 10K Startups. In august 2016, Telangana’s non-profit
organization, Telangana Academy for Skill and Knowledge (TASK) partnered with Internshala
to help students with internship courses and career services. In September 2016, Team Indus,
Google XPRIZE shortlisted, partnered with Internshala for college outreach for its initiative,
Lab2Moon.
2.2 Training
Learn new-age skills are on the go with these short-term online trainings. Best online
courses with certificates like python, web development, digital marketing & more are available
at Internshala Trainings. Internshala Student Partner (ISP) is India's largest campus ambassador
program where college students get a chance to become the face of Internshala. This program
helps students learn, earn & grow at the same time while developing essential marketing and
communication skills.
2.3 Internship
It provides 10,000+ internships from great companies to give a kickstart to your career.
Internshala Trainings certificate is recognized by over 1.8 lakh companies. We get internship &
job preparation training free on purchase of any online training. It makes us job ready in 6
weeks. It has 1:1 Doubt Solving and rated 4.5+ by 5 Lakh Students. 6 Lac+ Students are
certified through intenshala trainings.
2.4 Partnerships
In August 2016, Telangana's not-for-profit organization, Telangana Academy for Skill and
Knowledge (TASK) partnered with Internshala to help students with internship resources and
career services.
In September 2016, Team Indus, Google XPRIZE shortlisted entity, partnered with Internshala
for college outreach for its initiative, Lab2Moon.
CHAPTER 3
TASKS PERFORMED
CHAPTER 3
TASKS PERFORMED
This chapter includes all the tasks performed in the internship which included quiz and module
test after each video and module respectively, a final test and project.
WEEK 1
Before the introduction of VLSI technology, most ICs had a limited set of functions they
could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic.
VLSI lets IC designers add all of these into one chip.
The electronics industry has achieved a phenomenal growth over the last few decades,
mainly due to the rapid advances in large scale integration technologies and system design
applications. With the advent of very large scale integration (VLSI) designs, the number of
applications of integrated circuits (ICs) in high-performance computing, controls,
telecommunications, image and video processing, and consumer electronics has been rising at a
very fast pace.
The current cutting-edge technologies such as high resolution and low bit-rate video and
cellular communications provide the end-users a marvellous number of applications, processing
power and portability. This trend is expected to grow rapidly, with very important implications
on VLSI design and systems design.
3.1.1 History
Integrated Circuits are tiny electronic circuit used to perform a specific electronic function.
The first integrated Circuit (IC) was invented by Jack Kilby in 1958. As suggested by Moore, the
capacity doubled roughly every 18 months. Today, a large single VLSI chip can contain over one
billion transistors. These days, VLSI chiefly comprises of Front-End Design and Back End
design. Front end design includes digital design using HDL and design verification through
simulation and other techniques. The backend design comprises of CMOS library design and its
characterization. It also covers the physical design and fault simulation.
3.1.2 Evolution
In April 1965, one of the co‐founders of Intel, Dr. Moore, predicted that the number of
components in an integrated circuit would double every year. Ten years later in 1975, he revised
his prediction to a doubling of every 2 years. Moore’s prediction, which is commonly known as
Moore’s law nowadays, has been widely used in the semiconductor and microelectronic
industries as a tool to predict the increase of components in a chip for the coming generations.
To
date, Moore’s law has been proven to be valid for more than half a century. Fig 2.1 depicts the
progressive trend of the integration level for the semiconductor industry.
The design process starts with a given set of requirements. Initial design is developed and
tested against the requirements. When requirements are not met, the design has to be improved.
If such improvement is either not possible o, then the revision of requirements and its impact
analysis must be considered. The Y-chart shown in Fig. 1.4 illustrates a design flow for most
logic chips, using design activities on three different axes (domains) which resemble the letter
Y.
The Y-chart consists of three major domains, namely:
behavioural domain.
structural domain.
geometrical layout domain.
The design flow starts from the algorithm that describes the behavior of the target chip.
The corresponding architecture of the processor is first defined. The next design evolution in the
behavioral domain defines finite state machines
(FSMs) which are structurally implemented with
functional modules such as registers and ALUs.
These modules are then geometrically placed onto
the chip surface using CAD tools for automatic
module placement followed by routing, with a
goal of minimizing the interconnects area and
signal delays. The third evolution starts with a
behavioral module description. Individual modules
are then
implemented with leaf cells. At this stage the Figure 5.3 Y-Chart
chip is described in terms of logic gates (leaf
cells), which can be placed and interconnected by using a cell placement & routing program. The
last evolution involves a detailed Boolean description of leaf cells followed by a transistor level
implementation of leaf cells and mask generation. In standard-cell based design, leaf cells are
FUNCTION DESIGN
In this stage, main functional units of the system and the
interconnect requirements between the units are
identified. The main purpose of this stage is to specify
system behavior, in terms of Input, Output, and Timing of
each unit.
LOGIC DESIGN
In this stage, the logic for the VLSI system is designed. It
includes, Boolean expressions, control flow, register
allocation, etc. The outcome is a RTL description that is
expressed in a Hardware Description Language (HDL) Figure 6.4 VLSI Design Flow
like VHDL and Verilog.
CIRCUIT DESIGN
The purpose of the circuit design is to develop a circuit representation based on the logic design.
FABRICATION
Fabrication process includes lithography, polishing, deposition, diffusion, etc. This process
consists of several steps and requires various masks.
PACKAGING
Packaging involves putting together the chips on a Printed Circuit Board (PCB) or a Multi-Chip
Module (MCM).
A digital logic circuit is defined as the one in which voltages are assumed to be having a
finite number of distinct values. Types of digital logic circuits are combinational logic
circuits and sequential logic circuits. These are the basic circuits used in most of the digital
electronic devices like computers, calculators, mobile phones.
All these gates are combined together to form a complicated switching circuit. In a
combinational logic circuit, the output at any instant of time depends only on present input at that particular insta
Combinational digital logic circuits are classified into three major parts – arithmetic or
logical functions, data transmission and code converter.
Unlike combinational circuits, the sequential circuits have memory devices in order to store
the past outputs. In fact, sequential digital logic circuits are nothing but combinational
circuit with memory. These types of digital logic circuits are designed using finite state
machine.
Types of sequential logic circuits Sequential digital circuits are classified into three
major parts as Event driven, Clock drive and Pulse driven.
Vivado Design Suite is a software produced by Xilinx for synthesis and analysis
of HDL designs, with additional features for system on a chip development and high-level
synthesis.
It provides a set of tools used to design, program, and debug Xilinx’s line of FPGAs.
WEEK - 2
3.2 Verilog
It is a hardware description language used for the design and analysis of digital circuits.
The syntax and structure of Verilog is similar to that of the C programming language.
It is case sensitive.
Verilog is also more compact since the language is more of an actual hardware modeling
language.
3.2.1 Structure
Module name always start with an alphabet or underscore.
o Body of the module: Here we can assign the relationship between the inputs &
outputs.
3.2.2 Datatypes
Integer: It is declared by predefined word “integer”.
Net:
o They have continuously changing value by the circuits that are driving them.
o Net datatype can be declared by the predefined word using “wire”. Ex: wire w1, w2
Vectors: They are used to declare ‘n’ bit values. Register or net can be declared as
vectors. For ex,,,,, to declare total as a register as a 8 bits whose initial value is decimal
12.
Array: Registers and integers can be written as arrays. It is used to store the collection of
similar type of values. Example: integer [4:0] total [0:3];
o Here total is an array of 4 elements and each element has an integer of size 5 bit
3.2.3 Operators
Arithmetic Operators
Shift Operators
Relational Operators
Concatenation Operators
Bitwise Operators
Replication Operators
Logical Operators
Conditional Operator
Reduction Operators
b) Structural description:
Verilog has inbuilt gates such as AND, OR, NOT, XOR, XNOR.
Example: module half_add(a, b, s, c);
input a, b; output s,c;
xor x1(s, a, b);
and a1(c, a, b);
endmodule
Here used 2 gates XOR is labelled by x1 and AND gate is labelled by a1. Output is
written first, followed by inputs of each gates.
c) Behavioral description:
In this style, output behaves with the change in the inputs.
Predefined words like “always” or “initial” are used.
Outputs are declared as registers.
Example: module half_add (a, b, s, c);
input a,b; output s,c; reg s,c;
always@(a,b);
begin
#10 s=a^b; Here #10= delay of 10 screen time
units. #10 c=a&b;
end
endmodule
WEEK - 3
module FA_gate (
input a, input b, input c,
output sum, output cout);
wire s1, s2, s3;
xor x1 (s1, a, b);
and a1 (s2, a, b);
xor x2 (sum, s1, c);
and a2 (s3, s1, c);
or o1 (cout, s2, s3);
endmodule
Figure 7.5 Full Adder Schematic
module RPA_4bit (
input [3:0] a, input [3:0] b,
input cin,
output [3:0] s, output cout);
wire c1, c2, c3;
FA_if d0 (a[0], b[0], c, s[0], c1);
FA_if d1 (a[1], b[1], c1, s[1], c2);
FA_if d2 (a[2], b[2], c2, s[2], c3);
FA_if d3 (a[3], b[3], c3, s[3], cout);
endmodule Figure 9.7 Ripple Carry Adder Schematic
module MUX4x1(
input i0, input i1, input i2,
input i3, input s1, input s0,
output y);
wire p,q;
MUX_2x1_gate d0 (i0, i1, s0,
p); MUX_2x1_gate d1 (i2, i3,
s0, q); MUX_2x1_gate d2 (p, q,
s1, y);
endmodule Figure 11.9 4x1 MUX Schematic
module DEMUX1x4(
input x, input s1, input s0,
output y0, output y1, output y2,
output y3);
assign y0 = x&(~s1)&(~s0);
assign y1 = x&(~s1)&(s0);
assign y2 = x&(s1)&(~s0);
assign y3 = x&(s1)&(s0);
Figure 13.11 1x4 DEMUX Schematic
endmodule
5) 8:3 Encoder
The 8:3 Encoder is also known as Octal to Binary Encoder. In 8:3 encoder, there is a total of
eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and
A2. In 8-input lines, one input-line is set to true at a time to get the respective binary code in
the output side.
module encoder_8to3(
input [7:0] y, input
enable, output reg [2:0]
a);
always @(*)
begin if (enable
== 0)
a = 8'b0; else
Figure 15.13 8:3 Encoder Schematic
begin case (d)
8'b00000001 : a = 3'y0;
8'b00000010 : a = 3'y1;
8'b00000100 : a = 3'y2;
8'b00001000 : a = 3'y3;
8'b00010000 : a = 3'y4;
8'b00100000 : a = 3'y5;
8'b01000000 : a = 3'y6;
8'b10000000 : a = 3'y7;
default : a = 3'y0;
endcase end end
endmodule
6) 3:8 Decoder
A 3 to 8 decoder has three inputs (A, B, C) and eight outputs (D0 to D7). Based on the 3
inputs one of the eight outputs is selected. The truth table for 3 to 8 decoder is shown in the
below table. From the truth table, it is seen that only one of eight outputs (D0 to D7) is
selected based on three select inputs.
module Dec3to8(
input a, input b, input c,
output y0, output y1, output y2,
output y3, output y4, output y5,
output y6, output y7, input E);
wire p,q;
Dec_2to4_En d0 (E, c,0,p,q);
Dec_2to4_En d1 (p, a,b, y0,y1,y2,y3);
Dec_2to4_En d2 (q, a,b,y4,y5,y6,y7);
endmodule Figure 17.15 3:8 Decoder Schematic
Gray Code system is a binary number system in which every successive pair of numbers differs
in only one bit. It is used in applications in which the normal sequence of binary numbers
generated by the hardware may produce an error or ambiguity during the transition from one
number to the next. For ex, the states of a system may change from 3(011) to 4(100) as- 011 —
001 — 101 — 100. So, there is a high chance of a wrong state being read while the system
changes from the initial state to the final state.
This could have serious consequences for the machine using the information. The Gray code
eliminates this problem since only one bit changes its value during any transition between two
numbers.
module GtoB_data(
8) 1-bit Comparator
A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central processing units (CPUs) and
microcontrollers (MCUs).
module comp_1bit(
input a, input b,
output g, output e, output s);
assign g = a&(~b);
assign e = a ~^ b;
assign s =
(~a)&b; endmodule
WEEK - 4
Asynchronous sequential circuit: These circuits do not use a clock signal but uses the pulses of
the inputs. These circuits are faster than synchronous sequential circuits because there is clock
pulse and change their state immediately when there is a change in the input signal.
Synchronous sequential circuit: These circuits uses clock signal and level inputs (or pulsed).
The output pulse is the same duration as the clock pulse for the clocked sequential circuits. Since
they wait for the next clock pulse to arrive to perform the next operation, so these circuits are bit
slower compared to asynchronous.
1) SR Latch Design
An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and
relies only on the state of the S and R inputs. In the image, we can see that an SR latch can be
created with two NOR gates that have a cross-feedback loop.
module SR_latch(
input s, input r,
output q, output qbar);
nor(q, r, qbar);
nor(qbar, s, q);
endmodule
2) SR Flip Flop
Design
The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and RESET.
The SET input 'S' set the device or produce the output 1, and the RESET input 'R' reset the
device or produce the output 0. The SET and RESET inputs are labeled as S and R,
respectively.
The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get back the flip
flop to its original state from the current state with an output 'Q'. This output depends on the set
and reset conditions, which is either at the logic level "0" or "1".
3) D Flip Flop
A D (or Delay) Flip Flop (Figure 1) is a digital electronic circuit used to delay the change of state
of its output signal (Q) until the next rising edge of a clock timing input signal occurs.
module DFF(
input D, input clk,
output Q); reg Q;
always@(posedge clk)
begin Q = D;
Figure 4.5 D Flip Flop Schematic
end endmodule
4) T Flip Flop
The T flip-flop is also called toggle flip-flop. It is a change of the JK flip-flop. The T flip flop is
received by relating both inputs of a JK flip-flop. The T flip-flop is received by relating the
inputs 'J' and 'K'. When T = 0, both AND gates are disabled.
module TFF(
input T, input clk, output Q); reg
Q; initial begin Q = 0; end
always@(negedge clk)
begin if (T == 0)
Q = Q; else Q = ~Q;
Figure 4.7 T Flip Flop Schematic
End endmodule
5) JK Flip Flop
A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This
feedback selectively enables one of the two set/reset inputs so that they cannot both carry an
active signal to the multivibrator circuit, thus eliminating the invalid condition.
module JKFF (
always@(posedge clk)
begin case({J,K})
2'b00: Q = Q; 2'b01: Q = 0;
module reg_4bit(
always@(negedge clk)
begin Q = D; end
endmodule
module Reg_4bit_str(
endmodule
Figure 4.12 Bidirectional Shift Register Schematic
WEEK – 5
1) Mealy machine: A Finite State Machine is said to be Mealy state machine, if outputs depend
on both present inputs & present states. The block diagram of Mealy state machine is shown in
the following figure.
2) Mealy machine: A Finite State Machine is said to be Moore state machine, if outputs depend
only on present states. The block diagram of Moore state machine is shown in the following
figure.
WEEK – 6
The full form of FPGA is “Field Programmable Gate Array”. It contains ten thousand to
more than a million logic gates with programmable interconnection. Programmable
interconnections are available for users or designers to perform given functions easily. There
are I/O blocks, which are designed and numbered according to function. For each module of
logic level composition, there are CLB’s (Configurable Logic Blocks).
CLB performs the logic operation given to the module. The inter connection between CLB
and I/O blocks are made with the help of horizontal routing channels, vertical routing
channels and PSM (Programmable Multiplexers).
The number of CLB it contains only decides the complexity of FPGA. The functionality of
CLB’s and PSM are designed by VHDL or any other hardware descriptive language. After
programming, CLB and PSM are placed on chip and connected with each other with routing
channels.
Advantages
The gate array (GA) ranks second after the FPGA, in terms of fast prototyping capability.
While user programming is important to the design implementation of the FPGA chip, metal
mask design and processing is used for GA. Gate array implementation requires a two-step
manufacturing process.
The first phase results in an array of uncommitted transistors on each GA chip. These
uncommitted chips can be stored for later customization, which is completed by defining the
metal interconnects between the transistors of the array. The figure given below shows the
basic processing steps for gate array implementation.
In most of the modern GAs, multiple metal layers are used for channel routing. With the use
of multiple interconnected layers, the routing can be achieved over the active cell areas. Here,
the entire chip surface is covered with uncommitted nMOS and pMOS transistors.
A standard cell-based design requires development of a full custom mask set. The standard cell
is also known as the polycell. In this approach, all of the commonly used logic cells are
developed, characterized and stored in a standard cell library.
A library may contain a few hundred cells including inverters, NAND gates, NOR gates,
complex AOI, OAI gates, D-latches and Flip-flops. Each gate type can be implemented in
several versions to provide adequate driving capability for different fan-outs.
Each cell is characterized according to several different characterization categories, such as,
In a full-custom design, the entire mask design is made new, without the use of any library. The
development cost of this design style is rising. Thus, the concept of design reuse is becoming
famous to reduce design cycle time and development cost.
The hardest full custom design can be the design of a memory cell, be it static or dynamic. For
logic chip design, a good negotiation can be obtained using a combination of different design
styles on the same chip, i.e. standard cells, data-path cells, and programmable logic arrays
(PLAs).
Practically, the designer does the full custom layout, i.e. the geometry, orientation, and
placement of every transistor. In digital CMOS VLSI, full-custom design is hardly used due to
the high labor cost. These design styles include the design of high-volume products such as
memory chips, high- performance microprocessors and FPGA.
WEEK – 7
Using the concepts of opcodes, inputs, & circuits, design an 8-bit arithmetic logic unit with an
ability to perform eight different operations.
CHAPTER 4
REFLECTIONS
CHAPTER 4
REFLECTIONS
4.1 Final Project
This chapter discusses about the results obtained during the internship and the learning outcomes
of the internship is also discussed in this chapter.
ALU
An arithmetic logic unit (ALU) is a major component of the central processing unit of a
computer system.
It does all processes related to arithmetic and logic operations that need to be done on
instruction words.
In some microprocessor architectures, the ALU is divided into the arithmetic unit (AU) and
the logic unit (LU).
An 8-bit arithmetic logic unit (ALU) is a combinational circuit that operates on two 8-bit
input buses based on selection inputs.
The ALU performs common arithmetic (addition and subtraction) and logic (AND, SHIFT,
XOR, and OR) functions.
These operations are common to all computer systems and thus are an essential part of
computer architecture.
It takes two 8-bit numbers as inputs and consists of different blocks for different operations.
All these blocks are connected to the MUX which gives the values from the operation blocks
as output based on the opcodes values on the selection lines.
Operations
The operations that the 8-bit ALU can perform are:
Addition
Logical AND, OR
Subtraction
Logical XOR, XNOR
Multiplication
Logical NOR, NAND
Division
Greater Comparison
Logical Shift Left, Shift Right
Equal Comparison
Rotate left, Rotate right
Verilog Code
In the Verilog code we have declared A and B as 8-bit inputs, ALU_Sel is the 4-bit opcodes
(selection lines), ALU_Result is the output. Using a case statement we have declared different
opcodes for 16 operations. To perform a particular operation we have to first use the opcode and
then declare the respective inputs.
always @(*)
begin
case(ALU_Sel)
4'b0000:ALU_Result = A + B ; // Addition
4'b0001:ALU_Result = A - B ; // Subtraction
//4'b0010:ALU_Result = A * B; // Multiplication
4'b0011: ALU_Result = A/B; // Division
4'b0100: ALU_Result = A<<1;// Logical shift
left
4'b0101: ALU_Result = A>>1;// Logical shift right
4'b0110: ALU_Result = {A[6:0],A[7]};// Rotate left
4'b0111: ALU_Result = {A[0],A[7:1]}; // Rotate
right 4'b1000: ALU_Result = A & B; // Logical and
4'b1001: ALU_Result = A | B;// Logical or
4'b1010: ALU_Result = A ^ B;// Logical xor
4'b1011: ALU_Result = ~(A | B);// Logical nor
4'b1100: ALU_Result = ~(A & B); // Logical
nand 4'b1101: ALU_Result = ~(A ^ B); // Logical
xnor
4'b1110: ALU_Result = (A>B)?8'd1:8'd0 ; // Greater
comparison 4'b1111: ALU_Result = (A==B)?8'd1:8'd0 ;// Equal
comparison default: ALU_Result = 0;
endcase
end
endmodule
Testbench
Testbench is nothing but the different waveforms we want to generate for our main code. Here
we first declare the inputs as registers and outputs as wires or nets, then we connect the main
module and testbench using module instantiation. Then we can use different test cases.
module alu_tb;
reg [7:0] A, B;
reg [3:0] ALU_Sel;
Dept of EEE, RVCE 49
VLSI Design
ALU_Sel=4'b0000;//add
A=8'b11111111; B=8'b00000000; // A = 0, B = 0
Schematic
In the diagram as we can see in the schematic diagram there are different circuits for various
operations and the MUX selects the output of the given operation based the particular 4-bit
selection line input.
Output
Addition
Here the selection line is 0000 which means the MUX will opt for addition output. So, the
A=255 and B=255 and the output sum is 510.
Subtraction
Here the selection line is 0001 which means the MUX will opt for subtraction output. So, the
A=240 and B=15 and the output difference is 225.
Logical Nand
Here the selection line is 1100 which means the MUX will opt for logical Nand. So, the
A=11110000 and B=00001111 and the output is 11111111.
Logical XOR
Here the selection line is 1101 which means the MUX will opt for logical Xor. So, the
A=11111000 and B=00000000 and the output is 10000111.
Here the selection line is 1110 which means the MUX will opt for a greater comparison
value. So, the A=15 and B=255 and the output is 0 (False).
Applications of VLSI
VLSI (Very-Large-Scale Integration) is a process used to create integrated circuits (ICs) that
contain a large number of transistors and other components on a single chip. Here are some of
the common applications of VLSI:
Digital Signal Processing (DSP) chips used in audio and video processing.
Microprocessors and microcontrollers used in computers, smartphones, and
other electronic devices.
Field-Programmable Gate Arrays (FPGAs) used for digital signal processing and
data communication applications.
Memory chips, such as Dynamic Random Access Memory (DRAM), Static
Random Access Memory (SRAM), and NAND flash memory.
Graphics Processing Units (GPUs) used in computer graphics, gaming, and
high- performance computing.
Network processors used in routers, switches, and other networking devices.
System-on-a-Chip (SoC) devices used in consumer electronics, wearable devices,
and Internet of Things (IoT) applications.
Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) used in
signal processing and data communication applications.
Automotive electronics, such as engine control units, ABS systems, and
infotainment systems.
Medical devices, such as implantable pacemakers and insulin pumps.
These are just a few examples of the wide range of applications of VLSI technology. As the
demand for more powerful, compact, and energy-efficient electronic devices continues to
grow, the importance of VLSI will continue to increase.
Here is a list of technical skills that are acquired after learning VLSI (Very-Large-Scale
Integration) Design:
Circuit design: Learning how to design and develop various types of digital and
analog circuits.
Layout design: Become proficient in the use of computer-aided design (CAD) tools for
creating integrated circuit layouts.
IC fabrication process: Gaining knowledge about the IC fabrication process,
including photolithography, etching, doping, and thin film deposition.
Simulation and verification: Learning how to use simulation and verification tools to
test and validate your designs before they are fabricated.
Testing and debug: Learning various testing and debug techniques to identify and
resolve defects in integrated circuits.
Packaging and assembly: Learning about the various packaging and assembly
techniques used to protect and interconnect integrated circuits.
Design for Manufacturability (DFM): Having an understanding of how to
design integrated circuits that are optimized for the manufacturing process.
Power optimization: You will learn about the various techniques used to optimize
the power consumption of integrated circuits.
Emerging trends in VLSI: You will stay up-to-date with the latest trends and
technologies in the field of VLSI, including advanced design methodologies, advanced
fabrication technologies, and new application areas.
BIBLIOGRAPHY
[1] Pucknell, D. A., Basic VLSI design . New Delhi: PHI Learning (2017) (4th ed.).
[2] VLSI full form: Very-large-scale integration - javatpoint. www.javatpoint.com. (n.d.). from
https://www.javatpoint.com/vlsi-fullform#:~:text=VLS I%20Stands%20for%20Very
%20Large,)%2C%20and%20components%20are%20VLSI.
[4]Chatterjee, S., CMOS VLSI design: a circuits and systems perspective. Boston: Pearson
(2011) (4th ed.).
[5] YouTube. (n.d.). Hardware modeling using Verilog by IIT Kharagpur NPTEL. YouTube.
Retrieved February 11, 2023, from https://www.youtube.com/playlist?list=PLUtfVcb-
iqn- EkuBs3arreilxa2UKIChl
[6] TutorialsPoint. (2021, July 28). VLSI design tutorial. TutorialsPoint. Retrieved February
11, 2023, from https://www.tutorialspoint.com/vlsi_design/index.htm
[7] YouTube. (n.d.). Electronics - Digital VLSI System Design. YouTube. Retrieved February
11, 2023, from https://www.youtube.com/playlist?list=PLD2350A83B752C861
[8]Brown, D., CMOS circuit design, layout, and simulation. Hoboken, N.J.: Wiley (2011)
(3rd ed.).
[9] Online courses & credentials from top educators. for free. Coursera. (n.d.).
Retrieved February 11, 2023, from
https://in.coursera.org/learn/vlsi-cad-logic/home/week/1