Neuromorphic Computing With Memristor Crossbar

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REVIEW ARTICLE
Memristors www.pss-a.com
Neuromorphic Computing with Memristor Crossbar

Xinjiang Zhang, Anping Huang,* Qi Hu, Zhisong Xiao, and Paul K. Chu
DeepMind’s differentiable neural ma-

Neural networks, one of the key artificial intelligence technologies today, have chine, DeepStack for no-limit poker play,
the computational power and learning ability similar to the brain. However, and Stanford’s skin cancer classifica-
implementation of neural networks based on the CMOS von Neumann tion.[1–5] In addition, many of our daily
operations and services use neural net-
computing systems suffers from the communication bottleneck restricted by
works such as smartphone voice control,
the bus bandwidth and memory wall resulting from CMOS downscaling. shopping recommendation, voice recog-
Consequently, applications based on large-scale neural networks are energy/ nition, face recognition, etc. Neural
area hungry and neuromorphic computing systems are proposed for efficient networks are also widely implemented
implementation of neural networks. Neuromorphic computing system con- in autonomous driving, smart grids, and
so on, but implementation of neural
sists of the synaptic device, neuronal circuit, and neuromorphic architecture.
networks has drawbacks due to the
With the two-terminal nonvolatile nanoscale memristor as the synaptic device energy, area, and time consumption. It
and crossbar as parallel architecture, memristor crossbars are proposed as a is because learning systems based on
promising candidate for neuromorphic computing. Herein, neuromorphic neural networks command a large data/
computing systems with memristor crossbars are reviewed. The feasibility computation volume for both the training
and applicability of memristor crossbars based neuromorphic computing for and inference processes and network
models are getting larger and larger for
the implementation of artificial neural networks and spiking neural networks
real-world applications.
are discussed and the prospects and challenges are also described. To implement efficient neural networks,
it requires high-density and parallel synap-
tic storage and computation. Consisting of
neurons connected by synapses, neural
networks have the computational power and learning ability
1. Introduction similar to the brain.[6,7] As shown in Figure 1, neural networks
On the heels of the rapid development of internet, mobile can be classified into three types by the neuron models.[8–11]
internet, and internet of things, the volume and complexity of Artificial neural networks (ANNs) which use the McCulloch and
data are expanding exponentially. Meanwhile, driven by Pitts neurons and differential activation function neurons map a
massive data and high-performance computing hardware, vector space into a vector space. Spiking neural networks (SNNs)
emerging technologies such as big data, cloud computing, using spiking neurons map trains of spikes into trains of spikes.
machine learning, data mining, deep learning, and artificial Table 1 compares the various biological neural networks, SNNs,
intelligence (AI) are flourishing and thriving. Today, various and ANNs on synapse models, neuron models, network
intelligent applications affect all aspects of human life topology, learning algorithms, implementation, applications,
including business, education, medical care, security, and and other features.[12–17] Since ANNs and SNNs simulate
other walks of life and consequently, the human society is different characteristics of the biological neural networks,[18–20]
transforming from the information era to the intelligence era. ANNs based deep neural networks (DNNs) and SNNs based
In this historical revolution, neural networks play one of the learning systems are both being developed continuously for
key roles. Recently, a series of impressive AI technologies are different purposes.[21] Currently, implementations of neural
based on neural networks, for instance, Google’s AlphaGo, networks are mostly based on the von Neumann computing
system (VCS) such as CPU, GPU, and their cluster, which is
powerful for logical computing but not efficient for neuronal and
Dr. X. Zhang, Prof. A. Huang, Dr. Q. Hu, Prof. Z. Xiao
synaptic computing.[22–24] Figure 2(a) illustrates the complexity
School of Physics, Beihang University
Beijing 100191, China relationship between the data environment and machine.
E-mail: aphuang@buaa.edu.cn Although powerful software, efficient learning algorithms,
Prof. P. K. Chu and novel network topologies are emerging constantly,[25–29]
Department of Physics and Department of Materials Science and VCS-based DNNs and SNNs still have drawbacks pertaining to
Engineering the energy, area and time consumption.[30–33] Therefore, the
City University of Hong Kong neuromorphic computing system (NCS) has been proposed for
Tat Chee Avenue, Kowloon, Hong Kong, China
efficient implementation of neural networks.
The ORCID identification number(s) for the author(s) of this article NCS integrates a large amount of synapses and neurons in a
can be found under https://doi.org/10.1002/pssa.201700875. single chip and supports complex spatiotemporal learning
DOI: 10.1002/pssa.201700875 algorithms as described in Table 1. The evolution of computing
Phys. Status Solidi A 2018, 215, 1700875 1700875 (1 of 16) © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
18626319, 2018, 13, Downloaded from https://onlinelibrary.wiley.com/doi/10.1002/pssa.201700875 by Karlsruher Inst F. Technologie, Wiley Online Library on [31/03/2023]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
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systems for neural networks is shown in Figure 2(b). Generally,

NCS has two main purposes: accelerating ANNs-based DNNs Xinjiang Zhang is currently a Ph.D.
and developing SNNs.[34–36] Table 2 shows the different candidate at the School of Physics
approaches of NCS for SNNs in comparison with the human of Beihang University. He received
brain. The key operations for the training and inference his Bachelor’s degree in automation
processes of DNNs are the vector-matrix product, nonlinear science from Beihang University. His
function execution, and weights matrix update, while SNNs research interests include neural
require spiking neurons and synaptic devices. To accelerate networks, learning systems,
DNNs, various computing systems have been designed as DL memristors, van der Waals
accelerator (DLA), for instance, the FPGA based platforms, ASIC heterostructures, as well as
based TPU, DianNao, etc.[37–46] These DLAs use a novel neuromorphic computing.
computing architecture to expedite training or the inference
process of DNNs. To develop SNN, some impressive results have Prof. Anping Huang received his BS
been obtained,[47–49] for example, IBM TrueNorth,[50] SpiNNa- in physics from Lanzhou University
ker,[51] Neurogrid,[52,53] Darwin,[54] and so on. Whereas these in 1999 and Ph.D. in material
silicon transistor circuits based computing systems can still be science from Beijing University of
improved from device, circuit and architecture. Technology in 2004. His research
To achieve more efficient NCS, novel synaptic device, compact interests include solid state
neuronal circuit, and more paralleling neuromorphic architec- electronics, interface science and
ture are desirable. As shown in Figure 3, various devices with engineering, semiconductor devices,
different materials, structures, mechanisms, and features are as well as neuromorphic computing.
applicable to neuromorphic computing.[55] These neuromorphic He is the vice dean and professor of
device can be loosely classified into memristor-type and condensed matter physics in the School of Physics at
transistor-type. Yet, the downscaling problem restricts transis- Beihang University.
tor-type devices for future neuromorphic applications. Fortu-
nately, as a nanoscale, solid-state, two-terminal neuromorphic Prof. Paul K. Chu received his BS in
device, memristor is a potential candidate for future NCS.[56–60] mathematics from The Ohio State
Memristors can be used in both analog and digital computing for University in 1977 and MS and
various types of synapses and neurons in ANNs and SNNs. Ph.D. in chemistry from Cornell
Besides, memristors can be easily integrated into the crossbar University in 1979 and 1982,
architecture which naturally supports parallel in-memory respectively. His research covers
computing and high-density storage. With the nanoscale, two- quite a broad scope, encompassing
terminal, and solid-state memristor, the memristor crossbar plasma surface engineering,
(MC) is a parallel computing circuit boasting a high density and materials science and engineering,
low power consumption. Overall, neuromorphic computing as well as surface science. He is the
with MC represents a possible path for efficient implementation Chair Professor of Materials Engineering in the
of neural networks. Department of Physics and Department of Materials
Herein, neuromorphic computing with memristor crossbar is Science and Engineering at City University of Hong Kong.
reviewed. By exploiting the synaptic and neuronal characteristics
of memristors and parallel nature of the crossbar, MC is shown
to be suitable for both DNNs and SNNs implementation. Then,
MC-based vector-matrix multiplication for DNNs and spike- and molecular plasticity.[62–64] Synaptic devices are electrical
timing dependent plasticity (STDP) for SNNs are described, and switches which can simulate a biological synapse in both the
the prospects and key challenges of neuromorphic computing function and structure for synaptic computation. Generally,
using MC are discussed. synaptic weights are represented as the conductance of the device
and synaptic plasticity requires the device to be resistive
switching. Research on synaptic devices has been conducted
2. Synaptic Memristor for many years and spurred by the rapid development of
neuroscience and nanotechnology, different synaptic devices
2.1. Synapse have been designed and adopted. As shown in Figure 4, synaptic
devices can be classified into synaptic transistors and synaptic
A synapse is a two-terminal device between the presynaptic memristors according to the structure. Synaptic transistors
neuron and post synaptic neuron as shown in Figure 4(a). consist of floating gate transistors using charge storage on
Synaptic plasticity, basic function of synapse, is the foundation of floating gate electrodes to modulate the channel conductance and
learning, memory, and adaption.[61] Usually, the strength of store synaptic weights,[65–70] and ionic transistors using the ionic
synaptic connectivity in term of synaptic weight can be regulated concentration in the channels controlled by the gate to achieve
by the neuron activities including excitatory and inhibitory ones. resistive switching of the channels.[71–77] However, these synaptic
There are different types of synaptic plasticity such as long term transistors are ultimately limited by downscaling. To design more
plasticity (LTP), short term plasticity (STP), structural plasticity, synapse-like devices, memristors have been explored.
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Figure 1. Schematic of the biological neurons networks, spiking neural networks, and artificial neural networks.
2.2. Synaptic Memristor further classified according to the mechanism, materials system,
and switching phenomena. An ionic memristor changes its
Memristors, an abbreviation of memory resistors, were states by applying a voltage or current to move cations or anions
conceived by Leon Chua in 1971[78] and experimentally modeled in the switching layer, where the movement of the anions or
by HP Labs in 2008.[79,80] A memristor is a two-terminal non- cations is usually accompanied by chemical reactions (re-
volatile memory (NVM) device based on resistive switching with dox).[84,85,87,91,94,95,98–100] The ionic memristor can be classified
a pinched hysteresis current-voltage loop as fingerprints.[81–83] It into the anion memristor and cation memristor. In the anion
consists of a switching layer between the first electrode and memristor, anion motion changes the valance of the metal to
bottom electrode as shown in Figure 5. Since it has enormous produce resistance change in the switching materials, which is
scientific and commercial potential in the information and termed the valence change memory (VCM). The switching
computing technologies, especially neuromorphic computing, materials in an anion memristor contains an oxide insulator
many types of memristors have been developed and the such as TiOx, ZnO, WOx, SiOx, etc. and non-oxide insulator such
mechanism, materials, and switching phenomena have been as AlN, ZnTe, ZnSe, and so on. In the cation memristor, the
reviewed.[84–98] Basically, memristors can be loosely grouped into resistance change is induced by cation motion through the
three categories: ionic memristors, spin-based memristors, and electrochemical reaction. Thus, a cation memristor is also called
phase-change memristors (PCM), and each one of them can be the electrochemical memory (ECM). The materials system of the
Table 1. Comparison of biological neurons networks, spiking neural networks, and artificial neural networks about synapse models, neuron
models, network topology, learning algorithms, and developments.
Biological neural networks Spiking neural networks Artificial neural networks
Synapses Diverse Short term plasticity (STP), Long term plasticity Numerical Matrix
(LTP), etc.
Neurons Diverse Integrate & Fire, Hodgkin–Huxley, etc. Sigmoid, Tanh, ReLU, Leaky ReLU
Topology Complex Hopfield Network, Liquid State Machines, etc. FNN, CNN, RNN, LSTM, DNC, etc.
Learning – Spike timing dependent plasticity, etc. Gradient Descent Backpropagation, etc.
algorithm
Application Cognition, Inference, Imagination, etc. Realtime recognition camera, Brain-like Autonomous driving, Voice control system, Medical
Neuromorphic Chip, etc. Dignosis, etc.
Implementation Brain TrueNorth, SpiNNaker, Neurogrid, Darwin, etc. Tensorflow, PyTorch, MXNet, GPU, TPU, Cambrian,
etc.
Features The most complex and powerful Biological Close; Realtime; Online Learning; Low Multilayer; Feasible and practical with current
computing system and learning system power; Noise input; Spatio-Temporal computing system; Data/computation intensive
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memristor (STT) and magnetic-domain-wall

motion induced memristor. The PCM changes
the resistance by transforming between the
amorphous and crystalline phases of the
phase-change materials. The amorphous
phase represents the low-conductance and
the crystalline phase has high conduc-
tance.[99,100] The behavior of the PCM depends
on the phase-change materials but there are
only a few reliable phase-change materials
with the most common being Ge2Sb2Te5
(GST).
All the two-terminal solid-state memristors
can be considered synaptic devices regardless
of the device materials, physical mechanisms,
and switching phenomena.[56,101–114] From the
structural perspective, a memristor is a two-
terminal nanoscale device similar to the
biological synapse. From the functional per-
spective, the synaptic weight can be repre-
sented as the conductance of the memristor
and modified by applying a charge or flux to
the memristor to achieve synaptic plasticity.
Specifically, a two-terminal nanoscale mem-
ristor is suitable for the high-density synapse
of large scale neural networks. The nonvolatile
resistive switching properties of a memristor
simulate the synaptic plasticity and reduce
power consumption. Although all types of
memristors can be used as synapse in neuro-
morphic computing, different types of mem-
ristors have different synaptic plasticity
mimicking characteristics such as the LTP,
STP, and stochastic activation.[115–126] Besides,
ANNs and SNNs require different types of
synapse. Specifically, ANNs need nonvolatile
analog memories with a low write noise, linear
conductance change, and high on/off ratio,
whereas SNNs requires a dynamic memristor
with various synaptic properties. For example,
the SNNs-based learning system requires
volatility to simulate STP and a transition
Figure 2. Evolution of computing systems: (a) Relationship of machine complexity and data between STP and LTP to simulate memory
environments complexity. Currently, VCS is more efficient and NCS is still simple but as the data consolidation in biological synapse. On the
environment gets more complex, NCS has the advantage; (b) Illustration of computing system
other hand, an ANNs-based learning system
evolution with time.
requires nonvolatile memory and multi-bit
storage to reduce energy/area consumption.
cation memristor has the signature that the electrode is made of The different types of synaptic devices and their synaptic
electrochemically active materials such as Cu and Ag and the properties are summarized in Table 3.
counter electrode is usually an electrochemically inert metal As aforementioned, the synapses model of ANNs and SNNs
like W, Pt, and Au. A spin-based memristor changes its states by are different. ANNs map a numerical vector space to another
altering the electron spin polarization.[86,97] A spin-based numerical vector space through vector-matrix multiplication
memristor can be envisaged as a trilayer device consisting of and nonlinear activation functions. The computations in the
the first electrode, magnetic layer, and second electrode. By training and inference process of ANNs are performed
applying a current through the magnetic layer, the current synchronously. According to these characteristics, the synapse
electron spin changes the magnetization of the device and model of ANNs should behave like an analog memory device.
magnetization can be regulated by the cumulative effects of In VCS-based implementation of ANNs, multiple transistors
electron spin excitation. A spin-based memristor can be are used to represent the synaptic weight according to the
classified into two types: the spin-torque-induced magnetization accuracy requirement which varies for different applications.
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[36]
Table 2. A comparison of the major features of the human brain and neuromorphic systems for SNNs. (adapted from reference ).
Platform Human brain Neurogrid BrainScaleS TrueNorth SpiNNaker Darwin
Material/Devices Biology CMOS Wafer-Scale ASIC CMOS ARM Boards, Custom CMOS
Interconnection
Programmable structure Neuron & Neuron & Neuron & Synapses Neuron & Neuron & Synapses Neuron &
Synapses Synapses Synapses Synapses
Component complexity (Neuron/ 1/1 79/8 Variable 10/3 Variable >5//>5
Synapse)
Device technology Biology Analogue, Analogue, over Digital, fixed Digital Programmable Digital
subthreshold threshold Programmable
Device feature size 10/mm 180 nm Transistor 180 nm Transistor 28 nm Transistor 130 nm Transistor Regular
Device numbers – 23 M 15 M 5.4 B 100 M M
Synapse model Diverse Shared dendrite 4-bit digital Binary, 4 Programmable Digital
modulators Programmable
Synapse number 1015 108 105 2.56 108 1.6 106 Programmable
Synapse feature Size 10 nm 100 nm 100 nm 100 nm 100 nm 100 nm
Neuron model Diverse, fixed Adaptive quadratic Adaptive LIF Programmable Programmable
IF exponential IF
Neuron number 1011 6.5 104 6.5 10 4
10 6
1.6 10 4
Programmable
Neuron feature Size nm 20 mm Variable 10 mm Variable 10 mm
Network internet 3D direct Tree-multicast Hierarchical 2D 2D mesh-multicast Hierarchical
signaling mesh-unicast
Network topology SNN based SNN based SNN based SNN based SNN based SNN based
Learning algorithm STDP STDP STDP STDP STDP STDP
Energy performance 10 fJ 100 pJ 100 pJ 25 pJ 10 nJ 10 nJ
On-chip learning Yes No Yes No Yes Yes
Generally, in NCS-based implementation of ANNs, analog, implementation of SNNs. SNNs transfer a set of spikes to
digital, or mixed memory devices represent the synaptic weight another set of spikes by asynchronous computation based on
of ANNs. These memory devices vary from the traditional the STDP rule. In this context, the synaptic devices are required
MOSFETs to transistors using 2D materials and floating gates to be more biological. Usually, traditional MOSFETs based
and metal oxide memristors to memristors with novel materials implementations are either complex and inefficient or simple
and structures, as shown in Figure 3. When memristors are but impractical, since the biological synapses exhibit various
used as synapse, the conductance can be either analog or behaviors. Among them, the timing dependent plasticity is the
digital. Figure 6 shows the conductance behavior of this type of most important. When memristors are used for biological
memristors. M. Hu et al. of HP Labs built an dot-product synapse, the conductance behavior can emulate many plasticity
engine for ANNs accelerated with the Pt/TaOx/Ta memristor behaviors of the biological synapse. Figure 7 illustrates the
which exhibited 8 levels of resistance states with 0.1% accuracy conductance behavior of a diffusive memristor when applying
and showed 1000 distinguishable states.[127] Recently, this team the pre-spike and post-spike to the device.[124] In this work
developed analog signal and image processing with a large performed by J. J. Yang et al., the synapse consisted of a
memristor crossbar with the Ta/HfO2/Pd memristor.[128] The diffusive memristor connected with a drift memristor. In
resistance of this device could be tuned from about 2 MΩ to addition, other memristors can be used as this kind of synapse
2 kΩ and a resistance between 1.1–1.0 kΩ could be applied for and some exhibit interesting synaptic behavior such as the
practical vector-matrix multiplications. Many types of mem- short-term memory to long-term memory transition.[132–135]
ristors are applied to vector-matrix multiplication for ANNs Since SNNs still need more development for practical
acceleration, for example, WOx-based memristors proposed application, the precise requirements for this type of synaptic
by W. D. Lu et al.,[129] and Al2O3/HfO2-based memristors memristors vary.
proposed by P. Yao et al.[130] In addition, to developing more Overall, various types of memristors with different conductance
practical vector-matrix multiplication for ANNs acceleration, behavior can be used as neuromorphic computing hardware for
the memristors need a fast read/write speed, read/write the implementation of ANNs and SNNs. Except for synapse in
linearity, low read/write noise, and high programmability.[131] ANNs and SNNs, some memristors exhibit a spiking neuron-like
The requirements for the conductance behavior of mem- behavior, which can be called neuronal memristors, and this type
ristors are different for ANNs when it comes to the of memristor is discussed in the next section.
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3. Neuronal Memristor
3.1. Neuron
A neuron composed of dendrites, soma, and

axon performs a nonlinear function which
maps the neuronal input to output as shown in
Figure 8. The dendrites usually receive signals
from other neurons and transmit signals to the
soma and the axon usually transmits signals
generated by the soma to other neurons. The
soma processes the neuronal input and
generates the neuronal output. The typical
behavior of neurons is to accumulate charges
to change the membrane potentials of the
soma through the excitatory and inhibitory
postsynaptic signals received by the dendrites.
When the membrane potential reaches a
specific threshold, the soma generates an
action potential which travels along the axons
to change the charges on other neurons
through synapse. Following this action poten-
tial, the membrane potential of the soma is
reduced to the rest potential. As shown in
Table 1, there are two types of neurons in neural
networks: spiking neurons and artificial neu-
rons. To emulate spiking neurons, a threshold
circuit with charge accumulation is needed,
which is usually implemented by software or a
specific operational circuit. Most NCSs use
leaky integrate & fire (LIF) to achieve efficient
hardware implementation. As a key to NCS
Figure 3. Summary of neuromorphic hardware from devices to systems.
implementation, several neuronal circuits
such as floating gate transistor based LIF and
silicon neurons are designed.[136–138] Among
Figure 4. Biological synapse and synaptic devices. A biological synapse can be envisioned as a resistive switching. The floating gate transistor and ionic
transistor use conductance of the source and drain electrodes to represent the synapse. As a two-terminal device, a memristor is more similar with the
biological synapse and represents the synapse as the conductance of the top and bottom electrodes.
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3.2. Neuronal Memristor
Unlike a synaptic memristor, the neuronal

memristor requires an accumulative behavior
and threshold gate instead of continuous
conductance states. The conductance of the
neuronal memristor should remain until the
threshold is reached and the neuron
fires when the neuronal input arrives.[140]
In addition, when a memristor is used as a
neuron, non-volatility is not essential and
volatility can potentially be used to
implement the LIF dynamics. According to
recent investigations, PCM, STT, and neu-
ristors have been reported as neurons for
SNNs.
The neuronal PCM represents the mem-
brane potential in the phase configura-
tion.[110] In an all-PCM neuromorphic
system, both the neuronal and synaptic
elements are realized using phase change
devices.[141,142] Unlike the synaptic PCM
which involves a smaller change of conduc-
tance, a large change of conductance is
required for the neuronal PCM thus reducing
the durability of the PCM device. The
Figure 5. Schematic of a synaptic memristor. Reproduced from with permission.[56] Copyright conductance behavior of the neuronal mem-
2010, American Chemical Society. ristor is shown in Figure 9.[124] It is important
to ensure that spike firing is sparse through-
out the lifetime of the PCM-based neuron.
them, some types of memristors are exploited as neurons to obtain Alternatively, other materials with better durability can be
significant considered. The neuristor proposed as a Hodgkin–Huxley axon
area/power efficiency. Specifically, active memristor can be used as by Pickett et al. is built with two nanoscale Mott memris-
neurons but passive memristors are used as synapse.[139] tors.[143] The Mott memristor is a dynamic device that exhibits
Table 3. Different synaptic memristors including spiking synaptic memristors and analogy synaptic memristors. (adapted from reference [104]).
Dimensions D or Energy Programming Multi-level Max dynamic Achievable

Synaptic device WL consumption time states range retention/endurance
Phase change Ge2Sb2Te5 (Kuzum et al.) D ¼ 75 nm 2–50 pJ 50 ns 100 1000 Years/1012
Ge2Sb2Te5 (Suri et al.) D ¼ 300 nm 121–1552 pJ 50 ns 30 100
Resistive TiOx/HfOx (Yu et al.) 5 5 mm 2
0.85–24 pJ 10 ns 100 100 Years/1013
change
PCMO (Park et al.) D ¼ 150 nm–1 mm 6–600 pJ 10–1 ms 100 1000
TiOx (Seo et al.) D ¼ 250 nm 200 nJ 10 ms 100 >10, <100
WOx (Yang et al.) 25 25 mm2 40 pJ 0.1 ms >10 300
Conductive Ag/a-Si/W (Jo et al.) 100 100 nm2 720 pJ 300 mm 100 10 Years/108
bridge
Ag/Ag2 S/nanogap/Pt (Ohno Pt tip 250 nJ 0.5 s 10 >1000
et al.)
Ag/GeS2/W (Suri et al.) D ¼ 200 nm 1800–3100 pJ 500 ns 2 1000
Ferroelectric BTO/LSMO (Chathbouala et al.) D ¼ 350 nm 15 pJ 10–200 ns 100 1000 N/A
FET-based Ion-doped polymer-based FET 1.5 20 mm2 10 pJ 2 ms 50 >4 N/A
(Lai et al.)
NOMFET (Alibart et al.) 5 1000 mm2 5 mJ 2–10 s 30 15 N/A
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Figure 6. Conductance behavior of the synaptic memristor for ANNs: (a) 64 resistance levels obtained from the Pt/TaOx/Ta memristor using current
compliance; (b) 8 levels of resistance states with 0.1% accuracy showing potentially 1,000 distinguishable states. Reproduced with permission.[127]
Copyright 2016, IEEE.
transient memory and negative differential resistance due to characteristics for neuronal circuits.[144,145] STTs have also
the insulating-to-conducting phase transition driven by been proposed for neuronal circuits.[113,146–149] The STT neuron
Joule heating. By exploiting the functional similarity between is described by A. Sengupta et al. to transform an already fully-
the dynamic resistance behavior of Mott memristors and trained DNNs into a SNN for feedforward inference.[149] The
Hodgkin–Huxley Naþ and Kþ ion channels, a neuristor STT oscillator has been proposed for both synapse and neuron
comprising two memristors with NbO2 has been shown to implementation by J. Griller et al.[113] It should be noted that
exhibit the important neuronal functions of all-or-nothing the spinwave generated by STT is quiet small for synaptic
spiking with signal gain and diverse periodic spiking. The device adaption. In addition, the spiking neuron is also realized
stochastic activation behavior of Mott memristor has been in a compact circuit comprising the memristive and mem-
described by HP Labs and it possesses more complex capacitive devices based on the strongly correlated electron
Figure 7. Conductance behavior of the synaptic memristor for SNNs: (a) Illustration of a biological synaptic junction between the pre- and postsynaptic
neurons; (b) SRDP showing the change in the conductance (weight) of the drift memristor in the electronic synapse with change in the duration tzero
between the applied pulses; (c) Schematic of the pulses applied to the combined device for STDP demonstration; (d) Plot of the conductance (weight)
change of the drift memristor with variation in t showing the STDP response of the electronic synapse. Reproduced with permission.[124] Copyright 2017,
Nature Research.
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4. Neuromorphic Memristor Crossbar

4.1. Neuromorphic Architecture
A human brain has approximately 1011 neurons and each

neuron is connected to about 5000–10 000 other neurons thus
producing an enormous quantity (about 1015) of biological
synapses. To be more energy/area efficient, a neuromorphic
architecture is needed for NCS. The neuromorphic
architecture is a computing architecture which can integrate
synapse and neurons in a compact manner, configure the
topology of neural networks easily, and execute neuronal
and synaptic computation efficiently. Unlike the von Neumann
architecture, the neuromorphic architecture should integrate
computing and memory and provide high-density and
parallel data storage and computation.[151] Among the
various parallel architectures for NCS, the crossbar architecture
shows tremendous potential.[152–157] As a neuromorphic
architecture, the crossbar can integrate both transistors and
memristors. The device in each cross point can be treated as
synapse and the neuron can be connected to the edge of
the crossbar. This architecture is highly parallel, area
efficient, and fault tolerant. Although the transistor-based
crossbar has been proposed for intensive memory and
computational memory such as IBM TrueNorth,[50] the chip
Figure 8. Biological neuron and neuronal circuit. is still quite expensive and the area is inefficient due to
implementation of synapse and neuron based on
material vanadium dioxide (VO2) and chemical electromigra- transistors. Since most memristors are two-terminal cross-
tion cell Ag/TiO2x/Al.[150] The circuit can emulate the bar-type devices and memristors can be used for synapses
dynamic spiking patterns in response to an external stimulus and neurons for ANNs or SNNs, memristor crossbars show
including adaptation. more potential in neuromorphic computing.
Figure 9. Conductance behavior of the stochastic phase-change neurons. Reproduced with permission.[110] Copyright 2016, Nature Research.
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and adapt.[159] Read and write operations can

be performed by three modes: current control,
voltage control, and spiking control.[160] To
write a memristor in the crossbar, a specific
voltage is applied to both lines where the cross
point is the memristor. To read a memristor, a
relatively small voltage is applied to the top
and bottom lines (for example, less than Vwrite)
to a junction to measure the current. Compre-
hensive analyses of MC read and write
operations can be found elsewhere.[161–164]
Compared to other neuromorphic platforms,
MC can be either analog or digital according to
the conductance behavior of the memristors.
When used as an analog computing circuit,
MC has a high capacity to store multiple
bits of information per element and a small
energy is required to write distinct states
(<50 fJ/bit).[165,166] Besides, MC can perform a
variety of functions according to the properties
Figure 10. Neuromorphic architecture based on STT neurons. Reproduced with permis- of the memristors, for instance, look-up tables,
sion.[106] Copyright 2015, IEEE. content addressable memories, and random
number generators.[167] The detailed explana-
tion of the neuromorphic operation per-
4.2. Neuromorphic Memristor Crossbar formed by MC is described in the next section, including
vector-matrix multiplication for the ANNs-based deep leaning
As a neuromorphic computing circuit, MC integrates storage model and STDP for SNNs.
and computation in a very dense crossbar array where
memristors are injected at each junction of the crossbar
between the top electrode and bottom electrode. MC can be 5. Neural Networks Using Memristor Crossbar
used as the synaptic array and the neuron circuit can be
integrated with MC for hardware implementation of neural 5.1. Accelerating DNNs
networks. Figure 10 shows the neuromorphic architecture based
on the STT neuron, where a synaptic memristor crossbar array DNNs have reliable network topologies and learning algorithms.
and STT neurons are wired to implement a single layer of the Such networks, including feedforward neural networks, con-
neural network.[106,158] volutional neural networks, recurrent neural networks, and
The most important property of MC is that it can be other derivatives, are usually trained with the supervised
programed by involving the three basic operations of read, write learning and error-based back-propagation algorithm. The basic
operations of DNNs are vector-matrix multi-
plication, weight matrix updating, and nonlin-
ear function execution. Both vector-matrix
multiplication and weight matrix updating
need more parallelism and the nonlinear
function can be executed by artificial neurons
such as the sigmoid. As a neuromorphic
computing circuit, MC is suitable for DNN
acceleration.
Vector-matrix multiplication is performed
on MC by readout operation and weight matrix
updating for adaption of MC.[58,127,168–173]
Specifically, vector-matrix multiplication can
be accelerated by exploiting a simple crossbar
array in multiplication and summation oper-
ations. As shown in Figure 11, the multiplica-
tion operation is performed at every cross
point by Ohm’s law with current summation
along rows or columns performed by
Kirchhff’s current law. Operation of the
Figure 11. Memristor crossbar for vector-matrix multiplication. memristor-based vector-matrix multiplication
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Figure 12. DNN implemented with MC and pattern classification experiment with FNN (top-level description): (a) Input image; (b) Single-layer
perceptron for classification of 3 3 binary images; (c) Used input pattern set; (d) Flow chart of one epoch of the used in situ training algorithm. As
shown in (d), the grey-shaded boxes show the steps implemented inside the crossbar, while those with solid black borders denote the only steps required
to perform the classification operation. Reproduced with permission.[174] Copyright 2015, Nature Research.
can be divided into two basic parts: programming of the array training process of ANNs involves adaption of the memristor
and performing the computation functions. During array conductance matrix to the data environment. Generally, the
programming, the conductance of each cell is tuned to a synaptic matrix of ANNs can be mapped into a memristor
targeted value and read for verification. To achieve faster array matrix and adapted by back-propagation with gradient algo-
programming, multiple cells may be tuned in parallel. During rithms.[130,168] To illustrate the MC-based single layer ANNs,
computation, a vector input of voltages is driven across the rows Figure 12 shows a single-layer perception implemented with the
in parallel, while the current at every column is sensed digital metal oxide memristor by Prezioso, et al.[174] This ANN
simultaneously to compute the vector-matrix product. These uses tanh as the neuron activation function and the 12 12
multiplications-accumulated operations can be performed in Al2O3/TiO2x memristor crossbar as the synaptic weight matrix
parallel at the location of data with locally analog computing to with in situ learning. C. Yakopcic, et al. have developed a MC that
reduce power by avoiding the time and energy for moving the could perform N M convolution operations in parallel, where
weight data. Since accurate and reliable values are needed in the N is the number of input maps and M is the number of output
computation step, it is desirable to program to the arbitrary maps in a given layer in the CNN.[175] In this circuit, the
conductance states efficiently and rapidly. convolution kernels of CNN are assigned by software using an ex
With regard to neural network implementation, MC can situ training process. The convolution kernel circuit is divided
accelerate both the training and inference processes. The into two MCs such that positive and negative values can be
represented. Combined with the op-amp
circuit, this circuit can produce the same
result ( some analog circuit error) as a digital
software equivalent. A. Shafiee, et al. have
built in situ CNN implementation in which
MCs are used to store input weights and
perform dot-product operations in an analog
manner.[176] The Hopfield network is also a
typical RNN in which any two neurons are
linked through a weighted connection and the
MC-based Hopfield network has some analy-
sis and implementation.[177] P. Yao et al. have
proposed face classification neural networks
with 3320 memristors.[130] The energy con-
sumption in the analogous synapse for each
iteration is 1000 compared to the implemen-
tation using the Intel Xeon Phi processor with
off-chip memory. The accuracy on the test sets
Figure 13. SNN circuit: (a) Implementation of STDP with two-memristor-per-synapse scheme; is close to that using a CPU. Furthermore,
(b) Key spiking characteristics of spiking neural network: downstream spikes depend on the more ANNs have been implemented with MC
time integration of continuous inputs with the synaptic weight change dependent on relative for practical applications.[178–182] Thus, MC-
spike timing. Reproduced with permission. [111]
Copyright 2017; Taylor & Francis Ltd. based NCS can accelerate DNNs.
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5.2. Developing SNNs Table 4. Key challenges and potential approaches of neuromorphic
computing with memristor crossbars on the device level, circuit level,
To develop SNNs, the MC should consist of the spiking synaptic and system level.
memristor with STP, LTP, stochastic activation, and the
Key challenges Possible approaches
hardware-based spiking neurons are also required.[183–185]
Mapping of SNNs with STDP as a local learning rule for MC Device Level:
is highly intuitive as shown in Figure 13. One edge of -Materials • Various materials system. • Search from 2D materials,
the crossbar array represents the pre-synaptic neurons. The To achieve applicable conducting polymer, or
-Structures
orthogonal edge represents post-synaptic neurons and the memristor, core memristive design functional materials
-Mechanisms
voltage on the wiring leading to these latter neurons represents materials systems need
the membrane potential. One needs only to implement the developing
STDP learning rule to modify the memristor conductance based -Neuromorphic • Need nanoscale, solid- • Apply structures and
on the timing of the pulses in the pre- and post-synaptic state, crossbar-type experience in semiconductor
neurons.[186,187] As aforementioned, STDP can be implemented memristor technology
even with memristors that support small conductance changes -Behavior • Diversity but lack of • Develop simulation
only in one direction by separating the long-term potentiation -Device comprehensible and accurate software which models the
and long-term depression functionalities across two devices. In Modeling device from the basic
other words, STDP is only a local learning rule. When MCs are principles
used for SNNs, computation on MC is asynchronous.[188] Unlike • Stable and repeatable • Build SPICE model of
the MC-based ANNs, there are still lack of comprehensible conductance behavior for memristor and comparison
research work on MC based SNNs. Most of the published works different synapse models and with physical device
are sample simulation of SNNs with the memristor SPICE neuron models
model. Since MC-based SNNs have low power consumption and • The mechanism and
more brain-like properties, more research efforts are still conductance behavior are
needed. For example, the requirements for the conductance diversity. Need more general
conductance behavior of
behavior when memristors are used to implement SNNs should
memristor
be clarified and the learning algorithms for MC-based SNNs
should be explored. Circuit Level:
-Scaling • Sneak path and IR drop • Construct a large crossbar
or 3D crossbar or crossbar
array
6. Prospects and Conclusion
-Read/Write • Read/Write scheme, Analog • Develop memristor with
Neuromorphic computing with memristor crossbar is reviewed and digital mode rectifying effect
in this article. Owing to the large density and small power • Use selector device
consumption, MC is suitable for neuromorphic computing. As a System Level:
two terminal nanoscale device, memristors are mainly used as
-Neuromorphic • Scalable. Build large scale • Software simulation with
synapse and some types of memristors can be used to build neural networks memristor model
neuronal circuits due to its stochastic and chaotic behavior.
-Operations • General. Develop a general • Experimentally build some
According to the different synaptic properties of memristors,
purpose computing system application with memristor
different types of memristors can be used for DNNs and SNNs. for ANNs and SNNs, crossbar
As a neuromorphic architecture, the crossbar provides highly including data mapping, dot-
parallel computing. Together, memristor crossbar integrating product, STDP, etc
computing and memory can be used for efficient implementa- -Neural • Algorithm. Practical • Develop training
tion of neural networks including DNNs and SNNs. On the heels Networks network topology and algorithms for memristor
of the rapid development of AI technology, neuromorphic learning algorithm for both based SNNs and DNNs
computing using the memristor crossbar is likely to morph into MC based ANNs and SNNs
a practical and powerful platform for future AI applications. • Develop hybrid
To make further progress on MC-based neuromorphic neuromorphic system
computing systems and efficient implementation of neural consists of both ANNs and
networks, challenges remain. Table 4 lists the key challenges and SNNs
potential approaches from device level, circuit level, and system
level. On the device level, in order to obtain more reliable and
practical memristors, memristive mechanism needs to be When it comes to neuromorphic computing, the conductance
understood more thoroughly and the performance needs to behavior of the synaptic memristors or neuronal memristors
be improved.[196,197] To identify reliable and practical memristive needs to be studied thoroughly in order to fathom the
materials, two-dimensional materials are investigated for neuroscience or computer science. Furthermore, more simula-
memristors, such as graphene, MoS2, phosphorene, h-BN, tion work should be performed to make use of existing device
and two-dimensional perovskite.[189–195] In addition, crossbar- properties and providing guidance to the development of future
type memristors have better potential than planar memristors. devices for different performance requirements. On the circuit
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Neuromorphic Computing With Memristor Crossbar

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Neuromorphic Computing with Memristor Crossbar

DeepMind’s differentiable neural ma-

systems for neural networks is shown in Figure 2(b). Generally,

Biological neural networks Spiking neural networks Artificial neural networks

memristor (STT) and magnetic-domain-wall

Platform Human brain Neurogrid BrainScaleS TrueNorth SpiNNaker Darwin

A neuron composed of dendrites, soma, and

3.2. Neuronal Memristor

Unlike a synaptic memristor, the neuronal

Dimensions D or Energy Programming Multi-level Max dynamic Achievable

4. Neuromorphic Memristor Crossbar

A human brain has approximately 1011 neurons and each

and adapt.[159] Read and write operations can

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