Unit 2

Instruction Set and Addressing Modes
An instruction is any specified binary pattern which is placed inside the

microprocessor to perform a specific operation.
The instructions of the 8085 microprocessor are classified into five different groups,
namely, data transfer group, arithmetic group, logical group, branch control group,
I/O and machine control group.
The instruction set is the collection of all groups of instructions. Each instruction
has two parts:
The first part is the task to be performed. This is known as operation code (opcode).
The second part is data to be operated on, called operands.
There are various techniques to specify operand of instructions. These techniques

are known as addressing modes
Generally, instructions are stored in the memory devices. Before execution of any
instruction, the microprocessor locates the memory location and fetches the
operational code through a data bus. Then the decoder decodes the instruction and
performs the specified function.
Generally, the following addressing modes are used in the 8085 microprocessor :
1. Immediate addressing
2. Register addressing
3. Direct addressing
4. Indirect addressing
Direct Addressing
In this addressing mode, the address of the operand always exists within the
instruction.
This mode can be used to read data from output devices and store it in the
accumulator or write the data, content of the accumulator to the output devices.
In the instruction IN 00H, the address of an I/O port is 00H where the data is
available. From this location, data is to be read and stored in the accumulator.
Similarly, the content of the accumulator can be sent to the output port address 01H
using OUT 01H instruction.
Register Addressing
In the register addressing mode, one of the registers A, B, C, D, E, H and L can be
used as source of operands. Consequently, data is provided through the registers.
In this mode, the accumulator is implied as a second operand.

For example, the instruction ADD C says that the contents of the C register will be
added with the contents of the accumulator.
Register Indirect Addressing
In the register indirect mode, the contents of specified registers are used to specify
the address of the operand.
Therefore, in register indirect instructions, the address is not explicitly specified.
For example, the instruction MOV A, M means that move the contents of the
content of the memory location whose address is stored in H and L register pair, in
the accumulator.
The instruction LDAX B is also another example. In this instruction, load the
accumulator with the byte of data that is specified by the address in the B and C
register pair.
Immediate Addressing
In the immediate addressing mode, the operand or data is present within the
instruction. Load the immediate data to the destination, which is given in the
instruction.
The immediate instructions use the accumulator as an implied operand. The MVI
(move immediate) instruction can move its immediate data to any of the working
registers. For example, the instruction MVI D, FFH moves the hexadecimal data
FFH to the D register.
The LXI instruction (load register pair immediate) uses 16-bit immediate data. This
instruction is generally used to load addresses into a register pair.
Implicit Addressing
The addressing mode of certain instructions can be implied by the instruction’s
function. Actually, these instructions work on the content of the accumulator and
there is no need of the address of the operand.
Instruction Set
An instruction is a command applied to the microprocessor to perform a specific
function.
The instruction set of a microprocessor means the entire group of instructions.
Generally, instructions have been classified into the following five functional
groups.
Data transfer group
Arithmetic group
Logical group
Branch control group
I/O and machine control group
Data-Transfer Group
Instruction Set
Data transfer group
The data-transfer instructions copy data from a source to a destination without
modifying the contents of the source.
The term data transfer has been used for copying data.
The data transfer can be possible between registers or between memories or
between memory and registers or between I/O ports and the accumulator.
Instruction Set
Data transfer group
Examples
MOV Move
MVI Move immediate
LDA Load accumulator directly from memory
STA Store accumulator directly in memory
LHLD Load H and L registers directly from memory
SHLD Store H and L registers directly in memory
An ‘X’ in the name of a data-transfer instruction means that the data transfer
operation is performed with a register pair.
LXI Load register pair with 16-bit immediate data
LDAX Load accumulator from memory whose address is in a register pair
STAX Store the content of the accumulator in memory whose address is in the
register pair
XCHG Exchange H and L with D and E
XTHL Exchange top of stack with H and L
Instruction Set
Arithmetic Group
The arithmetic instructions perform arithmetic operations such as addition,
subtraction, increment, and decrement data in registers or memory.
Addition: The contents of a register or the contents of a memory location or any 8-
bit number can be added to the contents of the accumulator. After addition, the sum
is stored in the accumulator.
Subtraction: An 8-bit number or the contents of a register or the contents of a
memory location can be subtracted from the contents of the accumulator. After
subtraction, the result will be stored in the accumulator.
Increment / Decrement:
The content of a register or a memory location, 8-bit data can be incremented or
decremented by 1.
In the same way, the contents of a register pair H-L or B-C or D-E (16-bit data) can
be incremented or decremented by 1.
The increment and decrement operations can also be performed in a memory
location.
Instruction Set
Arithmetic Group
Examples
ADD Add to accumulator
ADI Add immediate 8-bit data to accumulator
ADC Add to accumulator using carry flag
ACI Add immediate data to accumulator with carry
SUB Subtract from accumulator
SUI Subtract immediate data from accumulator
SBB Subtract from accumulator with borrow (carry) flag
SBI Subtract immediate from accumulator with borrow (carry) flag
INR Increment specified 8-bit data or byte by one
DCR Decrement specified 8-bit data or byte by one
INX Increment register pair by one
DCX Decrement register pair by one
DAD Double register addition: Add content of register pair to H-L register pair
Instruction Set
Logical Group
This group of instructions performs various logical operations such as AND, OR,
Exclusive-OR, Rotate, Compare, and Complement with the contents of the
accumulator.
AND, OR, Exclusive-OR: The content of a register or content of a memory

location or content any 8-bit data can be logically ANDed, Ored, or Exclusive-
ORed with the contents of the accumulator. Then results must be stored in the
accumulator.
Rotate: Each bit of the accumulator can be shifted either left or right by one bit.
Compare: An 8-bit number or the content of a register or content of a memory

location be compared with the contents of the accumulator to check greater than or
equal or less than.
Complement: The contents of the accumulator can be complemented. Therefore,

all 0’s are replaced by 1’s and all 1’s are replaced by 0’s.
Instruction Set
Logical Group
Examples
ANA Logical AND with accumulator
ANI Logical AND with accumulator using immediate data
ORA Logical OR with accumulator
OR Logical OR with accumulator using immediate data
XRA Exclusive logical OR with accumulator
XRI Exclusive OR using immediate data
CMP Compare
CPI Compare using immediate data
RLC Rotate accumulator left
RRC Rotate accumulator right
RAL Rotate left through carry
RAR Rotate right through carry
CMA Complement accumulator
CMC Complement carry flag
STC Set carry flag
Instruction Set
Branch Control Group
This group includes the instructions that change the sequence of program execution
using conditional and unconditional jumps, subroutine call and return, and restart.
Jump: Jump instructions are generally conditional jump and unconditional jump
types. Conditional jump instructions always test certain conditions such as Zero or
Carry flag and then change the program execution sequence once the condition
arises. On the other hand, when conditions are not used in the instruction set, the
instruction is called unconditional jump.
Call and Return, and Restart :These instructions can also change the sequence of
a program execution by calling a subroutine or returning from a subroutine. Like
Jump instructions, Call instructions are conditional call and unconditional call.
Conditional call instructions test all condition flags.
The unconditional branch control instructions are as follows:
JMP Jump
CALL Call
RET Return
Instruction Set
Stack I/O and Machine Control Group
These instructions can perform various functions related to stack and input/output
ports and machine control.
The following instructions are related with the Stack and/or Stack Pointer:
PUSH Push two bytes of data onto the stack
POP Pop two Bytes of data off the stack
XTHL Exchange top of stack with H and L
SPHL Move content of H and L to stack pointer
The I/O instructions are given below:

IN Initiate input operation
OUT Initiate output operation
The Machine Control instructions are as follows:

EI Enable interrupt system
DI Disable interrupt system
HLT Halt
NOP No operation
Instruction and Data Formats
In the Intel 8085 microprocessor, instructions are used to perform specified
functions. Each instruction consists of two parts, namely, operation code (opcode)
and operand.
The opcode states the operation which will be performed. Each operation is always
performed with some data. These data are known as operand.
Instructions are performed operations with 8-bit data and 16-bit data. 8-bit data can
be obtained from a register or a memory location or input port. Similarly, 16-bit data
may be available from a register pair or two consequent memory locations.
Therefore binary codes of instructions are different. Due to different ways of
specifying data for instructions, the machine or binary codes of all instructions are
of different lengths.
The Intel 8085 instructions are classified into the following three groups as given
below:
One-byte or 1-word instructions
Two-byte or 2-word instructions
Three-byte or 3-word instructions
One-byte or 1-word instructions
A one-byte instruction consists of the opcode and operand in the same byte.
Operand(s) are internal register and are coded into the instruction
In the first instruction, MOV B, A both operand registers are specified in A and B
registers.
In the second instruction ADD C, one operand is specified in the C register and the
other operand is in the accumulator, which is assumed.
These instructions are one-byte long and each instruction requires only one memory
location.
Two-byte or 2-word instructions
In a two-byte instruction, the first byte specifies the operation code and the second
byte states the operand.
The source operand is an 8-bit data immediately subsequently the opcode
The above instructions are 2-byte instructions. This instruction would require two
consecutive memory locations to store in memory.
Three-byte or 3-word instructions
In a three-byte instruction, the first byte specifies the operation code (opcode), and
the following two bytes stand for the 16-bit address.
It may be noted that the second byte will be the lower-order address and the third
byte will be the higher-order address.
These instructions are three-byte instructions which consist of one opcode and two
data bytes.
Opcode Format
Opcode Format
Data Format
Data Format
Assembly Language Programming
A Program is a set of instructions arranged in the specific sequence to do the
specific task.
The process of writing the set of instructions which tells the microprocessor what to
do is called programming.
In other words, we can say that programming is the process of telling the processor
exactly how to solve a problem.
To do this the programmer must speak to the processor in a language which

processor can understand
Steps involved in Programming
Steps involved in Programming
Flow Chart
The flow chart is a graphical tool that allows programmer to
represent various actions which are to be performed.
Illustration: Adding two Hexadecimal Numbers
Illustration: Data Transfer from register to output port
Arithmetic Operations
Example 1
Example 2
Example 2
Flags Concepts and Cautions
The flags are FF that are set or rest after the execution of arithmetic and logical
operations with some exceptions.
1 2
3
1
Subtraction
The 8085 performs subtraction by using 2’s complement
10s complement method
Logic Operations
Logic Operations
Logic Operations
Logic AND
Simple AND gate has two inputs and one output, while the instruction ANA
simulates eight AND gates .
Suppose register B holds 77H and the accumulator A holds 81H.

The result of the instruction ANA is 01H and is placed in the accumulator
Logic Operations
Logic Operations
Logic Operations
Logic Operations
OR, Exclusive OR and NOT
Logic Operations
OR, Exclusive OR and NOT
Logic Operations
Logic Operations
Logic Operations
Branch Operations
Branch Operations
Branch Operations
Branch Operations
Branch Operations
Writing Assembly Language Program
Programming Techniques: Looping
Additional Data Transfer and 16-bit
Arithmetic Instructions
Arithmetic Operations Related to Memory
Logic Operations: Rotate
Logic Operations: Compare
Dynamic Debugging
Dynamic Debugging
Dynamic Debugging
Interrupts of 8085 Microprocessor
Interrupts is the facility provided by the microprocessor to communicate with the
outside environment, and the microprocessor can divert its operation based on
priority.
The interrupts can be used for various applications in different environments
An interrupt is a process where an external device can get the attention of the
microprocessor.
The microprocessor can scan
the interrupt pin on every
machine cycle.
When the interrupt signal is
present, microprocessor
suspends its present operation
after storing the current status
in the microprocessor so that
the microprocessor can restart
the suspended work again
from where it left.
An interrupt is considered to be an emergency signal which may be serviced. The
microprocessor may respond to it as soon as possible.
When the microprocessor receives an interrupt signal, it suspends the currently
executing program and jumps to an Interrupt Service Routine (ISR) to respond to the
incoming interrupt. Each interrupt will most probably have its own ISR
Responding to an interrupt may be immediate or delayed depending on whether the
interrupt is maskable or nonmaskable and whether interrupts are being masked or
not.
There are two different ways of redirecting the execution to the ISR depending on
whether the interrupt is vectored or nonvectored.
In a vectored interrupt, the address of the subroutine is already known to the
microprocessor.
In case of a nonvectored interrupt, the I/O devices will have to supply the address of
the subroutine to the microprocessor.
Classification of Interrupts
Interrupts can be classified into two types: maskable interrupts and nonmaskable
interrupts.
The maskable interrupts can be delayed or rejected but the nonmaskable interrupts
cannot be delayed or rejected.
Interrupts can also be classified into vectored and nonvectored interrupts. In vectored
interrupts, the address of the service routine is hard-wired but in nonvectored
interrupts, the address of the service routine needs to be supplied externally by the
device
When a device interrupts, it actually wants the microprocessor to give a service,
which is equivalent to asking the microprocessor to call a subroutine.
This subroutine is known as Interrupt Service Routine (ISR).
An interrupt is considered to be an emergency signal.

The Microprocessor should respond to it as soon as possible.
When the Microprocessor receives an interrupt signal, it suspends the currently

executing program and jumps to an Interrupt Service Routine(ISR) to respond to the
incoming interrupt.
The ‘EI’ instruction is a one-byte instruction and is used to enable the nonmaskable
interrupts.
The ‘DI’ instruction is a one-byte instruction and is used to disable the nonmaskable
interrupts.
Interrupt Vectors and Vector Table
An interrupt vector is a pointer in which the Interrupt Service Routine (ISR) is stored
in memory.
All vectored interrupts are mapped onto a memory area called the Interrupt Vector
Table (IVT)
The IVT is usually located in memory page 00(0000H -00FFH).

The purpose of the IVT is to hold the vectors that redirect the microprocessor to the
right place when an interrupt arrives.
The IVT is divided into several blocks. Each block is used by one of the interrupts to
hold its “vector”
The 8085 Non-Vectored Interrupt Process
1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If there is an interrupt, the microprocessor will complete the executing instruction,
and start a RESTART sequence.
4. The RESTART sequence resets the interrupt flip flop and activates the interrupt
acknowledge signal(INTA).
5. Upon receiving the INTA signal, the interrupting device is expected to return the
op-code of one of the 8 RST instructions.
6. When the microprocessor executes the RST instruction received from the device,
it saves the address of the next instruction on the stack and jumps to the appropriate
entry in the IVT.
7. The IVT entry must redirect the microprocessor to the actual service routine.
8. The service routine must include the instruction EI to re-enable the interrupt
process.
9. At the end of the service routine, the RET instruction returns the execution to
where the program was interrupted.
The 8085 recognizes 8 RESTART
instructions: RST0 -RST7.each of these
would send the execution to a
predetermined hard-wired memory
location:
Restart Sequence
The restart sequence is made up of three machine cycles.
In the 1st machine cycle:

The microprocessor sends the INTA signal.
When INTA is active the microprocessor reads the data lines expecting to
receive, from the interrupting device, the opcode for the specific RST
instruction.
In the 2nd and 3rd machine cycles:

The 16-bit address of the next instruction is saved on the stack.
Then the microprocessor jumps to the address associated with the specified RST
instruction.
Hardware Generation of RST Opcode
How does the external device produce the opcode for
the appropriate RST instruction?
– The opcode is simply a collection of bits.
– So, the device needs to set the bits of the data bus to
the appropriate value in response to an INTA signal.
The following is an example of generating RST :RST

5’s opcode is EF
Hardware Generation of RST Opcode
During the interrupt acknowledge machine cycle,

(the 1st machine cycle of the RST operation):
The Microprocessor activates the INTA signal.
This signal will enable the Tri-state buffers, which
will place the value EFH on the data bus.
Therefore, sending the Microprocessor the RST 5
instruction.
Issues in Implementing INTR Interrupts
How long must INTR remain high?
– The microprocessor checks the INTR line one clock cycle before the last T-state of
each instruction.
– The interrupt process is Asynchronous.
– The INTR must remain active long enough to allow for the longest instruction.
– The longest instruction for the 8085 is the conditional CALL instruction which
requires 18 T-states.
Therefore, the INTR must remain active for 17.5 T-states.

TRAP
TRAP is the only non-maskable interrupt.It does not need to be enabled because it
cannot be disabled.
•It has the highest priority amongst interrupts.

•It is edge and level sensitive.
It needs to be high and stay high to be recognized.
Once it is recognized, it won’t be recognized again until it goes low, then high again.
•TRAP is usually used for power failure and emergency shutoff.

Internal Interrupt Priority
Internally, the 8085 implements an interrupt priority scheme.

– The interrupts are ordered as follows:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR
However, TRAP has lower priority than the HLD signal used for DMA.
Internal Interrupt Priority
Internally, the 8085 implements an interrupt priority scheme.

– The interrupts are ordered as follows:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR
However, TRAP has lower priority than the HLD signal used for DMA.
Stack
The stack is an area of memory identified by the

programmer for temporary storage of information.
• The stack is a LIFO structure.

– Last In First Out.
• The stack normally grows backwards into memory.

– In other words, the programmer defines the bottom
of the stack and the stack grows up into reducing
address range.
Stack
Stack
Stack
Stack
Stack
Stack
Operation of the Stack
• During pushing, the stack operates in a “decrement then store” style.

The stack pointer is decremented first, then the information is placed on the stack.
• During poping, the stack operates in a “use then increment” style.

The information is retrieved from the top of the stack and then the pointer is
incremented.
The SP pointer always points to “the top of the stack”.
LIFO
The order of PUSHs and POPs must be opposite of each other in order to retrieve
information back into its original location.
PUSH B
PUSH D
...
POP D
POP B
Stack
The PSW Register Pair
• The 8085 recognizes one additional register pair called the PSW (Program Status
Word).
– This register pair is made up of the Accumulator and the Flags registers.
•It is possible to push the PSW onto the stack, do whatever operations are needed,
then POP it off of the stack.
– The result is that the contents of the Accumulator and the status of the Flags are
returned to what they were before the operations were executed.
Subroutine
Some operations/functions are repeatedly performed in a main program like
multiplication, division, and time delay between two operations, etc.,
Groups of instructions are written to perform these operations and these groups of
instructions are known as subroutines, which are called by the main program
whenever required.
When a main program calls a subroutine, the program execution is transferred to

the subroutine and after the completion of the subroutine, the program execution
returns to the main program.
The microprocessor uses the stack to store the return address of the subroutine.
For example, generally, subroutine are written for sine, cosine, logarithms, square
root, time delay, and multiplication functions in 8085 microprocessors.
InAssemblylanguage,asubroutinecanexistanywhereinthecode.
Subroutine
A subroutine is implemented with two associated instructions, namely, Call and
Return.
Call is used to call a subroutine and the Call instruction is written in the main
program.
Return is used to return from the subroutine and the Return instruction is written in
the subroutine to return to the main program.
When a subroutine is called, the contents of the program counter are stored on the
stack, and the program execution is transferred to the subroutine address.
When the Return instruction is executed at the end of the subroutine, the memory
address stored in the stack is retrieved and the sequence of execution is resumed in
the main program.
Subroutine
Opcode Operand Description

CALL 16 bit Call subroutine conditionally located at the
memory address specified by 16-bit operand.
This instruction places the address of the next
instruction on the stack and transfers the
program execution to the subroutine address.
RET Return unconditionally from the subroutine.
This instruction locates the return address on
the top of the stack and transfers the program
execution back to the calling program.
Subroutine
Call Execution
Subroutine
The sequence of
events in the
execution of the
CALL instruction
by the 8085 is
shown in figure.
Subroutine
Subroutine
Subroutine
Subroutine
Subroutine
Subroutine
Subroutine
Subroutine
Subroutine
Subroutine
in previous example
Subroutine
Restart, Conditional Call and Return
Nesting
Nesting

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Unit 2

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Instruction Set and Addressing Modes

An instruction is any specified binary pattern which is placed inside the

There are various techniques to specify operand of instructions. These techniques

In this mode, the accumulator is implied as a second operand.

AND, OR, Exclusive-OR: The content of a register or content of a memory

Compare: An 8-bit number or the content of a register or content of a memory

Complement: The contents of the accumulator can be complemented. Therefore,

The I/O instructions are given below:

The Machine Control instructions are as follows:

To do this the programmer must speak to the processor in a language which

Suppose register B holds 77H and the accumulator A holds 81H.

An interrupt is considered to be an emergency signal.

When the Microprocessor receives an interrupt signal, it suspends the currently

The IVT is usually located in memory page 00(0000H -00FFH).

In the 1st machine cycle:

In the 2nd and 3rd machine cycles:

The following is an example of generating RST :RST

During the interrupt acknowledge machine cycle,

How long must INTR remain high?

Therefore, the INTR must remain active for 17.5 T-states.

•It has the highest priority amongst interrupts.

•TRAP is usually used for power failure and emergency shutoff.

Internally, the 8085 implements an interrupt priority scheme.

Internally, the 8085 implements an interrupt priority scheme.

The stack is an area of memory identified by the

• The stack is a LIFO structure.

• The stack normally grows backwards into memory.

• During pushing, the stack operates in a “decrement then store” style.

• During poping, the stack operates in a “use then increment” style.

The SP pointer always points to “the top of the stack”.

When a main program calls a subroutine, the program execution is transferred to

Opcode Operand Description

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