System

Verilog

PROCEDURAL
STATEMENTS
CONTROL FLOW
INTRODUCTION
BLOCKING
ASSIGNMENT
PROCEDURAL
STATEMENTS NONBLOCKING
ASSIGNMENT

WHILE, DO-WHILE

FOREACH
LOOP STATE MEN T S
ENHANCED FOR LOOP

REPEAT, FOREVER

BREAK
JUMP
STATEMENTS
CONTINUE
 BLOCKING
ASSIGNMENT
A Syst e mVe r i l o g B l o c k i ng as s i g nme nt
i s an ass i g nme nt st at e me nt t hat
e x e c ut e s i n a s e r i e s o r de r , b l ock i ng t he
e x e c ut i on of t he ne xt s t at e me nt unt i l
t he c ompl e t i o n of t he cur r e nt
as s i g nme nt e xe c u t i on. The s e
as s i g nme nt s a r e ma de us i ng t he " = "
ope r at or an d a r e e xe c ut e d one aft e r
t he ot he r i n a pr o c e du r a l b l ock .
BLOCKI NG AS S I GN MENTS E XA MP L E S

OUTPUT
NONBLOCKING
ASSIGNMENT
Non- bl oc ki n g a s s i g nme nt s t at e me nt s
al l ow mul t i pl e a s s i g nme nt s t o occur i n
par al l e l wi t h o u t bl o c k i n g t he e x e cut i on
of fol l owi ng s t a t e me n t s . Thi s me ans
t ha t al l t he a s s i g nme nt s w i l l occur at
t he same t i me , du r i n g t he e nd of
s i mul a t i on t i me s t a mp.
Non- bl oc ki n g a s s i g nme nt s t at e me nt s
ar e spe c i fi e d u s i ng t h e l e s s t han or
e qual t o sym bo l ( < = ) . I t ' s i nt e r e s t i ng t o
not e t hat t h i s s ymbo l i s al s o us e d as a
r e l at i onal ope r a t o r i n e xp r e s s i ons .
NON- BLOCK I N G AS S I GN ME N TS E XA MP L E S

OUTPUT
BLOCKING ASSIGNMENTS EXAMPLES NON-BLOCKING ASSIGNMENTS EXAMPLES

OUTPUT OUTPUT
 LOOP STATEMENTS
WHILE LOOP
SYNTAX

The "while" loop in

SystemVerilog is used to
execute a block of code EXAMPLE
repeatedly while a
specific condition is true.
The loop will continue to
execute until the
condition becomes false.
 LOOP STATEMENTS
DO WHILE LOOP
SYNTAX

The "do-while" loop in

SystemVerilog is used to
execute a block of code
EXAMPLE
repeatedly until a specific
condition is met. This type of
loop is similar to the "while"
loop, but with one key
difference - in a "do-while"
loop, the block of code is
executed at least once,
regardless of whether the
condition is true or false.
 LOOP STATEMENTS
FOREACH LOOP
SYNTAX

The foreach loop is a

powerful construct in EXAMPLE

SystemVerilog that simplifies SI NGLE

DI MENSI ON AL

the process of iterating over

AR R AY.

elements in an array. It
eliminates the need for index
variables and can be used
with both single and multi- MULTI DI ME N S I O N AL
AR R AY

dimensional arrays.
 LOOP STATEMENTS
FOR LOOP EXAMPLE

The for loop is a control

statement that is used to
execute a set of statements
repeatedly based on a specified
condition.

SYNTAX
 LOOP STATEMENTS
REPEAT LOOP EXAMPLE
Thi s loop i s used to execute a s et
of statements for a fi xed n umber of
ti mes.
SYNTAX

FOREVER LOOP EXAMPLE

Thi s loop executes the s ta temen ts

wi thin the bl ock i ndefi nitel y.

SYNTAX
 JUMP STATEMENTS
BREAK

The "break" statement is us ed to

terminate a l oop earl y. Wh en th e
" break" statement i s en coun tered
wi thin a l oop, the l oop is
i mmedi atel y termi nated a n d th e
program conti nues executin g th e
code that f ol l ows the l oop.

EXAMPLE OUTPUT
 JUMP STATEMENTS
CONTINUE
SYNTAX
EXAMPLE
The "conti nue" statement is us ed to
ski p over certai n i teration s of a
loop. When the " con tin ue"
statement i s encountered with in a
loop, the l oop i mmedi atel y mov es
on to the next i teration with out
executi ng any further code with in
the loop f or the current itera tion .
OUTPUT
BLOCKING ASSIGNMENT AL STA
UR

TEM NT
OCED

E
R
NONBLOCKING

P
S

ASSIGNMENT WHILE, DO-WHILE

P
STATEM FOREACH

LOO

ENTS
ENHANCED FOR LOOP

REPEAT, FOREVER

STATEM
BREAK
JUMP

ENTS
CONTINUE
 Jairaj Mirashi
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