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Analysis ‐ Introduction
• Goal of TA is to estimate when the output of given circuit becomes stable.
Timing Analysis
• The output needs to be stable by t = T for the correct functionality. But how to make sure of it?
• Two Approaches
– Dynamic Timing Analysis (through simulation cycle by cycle)
– Static Timing Analysis (analyzing signal paths)
Purposes of Timing Analysis Dynamic Timing Analysis
• Timing verification The features of DTA are:
if a design meets a given timing constraint? • Both functionality and timing of the design are checked
Example: cycle‐time constraint • It requires two inputs to simulate the design:
– A transistor level or gate level circuit representation of the design
• Timing optimization
– Stimulus or input vectors
Optimizes the critical portion of a design • Ideal for small gate level circuits
Identifies critical paths (limits performance of design)
• Requires SPICE models to simulate transistor level circuits
• Requires functional and timing models to simulate gate level circuits
To verify timing of design , a SDF containing timing information of all cells in the design is used to
provide timing information for both DTA and STA.
Static Timing Analysis Static Timing Analysis
The features of STA are: Static timing analysis refers to the process used to verify timing of large gate level
• Only timing of large gate level netlists is checked using a non‐vector based approach circuits using a non‐vector based approach.
• The circuit is assumed to be functionally correct
• Requires Timing models
STA in ASIC Flow Approaches used by DTA and STA
DTA STA
Coverage can be increased in DTA by adding more False timing violations can be eliminated by
input vectors. adding timing exceptions.
Timing exceptions are nothing but constraints which don’t follow the default when doing timing analysis.
Advantages and Disadvantages of DTA and STA
Comparison of the Analysis Process of DTA & STA
Dynamic Timing Analysis (DTA) Static Timing Analysis (STA) DTA STA
SPICE Simulation
Advantages Disadvantages Advantages Disadvantages Gate Level Simulation (GLS)
(Transistor Circuits)
Quality of results Fast, exhaustive
Estimate is pessimistic Load transistor level netlist Load Gate level netlist Load Gate level netlist
depends on how because it is designed
Very accurate (Process, Voltage and
exhaustive the to check only timing
Temperature) Load functional and timing
stimulus vectors are not functionality Load SPICE models Load timing models
models
Considers both Load input vectors Load input vectors Load constraints (SDC)
Verifies the timing of Must define timing
functionality and Slow in simulation Set operating voltage,
all paths in the design requirements/exceptions Load Liberty file Load Liberty file
timing temperature
Suitable for small Not suitable for large Suitable for large Difficulty to handle Run simulation and write out Run simulation and write out Run timing analysis and write
designs designs designs asynchronous designs waveforms waveforms out timing reports
Standard Delay Format (SDF) Standard Delay Format (SDF) Generation
• Contain timing information of all cells in the design. • Pre‐layout SDF File:
• Timing values in SDF files usually from ASIC delay calculation tools that take connectivity, technology – Generated by using wire load models but doesn’t include clock trees in general.
and layout geometry information into account.
• The SDF specifies – Includes only the logic cell delay and interconnect delay.
– IOPATH delay For Ex: *_map.sdf (Contains gate delay only)
• Specifies cell delay, computed based on transition of input signal and output wire loading
– INTERCONNECT delay • Post‐layout SDF File:
• Point‐to‐point, path‐based delay, including the RC delay between driving and driven gate
contain delay values that are based on actual layout, including logic cell delay,
– Timing check
interconnect delay and clock tree delays.
• Contain value that determine required setup time and hold time of each sequential cell.
For Ex: *_timesim.sdf
CELL Delay CELL Delay – Supply Voltage
Cell Delay is not constant. It depends on several factors such as the supply voltage, load at the output
pin, slew of the signal at the input pin, and the temperature.
As the supply voltage increases, cell delay decreases.
When the supply voltage increases, the charge carriers are accelerated, which results in increase in current
(i.e. I = dQ/dt).
This phenomenon reduces the time it takes for a signal to pass from an input to the output of a logic gate
(cell) and from the Startpoint to the Endpoint in a circuit.
• As the load at the output pin increases, the cell delay also increases. • As the slew at the input pin increases, the cell delay also increases.
• Due to larger load at an output pin of a logic gate or cell, it takes longer time for a
signal to charge and discharge through the load capacitance. Note that Q = C.V, • Slew describes the rate of rise or fall of a signal.
where, • A signal with a larger slew takes a longer time to flow through the logic gates or cells.
C =the capacitance of the load,
Q =Charge associated with the load, and • Hence, larger slew associated with a signal increases the cell delay, which in turn increases
V =the voltage or potential across the load. the overall propagation delay of a signal from the Startpoint to Endpoint in a timing path.
• As the load capacitance increases, the charge and discharge time for a signal
propagating through it also increases, and this leads to the delay in propagation of a
signal from one node to another node in a circuit.
CELL Delay – Temperature CELL Delay – Other Factors
• Hence, with the increase in temperature it takes a longer time for a signal to flow from one
node to another node in a logic gate or circuit.
• A phenomenon called temperature inversion alters this behaviour.
Fan‐out
• It is the greatest number of inputs of gates of the same type to which the output can be safely
connected.
• The maximum fan‐out of an output measures its load driving capability.
Timing parameter Definition • Fan out for CMOS family depends upon the input and output current ratings of the logic circuit.
MODULE‐IV ASIC DESIGN 20
Rise and fall time
Fan‐in
tF tR
• Physical logic gates with a large fan‐in tend to be slower than those with a small fan‐in.
• Fan in of CMOS family can be more than 2 by extending series‐parallel design of CMOS using NAND V10%
and NOR gates.
t0 t1 t2 t3
• A gate with fan‐in ‘n’ is obtained by using n series and n parallel transistors.
• Rise time: measured from 10% point to 90% pointtR = t3 ‐ t2
Setup and Hold Times Understanding Setup and Hold Times: Data Transitions under
Different Conditions
• Flip‐flops are edge sensitive.
• The Setup and Hold times for an edge‐triggered sequential element will vary
depending on the data and the clock transition.
Condition 1: Data must remain stable within the Sampling window
Condition 2: Data transition happens in the Setup window
Setup Time Hold Time Condition 3: Data transition within the Hold window
It is the time interval before the It is the time interval after the arrival Condition 4: Data transition happens within both the Setup and the Hold windows
arrival of an active clock edge for of an active clock edge for which the
which the data must remain stable. data must remain stable.
MODULE‐IV ASIC DESIGN 23
Condition 1: Data must remain stable within the Sampling
Condition 2: Data transition happens in the Setup window
window
Condition 4: Data transition happens within both the Setup and
Condition 3: Data transition within the Hold window
the Hold windows
Timing Arcs
Timing Arcs
Cell Delay Arcs Cell Delay Arcs for a NOT Gate
• The cell delay arcs can also be classified as Combinational arcs and Sequential
arcs.
• Combinational arcs are defined between the input pin and the output pin of a
combinational cell.
• The Sequential arcs are defined between the CLK pin and the input/output pin of a
sequential cell.
• The source pin is the pin of the logic element from which timing arc originates.
• The sink pin is the pin of the logic element at which timing arc ends.
For example,
•Propaga on delay, from A → Y for a buffer
•CLK → Q delay for a flip‐flop
Cell Delay Arcs for a NOT Gate Delay Arcs for a Flip‐flop
Each of these timing arcs is represented as separate delay table in the Liberty file.
Timing Arcs Net Delay Arcs
• Net delay arcs represent the delay due to a net.
• The net delay arc represents delay from the source pin, OUT to the sink pin, IN2 of the net
connecting the two OR gates.
Timing Arcs Constraint Arcs
• A timing arc with well‐defined timing constraint that is defined for an input pin or between input pins
of a logic cell/element is known as constraint arc.
Delay and Constraint Arcs for a Flip‐flop Test for Understanding
• What are the limitations on Fan‐In of logic gates?
• Define Setup and Hold Time.
• Conditions to meet setup and hold time?
• What are timing arcs and it’s classification?
• Difference between delay arc and constraint arc
Cell delay arc, Net Delay arc and constraint arc Cell delay arc, Net Delay arc and constraint arc
Timing Paths Timing Paths
Path1: Register to Register (reg‐to‐reg)
Path2: Input port to Register (input‐to‐reg)
Path3: Register to Output port (reg‐to‐output)
Path4: Input port to Output port (input‐to‐output)
Key Terminologies – Timing Path Key Terminologies – Timing Path
Delay of each gate = 100ps Delay of each gate = 100ps
Constraint: Constraint:
Maximum delay from input Maximum delay from input
port to output port must be port to output port must be
less than 400ps less than 400ps
• The Critical path determines the maximum frequency of operation of a design.
• For the circuit shown, • A timing path that fails to meet the timing constraint by the largest margin in a design is
Delay A → Y = 500ps, B → Y = 400ps and C → Y = 100ps. called the Critical Path. If all timing paths are meeting the constraints, then the path that is
A → Y delay is the Cri cal Path for the circuit since it is failing by largest margin of 400‐500 = ‐100ps. closest to failing is called the Critical Path.
Arrival Time: Required Time
• The time elapsed for a signal to arrive at a certain point is known as the Arrival Time. • The latest time by which a signal should arrive at a certain point is known as the Required Time.
For this circuit, when pin A is the Startpoint:
For the circuit shown, Required time at pin Y is 400ps.
• Arrival Time at the output pin of I1 is 100ps, and
• Arrival time for pin Y is 500ps,
Key Terminologies – Timing Path Launch and Latch Edge
Slack
• The difference between the Required time and the Arrival time is called Slack.
For the circuit shown,
Slack at pin Y = Required time – Arrival time
Slack at pin Y= 400 – 500 = ‐100ps
A positive slack indicates that the timing is met, while a negative slack indicates that the timing is
violated by the amount of the slack.
MODULE‐IV ASIC DESIGN 50
Clock Path and Data Path Definitions
• The Clock path is the path starting from the common point of clock network (between the Launch
and Capture sequential cells or flip‐flops) to the clock pin of the capturing sequential cell or flip‐flop. Critical Path A timing path that fails to meet the timing constraint by the largest
• Data path is the path starting from the common point of clock network (between the Launch and margin in a design.
Capture sequential cells or flip‐flops) to the data pin of the capturing sequential cell/flip‐flop. Arrival Time The time elapsed for a signal to arrive at a certain point.
Required Time The latest time by which a signal should arrive at a certain point.
Slack The difference between the Required time and the Arrival time.
Launch Clock Clock connected to a launching flip‐flop.
Capture Clock Clock connected to a capturing flip‐flop.
Clock Path The path starting from the common point of a clock network to the
clock pin of the capturing sequential cell.
Data path The path starting from the common point of clock network to the
data pin of the capturing sequential cell
Clock Uncertainty Clock Slew or Transition time
• Normally clock uncertainty is refer to the target skew during the synthesis before the designer get • Amount of time it takes for a signal transition to occur.
the actual skew after CTS.
• Accounts for uncertainty in rise and fall time of the signal.
• Clock uncertainty is some margin that you add to the clock edge because you are not sure at what • Slew rate is measured in V/Sec
time the event will occur.
Ideal CLK1
CLK1
Clock skew Types of skew
The difference in the arrival of clock signal at the clock pin of related flops.
• Global skew
The difference in the arrival of clock signal at the clock pin of non related
flops.
Skew can be positive or negative.
When data and clock are routed in same direction then it is Positive skew.
When data and clock are routed in opposite then it is negative skew.
Types of skew Clock latency
Clock latency is the delay in the clock arrival.
Suppose a block receives a clock through a buffer, then the buffer delay causes the clock to
• Useful skew arrive late at the block.
Total Latency
= 100 ps
Ideal CLK1
Ideal
Useful skew is a concept of delaying the capturing flip‐flop clock path, this approach CLK1
Source Network Latency CLK1
helps in meeting setup requirement with in the launch and capture timing path. Latency = 80ps
=20ps
Setup (Late) Hold (Early)
Uncertainty Uncertainty
– But the hold‐requirement has to be met for the design = 80 ps = 70 ps
Source Delay (or Source Latency)
It is defined as "the delay from the clock origin point to the clock definition point in the design
(Delay from clock source to beginning of clock tree )
Network Delay(latency)
It is defined as "the delay from the clock definition point to the clock pin of the register
Timing Paths Clock Path and Data Path
• The Clock path is the path starting from the common point of clock network (between the Launch
and Capture sequential cells or flip‐flops) to the clock pin of the capturing sequential cell or flip‐flop.
• Data path is the path starting from the common point of clock network (between the Launch and
Capture sequential cells or flip‐flops) to the data pin of the capturing sequential cell/flip‐flop.
Path1: Register to Register (reg‐to‐reg)
Path2: Input port to Register (input‐to‐reg)
Path3: Register to Output port (reg‐to‐output)
Path4: Input port to Output port (input‐to‐output)
Clock gating path False Path
A timing path that is not required to meet its timing constraints for the design to
• LD pin is not a part of any clock but it is using for gating the original CLK signal. function properly is known as False path.
• These path neither a part of Clock path nor of Data Path.
Multi‐cycle paths Asynchronous path
Multi-cycle paths are paths between registers that take more than one clock cycle to become stable.
• A path from input port of an asynchronous set or clear pin of a sequential element
Output SIN/COS requires 4 clock-cycles after the input ANGLE is latched in.
This means that the combinatorial block (the Unrolled Cordic) can take up to 4 clock periods (25MHz) to
propagate its result.
• Timing critical path are those path that do not meet your timing.
• A timing path that fails to meet the timing constraint by the largest margin in a design is
called the Critical Path. If all timing paths are meeting the constraints, then the path that is
closest to failing is called the Critical Path.
Single Cycle Path Launch and Capture Path
• A Single‐cycle path is a timing path that is designed to take only one clock cycle for the data to
propagate from the start point to the endpoint.
Launch path is launch clock path which is responsible for launching the data at launch
flip flop.
Capture path is capture clock path which is responsible for capturing the data at
capture flip flop.
Longest and Shortest Path
• Longest path is the one that takes longest time, this is also called worst path or late path or a max
path.
• The shortest path is the one that takes the shortest time; this is also called the best path or early
path or a min path.
Timing Analysis
Calculating Gate Delay Calculating Gate Delay using Interpolation vs. Extrapolation
Calculation of gate delay using interpolation
Calculation of gate delay using interpolation • Calculation of gate delay using extrapolation
• For scenarios out of the range (for example, input slew of 25ps), STA uses extrapolation
• It is good to avoid using a value outside the characterization range of input slew and output loads
since extrapolation may not be so accurate.
Calculating Gate Delay using Interpolation vs. Extrapolation Estimating Path Delay for Combinational Circuits
Calculation of gate delay using extrapolation
• Estimating the path delay between IN and OUT.
Estimating Path Delay for Combinational Circuits
Estimating Path Delay for Combinational Circuits
• Propagation Delay of I1 • Propagation Delay of I2
To determine the propagation delay of I1 we need to know
To determine the propagation delay of I2 we need to know Input Capacitance at I2: 1pF
Slew at IN or A of I1 ‐ is 10ps as per specification Slew at A of I2 : 10ps
Slew at A of I2 ‐ derive this from the slew table of the inverter
Load at Y of I1 – is the pin capacitance at pin A of I2 = 1pF as given in the
specification Cell delay of I1: 40ps Load at Y or OUT of I2 is 2pF as per the specification Cell delay of I1: 50ps
Computing Path Delay
Steps for Analysing a Timing Path having sequential cells
Analysis of reg‐to‐reg Path for Setup Time:
Step 1 Analysis of reg‐to‐reg Path for Setup Time: Step 2
• Step 3: List the cells and corresponding timing arcs in the launch path • Step 4: Add all the timing arcs in the launch path that contribute to Arrival Time (AT)
• CK Q of FF1 to form an expression.
• A Y of B1 • Arrival time (AT) = (CK Q )of FF1 + (A Y) of B1
Analysis of reg‐to‐reg Path for Setup Time: Step 5 Analysis of reg‐to‐reg Path for Setup Time: Step 6
• Step 5: List the cells and corresponding timing arcs in the capture path • Step 6: Compute Required Time (RT) using timing arc delays from Step 5.
– Setup of FF2 – Required Time (RT) = CLK Period – Setup Time of FF2
– Note that FF2 Captures the data from FF1 in the next clock cycle.
• Step 7: Compute AT and RT by substituting timing arc delays from Liberty file in AT
and RT expressions and determine the slack as RT‐AT.
– Setup Slack = Required Time – Arrival Time
– Setup Slack = [(CLK Period – Setup Time of FF2 )] – [ (CK Q )of FF1 + (A Y) of B1]
– If set up is positive, it concludes that circuit has met setup requirement else it’s setup violation.
Setup Slack Calculation Hold analysis
For the data to be successfully latched, the flip‐flop FF2 takes a finite amount of
time.
Hence, if data at its input is over‐written, then the data is lost.
• To meet hold time requirement for FF2
• Arrival Time(AT) – Required Time(RT) = Hold slack > 0, where,
AT= (CK Q Delay of FF2) + (A Y delay of B1 )
RT= Hold time FF2
Hold Slack = Arrival Time – Required Time.
Input Delay Output Delay
Setup slack= RT‐AT
= [clock period‐(setup time of FF2)] –[(Ck Q delay of FF_i) + (AY delay of B1) + (A Y
Setup slack= RT‐AT
delay of B2)] = [clock period‐(setup time of FF_0)] –[(Ck Q delay of FF2) + (AY delay of B1)
+ (A Y delay of B2)]
Input Delay = (Ck‐Q delay of FF_i) + (AY delay of B1 )
Output Delay = (A Y delay of B2) – (setup time of FF_0 )
This circuit meets the hold time requirement if the following condition is satisfied:
Analysis of input‐to‐output Path
• Input‐to‐output paths are checked for timing using maximum delay and
minimum delay values specified as part of constraints
• These paths meet the timing requirements if:
• Delay (A → B) < (Maximum delay constraint)
• Delay (A → B) > (Minimum delay constraint)