STA, Timing paths, FF requirements

Constraints and Logic Synthesis

Islam Ahmed, Hossam Hassan

1
Outline
 Static Timing Analysis (STA)
 Timing paths
 FF operation and requirements
 Design Objects [for all Synopsys tools]
 Design Constraints
 Basics of Logic Synthesis
 Basic Synthesis flow

2
Basics of Static Timing analysis
• Static Timing Analysis (STA) is a method for determining if a circuit meets
timing constraints without having to simulate.
• Simulation (dynamic analysis) circuit response for a specified set of input
patterns.

• STA is used to:

 Validates if the design can operate at the set timing constraints. [reports timing
violations]
 Is a complete and exhaustive verification of all timing checks of a design.
 Is used instead of simulation.

3
Basics of Static Timing analysis

SC Derates and
Constraints .SPEF Gatelevel netlist (.v) Uncertainites
.libs

Static Timing Analysis (PT)

Timing reports SDF files

4
 Static Timing Analysis Gatelevel Timing Simulation
Usage check timing requirements: setup, hold, recovery, Functional and timing simulation, checking functionality by
removal, Logical DRCs. comparing output VS expected output.

More accurate
Much faster than timing-driven simulation. Can catch issues like glitches.
Exhaustive, checks every possible constrained
timing path.
No vector generation is required.
The signal at the input is propagated through the
gates at each level till it reaches the output

Limitations Only useful for synchronous digital circuits, can’t Analysis quality can be dependent on stimulus vectors
analyze asynchronous systems Takes a lot if time and computational power.
Less accurate Non-exhaustive.
Must define timing requirements, false paths..etc.

Required inputs gatelevel netlist, .lib files, .sdc, derates, .spef gatelevel netlist, library .v, .sdf, test vectors, expected output.

5
Basics of Static Timing analysis
- Much faster than timing-driven, gate-level simulation.
- Proper circuit functionality is not checked.
- Vector generation NOT required.

It is used to determine all the possible timing violations including setup, hold, recovery
removal and min_pulse_width in a design for a specified clock, without applying test
vectors.

6
Timing paths
- Three main steps are followed by STA tools (ex. PT):
1. Circuit is broken down into sets of timing paths.
2. Delay of each path is calculated.
3. Path delays are checked to see if timing constraints have been met.

A timing path is a point-to-point path in a design which can propagate data from
one flip-flop to another

7
Timing Path Types
There are 4 types of paths in any synchronous circuit

register-to- register-to-output
input-to-register (in2reg)
register(reg2reg) (reg2out)

D Q D Q
DFF DFF

CLK CLK

Clock

Input-to-output
(in2out)
Combinational
Logic

8
Timing paths
- A path is a route from a Startpoint to an Endpoint
• A startpoint can be:
1. clock pin of a FF,
2. An input port.
• An endpoint can be:
1. Input data pin of a FF
2. An output port.

Remember that STA is exhaustive, therefore:

- Many paths can be going to any one endpoint.
- Many paths can exist for each startpoint to endpoint combination.

9
Required Time
 Required time specifies the time point (interval) at which data is required to arrive at end point (data is
required to be stable after arrival).
 Time point after which data can become unstable (change) is called earliest required time
 Time point after which data cannot become unstable (change) is called latest required time
 The requirement is set by timing constraints like setup/hold, removal/recovery, etc.

cycle 1 cycle 2

clock

Hold violation will

occur here
Setup violation
latest will occur here
earliest
required time required time

10
Arrival Time
 Arrival time defines the time interval during which a data signal will arrive at a path endpoint (after arrival time
signal will be stable).
 Data is normally triggered by clock edge
 Data arrival depend on circuit delay, which vary (depend on temperature, supply voltage, etc.)
 Minimum delay, early arrival
 Maximum delay, late arrival

CLOCK
earliest
arrival time

latest
arrival time
Data Signal min
max

11
Slack and Critical Path


setup setup

clock clock

data data

12
Early and Latest Analysis
 STA tool calculates the slack of each logic path, in order to find critical path.
 Early and Latest analysis approaches:
 Assumes circuits have minimum delay, compares arrival time to earliest required time (hold check)
 Assumes circuits have maximum delay, compares arrival time to latest required time (setup check)

setup setup

clock clock

data data

13
 Clocked Storage Elements
Transparent Latch, Level Sensitive
– data passes through when clock high, latched when clock low

D-Type Register or Flip-Flop, Edge-Triggered

– data captured on rising edge of clock, held for rest of cycle

14
 Flip-Flops: Review of Internal Operation

→The main cause for setup and hold time requirements is

the feedback mechanism of the internal FF latches.

Setup time: the time the input should be stable BEFORE the
active clock edge, needed by first latch to sample the input and
store it correctly. [always > 0]
FF propagation delay (T[clk-to-Q]): the time
Hold time: the time the input should be stable After the needed by the slave latch to propagate the sampled
active clock edge, needed by the first latch to make sure no value by master latch to its output, AFTER the active
new value is sampled while the sampled logic value is being clock edge.
held, avoiding race conditions. [can be >0, 0, or <0 !!]
15
 Timing Verification of Synchronous Designs
A D-FF is characterized by 3 main parameters:
1. T[clk-to-q] – clock to output
2. T[setup] – setup time.
3. T[hold] – hold time

FF1
FF2
Q
F1 D
clk F1
Clk clk

0 2 4

16
5
T[clk-to-q]
 indicates the amount of time needed for a change in the flip flop-clock input (e.g.
rising edge) resulting in a permanent change at the flip-flop output (Q).

17
T[setup]
• Setup time is the minimum amount of time the data input should be held
steady before the clock event, so that the data is reliably sampled by the
clock.

18
T[hold]
• Hold time is the minimum amount of time the data input should be held
steady after the clock event, so that the data is reliably sampled by the clock.
• It’s not dependent on clock period!

19
 The requirements of Setup and Hold on timing paths

For Setup: T[clk-to-Q] + Tcomb + T[setup] ≤ Tclk + Tskew

For Hold: T[clk-to-Q] + Tcomb ≥ Thold + Tskew

Always start from launch FF clock, where the active edge is received!
20
Timing Constraints
 There are two main problems that can arise in a digital circuit:
1) Max Delay: the data doesn’t have enough time to pass from one register to the next
before the next clock edge.
2) Min Delay: the data path is so short that it passes through several registers during the
same cycle.

The data has to arrive at point B, Tsetup before the The data has to stay stable at point B, for Thold after
active clock edge. the active clock edge.

→ Therefore, the new data to be sampled has to be

21 delayed by [Tcq + Tprop] of at least Thold!
Interactive Flip-Flop operation, timing requirements

https://web.archive.org/web/20200701120033/http://onmyphd.com/?p=flip.flop

22
What is metastability?

 Whenever there are setup and hold time violations in any flip-flop, it enters a
state where its output is unpredictable: this state is known as metastable state
(quasi stable state);
 At the end of metastable state, the flip-flop settles down to either '1' or '0'.
 Whenever the input signal D does not meet the Tsetup and Thold of the given
D flip-flop, metastability occurs.

23
Exercise 5
For verifying chip proper operation; can we rely only on simulation or STA?

Where does optimization and analysis tools obtain a specific library FF characterstics
(tc2q/tsetup/thold)?

24
Exercise 6
Should we seek or avoid positive skew?

For next generation datacenter processors; what kind of STA violations is more concerning?

25
Back to Timing Paths

Synopsys timing reports format

26
 Static Timing Verification of FF2: Setup
FF1
FF2
Q
F1 U2 D
0ns 4ns
CLK
U3 F1
Clk CLK

FF1/clk 5.1ns
1.1ns

FF2/D

Setup

FF2/clk
1ns 5ns

27
8
PrimeTime Terminology
Data Arrival
FF1
FF2
Q
F1 U2 D
CLK
U3 F1
Clk CLK

Data Required

Data Arrival
Slack is the difference between
Time
data arrival and data required.

FF1/clk 5.1ns
1.1ns
Data
FF2/D Required
Time
Setup

FF2/clk
28 1ns 5ns
9
 Four Sections in a Timing Report
report_timing
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Header Path Group: Clk
Path Type: max

Point Incr Path

-----------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (propagated) 1.10 * 1.10
Data FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.50 * 1.60 r
arrival U2/Y (buf1a27) 0.11 * 1.71 r
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

clock Clk (rise edge) 4.00 4.00

Data clock network delay (propagated) 1.00 * 5.00
FF2/CLK (fdef1a15) 5.00 r
required library setup time -0.21 * 4.79
data required time 4.79
------------------------------------------------------------
data required time 4.79
Slack data arrival time -1.87
------------------------------------------------------------
29 slack (MET) 2.92 10
The Header

Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)

Header Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max
Capture clock

Report is for setup

FF1
FF2
Q
F1 U2 D
CLK
U3 F1
Clk CLK

30
11
Data Arrival Section Calculated
latency
Point Incr Path
-----------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
Data FF1/Q (fdef1a15) 0.50 * 1.60 r
arrival U2/Y (buf1a27) 0.11 * 1.71 r
Library reference names
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

.11ns
.11ns
.50ns .05ns
1.1ns Q
F1 r U2 D
r U3 r
r CLK r F1
0 2 4
FF1 CLK
Clk
FF2

31
12
Data Required Section
Point Incr Path
-----------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.50 * 1.60 r
U2/Y (buf1a27) 0.11 * 1.71 r
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

clock Clk (rise edge) 4.00 4.00

clock network delay (propagated) 1.00 * 5.00
Data FF2/CLK (fdef1a15) 5.00 r
required library setup time -0.21 * 4.79
data required time 4.79

FF1
FF2
Q
F1 U2 D 0.21ns
0 2 4 1.0ns CLK
U3 F1
r
Clk CLK
32
13
 Summary - Slack
report_timing
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max

Point Incr Path

-----------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.50 * 1.60 r
U2/Y (buf1a27) 0.11 * 1.71 r
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

clock Clk (rise edge) 4.00 4.00

clock network delay (propagated) 1.00 * 5.00
FF2/CLK (fdef1a15) 5.00 r
library setup time -0.21 * 4.79
data required time 4.79
------------------------------------------------------------
data required time 4.79
data arrival time -1.87
Slack ------------------------------------------------------------
33 slack (MET) 2.92 14
Static Timing Verification of FF2: Hold
FF1
FF2
Q
F1 U2 D
0ns 4ns CLK
U3 F1
Clk CLK

FF1/clk 5.1ns
1.1ns

FF2/D STABLE

Hold

FF2/clk
1ns 5ns

34
15
Which Edges are Used in a Timing Report?
FF1
FF2
Q
F1 U2 D
0ns 4ns U3 F1
CLK
Clk CLK

FF1/clk 5.1ns
1.1ns

FF2/D

Hold Setup

FF2/clk
1ns 5ns
35
16
 PrimeTime Terminology Data Arrival
FF1
FF2
Q
F1 U2 D
0ns 4ns U3 F1
CLK
Clk CLK

Data Required

Data Arrival

FF1/clk 5.1ns
1.1ns
Slack is the difference between
FF2/D data arrival and required.

Data Hold
Required
FF2/clk
36 1ns 5ns
17
Example Hold Timing Report
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: min

Point Incr Path

----------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.40 * 1.50 f
U2/Y (buf1a27) 0.05 * 1.55 f
U3/Y (buf1a27) 0.05 * 1.60 f
FF2/D (fdef1a15) 0.01 * 1.61 f
data arrival time 1.61

clock Clk (rise edge) 0.00 0.00

clock network delay (propagated) 1.00 * 1.00
FF2/CLK (fdef1a15) 1.00 r
library hold time 0.10 * 1.10
data required time 1.10
----------------------------------------------------------
data required time 1.10
data arrival time -1.61
----------------------------------------------------------
slack (MET) 0.51
37
18
Exercise
1. Identify all timing paths [assume i/p delay constraint = 0.3ns]
2. Calculate max. clock frequency

Setup requirement = 0.4 ns

for both FF’s

38
Exercise: Is there any setup or hold violation in this circuit?

Assume i/p delay constraint = 0.3ns

39
 3- Design Constraints

40
Timing Constraints
• “Simple Question”:
• How does the STA tool know what the required clock period is?
• Obvious Answer…
• We have to tell it! • We have to define constraints for the design.
• This is usually done using the Synopsys Design Constraints (SDC) syntax,
which is a superset of TCL.
• Three main categories of timing constraints:
• Clock definitions
• Modeling the world external to the chip
• Timing exceptions

41
Design Objects [for all Synopsys tools]
 Design: A circuit description that performs some logical function.
 The design may be stand-alone or may include other sub-designs.
 Cell: It is the instantiated name of the sub-design in the design.
 Reference: The original design to which the cell or instance refers.
 For example, a leaf cell in the netlist must be referenced from the link library, which
contains the functional description of the cell. Similarly an instantiated sub-design must be
referenced in the design, which contains functional description of the instantiated sub-
design.

 Port: These are the primary inputs, outputs or IO’s of the design.
 Pin: It corresponds to the inputs, outputs or IO’s of the cells in the design. (Note the
difference between port and pin).
 Net: These are the signal names, i.e., the wires that hook up the design together by
connecting ports to pins and/or pins to each other.
 Clock: The port or pin that is identified as a clock source. The identification may be internal
to the library or it may be done using dc_shell commands.

42
 Design Objects [for all Synopsys tools]
Cell Net Pin Design
Port

U1 U4
A U2
A AIN BUS0 INV0 OUT1[1:0]
B Q0 INV D0 Q[1:0]
B BIN
C C U3
CIN BUS1 INV1 D1
D D INV
Q1
DIN
CLK
CLK
ENCODER
Clock REGFILE
CLK CLK

RISC_CORE

The netlist defines 5 of the objects; you define the 6th:

create_clock –period 4 [get_ports CLK]

Stored as an attribute on the clock object. To see all attributes on the clock object: list_attributes –application –class clock
43
4
Timing Constraints

 Three main categories of timing constraints:

1. Timing definitions
2. Optimization goals and timing exceptions.
3. Modeling the world external to the chip.

44
Timing Constraints: Categories

Timing Modeling outside world Optimization goals and

Timing exceptions

create_clock set_driving_cell set_false_path

create_generated_clock set_load set_multicycle_path
set_input_delay
set_output_delay set_max_area
set_max_delay set_max_transition
set_max_capacitance
set_clock_uncertainty set_max_fanout

45
 Create_clock → The create_clock command creates a clock object in the current design. The command defines the specified
source_objects as clock sources in the current design. A pin or port can be a source for a single clock.
EX:
create_clock -name CLKP 10 [get_pins UPLL0/CLKOUT]
# Create a master clock with name CLKP of period 10ns
# with 50% duty cycle at the CLKOUT pin of the PLL.

 create_generated_clock → The create_generated_clock command creates a generated clock object in the current design. This
command defines a list of objects as generated clock sources in the current design. You can specify a pin or a port as a generated clock
object. The command also specifies the clock source from which it is generated. The advantage of using this command is that
whenever the master clock changes, the generated clock changes automatically.
EX:
The following example creates a frequency -divide_by 2 generated clock:
#create_generated_clock -divide_by 2 -source CLK [get_pins foo]

46
 set_clock_uncertainty and Setup Timing
Example:
create_clock -period 2 [get_ports CLK]
set_clock_uncertainty –setup 0.14 [get_clocks CLK]

D Q X D Q
FF1 FF2 FF2 setup check at:
2 - 0.14 - 0.08 = 1.78

FF1 Data Launch Edge

(No uncertainty!) / /
.14 .08

0 1 1.78 1.92 2
Max allowable delay
for block “X” Assume lib
setup = 0.08ns
47
Clock Specification for Synthesis
 Each clock in the design must be defined using the create_clock command.
 It is recommended that the set_dont_touch_network command be used for clocks to prevent synthesis from
buffering clock trees.

 Input delay constraint, and output delay constraint: define the length of the path OUTSIDE the block.

Example.
set_input_delay –max 0.8 –clock clk\
[remove_from_collection[all_inputs] [get_portsclk]]

set_output_delay –max 2.5 –clock clk[all_outputs]

48
Combinational Designs
 Sometimes the design is a combinational circuit
 There is no clock to constraint timing

Circuit under design

Combinational
Logic

49
Combinational Designs (2)
 Combinational circuit is put in the same clocked environment as the clocked one
 An abstract clock called “Virtual clock” is defined for this environment
 By setting correct clock period, input/output delays, the delay of the combinational logic can be controlled

Combinational Q
D
D Q Logic DFF
DFF
CLK
CLK

Clock
Delaymax= Tclk– Delayin – Delayout=7ns Delayout=3ns
Delayin=1ns

50
 set_min_delay
This command sets the minimm delay target for paths in the
current design. Minimum delay is considered as an optimization
constraint by the compile command. If a path violates the
requirement given in a set_min_delay command, compile adds delay
to fix the violation.
EX:
In the following example, the set_min_delay command requires that
any delay path that passes through the UI cell and ends at the Y port
is greater than 12.5 time units:
#set_min_delay 12.5 -through U1 -to Y
51
 set_max_delay
This command Specifies the desired maximum delay for paths in the
current design.This command specifies that the maximum path
length for any start point in from_list to any endpoint in to_list
must be less than delay_value.
EX:
The following example shows how to optimize the design so that
any delay path to a port named Y is less than 10 units.
#set_max_delay 10.0 -to {Y}
Boundary Conditions
 For modeling the world outside the block, we need to model:
1) The transitions on the input
2) A load capacitance on the output.

Example.
set_driving_cell –cell [get_lib_cells LIB/BUF2]
-pin X [remove_from_collection [all_inputs]
[all_clocks] ]

set_input_transition 0.02 [remove_from_collection [all_inputs]

[all_clocks] ]

set_load 0.12 [all_outputs]

52
 Exercise
0.3ns 0.3ns
Setup Time
Requirement
TO_BE_SYNTHESIZED

D Q M N D Q X D Q S T D Q
FF1 FF2 FF3 FF4
QB QB

Clk
Tclk= 2ns
◼ set_output_delay –max:
⚫ Describes the maximum time requirement of the external logic on the output ports
Note: we should make sure that our design helps the assumed FF outside the block to meet its
setup requirements! By choosing the appropriate value for max_output_delay
If FF has TSETUP = 0.3ns and TT = 0.3ns:
What is the max output_delay?
53
24
 Constraining Input Paths: Example 1
Spec:
Latest Data Arrival Time at Port A, after Jane’s launching clock edge = 0.6ns
mydesign.con
create_clock -period 2 [get_ports Clk] set_input_delay -max 0.6 -
clock Clk [get_ports A]

MY_DESIGN
JANE’s_DESIGN TSetup, FF2
0.2ns
Tmax
A
D Q M N D Q X D Q S
FF1 FF2 FF3
0.6ns
QB QB QB

Clk

What is the maximum delay Tmax for the input path N in

MY_DESIGN? __________________________
54
Constraining Output Paths : Example 1
Spec:
Latest Data Arrival Time at Port B, before Joe’s capturing clock = 0.8ns mydesign.con
create_clock -period 2 [get_ports Clk] set_input_delay -max 0.6 -
clock Clk [get_ports A]
set_output_delay -max 0.8 -clock Clk [get_ports B]

JOE’s_DESIGN
MY_DESIGN TT + Tsetup
Tmax 0.7ns 0.1ns
B
N D Q X D Q S T D Q
FF2 FF3 FF4
QB QB QB
Clk

What is the maximum delay Tmax for the output path through

S in MY_DESIGN? __________________________
55
 Multiple Inputs/Outputs - Same Constraints
MY_DESIGN
A Out1
D Q S
B M

C Out2
N D Q T
Clk

To constrain all inputs the same, except for the clock port:
set_input_delay –max 0.5 –clock Clk \
[remove_from_collection [all_inputs] [get_ports Clk]]

To constrain all outputs the same:

set_output_delay –max 1.1 –clock Clk [all_outputs]

56
Time Budgeting Example
timing_budget.tcl

# A generic Time Budgeting script file

# for MY_BLOCK, X_BLOCK and Y_BLOCK
create_clock -period 10 [get_ports CLK]

set_input_delay -max 6 -clock CLK [all_inputs]

remove_input_delay [get_ports CLK]
set_output_delay -max 6 -clock CLK [all_outputs]

X_BLOCK MY_BLOCK Y_BLOCK

X D Q S N D Q X D Q S N D Q X
FF1 FF2 FF3 FF4
10 4 4 10 4 4 10

57
 False Paths

Timing paths that are logically impossible!

Even if they violate a timing requirement according to STA, the data would never propagate
through this path in actual circuit operation.. No need to meet any timing constraint ☺

Therefore, we need to specify it to STA tools to avoid analyzing/reporting it.

Example.
set_false_path –through [get_pins Mux1/In0] –through [get_pins Mux2/In1]
set_false_path
58 –through [get_pins Mux1/In1] –through [get_pins Mux2/In0]
False path examples
set_false_path -from [get_clocks SCAN_CLK]
-to [get_clocks CORE_CLK]
set_false_path -to [get_ports TEST_REG*]
# Any path starting from the SCAN_CLK domain to the
# CORE_CLK domain is a false path. # All paths that end in port named TEST_REG* are false
paths.

set_false_path -through [get_pins UMUX0/S]

# Any path going through this pin is false.
set_false_path -through UINV/Z -through UAND0/Z

# Any path that goes through bothof these pins

set_false_path -through [get_pins SAD_CORE/RSTN]]
# The false path specifications can also be specified # in this order is false.
to,
# through, or from a module pin instance.

59
Multi-cycle Paths
 There are data paths that require more than one clock period for execution.

2 clock period delay

60
Multi_cycle Paths
 In some cases, the combinational data path between two flip-flops can take more
than one clock cycle to propagate through the logic.
 In such cases, the combinational path is declared as a multi cycle path.
 Even though the data is being captured by the capture flip-flop on every clock
edge, we direct
 STA that the relevant capture edge occurs after the specified number of clock
cycles.
 Since the data path can take up to three clock cycles, a setup multi cycle check of
three cycles should be specified.

61
 Exercise

-Do we need to specify false paths to synthesis and

physical synthesis as well?

-What are the consequences of not accurately specifying

false paths? [list two of them]

62
Multi_cycle Paths
 The multi cycle setup constraints specified to achieve this are given below.
create_clock -name CLKM -period 10 [get_portCLKM]
set_multicycle_path 3 -setup \
-from [get_pins UFF0/Q] \
-to [get_pins UFF1/D]
 The setup multi cycle constraint specifies that the path from UFF0/CK to UFF1/D
can take up to three clock cycles to complete for a setup check.
 This implies that the design utilizes the required data from UFF1/Q only every third
cycle instead of every cycle.

63
 A three cycle multipath

64
 Case analysis

A common case for designs is that some value should be assumed constant.
-For example; if the constant sets a multiplexer selector

-To propagate this constant through the design and disable irrelevant timing arcs, a
set_case_analysis constraint is used

-Example.
set_case_analysis 0 [get_ports testMode]

65
 Logical Design Rules

set_max_transiion 0.15
→ Sets the maximum transition time for all nodes of the design.

set_max_capacitance 0.08
→ Sets the maximum capacitance of a net for all nodes of the design.

set_max_fanout 10
→ Set the maximum number of load cells a pin can be connected to.

66
 Exercise

-What are the pros and cons of:

A. Setting a relatively high value for max. transition.
B. Setting a very tight value for max. transition.

-What are the pros and cons of setting a relatively low

value for max. fanout?

67
 4- Design Environment

68
Exercise
4ns For all FFs:
Buf2 1ns 2ns 3ns 1ns 1ns 2ns
- Tcq=0.04ns
- Tsetup=0.05ns
10 fF
- Thold=0.03ns

4ns 2ns
2ns 2ns

PLL jitter= 0.1ns

/2 /2

Write and SDC file for each of BLOCK A and BLOCK B

- For each input port; specify a suitable I/P delay constraint and boundary conditions.
- For each output port; specify a suitable O/P delay constraint and boundary conditions.
- For each clock and generated clock, specify it properly for each block.
- Clarify that CK1 and CK2 don’t have inter-clk paths.
69
Estimating Parasitics

Generalization Length components

▪ The more the fanout (output

connections) the larger the
length

▪ All parasitics depend on interconnect ▪ The larger the chip (the more
length gates it has) the more the length

R = length ∙ Runit length

C = length ∙ Cunit length
Area = length ∙ Areaunit length

length = f (gate count, fanout)

70
 4- Logic Synthesis

71
Logic Synthesis: Background
 (HDLs) such as VHDL and Verilog, has emerged as the primary means to
capture functionality and deal with a range of design issues.

 The use of logic synthesis has made it possible to effectively translate

designs captured in these high-level languages to designs optimized for area
and speed.

 Besides enabling control over design parameters such as silicon real-estate

and timing, logic synthesis tools facilitate the capture of designs in a
parametrizable and re-usable form. Moreover, logic synthesis makes it
possible to re-target a given design to new and emerging semiconductor
technologies.

72
Logic Synthesis Definition
 “Synthesis is achieving an optimal gate level netlist from HDL
code.”

 The logic synthesis process consists of two steps - translation and

optimization.
 Translation involves transforming a HDL (RTL) description to gates,
 optimization involves selecting the optimal combination of ASIC technology library
cells to achieve the required functionality.

 Synthesis is an iterative process aimed at achieving design goals

73
Logic synthesis and Formality: Basic Flow

RTL & SC
Uncertainties Constraints header .libs

Logic Synthesis (DC)

RTL & Prefloorplan SC

header .svf files netlist (.v) .libs

Formal Verification (Formality)

74
Basic Steps of Logic Synthesis

y=(a+b)&(c⊕d)&e
RTL

Logic Synthesis
a
b y
Gate c
d
e
Physical Synthesis

Layout

75
Synthesis and Optimization
 Synthesis/ Translation
 The process which converts an abstract
form of desired circuit behavior into a design y=(a+b)&(c⊕d)&e
implementation in terms of logic gates
a
 Optimization b y
c
 Changing design to achieve design goal d
(required by specification) e
 For example. Meeting a design rule (ex.
max_transition, max_fanout)
 For example. Optimizing the design to meet a
2
b
a certain design criteri (ex. minimumu 3 y
c
leakage, minimum area…etc.) 1
d
e

76
Logic synthesis: Basic Flow
Develop HDL files
Libraries objects
link_library Specify libraries
target_library
symbol_library analyze/elaborate
Read design read_file

Design optimization Set design constraints

constraints Design rule constraints
create_clock set_max_transition
set_clock_latency Define design environment set_max_fanout
set_propagated_clock set_max_capacitance
set_clock_uncertaintly
set_clock_transition Optimize the design compile
set_input_delay
set_output_delay check design
Analyze and resolve design problems report_area
set_max_area
report_constraint
write_file report_timing
Save the design database

77
78
 1- Library Specification

79
Library Requirements
1. Logic Libraries
2. Symbol Libraries
3. DesignWare Libraries
4. Physical Libraries

80
Logic Libraries
 maintained and distributed by semiconductor vendors,
 contain information about the characteristics and functions of each cell, such as cell
names, pin names, area, delay arcs, and pin loading.
 define design rule constraints.
 specify the operating conditions and wire load models for a specific technology.

81
Logic Libraries
 DC uses logic libraries for the following purposes:
 Implementing the design function
 Resolving cell references
 Calculating timing values and path delays
 Calculating power consumed

 Note
 DC Explorer requires the logic libraries to be in .db format. A .db file is a compiled
version of the ASCII .lib file, with smaller size which result faster tool execution.

82
Logic Libraries – Setup
 Target libraries
 They contain the cells used to generate the netlist.
 DC Explorer selects functionally correct gates from the target libraries to build a circuit during mapping.
 The target libraries that are used to map a design become the local link libraries for the design. DC saves this
information in the design's local_link_library attribute.
 To specify the target libraries, use the target_library variable.

 When optimizing the design, Design Compiler uses this library to search for alternative cells that can be used to
optimize the design for better timing, less power or less area.

83
Logic Libraries – Setup
 Link libraries
 They are used to resolve cell references.
 Link libraries contain the descriptions of library cells and sub-designs in a mapped netlist and can also contain
design files.
 Link libraries include local link libraries defined in the local_link_library attribute and system link libraries
specified in the link_library variable.
 Link libraries define the delay models that are used to calculate timing values and path delays.

84
Logic Libraries – Setup
 search_path
 This variable specifies a list of directory paths that the tool uses to find logic libraries and other files when you
specify a plain file name without a path. It also sets the paths where DC Explorer can continue the search for
unresolved references after it searches the link libraries.

 You can use the which command to list the library files in the order as found by DC Explorer.
dc_shell> which my_lib.db
/usr/lib/my_lib.db, /usr/vhdl/my_lib.db

85
Logic Libraries – Link Command
 For a design to be complete, it needs to be connected to all of the library components and designs it
references.
 The references must be located and linked to the current design in order for the design to be functional.

 The purpose of this command is to locate all of the designs and library components referenced in the current
design and connect (link) them to the current design.

 Search order during a link is

1. local_link_library ➔ 2. link_library ➔ 3. search_path
 The first occurrence of a design reference is used.

86
Library Requirements
1. Logic Libraries
2. Symbol Libraries
3. DesignWare Libraries
4. Physical Libraries

87
 2- Reading Design

88
Reading Design – analyze & elaborate commands
 The analyze command performs the following tasks:
 Reads an HDL source file
 Checks for errors without building logic for the design
 Creates HDL library objects in an HDL-independent intermediate format
 Stores the intermediate files in a location you define

analyze -format verilog -define $def -lib work "${verilog_files}"

89
Reading Design – analyze & elaborate
 The elaborate command performs the following tasks:
 Translates the intermediate design into a technology-independent logic design using
generic technology (GTECH) library elements
 Allows changing of parameter values defined in the source code
 Allows VHDL architecture selection
 Replaces HDL arithmetic operators in the code with DesignWare components

elaborate <.syn file> -arch “<architecture >” –param “<parameter>”

elaborate <top_cell_name> -arch “<architecture >” –param “<parameter>”

90
Reading Design – read_file
 The read_file command
 Reads several different formats
 Performs the same operations as the analyze and elaborate commands in a single step
 Creates .mr and .st intermediate files for VHDL
 Does not create any intermediate files for Verilog

read -def ${def} –format verilog adder.v

read_verilog adder.v

91
 5- Design Optimization

92
Overview of the Optimization Process
 Optimization is the step in the synthesis process that attempts to implement a
combination of library cells that meets the functional, speed, and area
requirements of your design.
 Optimization transforms the design into a technology-specific circuit based on
the attributes and constraints you place on the design.
 Design Compiler performs the following levels of optimization in the following
order:
 Architectural Optimization
 Logic-Level Optimization
 Gate-Level Optimization

93
Architectural Optimization
 Architectural optimization works on the HDL description. It includes such
high-level synthesis tasks as
 Sharing common subexpressions
 Sharing resources
 Selecting DesignWare implementations Reordering operators
 Identifying arithmetic expressions for datapath synthesis
 Notes:
 These high-level synthesis tasks occur only during the optimization of an unmapped
design - except for DesignWare implementations which can recur after gate-level
mapping-.
 High-level synthesis tasks are based on your constraints and your HDL coding style.
 After high-level optimization, circuit function is represented by GTECH library parts,
that is, by a generic, technology-independent netlist.

94
Logic-Level Optimization
 Logic-level optimization works on the GTECH netlist. It consists of the
following two processes:
 Structuring
 During structuring, Design Compiler searches for subfunctions that can be factored out and
evaluates these factors, based on the size of the factor and the number of times the factor
appears in the design.
 Structuring is constraint based
 It can result in reduced design area.

 Flattening
 The goal of this process is to convert combinational logic paths of the design to a two-level, sum-
of-products representation.
 Flattening is carried out independently of constraints.
 It is useful for speed optimization because it leads to just two levels of combinational logic.

95
Gate-Level Optimization
 Gate-level optimization works on the generic netlist created by logic synthesis
to produce a technology-specific netlist. It includes the following processes:
 Mapping
 Design rule fixing
 Delay optimization
 Area optimization

96
Cost Functions
 The synthesis tool performs optimization by minimizing cost functions .
 one for design rule costs and the other for optimization costs

 The optimization cost function consists of four parts in the following order of
importance:
 Max delay cost
 Min delay cost
 Max power cost
 Max area cost
 Notes:
 You can change the priority of the constraints by using the set_cost_priority command.
 You can disable design rule fixing by specifying the -no_design_rule option when you run the
compile command.

97
Compile Command
 The compile command performs logic-level and gate-level synthesis and
optimization on the current design.
 The compile command reports progress in real time by displaying a report

98
 6- Design Analysis

99
DC Analysis Commands
 report_cell/report_reference
 To get information about the cells/references used in your design.
 report_timing
 To get the timing information for paths
 report_constraints
 To get the endpoints that are violating your constraints
 report_area
 To get information about your design area.
 check_design
 To check the current design for problems, and issues error and warning messages to explain
them.
 check_timing
 To check for possible timing problems in the current design

100
 7- Saving Design

101
Write Command
 Use write command to save and export the design from memory to disk, in the
required format.
 write command is actually an alias for the write_file command.
 Options for this command:
-format file_format : Specifies the output format of the design. Supported output formats and their
descriptions are as follows:
 ddc - Synopsys internal database format (the default format)
 verilog - IEEE Standard Verilog
 svsim - SystemVerilog netlist wrapper
 vhdl - IEEE Standard VHDL

-hierarchy : Writes out all the designs in the hierarchy.

-output output_file_name

102