Scribd Logo
Upload

Welcome to Scribd!

  • Lecture09 Out of Order

    Uploaded by

    Prince Chaudhary
    10 views1 page
    This document describes an out-of-order processor implementation that uses a reorder buffer (ROB) to handle instruction reordering. It shows the branch prediction and instruction fetch stages feeding instructions into the ROB, where they are decoded, renamed, and issued to functional units in the issue queue before writing results back to the ROB and register file.

    Original Description:

    Original Title

    Lecture09 Out of Order (1)

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document describes an out-of-order processor implementation that uses a reorder buffer (ROB) to handle instruction reordering. It shows the branch prediction and instruction fetch stages feeding instructions into the ROB, where they are decoded, renamed, and issued to functional units in the issue queue before writing results back to the ROB and register file.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    10 views1 page

    Lecture09 Out of Order

    Uploaded by

    Prince Chaudhary
    This document describes an out-of-order processor implementation that uses a reorder buffer (ROB) to handle instruction reordering. It shows the branch prediction and instruction fetch stages feeding instructions into the ROB, where they are decoded, renamed, and issued to functional units in the issue queue before writing results back to the ROB and register file.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    An Out-of-Order Processor Implementation

    Reorder Buffer (ROB)

    Branch prediction Instr 1 T1


    and instr fetch Instr 2 T2
    Register File
    Instr 3 T3
    R1-R32
    Instr 4 T4
    Instr 5 T5
    Instr 6 T6
    R1  R1+R2
    R2  R1+R3
    BEQZ R2 Decode &
    R3  R1+R2 Rename
    T1  R1+R2 ALU ALU ALU
    R1  R3+R2
    T2  T1+R3
    BEQZ T2
    Instr Fetch Queue T4  T1+T2 Results written to
    T5  T4+T2 ROB and tags
    broadcast to IQ

    Issue Queue (IQ)


    2

    You might also like