VLSI DESIGN

MEL ZG621
Lecture-3
5-08-2023
Dr. Vilas H Gaidhane
BITS Pilani
Dubai Campus
 Lecture 4
Module 1 Module 2

1. MOSFET Scaling and Small 1. Fabrication process Flow:

Geometry Effect Basic steps

2. MOSFET Capacitances 2. CMOS n-well Process

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 Introduction: MOSFET Scaling

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 Introduction: MOSFET Scaling

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 Introduction: MOSFET Scaling

Table : Shows the Effects of full scaling upon key device characteristics.

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 Introduction: MOSFET Scaling

Table : Shows the Effects of Constant Voltage on device characteristics.

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 Scaling effect
➢ It is observed that the Constant-voltage scaling increases the drain
current density and the power density by a factor of S3 .
➢ This large increase in current and power densities may eventually
cause serious reliability problems for the scaled transistor, such as
Electromigration, hot-carrier degradation, oxide breakdown, and
electrical over-stress.

➢ Although the device dimensions reduced systematically, other

physical limitations become more dominant and restrict the scaling.

1. Short channel Effect

2. Narrow channel Effect

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 Short-Channel Effects
➢ MOSFET defined as a short-channel device if the effective channel
length Leff approximately equal to the source and drain junction depth
. xj
➢ It results into two physical phenomenon

(i) the limitations imposed on electron drift characteristics in the

channel, and

(ii) the modification of the

threshold voltage due to the

shortening channel length.

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 Short-Channel Effects
➢ Electron drift characteristics:

➢ Electric field E y along the channel increases, as the effective channel

length is decreased.  E y = dV 
 dy 
➢ Electron drift velocity vd in the channel is proportional to the electric
field for lower field values

➢ However, Drift velocity tends to saturate at high channel electric

fields.

➢ This drift velocity saturation has impact on the current-voltage

characteristics of the short-channel MOSFET.

➢ It reduces saturation current I ( sat )

D

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 Short-Channel Effects
➢ Electron drift characteristics:

➢ The charge velocity in the channel influence by vertical electric-field Ex

• It results into collisions of carriers in the channel region, thus mobility

reduced.  no 
 n( )
 eff =  where  is an empirical factor
 1 + Ex 

• It can be approximately represented by

 no 
 n ( eff ) =  where  is an empirical coefficient
 1 +  (VGS − VTO ) 

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 Short-Channel Effects
➢ Modification of Threshold Voltage due to short channel effect:

➢ In short channel, n+ Drain and Source regions in p-type substrate

induced a asymmetric depletion region.

➢ More depletion at drain due to +ve drain voltage (reversed bias)

compared to Source.

• Bulk depletion charge in the short-channel device is less than

expected, threshold voltage also reduced.

VTO (short Channel) = VTO − VTO

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 Short-Channel Effects

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 Narrow-Channel Effects
➢ Narrow Channel effect:
➢When Channel widths W equal to the maximum depletion region
thickness xdm , MOSFET is called as narrow-channel devices.
➢This Figure is the TOP view
Thick Field oxide (FOX)

•Gate electrode overlaps with the field Oxide .

•A relatively shallow depletion region
forms underneath this FOX-overlap area
It increases the threshold
voltage as

VTO(Narrow Channel) = VTO + VTO

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 Other Limitations imposed due to Scaling
➢ Subthreshold Conduction

➢ Oxide breakdown

➢ Hot carrier effect

➢ Electromigration

➢ Electrostatic discharge (ESD)

➢ Electrical over-stress (EOS).

Drain current vs. drain voltage characteristics of an n-channel MOS transistor before and after hot-carrier
induced oxide damage.

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 MOSFET Capacitances
➢ MOSFET capacitances are due to
geometry and manufacturing
processes and mostly distributed (not
lumped).

➢ Figure Cross-sectional view and

top view (mask view) of a
typical n-channel MOSFET

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 Oxide overlap Capacitances
➢Gate electrode overlaps both the Source region and Drain region at the
edges results into Oxide overlap capacitances.

1. Gate to Source Overlap capacitance

CGS (Overlap ) = Cox W  LD

2. Gate to Drain overlap Capacitance

CGD (Overlap ) = Cox W  LD

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 Oxide Capacitances
➢Now Consider the capacitances due to the interaction
between the gate voltage and the channel charge.
➢Gate voltage results into the capacitances

Cgb , Cgs , Cgd Cut-off Mode

➢Cut-off

Cgb = Cox W  L and Cgs = Cgd = 0

➢Linear Mode
1
Cgs  Cgd = Cox W  L
2 Linear Mode
Cgb = 0
➢Saturation Mode

2
Cgs  Cox W  L
3
Cgd = 0, Cgb = 0 Saturation Mode

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 Oxide Capacitances

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 Module 2

1. Fabrication process Flow: Basic steps

2. CMOS n-well Process

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 Fabrication process flow: Basic steps
To understand the basic fabrication
Si Wafer
Single die process, consider the Silicon dioxide
patterns on the Si wafer.

1. Thermal oxidation (1µm)

2. Photo resist coating

3. Mask and photolithography

4. Etching

You can watch the MOS fabrication video

https://www.youtube.com/watch?v=35j
From http://www.amd.com
WSQXku74
Going up to 12” (30cm)
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 Fabrication process flow: Basic steps
(a) Si substrate is a lightly doped p type Si
material

(b) The thermal oxidation on the

(a) silicon surface, of about 1 µm

thickness, is created on the
substrate.

(c) The entire oxide surface is then

covered with a layer of
(b)
photoresist, which is essentially a
light-sensitive polymer (Positive or
Negative)

(c)
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 Fabrication process flow: Basic steps
(d) The areas where the UV light can
pass through, on the other hand, the
photoresist is exposed and becomes
soluble. The type of photoresist which
(a)
becomes soluble after exposure to UV
light is called positive photoresist
(d)

(e) The silicon dioxide regions which

are not covered by hardened
photoresist can be etched away by
using a chemical solvent (HF acid)
(e)
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 Fabrication process flow: Basic steps
(f) After etching an oxide window is
obtained that reaches down to the Si
substrate.

(f)
(e) The remaining photoresist can
now be stripped from the silicon
dioxide surface by using another
solvent, leaving the patterned silicon
dioxide feature on the surface.
(g)

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 CMOS n-well Process
CMOS – Complementary MOSFET (consist of n-MOS and p-MOS together)
Typically use P-type substrate for NMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

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 CMOS n-well Process basic masks
n-well
n well

Polysilicon
Polysilicon

N+ diffusion
n+ Diffusion

P+ diffusion
p+ Diffusion

Contact
Contact

Metal
Metal

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 CMOS Fabrication steps
➢ Start with blank Si wafer . First step will be to form the n-well
➢ Consider the p substrate

p substrate

➢ Oxidation
Grow SiO2 layer on top of p type Si wafer
•900 – 1200 Celsius with H2O or O2 in oxidation furnace

SiO2

p substrate

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 CMOS Fabrication steps
➢ Photoresist : Spin on the photoresist (positive a light-sensitive organic polymer)

Photoresist
SiO2

p substrate

➢ Photolithography: Expose photoresist through n-well mask

Strip off exposed photoresist

Photoresist
SiO2

p substrate

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 CMOS Fabrication steps
➢ Etching : Etch oxide with hydrofluoric acid (HF)
Photoresist
SiO2

p substrate

➢ Stripping: Strip off remaining photoresist. Use mixture of acids called

piranha etch

SiO2

p substrate

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 CMOS Fabrication steps
N-well: is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implantation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si

SiO2

n well

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 CMOS Fabrication steps
Strip Oxide
Strip off the remaining oxide using HF

n well
p substrate

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 CMOS Fabrication steps
Polysilicon:
Deposit very thin layer of gate oxide (SiO2)
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer

Polysilicon
Thin gate oxide

n well
p substrate

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 CMOS Fabrication steps
Photolithography
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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 CMOS Fabrication steps
➢ Use oxide and masking to expose where n+ dopants should be diffused or
implanted

n well
p substrate

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 CMOS Fabrication steps
➢ N+ Diffusion

n+ Diffusion

n well
p substrate

n+ n+ n+

n well
p substrate

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 CMOS Fabrication steps
➢ N+ Diffusion: Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

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 CMOS Fabrication steps
Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

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 CMOS Fabrication steps
Contacts: Now we need to wire together the devices.
Cover chip with thick field oxide .
Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

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 CMOS Fabrication steps
Metalization: Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

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 CMOS Fabrication steps
Ohmic contacts provides the low resistance current path VDD

p MOS
A Y
nMOS

Input GND
A
GND VDD
output Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

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 CMOS Fabrication steps

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