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  • Cmos Logic

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    bharathababu
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    This document summarizes CMOS logic gates and combinational logic. It describes the schematics for inverters, NOR gates and NAND gates using CMOS. It explains that CMOS uses parallel connections for OR logic and series connections for AND logic. It also discusses using DeMorgan's laws to reduce logic functions for CMOS implementation and the use of AOI/OAI structured logic to implement XOR/XNOR gates. Finally, it reviews XOR/XNOR gates and transmission gates, which can be used to implement multiplexer functions.

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    This document summarizes CMOS logic gates and combinational logic. It describes the schematics for inverters, NOR gates and NAND gates using CMOS. It explains that CMOS uses parallel connections for OR logic and series connections for AND logic. It also discusses using DeMorgan's laws to reduce logic functions for CMOS implementation and the use of AOI/OAI structured logic to implement XOR/XNOR gates. Finally, it reviews XOR/XNOR gates and transmission gates, which can be used to implement multiplexer functions.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    10 views2 pages

    Cmos Logic

    Uploaded by

    bharathababu
    This document summarizes CMOS logic gates and combinational logic. It describes the schematics for inverters, NOR gates and NAND gates using CMOS. It explains that CMOS uses parallel connections for OR logic and series connections for AND logic. It also discusses using DeMorgan's laws to reduce logic functions for CMOS implementation and the use of AOI/OAI structured logic to implement XOR/XNOR gates. Finally, it reviews XOR/XNOR gates and transmission gates, which can be used to implement multiplexer functions.

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    © All Rights Reserved
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    Review: CMOS Logic Gates

    • INV Schematic • NOR Schematic • NAND Schematic

    = Vin

    • CMOS inverts • parallel for OR


    functions
    • series for AND
    • CMOS Combinational Logic
    • use DeMorgan relations to reduce functions
    • remove all NAND/NOR operations
    • implement nMOS network
    • create pMOS by complementing operations

    • AOI/OAI Structured Logic


    • XOR/XNOR using structured logic

    ECE 410, Prof. A. Mason Lecture Notes Page 3.1


    Review: XOR/XNOR and TGs
    • Exclusive-OR (XOR)
    b b
    – a b=a•b+a•b
    a a
    • Exclusive-NOR
    – a b=a•b+a•b

    • Transmission Gates
    XOR/XNOR in AOI Form

    y = x s, for s=1

    • MUX Function using TGs


    F = Po • s + P1 • s

    ECE 410, Prof. A. Mason Lecture Notes Page 3.2

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