Reconfigurable Computing

AEL ZG554 / ES ZG 554 / MEL ZG 554

Session 2
Pawan Sharma
BITS Pilani ps@pilani.bits-pilani.ac.in
Pilani Campus 30-07-2022
Last Lecture

Introduction to Reconfigurable Computing vs other

Computing Paradigms

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Today’s Lecture

• Simple Programmable Logic Devices

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Programmable Logic Devices

• Before PLD:
– Digital circuits available as SSI, MSI devices
– Logic determined at time of manufacture
– Cant be changed later and large volume fabrication
– Shelves of document for all devices
– Did not meet designer’s requirements for his/her exact specifications
– Forced to use multiple devices to meet requirements
• After PLDs:
– Device supplied with no logic function programmed in device
– Quick design creation
– Allows designer to program PLD in whatever way the design requires
– Meets exact designers' specifications
– Multiple functions can be combined and programmed onto single chip – lesser board space
required
– In system programmable – need not remove device from board for changing program
– No worry for device obsolescence
– But requires usage of specific tools and understanding of hardware architecture before
programming

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Idea: Memory as Programmable Logic

0
X A1
00
01 1
Y A0 10 1
11
0
D0
X xor Y
Address lines as inputs

Data line as output

Truth table is the content

Form minterms using AND gates and then OR the appropriate minterms for formation of the output

Circuit requires four 2-input AND gates and one OR gate that can take up-to four inputs.

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array of AND gates – AND plane

array of OR gates – OR plane

In the AND-plane all eight minterms for the three inputs, a, b, and c are generated. AND and OR Planes
The OR plane uses only the minterms that are needed for the outputs of the circuit.

Not all generated minterms may be used.minterm 7 that is generated in the AND-plane but not used in the OR plane.
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 • Although NOR gates are used, the left plane is still
called the AND-plane and the right plane is called the
OR-plane
• Hardware implementation with large fan-in and
routing becomes difficult.
• A circuit with 16 inputs, has 64k (216) minterms.
• In the AND-plane, wires from circuit inputs must be
routed to over 64,000 NOR gates.
• In the OR-plane, the NOR gates must be large enough
for every minterm of the function (over 64,000
minterms) to reach their inputs.
• Such an implementation is very slow because of long
lines, and takes too much space because of the
requirement of large gates.
All NOR Implementation

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Distributed NOR of the AND-plane Distributed NOR Gate of Output y

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• Transistors for the implementation of
minterms in the AND-plane are fixed, but
in the OR-plane there are fusible
transistors on every output column for
every minterm of the AND-plane.
• For realization of a certain function on an
output of this array, transistors
corresponding to the used minterms are
kept, and the rest are blown to eliminate
contribution of the minterm to the output
function.
• For example, for output y, only transistors
on rows m2, m5, and m6 are connected
and the rest are fused off.
• The dots in the AND-plane indicate
permanent connections, and the crosses in
the OR-plane indicate programmable or
configurable connections

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Memory View
PROM
• If we consider abc as the address inputs and wxyz as the data
read from abc designated address, then the circuit can be
regarded as a memory with an address space of 8 words and
data of four bits wide.
• Fixed AND-plane becomes the memory decoder, and the
programmable OR-plane becomes the memory array.
• Because this memory can only be read from and not easily
written into, it is referred to as Read Only Memory or ROM.
The basic ROM is a one-time programmable logic array.
• Programmable ROM is a one-time programmable chip that,
once programmed, cannot be erased or altered.
• In a PROM, all minterms in the AND-plane are generated, and
connections of all AND-plane outputs to OR-plane gate inputs
are in place.
• By applying a high voltage, transistors in the OR-plane that
correspond to the minterms that are not needed for a certain
output are burned out.
• A fresh PROM has all transistors in its OR-plane connected.
When programmed, some will be fused out permanently.

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Simple Programmable Logic Devices

• Implement 2 level logic circuits (AND/OR)

• Based on regular array structure
• Read Only Memories (ROMs and PROMs)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

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Classifying Three Basic PLDs

Fixed AND plane Programmable

INPUT (decoder) OR plane
OUTPUT

(Programmable) Read-Only Memory (ROM)

Programmable Programmable
AND plane OR plane
INPUT OUTPUT
Programmable Logic Array (PLA)

Programmable Fixed F/F

INPUT AND plane OR plane
OUTPUT
Programmable Array Logic (PAL) Devices

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Example: Lookup Table
 Design a square lookup table for F(X) = X2 using ROM

X F(X)=X2 X F(X)=X2

0 0 000 000000

1 1 001 000001

2 4 010 000100

3 9 011 001001

4 16 100 010000

5 25 101 011001

6 36 110 100100

7 49 111 110001

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Square Lookup Table using ROM

X F(X)=X2 1
X2 3-to-8 2
000 000000
3
001 000001 X1
Decoder 4
010 000100 X0 5
011 001001 6
100 010000 7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0

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Square Lookup Table using ROM

X F(X)=X2 1
X2 3-to-8 2
000 000000
3
001 000001 X1
Decoder 4
010 000100 X0 5
011 001001 6
100 010000 7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0
Not Used = X0

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Square Lookup Table using ROM

X F(X)=X2
0
000 000000
1
001 000001 X2 3-to-8 2
3
010 000100
X1
011 001001
Decoder 4
X0 5
100 010000
6
101 011001 7
110 100100

111 110001

F5 F4 F3 F2 F1 F0

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Programmable Logic Array (PLA)

A Programmable
OR Plane
• This is a 3 x 4 x 2 PLA (3
B
inputs, up to 4 product
terms, and 2 outputs), ready
C to be programmed.
• The left part of the diagram
replaces the decoder used in
a ROM.
• Connections can be made in
the “AND array” to produce
four arbitrary products,
Programmable instead of 8 minterms as
AND Plane with a ROM.
• Those products can then be
summed together in the
C C B B A A “OR array.”

F2
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Using NOR gates

Z = A + B’C
Y = AB
X = AB + A’B’C

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Regular k-map minimization

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PLA minimization

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PLA Example

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PLS 100

PLA (16x48x8): The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse
Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert
architecture to directly implement custom sum of product equations.
• Input variables: 16
• Output functions: 8
• Product terms: 48
• I/O propagation delay: 50ns (max.)
• Power dissipation: 600mW (typ.)
• The True, Complement, or Don’t Care condition of each of the 16 inputs can be ANDed
together to comprise one P-term.
• All 48 P-terms can be selectively ORed to each output.
• Applications: CRT display systems, Code conversion, Peripheral controllers, Function
generators, Look-up and decision tables, Microprogramming, Address mapping,
Character generators, Data security encoders

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LOGIC PROGRAMMING
PLS100/PLS101 is fully supported by industry
standard (JEDEC compatible) PLD CAD tools,
including Philips Semiconductors’ SNAP, Data
I/O Corporation’s ABELE and Logical Devices
Inc.’s CUPLE design
software packages.

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PLA

• Programmable AND and OR planes

• Less than 2n product terms
• Requires sharing of product terms across multiple functions
• Programming overhead
• For a single output, programmable OR is not required if we can somehow
disable remaining product terms by making their output to go to 0
• While PLAs have more flexibility than PROMs since the connections between
the AND and OR gates are programmable, this flexibility results in lower
performance.
• The performance degradation is primarily due to the fact that in a PLA a signal
must travel through two programmable connections (one in the AND plane, one
in the OR plane), while in a PROM the signal goes through only one
programmable connection.

• another option: can make OR plane fixed and program AND plane to generate
whatever product terms you require

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Programmable Array Logic

• The PAL is the opposite of the ROM, having a programmable set of ANDs
combined with fixed ORs.
• Disadvantage
– ROM guaranteed to implement any M functions of N
inputs. PAL may have few inputs to the OR gates (less than 2n
product terms per OR gate or dedicated product terms per OR gate)
• Advantages
– For given internal complexity, a PAL can have larger N and M
– Some PALs have outputs that can be complemented
– No multilevel circuit implementations in ROM (without external
connections from output to input).
– PAL has outputs from OR terms supplied as internal inputs to all AND
terms, making implementation of multi-level circuits easier.

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 AND gates inputs
0 1 2 3 4 5 6 7 8 9

4-input, 3-output PAL with fixed, 3-input OR terms

X
Product 1
term

What are the equations for F1 through F4?

X X
2 F1

F1 = A’B’ + C’ A
X X X
4
X X
5 F2
F2 = A’BC’ + AC + AB X X
6
B
F3 = AD + BD + F1 = AD + BD + A’B’+ C’ 7
X X

= AD + BD + A’B’ + C’ 8
X X
F3
X
9

F4 = AB + CD + F1’ = AB + CD + (A’B’ + C’)’ C

X
= AB + CD + AC + BC
X
10
X X
11 F4
X
12
D
0 1 2 3 4 5 6 7 8 9

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PAL 16L8
• 20 pin DIP
• active low output
• 10 primary inputs, 8 outputs
• with 6 out of 8 outputs fedback as
inputs to AND plane can support 16
inputs, giving 32 programmable inputs
per AND gate
• pin 19 and 12 act as dedicated outputs
and pins 13 to 18 act as both inputs
and putputs
• the output of top control AND gate of
each OR gate enables the tri state
inverter to generate final output.
usually always enabled (how?? –disable
all fuses and tie input of AND gate to
+5V) unless it connects to a shared data
bus that requires tri state behavior
• One section of output can generate
upto seven product terms
• can selectively use seven product terms
by disabling unwanted AND gates
(how?? – retain all 32 connections
connect both true and complement
inputs to AND gate (for example, A and
A’ together) to make output 0.

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Implement a function with 19 PTs

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Implement a function with 19 PTs

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Effect of cascading on delay

• cascading 3 sections (7+6+6)

– delay of each section= 10 ns
– 3 passes
– 3 section delays=30 ns
– 8 sections (7+6x7=49 PTs) 8 passes
• cascading two sections (7+7+5)
– 2 passes
– 2 section delay = 20 ns
– 8 sections (7x7=49 PTs) 2 passes
• reduce number of passes in cascading to minimize delays

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PAL C22V10

• CMOS Flash Erasable second- generation programmable array

logic device. It is implemented with the familiar sum-of-products
(AND-OR) logic structure and the programmable macrocell.
• The programmable macrocell provides the capability of defining
the architecture of each output – provide combinatorial or
registered inverting or non-inverting output
• Each of the 10 potential outputs may be specified as “registered”
or “combinatorial.”
• Polarity of each output may also be individually selected,
allowing complete flexibility of output configuration.
• Allows the 10 outputs to be reconfigured as inputs on an
individual basis, or alternately used as a combination I/O
controlled by the programmable array.

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• PALC22V10D features a variable product term architecture.
• There are 5 pairs of product-term-sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms per
output.
• it reduces the burden on the product term structures with
unusable product terms and lower performance.
• Since each of the 10 output pins may be individually configured
as inputs on a temporary or permanent basis, functions requiring
up to 21 inputs and only a single output and down to 12 inputs
and 10 outputs are possible. The 10 potential outputs are
enabled using product terms

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PAL C22V10

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