Dien Tu y Sinh - Amplifiers and Signal Processing

HCMUT
Course: Biomedical Electronics

Instructor: Hồ Trung Mỹ
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Ch 3
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Amplifiers & Signal Processing
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(Các mạch khuếch đại và xử lý tín hiệu)
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Refs:
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1. Prof. Andrew Mason - Michigan State University, USA

2. J.G. Webster, “Medical Instrumentation Application and
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Design”, John Wiley & Sons, 2010
CuuDuongThanCong.com https://fb.com/tailieudientucntt
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Outline
1. Ideal Op Amps 11. Frequency Response
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2. Inverting Amplifiers 12. Offset Voltage
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3. Noninverting Amplifiers 13. Bias Current
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4. Differential Amplifiers 14. Input and Output Resistance
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15. Phase-Sensitive
5. Comparators
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Demodulators
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6. Rectifiers ng 16. Timers
7. Logarithmic Amplifiers 17. Microcomputers in Medical
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8. Integrators Instrumentation
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9. Differentiators
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10. Active Filters
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Amplifiers and Analog Signal Processing
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Applications of Operational Amplifier
In Biological Signals and Systems
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The three major operations done on biological signals using
Op-Amp:
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1) Amplifications and Attenuations
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2) DC offsetting: add or subtract a DC
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3) Filtering: Shape signal’s frequency content
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3.1 Ideal Op-Amp
Most bioelectric signals are small and require amplifications
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Figure 3.1 Op-amp equivalent circuit.
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The two inputs are 1 and  2. A differential voltage between them

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causes current flow through the differential resistance Rd. The

differential voltage is multiplied by A, the gain of the op amp, to
generate the output-voltage source. Any current flowing to the output
terminal vo must pass through the output resistance Ro.
5
Inside the Op-Amp (IC-chip)
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20 transistors th
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11 resistors
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1 capacitor
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Ideal Characteristics
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+
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1- A =  (gain is infinity)
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2- Vo = 0, when v1 = v2 (no offset voltage)

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3- Rd =  (input impedance is infinity)

4- Ro = 0 (output impedance is zero)
5- Bandwidth =  (no frequency response limitations) and no phase shift
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Đặc tuyến truyền đạt của opamp
(Đường cong truyền đạt áp)
+VCC or VDD
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v+ or v2 vo
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v- or v1
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–VEE or –VSS
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o ng
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Chú ý: Linear region:

• Với opamp BJT: CC (Collector) và EE VO = A(V2 – V1)
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(Emitter)
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• Với opamp FET: DD (Drain) và SS (Source)

• Cấp nguồn lưỡng cực: Typical values: X =-25 and Y = 25
Thường VCC = VEE Vsat+ = +VS (Vs < VCC)
•Cấp nguồn đơn (thường gặp trong ĐTYS): Vsat- = -VS
 VEE = 0 (thường gặp), hoặc
 VCC = 0
8
Op-Amp Properties
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The ideal characteristics for an op amp and typical
actual values for a 741 op amp
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Basic Op-Amp Principles
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Basic Opamp Configuration
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Two Basic Rules
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Rule 1
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When the op-amp output is in its linear range, the two input terminals
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are at the same voltage.
Rule 2
No current flows into or out of either input terminal of the op amp.
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3.2 Inverting Amplifier
o
10 V
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Rf
-10 V 10 V
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i
Ri
i -
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o Slope = -Rf / Ri
+
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-10 V
(a)
an
(b)
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R f
ng vo R f
vo  - vi G   -
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Ri vi Ri
du
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Figure 3.3 (a) An inverting amplified. Current flowing through the

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input resistor Ri also flows through the feedback resistor Rf . (b) The
input-output plot shows a slope of -Rf / Ri in the central portion, but the
output saturates at about ±13 V.
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Summing Amplifier (Mạch KĐ tổng đảo)
R1 Rf
1
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-  v1 v2 
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R2 o vo  -Rf   
 
R
 1 R 2 
ng
2 +
co
an
th
o ng
du
u
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15
Example 3.1
The output of a biopotential preamplifier that measures the electro-
oculogram is an undesired dc voltage of 5 V due to electrode half-
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cell potentials, with a desired signal of 1 V superimposed. Design a
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circuit that will balance the dc voltage to zero and provide a gain of -
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10 for the desired signal without saturating the op amp.
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an
th
+10
Rf
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Ri
10 kW 100 kW i
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i
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- Voltage, V i + b /2
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+15V Rb o 0
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20 kW Time
5 kW +
vb
-15 V
-10 o
(a) (b)
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Fundamental Circuit: Source and Load
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Follower ( buffer)
Used as a buffer, to prevent a high
-
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source resistance from being loaded
o
down by a low-resistance load. In i
.c
+
another word it prevents drawing
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current from the source. vo  vi G 1
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th
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3.3 Noninverting Amplifier
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o
.c
i i 10 V
Slope = (Rf + Ri )/ Ri
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Ri Rf
-10 V 10 V
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i
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-
o
th
i
-10 V
+ ng
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 Ri  Ri  
u
R f
R f
Rf
 1  
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vo  vi G 
 
Ri Ri  Ri 
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Mạch KĐ tổng không đảo
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(a) Four input non-inverting summer. (b) Equivalent circuit for calculating vO.
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Input modes for op-amp
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(a) Single-ended input b) Differential input (c) Common-mode

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Ref: Floyd
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Differential vs. Common Mode Signal
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Noise in Differential Amplifiers
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Desirable Properties of Amplifiers
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3.4 Mạch KĐ vi sai (Differential Amplifiers)
Mạch KĐ hiệu Mạch KĐ vi sai
(Difference Amplifier)
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R4
an
vo  (v4 - v3 )
R3
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Áp dụng nguyên tắc xếp chồng  Độ lợi VS: Gd = Vo/(V4 – V3) = R4/R3
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(supersition principle) ta có:  Độ lợi cách chung Gc: lý tưởng thì
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Gc = 0, nhưng thực tế thường Gc 0.

VO = (1 + R2/R1)R4VI2/(R4+R3) – R2/R1VI1
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 Tỉ số triệt cách chung CMRR

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Nếu R4/R3 = R2/R1 thì ta có mạch

(Common Mode Rejection Ration):
KĐVS
CMRR = |Gd/Gc| hoặc
VO = (R2/R1)(VI2 – VI1) CMRRdB = 20 log10 |Gd/Gc|
= (R4/R3)(VI2 – VI1)
 Bất lợi của mạch này là tổng trở vào
nhỏ: Rin = 2R3 25
Mạch KĐ vi sai có thêm mạch đệm
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Mạch này có tổng trở vào: Rin = 

26
Mạch KĐ đo lường (IA) dùng 3 opamp
IA = Instrumentation Amplifier
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 2R2  R1  R4
vo  



v 2 - v1 
th
ng  R1  R3
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Differential Mode Gain: v3 - v 4  i( R 2  R1  R 2 )

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v 1 - v 2  iR 1
v3 - v4 2 R 2  R1
Gd  
v1 - v 2 R1
Advantages: High input impedance, High CMRR, Variable gain

27
Mạch KĐ đo lường (IA) dùng 2 opamp
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• Điện áp ra Vo = G1V1 + G2V2
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với
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G1 = –(1 + R2/R1)R4/R3 và G2 = 1 + R4/R3

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• Nếu R1/R2 = R4/R3 thì ta có mạch KĐVS:

Vo = (1 + R4/R3)(V2 – V1)
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3.5 Mạch so sánh (Comparator)
• Mạch so sánh là mạch op-amp so sánh hai điện áp đầu
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vào và tạo ra đầu ra chỉ ra mối quan hệ giữa chúng. Các
đầu vào có thể là hai tín hiệu (như hai sóng hình sin)
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hoặc tín hiệu và điện áp tham chiếu dc cố định VREF (còn
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được gọi là điện áp chuẩn)
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• Thường được sử dụng như một giao tiếp giữa tín hiệu số
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và tín hiệu tương tự.
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Vấn đề Giải pháp
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Mạch so sánh đơn giản
Vo Vo
VPS VPS
Vi + Vo
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_ Vi Vi
Vref
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0 Vref 0 Vref
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VNS VNS
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Vo = VSAT sign(Vi – Vref )
Đặc tuyến truyền đạt Đặc tuyến truyền đạt thực tế
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Chú ý: lý tưởng
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 Điện áp bão hòa dương VPS = Vsat+ = +VSAT
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 Điện áp bão hòa âm VNS = Vsat– = –VSAT
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 Nếu cấp nguồn lưỡng cực và đối xứng thì (lý tưởng) VSAT = VCC = VEE.
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 Nếu hoán đổi các đầu vào thì Vo = –VSAT sign(Vi – Vref ) và đặc tuếy truyền đạt
sẽ đảo ngược.
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 Đây là mạch phát hiện mức zero.
30
Mạch so sánh với mức ngưỡng VTH
R1 o
i VPS
- VTH = –R1Vref/R2
R2
o
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ref i
+
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VTH
ng
co
VNS
Mạch so sánh có ngưỡng Đặc tuyến truyền đạt
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• Điện thế tại ngõ đảo là (tổng quát thì Vref có thể dương, âm hay 0)
th
ng
V- = (R2Vi + R1Vref)/(R1 + R2)
• Ta xét dấu V+ – V- = –(R2Vi + R1Vref)/(R1 + R2)
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Vi < VTH VTH > VTH

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V+ – V- + 0 –
Opamp bão hòa + –
Ngõ ra Vo VPS = +VSAT VNS = –VSAT
với điện áp ngưỡng (threshold voltage) VTH = –R1Vref/R2 31

Mạch so sánh với tham chiếu zero
Mạch phát hiện mức zero
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+VSAT
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Mạch so sánh với tham chiếu zero có giới hạn
1. Giới hạn ở trị dương
Dz Vo
R +V +Vz
Vi _
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Vo 0
+
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-V -0.7V
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2. Giới hạn ở trị âm
co
Dz
an
R Vo
+V
th
Vi _ +0.7V
0
ng
Vo
+
o
-V
du
-Vz
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3. Giới hạn 2 đầu Vo

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Dz1 Dz2 Vz2 + 0.7V

R +V 0
Vi _
Vo
+ - (Vz1 + 0.7V)
-V 33
Mạch so sánh có vòng trễ (hysteresis)
• Còn được gọi là mạch Schmitt trigger (có nhiều dạng mạch)
• Có hồi tiếp dương và đặc tuyến truyền đạt có vòng trễ.
 TD: Vo Vòng trễ= UTP – LTP
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R1 VPS
Vi
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-
R2
ng
Vo Vi
Vref +
co
R3 LTP UTP
an
R4
th
ng VNS
• Xét dấu của V+ – V- với UTP = –R1Vref/R2 + (1 + R1/R2)R4VSAT/(R3 + R4)
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• V- = (R2Vi + R1Vref)/(R1 + R2) LTP = –R1Vref/R2 – (1 + R1/R2)R4VSAT/(R3 + R4)
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• V+ = R4Vo/(R3 + R4) UTP – LTP = 2(1 + R1/R2)R4VSAT/(R3 + R4)

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• Khi Vi tăng trị từ trái qua phải, opamp bão hòa dương, Vo = VPS; tại điểm UTP thì
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chuyển sang bão hòa âm.

UTP = –R1Vref/R2 + (1 + R1/R2)R4VSAT/(R3 + R4)
• Ngược lại, khi Vi giảm trị từ phải (từ điểm > UTP) ta có
LTP = –R1Vref/R2 – (1 + R1/R2)R4VSAT/(R3 + R4)
Chú ý: Còn nhiều dạng mạch so sánh khác!
34
Normal diode
3.6 Rectifier
Superdiode
vi
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vo
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VTC (or Transfer Char.)
Voltage Transfer Curve (VTC) vo
co
an
th
Slope = 1
Slope = 1
o ng
VON (= 0.7V - Si) vi
du
The circuit will not work well with high frequency

VON vi signals.
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• When the input signal becomes negative, the op amp

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has no feedback at all, so the output pin of the op amp

vo swings negative as far as it can.
• When the input signal becomes positive again, the op
amp's output voltage will take a finite time to swing
back to zero, then to forward bias the diode and
VON
produce an output. This time is determined by the op
amp's slew rate 35
Another Circuit
• The circuit below accepts an incomimng waveform and as usual with
op amps, inverts it. However, only the positive-going portions of the
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output waveform, which correspond to the negative-going portions of
the input signal, actually reach the output.
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• The direct feedback diode shunts any negative-going output back to
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the "-" input directly, preventing it from being reproduced. The slight
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voltage drop across the diode itself is blocked from the output by the
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second diode. D1 allows positive-going output voltage to reach the
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output.
VO = –R2Vi/R1 when Vi < 0
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VO = 0 when Vi > 0
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du
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R2
R1
36
o
Rectifier 10 V
R
-10 V 10 V
D1 D2
xR (1-x)R i
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-
-10 V
i
.c
+ (b)
R
i
ng
D4
o=
D3 x xR (1-x)R
co
- vo
- D2
an
+
(a) i +
th
ng (a)
VO = (1 + R2/R1)Vi when Vi > 0

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du
Full-wave precision rectifier: VO = 0 when Vi < 0

Therefore, when Vi > 0:
a) For i > 0,
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VO = (1 + (1-x)/x)Vi = Vi/x

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D2 and D3 conduct, whereas D1 and D4 are

reverse-biased.
Noninverting amplifier at the top is active
37
Rectifier xRi R
R
D1 i vo
D2
xR (1-x)R - D4
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- +
i
.c
+ (b)
R VO =  –R2Vi/R1 when Vi < 0
i
ng
D4
o=
VO = 0 when Vi > 0
D3 x Therefore, when Vi <0:
co
-
VO =  –R/xR Vi = –Vi/x
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+ o
(a)
th
10 V
ng -10 V 10 V
i
o
du
-10 V
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Full-wave precision rectifier:

cu
b) For i < 0, (b)
D1 and D4 conduct, whereas D2 and D3 are reverse-biased.

Inverting amplifier at the bottom is active
38
One-Op-Amp Full Wave Rectifier
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Ri = 2 kW Rf = 1 kW
i
v
.c
o
- D
ng
RL = 3 kW
co
+
an
th
(c) ng
o
du
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For i < 0, the circuit behaves like the inverting amplifier rectifier with
a gain of +0.5. For i > 0, the op amp disconnects and the passive
resistor chain yields a gain of +0.5.
39
3.7 Mạch KĐ Logarithm
 Mạch KĐ Logarithm dùng diode
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 Mạch KĐ Logarithm dùng BJT
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Logarithmic Amplifiers
Khi BJT ở chế độ tích cực:
Uses of Log Amplifier IC = ISexp(VBE/VT)
với VT = kT/q = 26mV ở T = 300K
1. Multiply and divide variables
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Suy ra VBE = VTln(IC/IS) = 2.303VTlog(IC/IS)
2. Raise variable to a power Nếu T = 300 K  2.303VT  0.06 V
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3. Compress large dynamic range into small ones
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4. Linearize the output of devices
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 IC 
an
Rf /9 V BE  0 . 06 log  
Ic  
th
ng  IS 
VBE
Rf
 
o
vi
 0 . 06 log  
du
Ri vo
-
i  - 13 
o  R i  10 
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+
cu
Vo = –VBE = –VTln(IC/IS) = –VTln(Vi/(RiIS))

(a)
Figure 3.8 (a) A logarithmic amplifier makes use of the fact that a
transistor's VBE is related to the logarithm of its collector current.
For range of Ic equal 10-7 to 10-2 and the range of vo is -.36 to -0.66 V.
41
Logarithmic Amplifiers
VBE Rf /9 vo
Ic
om
10 V
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VBE Rf -10 V 10 V
9VBE
ng
Ri
i - 1 i
o
co
+
-10 V 10
an
(b)
(a)
th
o ng
Figure 3.8 (a) With the switch thrown in the alternate position, the
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circuit gain is increased by 10. (b) Input-output characteristics show

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that the logarithmic relation is obtained for only one polarity; 1 and
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10 gains are indicated.
42
3.8 Integrators (Low-pass filter)
t1
1
vo  - v dt  v ic
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i
R iC f 0
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V o ( j ) Z f
 -
ng
V i ( j ) Zi
co
an
R f

th
Z f
1  j R f C f
ng
V o  j  - R / Ri - R
o

f vo for f << fc
du
f
V i  j  1  j R f C 
f
vi Ri
u
cu
• Rf/Ri must be sufficiently small to minimize the

vo -1
effect of the offset  for f >> fc
• RfCf must be sufficiently large so as to negligibly v
i
j R iC f
impact the input signal frequencies of interest 1
fc 
A large resistor Rf is used to prevent saturation 2 R f C 43
CuuDuongThanCong.com https://fb.com/tailieudientucntt f
Integrators
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du
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Figure 3.9 A three-mode integrator With S1 open and S2 closed, the

cu
dc circuit behaves as an inverting amplifier. Thus o = ic and o can

be set to any desired initial conduction. With S1 closed and S2 open,
the circuit integrates. With both switches open, the circuit holds o
constant, making possible a leisurely readout. 44
Example 3.2
The output of the piezoelectric sensor may be fed directly into the
negative input of the integrator as shown below. Analyze the circuit
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of this charge amplifier and discuss its advantages.
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isC = isR = 0 R
ng
i
vo = -vc s
co
C
dqs/ dt = is = K dx/dt -
an
o
th
isC isR
ng
+ FET
o
du
Piezo-electric
sensor
u
cu
1 t1 Kdx Kx
vo  -
C

0
dt
dt  -
C
Long cables may be used without changing sensor sensitivity or time
constant. 45
3.9 Differentiators (High-pass filter)
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ng
co
an
Lý tưởng thì R1 = 0, RF = R và
th
C1 = C ng
dv
v o  - RC
i
o
dt
du
V o ( j ) Z
u
f
 -  - j  RC
cu
V i ( j ) Zi
Figure 3.11 A differentiator The dashed lines indicate that a small

capacitor must usually be added across the feedback resistor to
prevent oscillation. 46
Integrating/Differentiating Configurations
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47
Converting Configurations
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Tải thả nổi Tải nối đất
th
o ng
du
Vin
io=vin/Rf
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cu
48
3.10 Active Filters
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th
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49
Active Filters- Low-Pass Filter Cf
V o  j
 - R f 1 Ri Rf
Gain = G =  i -
V i  j  1  j R f C o
om
Ri f
+
.c
(a)
|G|
ng
co
Rf/Ri
an
th
0.707 Rf/Ri ng
o
du
u
freq
cu
fc = 1/2RfCf
Active filters
(a) A low-pass filter attenuates high frequencies
50
Active Filters (High-Pass Filter)
Ci Ri Rf
-
om
V o  j  i
- R f j R iC i o
Gain = G =  +
.c
V i  j  Ri 1  j R iC i (b)
ng
|G|
co
an
th
Rf/Ri ng
0.707 Rf/Ri
o
du
u
cu
fc = 1/2RiCi freq
Active filters
(b) A high-pass filter attenuates low frequencies and blocks dc.
51
Active Filters (Band-Pass Filter)
Cf
V o  j  - j R f C i
om
Ci R Rf

i
-
i
V i  j  1  j R f C 1  j R iC i  o
.c
f
+
ng
|G| (c)
co
an
th
Rf/Ri ng
0.707 Rf/Ri
o
du
u
cu
fcL = 1/2RiCi fcH = 1/2RfCf freq
Active filters
(c) A bandpass filter attenuates both low and high frequencies.
52
3.11 Frequency Response of op-amp and
Amplifier
om
Open-Loop Gain
Compensation
.c
Closed-Loop Gain
ng
Loop Gain
co
Gain Bandwidth Product
an
Slew Rate
th
o ng
du
u
cu
fT
53
3.12 Offset Voltage (non-ideal characteristics)
om
.c
ng
co
an
th
o ng
du
u
cu
54
om
.c
ng
co
an
th
o ng
du
u
cu
55
om
.c
ng
co
an
th
o ng
du
u
cu
56
om
.c
ng
co
an
th
o ng
du
u
cu
57
om
.c
ng
co
an
th
o ng
du
u
cu
58
om
.c
ng
co
an
th
o ng
du
u
cu
59
om
.c
ng
co
an
th
o ng
du
u
cu
60
OFFSET VOLTAGE ADJUSTMENT USING “OFFSET-NULL" PINS
om
.c
ng
co
an
th
o ng
du
u
cu
Ref: Analog Devices CuuDuongThanCong.com https://fb.com/tailieudientucntt

61
OFFSET ADJUSTMENT (EXTERNAL METHODS) – 1/2
If an op amp doesn't have offset adjustment pins (popular duals and all quads
do not), and it is still necessary to adjust the amplifier and system offsets, an
external method can be used.
om
Inverting Op Amp External Offset Trim Methods
.c
ng
co
an
th
o ng
This circuit (B) is preferred.
du
u
cu

62
OFFSET ADJUSTMENT (EXTERNAL METHODS) – 2/2
Non-Inverting Op Amp External Offset Trim Methods
om
.c
ng
co
an
th
o ng
du
u
cu
The circuit can be used to inject a small offset voltage when using an op amp in the
non-inverting mode. This circuit works well for small offsets, where R3 can be made
much greater than R1. Note that otherwise, the signal gain might be affected as the
offset potentiometer is adjusted. The gain may be stabilized, however, if R3 is
connected to a fixed low impedance reference voltage sources, ±VR.
63
3.13 Bias Current
om
.c
ng
co
an
th
o ng
du
u
cu
64
om
.c
ng
co
an
th
o ng
du
u
cu
65
om
.c
ng
co
an
th
o ng
du
u
cu
66
om
.c
ng
co
an
th
o ng
du
u
cu
67
om
.c
ng
co
an
th
o ng
du
u
cu
68
om
.c
ng
co
an
th
o ng
du
u
cu
69
Non-ideal Characteristics
om
.c
ng
co
an
th
o ng
du
u
cu
70
3.14 Input and Output Resistance
om
.c
-
ng
co
Ro o
ii Rd d
an
+
Ad io
th
i -
+
ng RL CL
o
du
u
cu
 vi  vo Ro
R ai   ( A  1) R d R ao  
 ii  io A 1
Typical value of Rd = 2 to 20 MW Typical value of Ro = 40 W

71
3.15 PHASE-SENSITIVE DEMODULATORS
Phase Modulator for Linear variable differential transformer LVDT
om
.c
ng
co
+
an
-
th
ng
+
o
-
du
u
cu
72
Phase Modulator for Linear variable
differential transformer LVDT
om
.c
ng
co
+
an
-
th
ng
+
o
-
du
u
cu
73
Phase-Sensitive Demodulator
om
Used in many medical
instruments for signal detection,
.c
averaging, and Noise rejection
ng
co
an
th
o ng
du
u
cu
74
The Ring Demodulator
If vc is positive then D1 and D2 are forward-biased and vA = vB. So vo = vDB
If vc is negative then D3 and D4 are forward-biased and vA = vc. So vo = vDC
om
.c
ng
co
an
th
o ng
du
vc  2vi
u
cu
Figure 3.17 A ring demodulator This phase-sensitive detector produces a

full-wave-rectified output vo that is positive when the input voltage vi is in phase
with the carrier voltage vc and negative when vi is 180o out of phase with vc.
75

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HCMUT

Course: Biomedical Electronics

1. Prof. Andrew Mason - Michigan State University, USA

Design”, John Wiley & Sons, 2010

10. Active Filters

Most bioelectric signals are small and require amplifications

The two inputs are 1 and  2. A differential voltage between them

causes current flow through the differential resistance Rd. The

2- Vo = 0, when v1 = v2 (no offset voltage)

3- Rd =  (input impedance is infinity)

Chú ý: Linear region:

• Với opamp FET: DD (Drain) và SS (Source)

are at the same voltage.

Figure 3.3 (a) An inverting amplified. Current flowing through the

another word it prevents drawing

(a) Single-ended input b) Differential input (c) Common-mode

Gc = 0, nhưng thực tế thường Gc 0.

 Tỉ số triệt cách chung CMRR

Nếu R4/R3 = R2/R1 thì ta có mạch

Mạch này có tổng trở vào: Rin = 

Differential Mode Gain: v3 - v 4  i( R 2  R1  R 2 )

Advantages: High input impedance, High CMRR, Variable gain

G1 = –(1 + R2/R1)R4/R3 và G2 = 1 + R4/R3

• Nếu R1/R2 = R4/R3 thì ta có mạch KĐVS:

 Đây là mạch phát hiện mức zero.

Mạch so sánh có ngưỡng Đặc tuyến truyền đạt

Vi < VTH VTH > VTH

với điện áp ngưỡng (threshold voltage) VTH = –R1Vref/R2 31

3. Giới hạn 2 đầu Vo

Dz1 Dz2 Vz2 + 0.7V

• V+ = R4Vo/(R3 + R4) UTP – LTP = 2(1 + R1/R2)R4VSAT/(R3 + R4)

chuyển sang bão hòa âm.

The circuit will not work well with high frequency

• When the input signal becomes negative, the op amp

has no feedback at all, so the output pin of the op amp

VO = (1 + R2/R1)Vi when Vi > 0

Full-wave precision rectifier: VO = 0 when Vi < 0

VO = (1 + (1-x)/x)Vi = Vi/x

D2 and D3 conduct, whereas D1 and D4 are

Full-wave precision rectifier:

b) For i < 0, (b)

D1 and D4 conduct, whereas D2 and D3 are reverse-biased.

Vo = –VBE = –VTln(IC/IS) = –VTln(Vi/(RiIS))

circuit gain is increased by 10. (b) Input-output characteristics show

10 gains are indicated.

• Rf/Ri must be sufficiently small to minimize the

Figure 3.9 A three-mode integrator With S1 open and S2 closed, the

dc circuit behaves as an inverting amplifier. Thus o = ic and o can

Figure 3.11 A differentiator The dashed lines indicate that a small

fcL = 1/2RiCi fcH = 1/2RfCf freq

Ref: Analog Devices CuuDuongThanCong.com https://fb.com/tailieudientucntt

Ref: Analog Devices CuuDuongThanCong.com https://fb.com/tailieudientucntt

Typical value of Rd = 2 to 20 MW Typical value of Ro = 40 W

Phase Modulator for Linear variable differential transformer LVDT

Figure 3.17 A ring demodulator This phase-sensitive detector produces a

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