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Internship Project Report

On
DESIGN AND SIMULATION OF SEQUENCE DETECTOR OF THE GIVEN SEQUENCE

Submitted in the partial fulfilment of the requirements for the award

of the degree of

BACHELOR OF TECHNOLOGY

In

ELECTRONICS AND COMMUNICATION ENGINEERING

By

LANKA CHETAN SAI 20311A04F0

UNDER THE GUIDANCE OF

Mrs. E. LAVANYA

ASSISTANT PEOFESSOR

DEPARTMENT OF ECE

Department of Electronics and Communication Engineering

SREENIDHI INSTITUTE OF SCIENCE AND TECHNOLOGY

(Affiliated to Jawaharlal Nehru Technological University, Hyderabad)

Yamnampet (V), Ghatkesar (M), Hyderabad - 501 301

SEPTEMBER 2022-NOVEMBER 2022

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SREENIDHI INSTITUTE OF SCIENCE AND

TECHNOLOGY

(Affiliated to Jawaharlal Nehru Technological University, Hyderabad)

Yamnampet (V), Ghatkesar (M), Hyderabad - 501 301

CERTIFICATE

This is to certify that this Summer Industry Internship –I project report entitled
“DESIGN AND SIMULATION OF SEQUENCE DETECTOR OF THE GIVEN SEQUENCE”, is
being submitted by

LANKA CHETAN SAI 20311A04F0

in partial fulfilment of the requirements for the award of Bachelor of Technology degree in
Electronics and Communication Engineering to Sreenidhi Institute of Science and Technology
affiliated to Jawaharlal Nehru Technological University, Hyderabad (Telangana). This record is a
bonafide work carried out by them under our guidance and supervision . The results embodied in the
project report have not been submitted to any other University or Institution for the award of any
degree or diploma.

Internal guide : Head of The Department

Mrs. E. Lavanya Dr. SPV. Subba Rao

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Assistant Professor Professor

Department of ECE Department of ECE

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DECLARATION

LANKA CHETAN SAI ( 20311A04F0 ) student of SREENIDHI INSTITUTE OF SCIENCE AND

TECHNOLOGY , YAMNAMPET, GHATKESAR, studying in III year Isemester, ELECTRONICS &
COMMUNICATION ENGINEERING solemnly declare that the Summer Industry Internship-I report,
titled “DESIGN AND SIMULATION OF SEQUENCE DETECTOR OF THE GIVEN SEQUENCE”
is submitted to SREENIDHI INSTITUTE OF SCIENCE AND TECHNOLOGY for partial fulfilment
for the award of degree of Bachelor of technology in ELECTRONICS & COMMUNICATION
ENGINEERING.

It is declared to the best of our knowledge that the work reported does not form part of any dissertation
submitted to any other university or institute for award of any degree.

LANKA CHETAN SAI 20311A04F0

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ACKNOWLEDGEMENT

I would like to express my gratitude to all the people behind the screen who helped me to transform
an idea into a real application.

I would like to express my heart-felt gratitude to my parents without whom I would not have been
privileged to achieve and fulfil my dreams. I am grateful to our principal, Dr. T. Ch. Siva Reddy,
who most ably run the institution and has had the major hand in enabling me to do my project.

I profoundly thank Dr. SPV. Subba Rao, Head of the Department of Electronics & Communication
Engineering who has been an excellent guide and also a great source of inspiration to my work.

.I would like to thank my internal guide Mrs. E. Lavanya for her technical guidance, constant
encouragement and support in carrying out my project at college.

The satisfaction and euphoria that accompany the successful completion of the task would be great
but incomplete without the mention of the people who made it possible with their constant guidance
and encouragement crowns all the efforts with success. In this context, I would like thank all the other
staff members, both teaching and non-teaching, who have extended their timely help and eased

my task.

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TABLE OF CONTENTS

Page No.

Abstract …………... i
List of Figures ……………. ii
Chapter 1. Introduction 1
Chapter 2. Source Code 8
2.1 Test bench for the Verilog code 10
Chapter 3. Results 13
Chapter 4. Conclusion 15
4.1 Advantages and Disadvantages 16
4.2 Applications 17

References: 18

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ABSTRACT
FIFO is a First-In-First-Out memory queue with control logic that manages the read and
write operations, generates status flags, and provides optional handshake signals for interfacing
with the user logic. It is often used to control the flow of data between source and
destination. FIFO can be classified as synchronous or asynchronous depending on whether same
clock or different (asynchronous) clocks control the read and write operations. In this project the
objective is to design, verify and synthesize a synchronous FIFO using binary coded read and
write pointers to address the memory array. FIFO full and empty flags are generated and passed
on to source and destination logics, respectively, to pre-empt any overflow or underflow of data.
In this way data integrity between source and destination is maintained.

In computer programming, FIFO (first-in, first-out) is an approach to handling program work

requests from queues or stacks so that the oldest request is handled first. In hardware it is either
an array of flops or Read/Write memory that store data given from one clock domain and on
request supplies with the same data to other clock domain following the first in first out logic.
The clock domain that supplies data to FIFO is often referred as WRITE OR INPUT LOGIC
and the clock domain that reads data from the FIFO is often referred as READ OR OUTPUT
LOGIC. FIFOs are used in designs to safely pass multi-bit data words from one clock domain to
another or to control the flow of data between source and destination side sitting in the same
clock domain. If read and write clock domains are governed by same clock signal the FIFO is
said to be SYNCHRONOUS and if read and write clock domains are governed by different
(asynchronous) clock signals FIFO is said to be ASYNCHRONOUS. FIFO full and FIFO empty
flags are of great concern as no data should be written in full condition and no data should be
read in empty condition, as it can lead to loss of data or generation of non relevant data. The full
and empty conditions of FIFO are controlled using binary or gray pointers. In this report we deal
with binary pointers only since we are designing SYNCHRONOUS FIFO. The gray pointers are
used for generating full and empty conditions for ASYNCHRONOUS FIFO

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LIST OF FIGURES.

Fig. No. Fig. Name Page. No

Fig 1.1 Block diagram of FIFO 2

Fig 1.2 State diagram of FIFO 4

Fig 1.3 Functional block diagram 6

Fig 3.1 Output Waveforms of FIFO 14

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CHAPTER 1. INTRODUCTION

FIFO is an acronym for First In First Out, which describes how data is managed relative to time
or priority. In this case, the first data that arrives will also be the first data to leave from a
group of data. A FIFO Buffer is a read/write memory array that automatically keep track of
the order in which data enters into the module and reads the data out in the same order. In
hardware FIFO buffer is used for synchronization purposes. It is often implemented as a circular
queue, and has two pointers;
1. Read Pointer/Read Address Register
II. Write Pointer/Write Address Register
Read and write addresses are initially both at the first memory location and the FIFO queue is
Empty. When the difference between the read address and write address of the FIFO buffer is
equal to the size of the memory array then the FIFO queue is Full
FIFO can be classified as synchronous or asynchronous depending on whether same clock
(synchronous) or different clocks (asynchronous) control the read and write operations.
Synchronous FIFO
A synchronous FIFO refers to a FIFO design where data values are written sequentially into a
memory array using a clock signal, and the data values are read out sequentially from the
memory array using the same clock signal. Figure 1 shows the flow of the operation of a typical
FIFO.

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Figure 1.1: Operation of FIFO with the three data values

Block diagram
Figure 2 presents the Verilog module of the FIFO Buffer. This FIFO Buffer can store eight 32-
bit values. The FIFO Buffer module consists of a 32-bit data input line, data In and a 32-bit data
output line, data Out. The module is clocked using the 1-bit input clock line Clk. The module
also has a 1-bit enable line, EN and a 1- bit active high reset line, Rst.
The 1-bit RD line is used to signal a data read operation on the FIFO Buffer and the 1-bit WR
line is used to signal a data write operation on the FIFO Buffer.
Both the RD and WR lines are active high. The module also has two output lines FULL and
EMPTY which are each 1-bit wide. The FULL line becomes high when the FIFO Buffer is or
becomes full (internal counter becomes eight). The EMPTY line becomes high when the FIFO
Buffer is or becomes empty (internal counter becomes zero).

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 Figure 1.2: Verilog module of a FIFO Buffer
PORT LIST :

NAME I/O Description

clk I Clock input to the FIFO. This is common
input to both read and write sides of FIFO.
reset_n I active-low asynchronous reset input to FIFO
read and write logic
Flush I Active-high synchronous flush input to
FIFO. A clock-wide pulse resets the FIFO

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WRITE SIDE PORTS:

NAME I/ DESCRIPTION
O
write_data I Data input to FIFO
fifo_full O Qualifies the write data. Logic high indicates
the data on write_data bus is valid and need
to be sampled at next rising edge of the
clock.
write_ack O Write acknowledgement to source.

READ SIDE PORTS:

NAME I/O DESCRIPTION

read_data O Read data in response to a read request
fifo_empty O Indicates that FIFO’s internal memory
is empty and therefore has no data to
serve upon.

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 FUNCTIONAL DESCRIPTION :

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Figure 1.3: Functional Block Diagram

The above figure depicts the basic building blocks of a synchronous FIFO which are: memory
array, write control logic and read control logic. The memory array can be implemented either
with array of flip-flops or with a dual-port read/write memory. Both of these implementations
allow simultaneous read and write accesses. This simultaneous access gives the FIFO its inherent
synchronization property. There are no restrictions regarding timing between accesses of the two
ports. This means simply, that while one port is writing to the memory at one rate, the other can
be reading at another rate totally independent of one another. The only restriction placed is that
the simultaneous read and write access should not be from/to the same memory location. The
Synchronous FIFO has a single clock port clk for both data-read and data-write operations.

Data presented at the module's data-input port write_data is written into the next available empty
memory location on a rising clock edge when the write-enable input write_enable is high. The
full status output fifo_full indicates that no more empty locations remain in the module's internal
memory. Data can be read out of the FIFO via the module's data-output port read_data in the
order in which it was written by asserting read-enable signal read_enable prior to a rising clock
edge. The memory-empty status output fifo_empty indicates that no more data resides in the
module's internal memory. There are almost empty and almost full flags too viz. fifo_aempty and
fifo_afull which can be used to control the read and write speeds of the requestor and the
source.

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 WRITE CONTROL LOGIC:
Write Control Logic is used to control the write operation of the FIFO’s internal memory. It
generates binary-coded write pointer which points to the memory location where the incoming
data is to be written. Write pointer is incremented by one after every successful write operation.
Additionally, it generates FIFO full and almost full flags which in turn are used to prevent any
data loss. For example, if a write request comes when FIFO is full then Write
Control Logic stalls the write into the memory till the time fifo full flag gets de-
asserted. It intimates the stalling of write to source by not sending any
acknowledgement in response to the write request.

READ CONTROL LOGIC:

Read Control Logic is used to control the read operation of the FIFO’s internal memory. It
generates binary-coded read pointer which points to the memory location from where the data is
to be read. Read pointer is incremented by one after every successful read operation. Additionally,
it generates FIFO empty and almost empty flags which in turn are used to prevent any spurious
data read. For example, if a read request comes when FIFO is empty then Read Control Logic
stalls the read from the memory till the time fifo_empty flag gets de-asserted. It intimates the
stalling of read to the requestor by not asserting rdata_valid in response to the read

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 FULL AND EMPTY FLAG GENERATION
FIFO full and almost full flags are generated by Write Control Logic whereas empty and almost
empty flags are generated by Read Control Logic. FIFO almost full and almost empty flags are
generated to intimate the source and the requestor about impending full or empty conditions. The
almost full and almost empty levels are parameterized. It is important to note that read and write
pointers point to the same memory location at both full and empty conditions. Therefore, in order
to differentiate between the two one extra bit is added to read and write pointers. For example if
a FIFO has depth of 256 then to span it completely 8- bits will be needed. Therefore with
one extra bit read and write pointers will be of 9-bits. When their lower 8-bits point to same
memory location their MSBs are used to ascertain whether it is a full condition or empty
condition. In empty conditions the MSBs are equal whereas in full condition MSBs are different.

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 CHAPTER 2 .SOURCE CODE

Fig 2.0 Design Code for FIFO Buffer

1. module FIFObuffer( Clk, dataIn, RD,WR,EN, dataOut, Rst, EMPTY, FULL );

2. input Clk, RD, WR, EN, Rst;

3. output EMPTY, FULL;

4. input [31:0]dataIn;

5. output reg [31:0] dataOut; // internal registers

6. reg [2:0] Count = 0;

7. reg [31:0] FIFO [0:7];

8. reg [2:0] readCounter = 0,

9. writeCounter = 0;

10. assign EMPTY = (Count==0)? 1'b1:1'b0;

11. assign FULL = (Count==8)? 1'b1:1'b0;

12. always @ (posedge Clk)

13. begin

14. if (EN==0);

15. else begin

16. if (Rst) begin

17. readCounter = 0;

18. writeCounter = 0;

19. end

20. else if (RD ==1'b1 && Count!=0) begin

21. dataOut = FIFO[readCounter];

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 22. readCounter = readCounter+1;
` end

23. else if (WR==1'b1 && Count<8) begin

24. FIFO[writeCounter] = dataIn;

25. writeCounter = writeCounter+1;

26. end

27. else;

28. end

29. if (writeCounter==8)

30. writeCounter=0;

31. else if (readCounter==8)

32. readCounter=0;

33. else;

34. if (readCounter > writeCounter) begin

35. Count=readCounter-writeCounter;

36. end

37. else if (writeCounter > readCounter)

38. Count=writeCounter-readCounter;

39. else;

40. end

41. endmodule

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Verilog Test Bench for FIFO Buffer
1. `timescale 1ns / 1ps

2. module FIFObuffer_tb;

3. // Inputs

4. reg Clk;

5. reg [31:0] dataIn;

6. reg RD;

7. reg WR;

8. reg EN;

9. reg Rst;

10. // Outputs

11. wire [31:0] dataOut;

12. wire EMPTY;

13. wire FULL;

14. // Instantiate the Unit Under Test (UUT)

15. FIFObuffer uut (

16. .Clk(Clk),

17. .dataIn(dataIn),

18. .RD(RD),

19. .WR(WR),

20. .EN(EN),

21. .dataOut(dataOut),

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22. .Rst(Rst),

23. .EMPTY(EMPTY),

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 24. .FULL(FULL)

25. );

26. initial begin

27. // Initialize Inputs

28. Clk = 1'b0;

29. dataIn = 32'h0;

30. RD = 1'b0;

31. WR = 1'b0;

32. EN = 1'b0;

33. Rst = 1'b1;

34. // Wait 100 ns for global reset

to finish

. #100;

36. // Add stimulus here

37. EN = 1'b1;

38. Rst = 1'b1;

39. #20;

40. Rst = 1'b0;

41. WR = 1'b1;

42. dataIn = 32'h0;

43. #20;

44. dataIn = 32'h1;

45. #20;

46. dataIn = 32'h2;

47. #20;

48. dataIn = 32'h3;

49. #20;

50. dataIn = 32'h4;

51. #20;

52. WR = 1'b0;

53. RD = 1'b1;
54. end

55. always #10 Clk = ~Clk;

56. endmodule

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CHAPTER 3. Results
Figure 3.1: Output waveforms:

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Figure 6. Timing Diagram of FIFO Buffer

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CHAPTE R 4. Conclusion
The design of synchronous FIFO was studied and also verified using System Verilog. The following
concepts of System Verily were used in our project :
1. Class
2. Interface
3. Randomization
4. Ports
5. Program
The verification components in our project were split by the following blocks :

1. Push Generator
2. Pop Generator
3. Push Monitor
4. Pop Monitor
5. Scoreboard
6. System Verilog Testbench Top
7. System Verilog Interface File

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4.1 Advantages and disadvantages

Advantages

1. FIFO method saves money and time in calculating the exact cost of the inventory being
sold because the cost will depend upon the most former cash flows of purchases to be
used first.
2. It is a simple concept which is easy to understand. Even a layman can grab the idea
with little explanation. The managers with little to no accounting information would be
able to understand it easily.

Disadvantages

 One of the biggest disadvantages of FIFO approach of valuation for inventory/stock is that
in the times of inflation it results in higher profits, due to which higher “Tax Liabilities”
incur. It can result in increased cash out flows in relation to tax charges.

 FIFO may not be a suitable measure in times of “hyper inflation”. In such times there exist
no reasonable pattern of inflation and prices of goods could inflate drastically. And in
such cases the matching of most prior purchases with most recent sales would not be
appropriate and may pump up profits to present a distorted picture

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4.2 Applications

 FIFO’s are used to safely pass data between two asynchronous clock domains. In System-
onChip designs there are components which often run on different clocks. So, to pass data
from one such component to another we need ASYNCHRONOUS FIFO. · Some times
even if the Source and Requestor sides are controlled by same clock signal a FIFO is
needed.

 This is to match the throughputs of the Source and the Requestor. For example in one case
source may be supplying data at rate which the requestor can not handle or in other case
requestor may be placing requests for data at a rate at which source can not supply. So, to
bridge this gap between source and requestor capacities to supply and consume data a
SYNCHRONOUS FIFO is used which acts as an elastic buffer.

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REFERENCES

 http://www.systemverilog.us/req_verif_plan.pdf
 http://abramovbenjamin.net/labs/FIFO_design.pdf
 http://www.asic-world.com/examples/systemverilog/fifo1.html#Verification_Of_FIFO
 http://www.cypress.com/?docID=46919

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