Even Semester/CT-1/PCC-CS402/DG/TKM/2020-2021

College of Engineering & Management, Kolaghat

Department of Computer Science & Engineering
Subject: Computer Architecture Subject Code: PCC-CS402
First Class Test Time Allotted: 1 hour Full Marks: 15
(Branch: 4thSemester CSE)
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Group A
Answer any two questions (1 × 2 =2)
Write the correct answers
1 a) Pipelining uses:
i) data parallelism ii) temporal parallelism 1
iii) spatial parallelism iv) None of these
b) What will be the speedup for a 4-segment linear pipeline when the number of instruction 1
n = 64? i) 3.82 ii) 4.5 iii) 2.82 iv) 4.0
c) Structural hazards occur due to : i) Resource conflict ii) Data dependency 1
iii) Branching instruction iv) None of these

Group B
(Short Answer Type Questions)
Answer any one of the following. [3×1 = 3]

2 What are the different parameters used to measure the CPU performance? Briefly discuss each. 3
3 When Program-A is run in a computer system, the user |CPU time is 5 seconds, the elapsed 3
wall-clock time is 6 seconds and the system performance is 16 MFLOPS. Assume that at any
instant, the computer is either doing calculations in CPU or performing I/O operations, but not
both of them simultaneously. Now, the processor is enhancing 5 times faster without changing
the IO speed. What will be the user CPU time, the wall-clock time and MPLOPS performance
in enhanced version?
4 The execution time (in seconds) of four programs on three computers is given below. Total 3
1010 instructions were executed in each of four programs. Find MIPS of each computer.
Program Execution time in seconds
Computer A Computer B Computer C
Program 1 20 1 10
Program 2 20 1000 100
Program 3 50 500 1000
Program 4 100 100 800

Group C
(Long Answer Type Questions)
Answer any one of the following. [ 10×1 = 10 ]

5 a) What is meant by pipeline hazards? Briefly discuss about different hazards. 4

b) Derive the expression of throughput and speedup considering the branch effect. 3
c) A program has 20% branch instruction. When it is run on a five stages pipeline processor, 3
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 Even Semester/CT-1/PCC-CS402/DG/TKM/2020-2021

it was observed that 60% of the branches were successful. Calculate what is the speedup?
6 a) i) What do you mean by job collision in pipeline processor? 1
ii) Draw the state transition diagram from the following reservation table (Fig. 1) and 3+1
identify the greedy cycle.
iii) Determine minimal average latency and throughput if clock period is 20ns. 1+1
1 2 3 4 5 6
S1 X X
S2 X X
S3 X X
Fig. 1 Fig. 2
b) Consider a 4-stage pipeline that consists of Instruction Fetch (IF), Instruction Decode
(ID), Execute (Ex) and Write Back (WB) stages. The times taken by these stages are 50ns, 3
60ns, 110ns and 80ns respectively. The pipeline registers are required after every pipeline
stage, and each of these pipeline register consumes 10 ns delay. What is the speedup of
the pipeline under ideal conditions compare to the corresponding non-pipelined
implementation?
7 a) State Amdahl’s Law. 1
b) Consider a two-function (A and B) given in Fig. 2. If both of the functions take exactly 6
cycles to finish, then
i) Determine the stage utilization sequence for each of function A and function B. 1
ii) Show their respective reservation tables. 1
iii) Find out the initial collision matrices. 3
c) In a computer system 4 types of instructions (ALU, load, store and branch) are mixed
together at rate of 40%, 20%, 10% and 30%. The CPIs of them are 1, 4, 3, 2 respectively.
i) Calculate the overall effective CPI. 1
ii) How much faster would it be if the average load time reduced to 2 cycles? 1
iii) How does it perform with branch prediction to shave a cycle off the branch time? 1
iv) What will its performance be if two ALU instructions are executed at once? 1

Ability to understand quantitative measures to design and evaluate

computer and their performance analysis.
Learn the concept of pipelining and hazards to improve
system performance.

Computer
Architecture

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