Four Latches as a 4-Bit Register

Block Diagrams of a 4-Bit Register

4 x 8-Bit Register
4 x 8-Bit Register from two 4 x 4bit
memory chips
8 x 8 memory
8 x 8 memory from two 4 x 8bit
memory chips
 Addressing Eight Registers with
Four Address Lines
(complete or absolute decoding )
 Memory Map and Addresses
• picture representation of the address
range
• shows where the different memory chips
are located within the address range.
Memory Map and Addresses
Address Range of a Memory Chip
• The list of all addresses that are mapped
to the chip.
The 8085 and Address Ranges
• 8085 has16 address lines
• So, it can address a total of 216 = 64K memory
locations
• If we use memory chips with 1K locations each,
then we will need 64 such chips
• The 1K memory chip needs 10 address lines to
uniquely identify the 1K locations.(log21024=10)
• That leaves 6 address lines which is the exact
number needed for selecting between the 64
different chips (log264=6).
 The 8085 and Address Ranges

• Now, we can break up the 16-bit address of the

8085 into two pieces:

Depending on the combination on the address

lines A15-A10 , the address range of the
specified chip is determined.
 Chip Select Example
• A chip that uses the combination A15 -A10
= 001000 would have addresses that
range from 2000H to 23FFH.

• 10 address lines on the chip gives a range

of 000000 0000 to 11 1111 1111 or 000H to
3FFH for each of the chips.
 Chip Select Example

• The memory chip in this example would require

the following circuit on its chip select input:
 Chip Select Example
• If we change the above combination to the
following:

A15-A10= 100100 & A9-A0= 000H to 3FFH

chip addresses ranging from:
100100 0000000000 To 100100 1111111111
i.e. 2400 to 27FF.
 Chip Select Example
first case, the memory chip occupies the piece of the memory
map identified as before.

second case, it occupies the piece identified as After.

 Example
Illustrate the memory address range of the
chip with 256 bytes of memory, shown in
Figure 3.10(a), and explain how the range
can be changed by modifying the hardware
of the Chip Select CS line in Figure 3.10(b).
Example-1
Example-1
Example-1

The memory address

range in Figure (b) will
be
8000H to 80FFH.
 Example-2
• Explain the memory address range of 1K
(1024 x 8) memo shown in Figure
• explain the changes in the addresses if the
hardware of the CS line is modified.
Example-2
 Example-2

The memory addresses ranges from

0000H to 03FFH.
 Example-2
• if A is connected to the NAND gate without
an inverter,
• the memory addresses will range from
8000 to 83FFH.
 Example-3
• Calculate the address lines required for an
8K-byte (1024 x 8 = 8192 registers)
memory chip.

• Ans : 13
 Example-4
• Calculate the number of memory chips
needed to design 8K-byte memory if the
memory chip size is 1024 x 1.

• Ans : 64
 Example-5
• The instruction code 0100 1111 (4FH) is
stored in memory location 2005H.
• Illustrate the data flow and
• list the sequence of events when the
instruction code is fetched by the MPU.
Example-5
 Example-5
• The program counter places the 16-bit address
2005H of the memory location on the address bus
• The control unit sends the Memory Read control
signal (MEMR, active low) to enable the output
buffer of the memory chip.
• The instruction (4FH) stored in the memory
location is placed on the data bus and transferred
(copied) to the instruction decoder of the
microprocessor.
• The instruction is decoded and executed
according to the binary pattern of the instruction.
Memory Classification