PH DKoentotal

KATHOLIEKE UNIVERSITEIT LEUVEN
FACULTEIT TOEGEPASTE WETENSCHAPPEN

DEPARTEMENT ELEKTROTECHNIEK
AFDELING ESAT - DIVISIE INSYS
Kasteelpark Arenberg 10, B-3001 Leuven, België
ELECTRICAL CHARACTERIZATION AND MODELING

OF GE/III-V - DIELECTRIC INTERFACES
Promotoren : Proefschrift voorgedragen tot

Prof.Dr.ir. Guido GROESENEKEN het behalen van het doctoraat
Prof.Dr.ir. Herman MAES in de Toegepaste Wetenschappen
door
Koen MARTENS
Januari 2009
in samenwerking met
VZW
Interuniversitair Micro-Elektronica Centrum vzw

Kapeldreef 75
B-3001 Leuven (België)
KATHOLIEKE UNIVERSITEIT LEUVEN
FACULTEIT TOEGEPASTE WETENSCHAPPEN
DEPARTEMENT ELEKTROTECHNIEK
AFDELING ESAT - DIVISIE INSYS
Kasteelpark Arenberg 10, B-3001 Leuven, België
ELECTRICAL CHARACTERIZATION AND MODELING

OF GE/III-V - DIELECTRIC INTERFACES
Examencommissie : Proefschrift voorgedragen tot

Prof.Dr.Ir. A. Haegemans, voorzitter het behalen van het doctoraat
Prof.Dr.Ir. G. Groeseneken, promotor in de Toegepaste Wetenschappen
Prof.Dr.Ir. H. Maes, promotor
Prof.Dr.Ir. W. Sansen door
Prof.Dr.Ir. K. De Meyer Koen MARTENS
Dr. M. Meuris
Prof.Dr.Ir. M. Heyns
Prof.Dr.Ir. J. Schmitz, MESA+
onderzoeksinstelling, Universiteit van Twente,
Nederland
U.D.C. : 1 621.3.049.77
Januari 2009
in samenwerking met
VZW
Interuniversitair Micro-Elektronica Centrum vzw

Kapeldreef 75
B-3001 Leuven (België)
©2009 Katholieke Universiteit Leuven - Faculteit Toegepaste Wetenschappen
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uitgave mag worden vermenigvuldigd en/of openbaar gemaakt door middel van druk,
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All rights reserved. No part of this publication may be reproduced in any form
by print, photoprint, microfilm, or any other means without written permission from
the publisher.
ISBN 978-94-6018-020-0
Wettelijke depotnummer: D/2009/7515/3

Acknowledgement
This work has been realized thanks to fruitful guidance and cooperation. These pages
are dedicated to the people involved in this project. First of all I’d like to thank my
promotor Prof. Guido Groeseneken who has provided thorough support and advice
and to Prof. Marc Heyns who has introduced and supported me in this successful
topic. To Ben Kaczer, daily councillor to count on during the course of my PhD,
many thanks. Also thanks to Prof. Herman Maes, promotor, for advice and Marc
Meuris, Ge/III-V program director, for discussions, advice and support. A particular
thanks goes to Jeroen Croon, now at NXP, who helped me extensively write my IWT
funding proposal.
Also thanks to Marc Meuris, Prof. Marc Heyns, Prof. Kristin De Meyer, Prof.
Willy Sansen and Prof. Jurriaan Schmitz for evaluating my PhD work.
I am heavily indebted to the crucial Ge processing and characterization team, Brice
De Jaeger, Frederik Leys, Matty Caymax, Renaud Bonzom, Gang Wang, Annelies De-
labie, Evi Vrancken, Johnny Steenbergen, IMEC P-lijn, Geert Eneman, Jerome Mi-
tard, Paul Zimmerman, David Brunco, and Gareth Nicholas. AMSIMEC is thanked
for their patience and great service: Joris Van Laer, Bruno Knuts, Marc Van Dievel,
Tom Daenen, Jurgen Van Den Bosch, Albert Van Helmont and Luc Dupas. Jan
Putzeys and Vladmir Luppov of Janis are thanked for cryostat support and Albert
Debie for technical support.
My gratitude goes to the reliability and characterization team: Marc Aoulaiche,
Philippe Roussel, Robin Degraeve, Luigi Pantisano and also to two students Angelo
Di Chello and Franco Minucci and their professor Felice Crupi.
A unique opportunity was granted to me by Prof. Krishna Saraswat to do an
internship at the Center for Integrated Systems at Stanford University. Thanks to
Tejas Krishnamohan for support and guidance and many inspiring discussions during
my stay at Stanford. Thanks to the work with Chi On Chui, currently a professor
at UCLA, it was possible to gain in depth understanding of Ge MOS admittance
characteristics and compose the full conductance method by bringing together and
investigating state-of-the-art Ge MOS devices from Stanford and IMEC. Thanks to
Duygu Kuzum, Arash Hazeghi, Donghyun Kim, Kyung Hoae Koo, Sarves Verma,
Hoon Cho, Ali Kemal Okyay, Jungyup Kim for discussions, help with the cryostat
and my crashed laptop and some fun times. More thanks to Philippe Jansen and his
wife Carina for their hospitality and for introducing me to the South Bay Belgians
and to thanks to Nicolas Braem for some surfing.
Plenty of thanks goes to Eddy Simoen of IMEC for good advice and proposing
and helping with DLTS measurements. Further thanks goes to prof. Paul Clauws,
i
Piet Van Meerbeek, Jochen Van Gheluwe, Johan Lauwaert, Stefaan Forment, Andriy
Hikavyy of the University of Gent for DLTS measurements.
I am grateful to prof. V. Afanas’ev and prof. A. Stesmans of KULeuven, for dis-
cussions, advice and help with measurements. Tibor Grasser of TU Wien is thanked
for charge pumping simulations and Yan Zhang of the University of Massachusetts is
thanked for mobility simulations. Also thanks to Guy Brammertz, Wenfei Wang and
Gustaaf Borghs for III-V MOS. I am also thankful to Prof. P. Ye, Dennis Lin, Tian
Shen, Yanqing Wu, Yi Xuan of Purdue University for collaboration and discussions.
The core partners of the IMEC Industrial Affiliation Program (IIAP) are thanked
and the Flemish institute for science and technology (IWT) is acknowledged for the
scholarship.
Finally, a special dedication to the pool and snooker buddies: Geert, Ali, Brice,
Mireilla and Kristina and also to Stefan and Raghu for the interesting discussions
during our noon walks in the forest. Obviously, family and friends are thanked.
Koen Martens
Leuven, January 2009
ii
Abstract
A combination of electrical characterization methods to evaluate MOS interface passi-

vation quality is investigated and adapted for Ge/III-V MOS. This allows to provide
accurate feedback for improving interface passivation, a key challenge in Ge/III-V
MOSFET development. The interface passivation quality and its impact on the prop-
erties of Si-passivated Ge MOSFETs are investigated.
The admittance behavior of Ge and III-V MOS-capacitors, which can deviate
strongly from Si/SiO2 admittance behavior, is explained. The MOS admittance is
shown to be affected in several ways for Ge/III-V MOS.
Several admittance behavior issues can incur large under-and overestimations of in-
terface trap density for Ge/III-V MOS structures when using the conductance method.
It is shown that these issues can be resolved by modifying the conductance method to
a full conductance method. A method was developed which distinguishes weak Fermi
level pinning from other sources of large C-V frequency dispersion.
A pulsed Q-V/C-V technique is introduced which solves the issues of the con-
ventional pulsed C-V and RF C-V methods for sub-nm EOT gate stacks. Ge MOS
DLTS measurements are evaluated. Charge pumping characteristics of germanium
MOSFETs are investigated for the first time and the validity of emission level theory
is confirmed for Ge MOSFETs. To increase the measured fraction of traps in the
bandgap low temperature measurements or transition times down to 6ns are needed
for Ge MOS. Charge pumping results agree with full conductance results.
The Ge/Si/SiO2 /HfO2 gate stack does not show the excellent Si/SiO2 gate stack
passivation properties. It is proposed that for the Si-passivated germanium interface,
traps in the valence band half are of a double acceptor nature and are caused by the
presence of surface segregated Ge at the Si/SiO2 interface. Traps in the conduction
band half are of an acceptor nature. The reduction of Ge segregation leads to bet-
ter passivated interfaces for thinner Si layers and when using the low temperature
SilcoreT M precursor for Si layer growth. Threshold voltage behavior is explained by
the interface traps. Threshold voltage control is found not to be a significant issue
for Si-passivated Ge pMOSFETs. However, the present interface traps profoundly
impact the threshold voltage variability and significantly influence the subthreshold
slope. Three phenomena cause the extracted mobility (2.5x Si universal) to be re-
duced in Si-passivated pMOSFETs: a characterization bias due to stretch-out because
of interface traps, remote phonon scattering, and interface trap Coulomb scattering.
pMOS mobility shows promise for further improvement. The interface trap properties
also explain the major trends in the highly degraded nMOS performance. Interface
trap charge is much higher for nMOS.
iii
iv
List of Symbols
Symbol Unit Description

A m2 Area
B T Magnetic Field
Cdep F/m2 MOS capacitance in depletion
Cit F/m2 Interface trap capacitance
Cox F/m2 Oxide capacitance
CP F/m2 Parallel capacitance
Cs F/m2 Semiconductor capacitance
CT F/m2 Trap capacitance (in Y-circuit)
CT p F/m2 Hole trap capacitance
CT n F/m2 Electron trap capacitance
Dit ,Dit (E) cm−2 eV −1 Interface trap density (as a function of energy)
dSi , dGe m Lattice constant of silicon and germanium
∆E eV Energy difference between a trap and a band
Eg J Semiconductor bandgap
Ei J Intrinsic Energy Level
EF J Fermi-level energy
ε0 F/m Vacuum dielectric permittivity
εSiO2 F/m Dielectric permittivity of SiO2
εs F/m Dielectric permittivity of the semiconductor
f Hz Frequency
f0 (E) 1 Fermi-Dirac function
gd S Drain conductance
GP S Parallel conductance
Gp S Hole trap conductance
Gn S Electron trap conductance
Φms eV Metal-semiconductor work function difference
φm,ef f eV Effective Metal gate Work function
φm,vac eV Vacuum Effective Work function
Icp A Charge pumping current in a MOSFET
Id A Drain current in a MOSFET
Ids A Drain-to-source current in a MOSFET
Ig A Gate current in an MOS stucture
Is A Source current in a MOSFET
k J/K Boltzmann’s constant
v
Symbol Unit Description
L m Gate length of a MOSFET
m kg Carrier mass
n m−3 Electron density
ni m−3 Intrinsic carrier concentration
N m−3 Density of dopant atoms
NA m−3 Density of acceptor dopant atoms
ND m−3 Density of donor dopant atoms
Nef f m−3 Effective density of states of a band
ω Hz Pulsation
p m−3 Hole density
q C Elementary charge
Q 1 Quality factor
Qf Cm−2 Fixed oxide charge
Qinv Cm−2 Inversion charge density
Rseries Ω Series resistance
S mV/dec Subthreshold slope
σ m2 Trap capture cross section
σs kT/q Surface potential fluctuation
T K Temperature
tox m Oxide Thickness
tSi m Silicon Thickness
tr s Rise time
tf s Fall time
τRC s RC time constant
τit s Interface trap time constant
Vbs V Voltage between bulk and source in a MOSFET
Vds V Voltage between drain and source in a MOSFET
Vdd V Supply voltage in a MOSFET
Vg V Gate voltage in a MOSFET
Vgs V Voltage between gate and source in a MOSFET
Vf b V Flatband voltage
VT V Linear threshold voltage of a MOSFET
Vt V Thermal voltage, is equal to kT /q
vth m/s Thermal velocity of a charge carrier
W m Width of a MOS MOSFET
²k F/m Electrical permittivity
~ J·s The reduced Planck constant
µ, µn , µp m2 /Vs Mobility, mobility of electrons and holes
σn , σp m2 Capture cross section for electron and holes
W m Gate width of a MOSFET
wdep m Depletion width
Z Ω Impedance
χ eV Electron affinity
vi
List of Acronyms
Acronym Description
AC Alternating Current
ALD Atomic Layer Deposition
BD Dielectric Breakdown
CMOS Complementary Metal Oxide Semiconductor
C-V Capacitance - Voltage
CET Capacitance Equivalent Thickness
CP Charge Pumping
DC Direct Current
DLTS Deep Level Transient Spectroscopy
DUT Device Under Test
EOT Equivalent Oxide Thickness
E-V Energy-Voltage
EWF Effective Work Function
FCM Full Conductance Method
FGA Forming Gas Anneal
FLPDM Fermi Level Pinning Detection Method
FLE Fermi Level Efficiency
FTDLTS Fourier Transform Deep Level Transient Spectroscopy
G-V Conductance - Voltage
GGO Gallium Gadolinium Oxide
GOI Germanium on Insulator
HDD Highly-Doped Drain
HF High frequency
IC Integrated Circuit
ICP Inversion Charge Pumping
ITRS International Technology Roadmap for Semiconductors
MOCVD Metallo-Organic Chemical Vapor Deposition
MOS/MOSFET Metal Oxide Semiconductor Field-Effect Transistor
PL Photoluminescence
ML Monolayers
NBTI Negative Bias Temperature Instability
nMOS n-type MOSFET
PAI Pre-amorphization implant
pMOS p-type MOSFET
vii
Acronym Description
Q-V Charge - Voltage
QP Quadratic Programming
RF Radio Frequency
RMS Root-Mean-Square
S/D Source/Drain
SBD Soft Breakdown
SRH Shockley-Read-Hall
SS Subthreshold Slope
SSDD Steady State non-equilibrium Deep Depletion
TDDB Time Dependent Dielectric Breakdown
TOFSIMS Time-of-flight Secondary Ion Mass Spectrometry
WF Work Function
viii
Publication List
First Author Journal Papers

[1] K. Martens, B. De Jaeger, M. Meuris, G. Groeseneken, and H.E. Maes. Inter-
face characterization of Si-passivated Hf O2 germanium capacitors using DLTS
measurements. Materials Science in Semiconductor Processing, 9:742–749, 2006.
[2] K. Martens, B. De Jaeger, R. Bonzom, M. Meuris, G. Groeseneken, and H.

Maes. A new interface state density extraction method applicable to peaked and
high-density distributions for Ge MOSFET development. IEEE Electron Device
Letters, 27:405 – 408, 2006.
[3] K. Martens, W. Wang, K. De Keersmaecker, G. Borghs, G. Groeseneken, and

H.E. Maes. Impact of weak Fermi-level pinning on the correct interpretation of III-
V MOS C-V and G-V characteristics. Microelectronic Engineering, 84:2146–2149,
2007.
[4] K. Martens, M. Rosmeulen, B. Kaczer, G. Groeseneken, and H.E. Maes. Elec-

trical characterization of leaky charge-trapping high-κ MOS devices using pulsed
Q-V. IEEE Electron Device Letters, 28(5):436 – 439, 2007.
[5] K. Martens, W.F. Wang, A. Dimoulas, G. Borghs, M. Meuris, G. Groeseneken,

and H.E. Maes. Determining weak Fermi-level pinning in MOS devices by conduc-
tance and capacitance analysis and application to GaAs MOS devices. Solid-State
Electronics, 51(8):1101 – 1108, 2007.
[6] K. Martens, C.O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Heyns, T.

Krishnamohan, K. Saraswat, H. Maes, and G. Groeseneken. On the correct extrac-
tion of interface trap density of MOS devices with high-mobility semiconductor
substrates. IEEE Transactions on Electron Devices, 55(2):547, 2008.
[7] K. Martens, B. Kaczer, T. Grasser, B. De Jaeger, M. Meuris, H.E. Maes, and G.

Groeseneken. Applicability of charge pumping on germanium MOSFETs. IEEE
Electron Device Letters. accepted for publication.
ix
OTHER CONTRIBUTIONS
First Author Conference Contributions

[1] K. Martens, B. Kaczer, Ph. J. Roussel, G. Groeseneken, and H.E. Maes. In-
terface trap characterization and Fermi-level pinning in Si-passivated Ge/Hf O2
capacitors. In Electrochemical Society Fall Meeting Proceedings, Los Angeles, 2005.
[2] K. Martens, B. De Jaeger, M. Meuris, G. Groeseneken, and H.E. Maes. Interface
characterization of Si-passivated Hf O2 germanium capacitors using DLTS mea-
surements. In Proceedings of the European Materials Research Society Meeting,
Nice, 2006.
[3] K. Martens, B. Kaczer, P. Zimmermann, B. De Jaeger, M. Meuris, G. Groe-
seneken, and H.E. Maes. Improvement of interfacial characteristics for Si-
passivated Ge/Hf O2 mosfets. In 37th IEEE Semiconductor Interface Specialists
Conference, San Diego, 2006.
H.E. Maes. Impact of weak Fermi-level pinning on the correct interpretation of
III-V MOS C-V and G-V characteristics. In 15th Biannual Conf. Insulating Films
on Semiconductors, Athens, 2007.
[5] K. Martens, B. Kaczer, B. De Jaeger, M. Meuris, H.E. Maes, and G. Groe-
seneken. Charge pumping characterization of germanium MOSFETs. In 38th
IEEE Semiconductor Interface Specialists Conference, Arlington, Virginia, 2007.
[6] K. Martens, B. Kaczer, H.E. Maes, and G. Groeseneken. Electrical interface
characterization of non-Si based MOSFETs: Challenges and solutions. In 4th
International SiGe Technology and Device Meeting (ISTDM), Hsin Chu, 2008.
invited talk.
[7] K. Martens, H.E. Maes, and G. Groeseneken. C-V interpretation and the con-
ductance technique for III-V and Ge based CMOS. In 32nd Workshop on Com-
pound Semiconductor Devices, Leuven, 2008.
[8] K. Martens, F. Minucci, J. Mitard, B. De Jaeger, M. Meuris, F. Crupi, H.E.
Maes, and G. Groeseneken. Impact of Si-thickness on interface and device prop-
erties of Si-passivated Ge pMOSFETs. In European Solid State Devices Research
Conference, Edinburgh, 2008.
[9] K. Martens, F. Leys, J. Mitard, B. De Jaeger, M. Caymax, M. Meuris, B. Kaczer,
G. Groeseneken, and H. Maes. Impact of interface states on mobility and thresh-
old voltage of Si-passivated Ge MOSFETs. In Semiconductor Interface Specialist
Conference, San Diego, 2008.
Other Contributions
[1] Meuris M., Martens K., De Jaeger B., Van Steenbergen J., Bonzom R., Caymax
M., Houssa M., Kaczer B., Leys F., Nelis D., Opsomer K., Pourghaderi M., Satta
A., Simoen E., Terzieva V., Souriau L., Bellenger F., Brammertz G., Nicholas G.,
Scarrozza M., Huyghebaert C., Winderickx G., Loo R., Clarysse M., Conard T.,
x
OTHER CONTRIBUTIONS
Bender H., Bender H., Todi R., Delabie A., Hellin D., Van Daele B., Sioncke S.,
Mertens P., De Meyer K., Van Elshocht S., Vandervorst W., Zimmerman P., and
Brunco. Key issues for the development of a Ge CMOS device in an advanced
IC circuit. In ECS proceedings SiGe and Ge: Materials Processing and Devices,
pages 783 – 787, Cancun Mexico, 2006.
[2] Leys F., Bonzom R., Kaczer B., Janssens T., Vandervorst W., De Jaeger B.,
Van Steenbergen J., Martens K., Hellin D., Rip J., Dilliway G., Delabie A.,
Zimmerman P., Houssa M., Theuwis A., Loo R., Meuris M., Caymax M., and
Heyns M. Thin epitaxial Si films as a passivation method for (100) Ge: influence
of deposition temperature on ge surface segregation and the high-κ/Ge interface
quality. Materials Science in Semiconductor Processing, 9(4-5):679–684, Decem-
ber 2006.
[3] Simoen E., Satta A., D’Amore A., Janssens T., Clarysse T., Martens K.,
De Jaeger D., Benedetti A., Hoflijk I., Brijs B., Meuris M., and Vandervorst
W. Ion-implantation issues in the formation of shallow junctions in germanium.
Materials Science in Semiconductor Processing, 9(4-5):634–639, December 2006.
[4] Eneman G., Delabie A., Van Elshocht S., De Jaeger B., Nicholas G., Martens
K., Brunco D., Zimmerman P., Houssa M., Pourtois G., Kaczer B., Leys F.,
Winderickx G., Huyghebaert C., Terzieva V., Loo R., Caymax M., Meuris M.,
and Heyns M. Atomic layer deposition as an enabling technology for fabrication
of Germanium MOS transistor. In 7th International Conference Atomic Layer
Deposition Conference - ALD, pages 783 – 787, San Diego CA USA, June 2007.
[5] Pourtois G., Houssa M., De Jaeger B., Leys F., Kaczer B., Martens K., Cay-
max M., Meuris M., Groeseneken G., and Heyns M. A step towards a better
understanding of silicon passivated (100) Ge p-channel. In ECS Proceedings Ad-
vanced Gate Stack Source/Drain and Channel Engineering for Si-Based CMOS
3, pages 53–63, Chicago IL USA, May 2007.
[6] Kaczer B., De Jaeger B., Nicholas G., Martens K., Degraeve R., Houssa M.,
Pourtois G., Leys F., Meuris M., and Groeseneken G. Electrical and reliability
characterization of metal-gate/HfO2 /Ge FETs with Si passivation. Microelec-
tronic Engineering, 84(9-10):2067–2070, December 2007.
[7] Brammertz G., Martens K., Sioncke S., Delabie A., Caymax M., Meuris M.,
and Heyns M. Characteristic trapping lifetime and capacitance-voltage measure-
ments of GaAs metal-oxide-semiconductor structures. Applied Physics Letters,
91(133510):547, December 2007.
[8] Nicholas G., De Jaeger B., Brunco D., Zimmerman P., Eneman G., Martens
K., Meuris M., and Heyns M. High-performance deep submicron Ge pMOSFETs
with halo implants. IEEE Trans. Electron Devices, 54(9):2503–2511, 2007.
[9] Brunco D., Dimoulas A., Boukos N., Houssa M., Conard T., Martens K., Zhao
C., Bellenger F., Caymax M., Meuris M., and Heyns M. Materials and electrical
characterization of molecular beam deposited CeO2 . Journal of Applied Physics,
102(2):024104, 2007.
xi
OTHER CONTRIBUTIONS
[10] Meuris M., De Jaeger B., Van Steenbergen J., Bonzom R., Caymax M., Houssa
M., Kaczer B., Leys F., Martens K., Opsomer K., Pourghaderi M., Satta A.,
Simoen E., Terzieva V., Van Moorhem E., Winderickx G., Loo R., Clarysse T.,
Conard T., Delabie A., Hellin D., Janssens T., Onsia B., Sioncke S., Mertens P.,
Snow J., Van Elshocht S., Vandervorst W., Zimmerman P., Brunco D., Raskin
G., Letertre F., Akatsu T., Billon T., and Heyns M. Advanced Gate Stacks for
High-Mobility Semiconductors, chapter Germanium deep-submicron p-FET and
n-FET devices fabricated on germanium-on-insulator substrates, pages 333–340.
Springer, 2007.
[11] Caymax M., Houssa M., Pourtois G., Bellenger F., Martens K., Delabie A.,
and Van Elshocht S. Interface control of high-κ gate dielectrics on Ge. In 5th In-
ternational Symposium on Control of Semiconductor Interfaces ISCSI-V, Tokyo
Japan, November 2007.
[12] Heyns M., Adelmann C., Bellenger F., Brammertz G., Brunco D., Caymax M.,
De Jaeger B., Delabie A., Eneman G., Houssa M., Kaczer B., Lin D., Martens
K., Meuris M., Mitard J., Opsomer K., Pourtois G., Satta A., Scarrozza M.,
Simoen E., Sioncke S., Souriau L., Terzieva V., and Van Elshocht S. Ge and
III/V: the CMOS of the future. In 38th Semiconductor Interface Specialists
Conference - SISC, pages 53–63, Washington DC USA, December 2007.
[13] Aoulaiche M., Kaczer B., De Jaeger B., Houssa M., Martens K., Degraeve R.,
Roussel P., Mitard J., De Gendt S., Maes H., Groeseneken G., Meuris M., and
Heyns M. Negative bias temperature instability on si-passivated ge-interface.
In IEEE International Reliability Physics Symposium Proceedings - IRPS, pages
358–362, Phoenix AZ USA, April 2008.
[14] Mitard J., De Jaeger B., Leys F., Hellings G., Martens K., Eneman G.,
Brunco D., Loo R., Shamiryan D., Vandeweyer T., Winderickx G., Vrancken
E., De Meyer K., Caymax M., Pantisano L., Meuris M., and Heyns M. Record
Ion/Ioff performance for 65nm Ge pMOSFET and novel Si passivation scheme for
improved EOT scalability. In Proceedings of the International Electron Devices
Meeting, San Francisco USA, December 2008.
[15] Lin D., Martens K., Brammertz G., and M. Heyns. The Fermi level efficiency
method and its applications on high interface trap density oxide-semiconductor
interfaces. to be published, 2009.
[16] Brammertz G., Lin H.-C., Martens K., Mercier D., Sioncke S., Delabie A.,
Wang W.E., Caymax M., Meuris M., and Heyns M. Capacitance-voltage charac-
terization of GaAs-Al2 O3 interfaces. Applied Physics Letters, 93:183504, Novem-
ber 2008.
xii
Nederlandse Samenvatting
Elektrische karakterisering en modellering

van germanium III-V diëlektricum grensvlakken
Inleiding
Figuur 1: Illustratie van de performantiekloof tussen de geprojecteerde perfor-

mantie en de eigenlijke performantie voor de schaling van CMOS circuits. Van
J.A. del Alamo and D. Antoniadis [1].
CMOS schaling is hoofdzakelijk gedreven door geometrische schaling, maar een

performantiekloof ontstaat bij verdere miniaturisering. Zie figuur 1. Een oplossing
voor dit probleem kan bekomen worden door de de performantie op te drijven door
halfgeleiders te gebruiken met een hogere mobiliteit dan Si: Ge en III-V halfgeleiders.
De drive stroom performantie bij heel korte kanaallengtes wordt door de mobiliteit bij
laag veld bepaald volgens de theorie van Lundstrom et al. [2] In deze theorie wordt
xiii
NEDERLANDSE SAMENVATTING
de drive stroom beschreven als volgt:

1
IDS = QW 1 1 (1)
νT + µ0 ε0
waar W de breedte is van de MOSFET, Q de inversielading, µ0 de mobiliteit bij

laag veld, ε0 de permittiviteit en νT de thermische snelheid van de ladingsdragers.
Ge MOSFETs worden verwacht een hogere drive stroom te hebben dan Si door de
hogere drift mobiliteit bij laag veld van Ge (zie figuur 2).
Het is ook mogelijk het verbruikte vermogen te verminderen met Ge III-V. De
hogere drivestroom laat toe om de voedingsspanning te reduceren zonder perfor-
mantieverlies. De sleuteluitdagingen voor de introductie van Ge CMOS zijn de op-
pervlaktepassivatie van Ge III-V MOS structuren, de lek door de kleinere bandgap,
en de Si process flow compatibiliteit.
Figuur 2: Ladingsdragersnelheden in functie van elektrisch veld voor Ge, Si en

GaAs. De mobiliteit is de proportie tussen driftsnelheid en veld.
De algemene doelstelling van dit werk is om de perspectieven voor IMEC Si-

gepassiveerde Ge MOSFETs in kaart te brengen met focus op grensvlakpassivatie.
De bedoeling is om inzicht te verwerven in grensvlakpassivatie door karakterisering
en modellering. Dit dient als feedback voor de verbetering van processen en devices.
Karakterisering zal aangewend worden om de toepasbaarheid van bestaande silicium
methodologieën voor de bepaling van grensvlakkwaliteit te evalueren. Indien nodig
zullen nieuwe methoden ontwikkeld worden. Modellen worden opgesteld op basis van
experimentele gegevens van karakteriseringsmethoden om de toepasbaarheid van Ge
MOSFETs te evalueren. Modellering wordt ook gebruikt om geschikte karakteriser-
ingsmethoden te ontwikkelen.
Admittantiegedrag van Ge/III-V MOS capaciteiten

Het MOS Admittantie gedrag van Ge/III-V MOS capaciteiten kan sterk verschillen
van het typische Si MOS gedrag. We hebben de geldigheid van de klassieke MOS ad-
xiv
mittantie theorie bevestigd voor Ge/III-V MOS. Het is aangetoond dat Fermi-niveau
pinning en admittantiegedrag van MOS capaciteiten met een hoge oppervlaktetoes-
tandsdichtheid in verband kunnen gebracht worden en verstaan worden door het con-
cept zwakke Fermi-niveau pinning te introduceren. C-V karakteristieken met hoge Dit
werden uitgelegd. Een typisch fenomeen voor capaciteiten met een hoge oppervlakte-
toestandsdichtheid dat werd uitgelegd is de “frequentieafhankelijke vlakkebandspan-
ningsverschuiving”. Zie figuur 3.
5x10
-7 Trap density
13 -2
1.5x10 cm
Capacitance [F/cm ]
2
4
1 kHz
3 2.7 kHz
7.2 kHz
19 kHz
2 52 kHz
139 kHz
373 kHz
1 1 MHz
0
-0.5 0.0 0.5 1.0 1.5 2.0
Gate Voltage [V]
Figuur 3: Gesimuleerde C-V curve bij kamertemperatuur in het 1kHz - 1MHz

meetbereik van een GaAs MOS capaciteit met een grote oppervlaktetoestands-
dichtheid bij de conductieband. Oxidedikte is 6.1 nm (∼3.5×1012 cm−2 accumu-
latieladingsdragerdichtheid bij 1 V gate overdrive) en de dopering is 1×1016 cm−3 .
Een “frequentieafhankelijke vlakkebandspanningsverschuiving” is aanwezig, een
teken van zwakke Fermi-niveau pinning.
Het belang van de zwakke inversie respons in Ge MOS capaciteiten werd aange-
toond. De zwakke inversie respons van oppervlaktetoestanden is de admittantie bi-
jdrage die tot stand komt door de interactie van oppervlaktetoestanden met beide
banden. Deze zwakke inversierespons is sterker dan de depletierespons van opper-
vlaktetoestanden en doet zich typisch voor in het zwakke inversie regime. Zie figuur
4.
De tijdsconstante van oppervlaktetoestanden speelt een cruciale rol in het MOS
admittantiegedrag. De tijdsconstante van oppervlaktetoestanden bepaalt de frequen-
tiedispersie van de oppervlaktetoestandscapaciteit en de conductantiepiekfrequentie
(fit = 1/2πτit ) en dus de observeerbaarheid van traps in de admittantiekarakter-
istieken.
Inzicht in MOS-admittantie gedrag is belangrijk voor extractie van de oppervlak-
tetoestandsdichtheid. Het is aangetoond dat de MOS admittantie beı̈nvloed wordt
op verschillende manieren wanneer het substraat en de oppervlaktepassivatie gewi-
jzigd worden. De correcte interpretatie van de routinematig gebruikte admittantie
karakteristieken is van groot belang in Ge/III-V MOS ontwikkeling en vooral voor
oppervlaktetoestandsextractiemethoden.
xv
-7
5x10 Frequencies
Capacitance [F/cm ]
2
1kHz ® 1MHz
4 300K
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Gate Voltage [V]
Figuur 4: Simulatie van de C-V bij kamertemperatuur van een zwakke in-
versierespons van oppervlaktetoestanden van een Ge MOS capaciteit met een
constant oppervlaktetoestandsdichtheid van 7×1011 cm−2 eV−1 .
Interface trap frequency [Hz]
9
10
8
10
7 300 K 300 K
10
210 K 210 K
6
10
5 140 K 140 K
10
+ -
10
4 h e
3
10
2
80 K 80 K
10
1
10
0.0 0.2 0.4 0.6
Valence band offset E-E v [eV]
Figuur 5: Berekende oppervlaktetoestandsfrequentie of conductantiepiekfre-

quentie in functie van de energie in de bandgap voor verschillende temperaturen
voor Ge. De vangstdoorsnede is 1×1015 cm2 . De donkergeschaduwde gebieden
tonen het niet-observeerbare bereik. De lichtgeschaduwde gebieden tonen welk
deel van de bandgap observeerbaar is bij elke temperatuur.
xvi
-6
2.5x10
Frequencies
Capacitance [F/cm ]
2
1k ® 1M
2.0
80 K
1.5
1.0
0.5
0.0
-0.5 0.0 0.5 1.0 1.5
Gate Voltage [V]
Figuur 6: Simulaties van de C-V bij 80K en 300K van een n-type Si-
gepassiveerde Ge MOS capaciteit. Een grote frequentiedispersie is aanwezig bij
80K terwijl dit niet het geval is voor 300K. De simulatie maakt gebruik van een
grote, dominante oppervlaktetoestandsdichtheid bij de conductiebandrand. Het
is duidelijk dat de grote oppervlaktetoestandsdichtheid enkel duidelijk aanwezig
blijkt bij 80K en dat de 300K data gemakkelijk verward kan worden met een
ideaal C-V gedrag.
Extractiemethoden voor Ge/III-V oppervlaktetoestands-

dichtheid
Figuur 7: Het berekende energiebereik waar traps zichtbaar zijn in functie van
temperatuur voor GaAs.
We hebben aangetoond dat het gedrag van de oppervlaktetoestandstijdconstante

(zie figuur 2.24) en de zwakke en sterke inversierespons (zie figuur 8) een nefast
effect hebben op de extractie van de oppervlaktetoestandsdichtheid met de con-
ductantiemethode op Ge/III-V MOS structuren. De conductantiemethode wordt
beschouwd als de meest accurate admittantie gebaseerde methode voor Si/SiO2 . Deze
xvii
problemen kunnen opgelost worden door de conductantiemethode te modificeren in

een “full conductance method” (FCM). In deze methode worden full conductance
metingen gedaan. In een full conductance meting wordt de conductantie gemeten
tussen de gate van een MOSFET of gated diode en de kortgesloten source/drain en
bulk (zie figuur 9). Deze meetconfiguratie elimineert de problemen met zwakke en
sterke inversie en laat toe de oppervlaktetoestandsdichtheid te meten over de hele
bandgap. Metingen worden gedaan in een bereik van temperaturen die garanderen
dat traps in de volledige bandgap gemeten worden.
-7 -7
1.4x10 1.2x10
-0.7 V 300K 300 K
Conductance [F/cm ]
1.2
2
1.0
G/w [F/cm ]
1.0 -0.88 V
2
0.8
0.8 -0.25 V
0.6
0.6 0V
0.4
0.4
0.2 0.2
0.0 0.0
2 4 6 2 4 6 2 4 6 2 4 6 2 4 6 2 4 6
3 4 5 6 3 4 5 6
10 10 10 10 10 10 10 10
Frequency [Hz] Frequency [Hz]
13
1.0x10 1.0x10
13
0.8
Dit [eV cm ]
Dit [eV cm ]
0.8
-2
-2
0.6 0.6
0.4 0.4
-1
-1
0.2 0.2
0.0 0.0
0.0 0.6 0.0 0.6
Energy [eV] Energy [eV]
Figuur 8: Simulatie van de conductantie bij 300K van een zwakke inversie
respons van oppervlaktetoestanden (boven links) van een Ge MOS capaciteit met
een constante oppervlaktetoestandsdichtheid van 7×1011 cm−2 eV−1 (onder links).
Simulatie van de conductantie (boven rechts) bij 300K van een depletierespons
van een gepiekte oppervlaktetoestandsdistributie van een Ge MOS capaciteit
met een piekdensiteit van 8×1012 cm−2 eV−1 (onder rechts). De linkse en rechtse
karakteristieken zijn duidelijk gelijkaardig.
Een kwalitatieve methode werd ontwikkeld die het mogelijk maakt om zwakke
Fermi-niveau pinning door een dominante hoeveelheid oppervlaktetoestanden te on-
derscheiden van andere bronnen van grote C-V frequentiedispersie (zie figuur 10).
Een andere methode werd ontwikkeld door Dennis Lin en mij die de relatieve graad
van Fermi-niveau pinning bepaalt om de passivatie van niet-ideale capaciteiten te
bestuderen, meestal betreft dit GaAs of InGaAs MOS ( zie figuur 3.15). De admit-
tantie methodes gekend als de Gray-Brown methode en de Terman methode werden
niet geschikt gevonden om oppervlaktetoestandsdichtheden te evalueren van exper-
imentele niet-Si/SiO2 devices. De lage frequentie/hoge frequentie methode is een
relatief snelle en gemakkelijk te gebruiken methode maar kan resulteren in het missen
van een grote oppervlaktetoestandsdichtheid dicht bij de bandranden en de methode
xviii
kortsluiting
Figuur 9: In een full conductance meting wordt de conductantie gemeten tussen
de gate van een MOSFET of gated diode en de kortgesloten source/drain en bulk
(links). Dit resulteert in een gesimplificeerd equivalent circuit (rechts).
heeft ook een beperkte gevoeligheid. De full conductance methode (FCM) is de meest
adequate methode om experimentele Ge/III-V MOS oppervlaktetoestandsdichtheden
te karakteriseren over de hele bandgap.
Ga2O3 Conductance
-4
10 Ga2O3 Capacitance
Ga2O3 Capacitance
Series Resistance
extrapolation
Time constant [s]
Ga2O3 Conductance
Series R extrap.
-5 Al 2O3 Conductance
10 Al 2O3 Capacitance
-6
10
-7
10
-2 -1 0 1 2
Gate Voltage [V]
Figuur 10: Plot van de tijdsconstante geëxtraheerd van de conductantie en ca-

paciteit afzonderlijk in functie van de spanning voor een Al2 O3 GaAs sample en
voor een GdO2 GaAs sample. Ook de tijdsconstante door een serieweerstandsef-
fect is geplot als functie van de spanning. Die laatste werd afgeleid van een laag
frequentie GdO2 meting geëxtrapoleerd naar hoge frequenties veronderstellend
dat enkel een serieweerstand van 2 kΩ aanwezig is.
Gepulste technieken
In dit hoofdstuk worden gepulste analysetechnieken behandeld en het karakterisering
arsenaal wordt uitgebreid om MOS eigenschappen te evalueren. De grotere toolset
laat toe om complementaire karakterisering en bevestiging van resultaten door ver-
xix
Figuur 11: Fermi level efficientie (FLE) plots voor p-type InGaAs MOS sam-
ples. Voor 15% indium samples werd de meting bij 423K uitgevoerd om de
midgap traps te bereiken. De andere samples werden gemeten bij kamertemper-
atuur.
-12
1.8x10 pulsed Q-V
2
on regular 10x10 mm
1.6 RF C-V 100 MHz
on RF structure
Capacitance [F]
1.4 RF-IV C-V 100 MHz

on RF structure
regular C-V 100 kHz
1.2 on regular 10x10 mm
2
1.0
Gate leakage [A/cm ]
100
2
0.8 1
0.01
0.6
0.0001
-2 0 2
0.4 Gate Voltage [V]
-2.0 -1.6 -1.2 -0.8 -0.4

Gate Voltage [V]
Figuur 12: Een vergelijking van gewone C-V, RF C-V, RF-IV C-V en pulsed
Q-V metingen op een 1.7 nm EOT Si/SiON nMOSFET met 5 Acm−2 lek bij -2
V, wat de lekresistentie demonstreert van de pulsed Q-V methode. Het base level
is 0.7 V.
xx
schillende technieken te gebruiken. Een gepulste Q-V/C-V techniek wordt voorgesteld

die de problemen oplost van de conventionele pulsed C-V and RF C-V methoden bij
het meten van sub-nm EOT gate stacks. De pulsed Q-V techniek is lekbestendig (zie
figuur 12) en kan ook Q-V of C-V opmeten zonder invloed van oxide charge trap-
ping en kan ook de trappingkarakteristieken opmeten (zie figuur 13). Voor DLTS,
is het duidelijk dat de extractie van oppervlaktetoestandsdichtheden niet haalbaar is
met een relatief eenvoudige methode voor grote oppervlaktetoestandsdichtheden (zie
figuur 14). Geen teken van halfgeleider bulk traps is gevonden met DLTS metin-
gen in de onderzochte samples(zie figuur 15). Echter, bij de aanwezigheid van een
hoge oppervlaktetoestandsdichtheid is de karakterisering van halfgeleider bulk traps
gecompromitteerd.
Starting edge:
200 Ending edge:
pulse width
1 µs
Charge [pC]
10 µ s
150 100 µ s
1 ms
10 ms
100
50
1.0 2.0 3.0 4.0
Amplitude [V]
Figuur 13: Toepassing van de pulsed Q-V methode op een dikke high-κ Si
nMOS. De gemeten verplaatsingslading (Qd ) is getoond in functie van de ampli-
tude. Het verschil in verplaatsingslading tussen de startpulsrand (geen invloed
van trapping) en de eindpulsrand met verschillende pulsbreedtes is gebruikt om
de vlakkebandspanning af te leiden in functie van pulsbreedte en spanning om
de trapping karakteristiek te meten.
Charge pumping karakteristieken van germanium MOSFET’s werden onderzocht

en de geldigheid van de emissieniveau theorie werd bevestigd voor Ge MOSFET’s (zie
figuur 16). Uit theorie en experiment is het duidelijk dat 300K charge pumping met
transitietijden groter dan 100ns, zoals gebruikt voor Si/SiO2 , enkel een hoeveelheid
oppervlaktetoestanden kan karakteriseren nabij midgap voor Ge. Dit legt uit waarom
Si/SiO2 charge pumping praktijken tot een onderschatting van de eigenlijke totale
oppervlaktetoestandsdichtheid kunnen leiden. Om de gemeten fractie van de bandgap
op te drijven kunnen lage temperatuurmetingen gebruikt worden. Door transitietijden
tot 6ns kort te gebruiken kan de oppervlaktetoestandsdichthied tot dichter bij de
bandranden geëxtraheerd worden op germanium MOSFET’s bij 300K. Dit maakt
een gemakkelijke extractie van de oppervlaktetoestandsdichtheid mogelijk over een
groot deel van de bandgap voor processen betrouwbaarheidsevaluatiedoeleinden.
De bekomen resultaten zijn in overeenstemming met de resultaten bekomen met de
full conductance methode (zie figuur 17).
xxi
Extractred interface state density [a.u.]

1
Quiescent voltage
0.5 V
0.1
1V
1.5 V
2V
0.01
0.001
0.0001
0.1 0.2 0.3 0.4 0.5 0.6
Valence band offset [eV]
Figuur 14: Oppervlaktetoestandsdichtheid in functie van de energie

geëxtraheerd van de DLTS metingen apart afgeleid voor elke quiescente span-
ning. De grote verschillen en de aanwezigheid van de staart naar de valentie
band toe tonen de onbruikbaarheid aan van de gebruikte eenvoudige Dit extrac-
tiemethode.
0.6
Quiesce nt vo ltage
0.5 0.5 V
1V
1.5 V
0.4 2V
b1 [pF]
0.3
0.2
0.1
0.0
-0.1
80 100 120 140 160 180 200 220
T [K]
Figuur 15: Het DLTS spectrum (b1 coëfficient zoals voorgesteld door Weiss et
al. [3]) voor verschillende quiescente spanningen tonen aan dat de traps opper-
vlaktetoestanden zijn.
xxii
Figuur 16: Electron en gat emissieniveau’s berekend met Boltzmann [4]

en Fermi-Dirac statistieken in functie van pulsrand slew rate bij verschillende
temperaturen voor germanium. Equivalente emissie niveau’s afgeleid van gede-
tailleerde simulaties zijn ook getoond.
Figuur 17: De geëxtraheerde karakteristieken gebruikmakend van een kleinste

kwadraten lineaire fit zijn getoond in deze figuur vergeleken met een extractie
gebruikmakend van de full conductance methode. Beide komen goed overeen.
Het gelimiteerde verschil zou kunnen liggen aan het feit dat de samples van
verschillende loten afkomstig zijn. De Si dikte toont variaties van ± 1 ML van
lot tot lot.
xxiii
Si-passivatie van Ge MOSFETs
De Ge/Si/SiO2 /HfO2 gate stack vertoont de schitterende gate stack passivatie eigen-
schappen van Si/SiO2 niet. De oppervlaktetoestandsdichtheid (zie figuure 18) is hoger
dan voor de Si/SiO2 gate stack. Het werd gevonden dat de oppervlaktetoestands-
dichtheid in de valentiebandhelft afneemt met toenemende Si-passivatie dikte. De
oppervlaktetoestandsdichtheid in de conductiebandhelft neemt initieel af met toene-
mende Si dikte en dit neemt significant toe voor dikke Si lagen. Voor de SilcoreT M
precursor is de oppervlaktetoestandsdichtheid in de valentiebandhelft gereduceerd in
vergelijking met de silaan precursor.
Interface trap density [eV cm ]

Interface trap density [cm eV ]
-2
-1
14
10 -1 14 TM
3 ML Silcore
-2
6 10
4
3ML silane
2
77 K 10
13
13 153 K 80 K
10 150 K
6
228 K
300 K 230 K
4
12 300 K
10
0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6
Energy relative to valence band [eV] Energy relative to valence band [eV]
-2
-1
14 5ML silane 5 ML Silcore

TM
10
77 K 14
-2
-1
6 10 80 K
153 K 150 K
4
228 K 230 K
2 300 K 300 K
13
13
10
10
6
4
12
10
0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6

-1
-2
14 7ML Silane 7 ML Silcore

TM
10
-2
77 K 14
-1
6 10 80 K
153 K 150 K
4
228 K 230 K
2 300 K 300 K
13
10
13
10
6
4 12
10
0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6
Figuur 18: Geëxtraheerde oppervlaktetoestandsdichtheid van Si-gepassiveerde

Ge pMOSFETs met verschillende Si diktes (in monolagen, ML) en precursor
gebruikmakend van de full conductance methode (FCM) bij 4 temperaturen van
77K tot 300K om de hele bandgap op te meten.
xxiv
Een oppervlaktetoestandsmodel is voorgesteld voor de Si-gepassiveerde germa-

nium interface. Traps in de valentiebandhelft zijn dubbele acceptoren en worden
veroorzaakt door de aanwezigheid van oppervlaktegesegregeerd germanium aan het
Si/SiO2 grensvlak. Traps in de conductiebandhelft zijn van een acceptor aard en het
wordt gespeculeerd dat de toename in oppervlaktetoestandsdichtheid voor dikkere
Si lagen veroorzaakt wordt door een quantummechanisch insluitingseffect. Dangling
bond type traps zijn geen dominante bijdrage aan de oppervlaktetoestandsdichtheid
. De reductie van Ge segregatie leidt tot een beter gepassiveerd grensvlak voor dun-
nere Si lagen en voor de lage temperatuursprecursor SilcoreT M . Verdere reducties
in de valentiebandhelft oppervlaktetoestandsdichtheid zou kunnen door een verdere
verlaging van de groeitemperatuur, door oppervlaktebehandelingstechnieken om Ge
segregatie te verwijderen of segregatie te vermijden tijdens de groei.
PMOS Vt calculated from

NMOS Vt calculated from
2.0 Dbl. Acc./Acc. 0.8
3.5 Acc./Donor
Threshold voltage [V]
Acc./Dbl. Acc.
Donor/Acc.
Dbl. Acc./Dbl. Acc.
3.0 Dbl. Acc./Acc.
1.5 Val. Half / Con. Half 0.6 Val. Half / Con. Half
Measured Vt 2.5 Measured
0.4 nMOS Vt
1.0
2.0
0.2
0.5 1.5
0.0 1.0
0.0 Silane TM
Silane
Silcore
3 4 5 6 7 8 9 3 4 5 6 7 3 4 5 6 7 8
Grown Si ML Grown Si ML Grown Si ML
Figuur 19: Gemeten VT in functie van gegroeide Si dikte voor pMOS met silaan
(links), voor pMOS met SilcoreT M (midden) en silaan nMOS (rechts). De VT
berekend met de geëxtraheerde oppervlaktetoestandsdichtheid is ook aangegeven
voor verschillende Donor/Acceptor/Dubbele Acceptor configuraties van traps in
elke helft van de bandgap.
Drempelspanningsgedrag in functie van de Si dikte en precursor kan uitgelegd

worden door de oppervlaktetoestandsdichtheid en het voorgestelde model (zie figuur
19). Het werd gevonden dat drempelspanningscontrole niet een significant probleem
is voor Si-gepassiveerde Ge pMOSFET’s als de oppervlaktetoestandsdichtheid in de
valentiebandhelft voldoende gereduceerd kan worden (< 7-16×1011 cm−2 ).
De aanwezigheid van oppervlaktetoestanden heeft een groot effect op de drem-
pelspanningsvariabiliteit. Dit fenomeen vereist een oppervlaktetoestandsdichtheid in
de valentiebandhelft van ten meeste 1-10×1010 cm−2 . Oppervlaktetoestandsdichtheid
heeft ook een significante impact op de subthreshold slope en oppervlaktetoestands-
dichtheden in het subthreshold swing energiebereik zouden moeten onder de 8-20
×1011 cm−2 eV−1 gehouden worden. De Si-passivatielaag vermeerdert de EOT van de
MOSFET met een gelimiteerde hoeveelheid en laat nog sub-nm EOT MOSFET’s toe.
De Si-gepassiveerde pMOS en nMOS mobiliteit is ook onderzocht. De mobiliteit
bereikt tot 2.5x de waarde van de universele Si gatenmobiliteit ( zie figuur 20). Drie
fenomenen veroorzaken degradatie van de geëxtraheerde mobiliteit. Eerst is er de
conventionele split C-V mobiliteit extractietechniek die een onderschatting van de
xxv
400
Mobility [cm V s ] 294 K Experimental Ge
2 -1 -1
Si universal
300 2.5x Si universal
200
100
0
6
0.2 0.4 0.6 0.8 1.0 1.2x10
Effective Field [V/cm]
Figuur 20: De gemeten mobiliteit van de Si-gepassiveerde Ge MOSFET met

7ML van Si vergeleken met de universele gatenmobiliteit van silicium.
Mobility [cm V s ]
5
2 -1 -1
Inversion charge
Measurement Linear interp. 130K-294K
12 -2
5x10 cm a = -0.79
2 12 -2
2x10 8x10 cm a = -0.73
13 -2
1x10 cm a = -0.68
7 8 9 2
100
Temperature [K]
Figuur 21: Gatenmobiliteit in functie van de temperatuur en voor verschillende

inversielaagdichtheden voor een Si-gepassiveerde high-κ Ge pMOSFET met 7ML
van gegroeid silicium.
xxvi
mobiliteit induceert, wat veroorzaakt wordt door stretch-out door oppervlaktetoe-

standen. Remote phonon verstrooiing wordt ook aangetoond aanwezig te zijn (zie
figuur 21). Mobiliteitsdegradatie door remote phonon verstrooiing kan verzwakt wor-
den door de verdikking van de grensvlak SiO2 of SiON laag. Een metaal gate moet
worden behouden. Tenslotte wordt het ook aangetoond dat oppervlaktetoestanden
ook de mobiliteit degraderen (zie figuur 22). Om deze degradatie te vermijden voor
pMOSFET’s zou de oppervlaktetoestandsdichtheid in de valentiebandhelft vermin-
dert moeten worden tot onder 5-50 ×1010 cm−2 . De Si-gepassiveerde Ge pMOSFET
mobiliteit kan waarschijnlijk verder worden verhoogd door remote phonon scattering
te reduceren en ook door de oppervlaktetoestandsdichtheid te reduceren. Het opper-
vlaktetoestandsmodel legt ook de gedegradeerde nMOS performantie uit. Oppervlak-
tetoestandslading is veel hoger voor nMOS en de inversielaag is veel dichter tegen
de interface aan, wat meer mobiliteitsdegradatie veroorzaakt. Om een performante
nMOS te bekomen moet de oppervlaktetoestandsdichtheid drastisch verminderd wor-
den over de hele bandgap.
190
Experiment
180
Mobility [cm /Vs]
Model fit
170
2
160
150
140
130
12
2 4 6 8 10x10
-2
Valence side traps [cm ]
Figuur 22: Gatenmobiliteit in functie van de valentiebandhelft oppervlak-

tetoestandsdichtheid (voor verschillende Si diktes en beide precursoren ). Een
goede correlatie werd gevonden tussen de mobiliteit en de oppervlaktetoestands-
dichtheid.
Conclusies
Het Ge/III-V MOS admittantiegedrag is volledig in kaart gebracht. Hierdoor kon een
full conductance methode worden ontwikkeld om de oppervlaktetoestandsdichtheid
van Ge/IIIV MOS capaciteiten accuraat te meten over de hele bandgap. Ook werden
kwalitatieve methodes om Dit te evalueren voor heel hoge Dit ontwikkeld. Er werd een
pulsed Q-V methode ontwikkeld en de toepasbaarheid van DLTS werd geëvalueerd op
Ge MOS. De toepasbaarheid van charge pumping werd geëvalueerd en de methodes
aangepast. De oppervlaktetoestandsdichtheid werd bepaald voor Si-gepassiveerde
Ge MOSFET’s en een model voor Dit in Si-passivatie werd voorgesteld. VT , mo-
biliteit en subthresholdlek van Si-gepassiveerde Ge MOSFET’s worden uitgelegd door
xxvii
Dit . VT -controle is geen significant probleem voor Ge. Er is ook aangetoond dat de
geëxtraheerde mobiliteit gereduceerd wordt door de invloed van stretch-out in de
split C-V extractie, door remote phonon verstrooiing en door verstrooiing door op-
pervlaktetoestanden. Voor de Si-gepassiveerde pMOS zijn er perspectieven voor de
verbetering van mobiliteit, SS, en VT door verhindering van Ge segregatie. De reduc-
tie van remote phonon verstrooiing kan ook tot een mobiliteitsverbetering leiden. Om
de Si-gepassiveerde nMOS te verbeteren is een dramatische verlaging van Dit nodig.
xxviii
BIBLIOGRAFIE
Bibliografie
[1] Jesus del Alamo and D. Antoniadis. CMOS extension via III-V compound semi-
conductors. In IEDM 2007 Short Course: Emerging Nanotechnology and Nano-
electronics, Washington DC, 2007.
[2] M. Lundstrom. Elementary scattering theory of the Si MOSFET. IEEE Electron
Device Letters, 18:361–363, 1997.
[3] S. Weiss and R. Kassing. Deep level transient fourier spectroscopy (DLTFS) - a
technique for the analysis of deep level properties. Solid-State Electonics, 31:pp.
1733–1742, April 1988.
[4] G. Groeseneken, H.E. Maes, N. Beltran, and R.F. De Keersmaecker. A reliable ap-
proach to charge-pumping measurements in MOS transistors. IEEE Transactions
on Electron Devices, 31:42–53, January 1984.
xxix
BIBLIOGRAFIE
xxx
Contents
List of Symbols v
List of Acronyms vii
Publication List ix
Nederlandse Samenvatting xiii
1 Introduction 1
1.1 The Scaling of CMOS Technology: Spotlight on Speed and Power . . . 1
1.2 Ge/III-V CMOS: A Promising Route or the Holy Grail? . . . . . . . . 3
1.3 Problem Statement and Objectives of the Thesis . . . . . . . . . . . . 7
1.4 Devices Used in the Work . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Admittance Behavior of Ge/III-V MOS Capacitors 17

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Setup and Ideal MOS behavior . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Gate Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Impact of Interface Traps . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.1 Depletion Regime . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.2 Weak Inversion Regime . . . . . . . . . . . . . . . . . . . . . . 35
2.5.3 Interface Trap Time Constant and MOS Admittance Temper-
ature Dependence . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6 Inversion Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.7 Other Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.7.1 Dielectric Effects . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.7.2 Quasi-Accumulation Layer and Dipoles . . . . . . . . . . . . . 54
2.7.3 Semiconductor Bulk Traps . . . . . . . . . . . . . . . . . . . . . 55
2.7.4 Oxide Charge Trapping . . . . . . . . . . . . . . . . . . . . . . 55
2.7.5 Steady State Non-Equilibrium Deep Depletion . . . . . . . . . 55
2.8 Similarities in Admittance . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
xxxi
CONTENTS
3 Ge/III-V Interface Trap Extraction Methods 69

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2 Conventional Conductance Method and Full Conductance Method . . 70
3.2.1 Principles of the Conductance Method . . . . . . . . . . . . . . 70
3.2.2 Issues of the Conductance Method Applied to Ge/III-V MOS
and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.2.2.1 Influence of the Time Constant . . . . . . . . . . . . . 71
3.2.2.2 Indistinguishability of the Weak Inversion and Deple-
tion Response . . . . . . . . . . . . . . . . . . . . . . 72
3.2.2.3 Influence of Large Stretch-out and the E-V Relation-
ship Extraction . . . . . . . . . . . . . . . . . . . . . . 76
3.2.2.4 High Trap Density Influence on the Conductance . . . 77
3.2.2.5 Measuring Traps Across the Entire Bandgap . . . . . 78
3.2.3 The Full Conductance Method . . . . . . . . . . . . . . . . . . 78
3.3 Qualitative Interface Trap Density Analysis Methods . . . . . . . . . . 81
3.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.3.2 Fermi Level Pinning Detection Method (FLPDM) . . . . . . . 82
3.3.2.1 Methodology . . . . . . . . . . . . . . . . . . . . . . . 83
3.3.2.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . 84
3.3.2.3 Illustration . . . . . . . . . . . . . . . . . . . . . . . . 86
3.3.2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . 88
3.3.3 Fermi Level Pinning Severity Analysis Method . . . . . . . . . 90
3.3.3.1 Methodology . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.3.2 Applicability . . . . . . . . . . . . . . . . . . . . . . . 91
3.3.3.3 Experimental . . . . . . . . . . . . . . . . . . . . . . . 91
3.3.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . 92
3.4 Investigation of Dit Extraction Methods . . . . . . . . . . . . . . . . . 92
3.4.1 Low frequency (Quasi-static) Method . . . . . . . . . . . . . . 92
3.4.2 Terman Method . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.4.3 Gray-Brown Method . . . . . . . . . . . . . . . . . . . . . . . . 99
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4 Pulsed Signal Techniques 105

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.2 Measuring C-V and Hysteresis in Ultra-Thin EOT MOS: Pulsed Q-V 105
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.2.2 Measurement Principle and Setup . . . . . . . . . . . . . . . . 109
4.2.3 Experimental Q-V and C-V Measurements of Leaky Devices . 114
4.2.4 Q-V Measurement and Characteristics of Charge-Trapping De-
vices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.2.5 Q-V and Trapping Characteristic Measurement of Leaky Oxide-
Charge-Trapping Devices . . . . . . . . . . . . . . . . . . . . . 118
4.2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3 Deep Level Transient Spectroscopy Study of Ge MOS Capacitors . . . 120
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
xxxii
CONTENTS
4.3.2 Theory of DLTS and Fourier Transform DLTS, Devices and

Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 121
4.3.3 Analysis of DLTS Measurements . . . . . . . . . . . . . . . . . 123
4.3.4 Evaluation of DLTS Applicability for Ge MOS Capacitors . . . 126
4.3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4 Charge Pumping Applicability on Ge MOS . . . . . . . . . . . . . . . 127
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.2 Charge Pumping Theory and Devices . . . . . . . . . . . . . . 128
4.4.2.1 Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.2.2 Review of Charge Pumping Theory for Germanium
MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . 132
4.4.2.3 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.4.3.1 Room Temperature . . . . . . . . . . . . . . . . . . . 134
4.4.3.2 Temperature Dependence . . . . . . . . . . . . . . . . 134
4.4.3.3 Short Pulse Times . . . . . . . . . . . . . . . . . . . . 136
4.4.3.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . 137
4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5 Si-passivation of Ge MOSFETs 143

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2 Influence of Processing Conditions on Si-Passivation . . . . . . . . . . 143
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2.2 Si-Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.2.3 Influence of Si Thickness and Precursor: Relation of Interface
Traps with Mobility, Drive Current and Threshold Voltage . . 144
5.2.4 Influence of N2 and H2 Anneal . . . . . . . . . . . . . . . . . . 151
5.3 Origin of Interface Traps in Si-passivated Germanium MOS . . . . . . 153
5.3.1 Ge Diffusion and Segregation . . . . . . . . . . . . . . . . . . . 154
5.3.2 Band Structure Effects . . . . . . . . . . . . . . . . . . . . . . . 156
5.3.3 Si and Ge Dangling Bonds . . . . . . . . . . . . . . . . . . . . . 158
5.4 Threshold Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.5 Impact of Interface Passivation on Variability, Leakage and EOT . . . 162
5.5.1 Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.5.1.1 Parameter Variations due to the Spatial Arrangement
of Interface Traps . . . . . . . . . . . . . . . . . . . . 163
5.5.1.2 Parameter Variations due to Si Thickness Variations . 166
5.5.2 Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.5.3 EOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.6 Mobility in Si-passivated Ge MOSFETs . . . . . . . . . . . . . . . . . 169
5.6.1 Mobility Extraction Technique . . . . . . . . . . . . . . . . . . 169
5.6.2 Temperature Dependence of Mobility . . . . . . . . . . . . . . 171
5.6.2.1 First Mobility vs. Temperature Experiment: Remote
Phonon Scattering and Stretch-out Correction . . . . 172
5.6.2.2 Second Mobility vs. Temperature Experiment: Re-
mote Phonon Scattering and Different Si Thicknesses 173
xxxiii
CONTENTS
5.6.3 Interface Passivation and Mobility in pMOS Devices . . . . . . 175

5.6.4 Interface Passivation and Mobility in nMOS Devices . . . . . . 178
5.6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
5.7 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.7.1 TDDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.7.2 NBTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6 Conclusions, Future Work and Outlook 191

6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.3 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
xxxiv
Chapter 1
Introduction
1.1 The Scaling of CMOS Technology: Spotlight on

Speed and Power
The continued downscaling of the MOSFET dimensions according to Moore’s law
and scaling guidelines, is an unprecedented technological feat (see figures 1.1 and 1.2,
[1][2][3]). The scaling phenomenon has large economical implications. As Intel CEO
Otellini[4] states: “Our business model is one of very high risk: We dig a very big hole
in the ground, spend three billion dollars to build a factory in it, which takes three
years, to produce technology we haven’t invented yet, to run products we haven’t
designed yet, for markets which don’t exist.” “We do that two or three times a year.”
He added: “Everything we do has an inherent belief in technology.”
Figure 1.1: Illustration of Moore’s law:“Doubling of number of components on

a chip roughly every two years.”
1
1. INTRODUCTION
The scaling of the MOSFET has allowed increased functionality per unit chip-area,
reduced cost per functionality, increased performance, and reduced device switching
power. Further progress along the exponential miniaturization roadmap has always
been under scrutiny. In the recent past further progress seemed to be made impos-
sible by the downscaling trajectory of the silicon oxide thickness to unfeasibly thin
layers which would increase the gate leakage current prohibitively due to fundamental
quantum mechanical tunneling. The properties of silicon dioxide are seen as key to
the success of the CMOS industry due to the high electrical quality of the Si/SiO2
interface, its favorable material properties and reliability. The “irreplaceable” SiO2 ’s
dielectric constant made the material unfit for further scaling because it required such
thin layers to maintain electrical channel control. This put in danger further progress
along the scaling itinerary.
Materials with a higher κ-value maintain channel control for larger thicknesses
and improve drive current. The introduction of high-κ metal gate technology, which
resolved the gate leakage issue in 45 nm production MOSFETs[5] is deemed one of
the largest innovations in CMOS technology since the introduction of the poly gate,
or even the invention of the MOS integrated circuit itself. Several other technological
features have been included in production MOSFETs recently to propel CMOS along
the roadmap such as the further lowering of the κ-value of interconnect dielectrics to
reduce interconnect delay, advanced straining techniques to boost performance, and
numerous other innovations.
year
Figure 1.2: Illustration of technology scaling according to Moore’s law and

related scaling roadmaps (left) and an illustration of the increase in device speed
(right) approaching the fundamental limit h/Eel [6]. From Suman Datta [7].
Further challenges arise to realize the future generations of MOSFETs. To main-

tain electrical channel control at reduced channel lengths finfets or multi-gate FETs
are considered needed. The semiconductor industry’s priority is the geometrical scal-
ing and increase in functionality per unit area. However, as devices are scaled a per-
formance gap arises: performance is no longer keeping up with the scaling trend[8], see
figure 1.3. This is related to the increase in parasitic charges as the devices are scaled
down[8]. Further performance increases can be achieved by using more advanced
straining techniques but introducing strain is not judged sufficient. Alternatives to
boost performance are being considered such as Ge/III-V channel materials, carbon
2
1.2 Ge/III-V CMOS: A Promising Route or the Holy Grail?
nano tubes and graphene. Of these possibilities Ge/III-V channel materials are the
most promising and the most mature because they can be integrated into a Si CMOS
front-end process more easily then the other alternatives.
Figure 1.3: Illustration of the performance gap between projected performance

and actual performance for CMOS circuit downscaling. From J.A. del Alamo and
D. Antoniadis [8].
IC Power consumption has also become an important consideration recently and

has motivated architectural changes in microprocessors: the introduction of multi-core
processors. On a device level the importance of power consumption has translated
into the introduction of high-κ dielectrics. Although Moore’s law entails that the
switching energy of a MOSFET decreases as scaling continues, the power density
increases (see figure 1.4). The increasing power density causes system power con-
sumption, cost and thermal management issues. Additionally, successful mobile IC
applications require strongly reduced IC power consumption. The recent energy cri-
sis and environmental concerns add to the importance of power consumption. Also
in the power consumption arena Ge/III-V channel materials offer prospects. Those
materials increase drive current performance and allow one to lower the power supply
voltage without compromising on performance. This allows to reduce the IC power
consumption while maintaining similar or higher performance levels.
The introduction of Ge/III-V MOS channels promises increased drive currents
which can be exchanged for decreased power consumption by lowering the power
supply voltage.
1.2 The Search for Viable Ge/III-V CMOS: A Promis-

ing Route or the Quest for the Holy Grail?
In this work the focus is on Ge MOSFETs. In an eventual CMOS technology a Ge
pMOSFET can be combined with either a Ge nMOSFET or a III-V nMOSFET.
The learning obtained from Ge pMOSFETs will also be shown to be useful for III-V
3
1. INTRODUCTION
Figure 1.4: Illustration of the exponential decrease in switching energy ap-

proaching the fundamental limit Eel = kT ln(2)[6] (left) and the simultaneously
increasing device power density (right) as a consequence of device downscaling.
From Suman Datta [7].
MOSFETs.
The first transistor that was invented in 1947 by Brattain, Bardeen and Shockley
and also the first integrated circuit that was developed in 1958 by Kilby was made of
germanium. The first MOSFET was fabricated in 1960 by Kahgn and Atalla, made
of silicon, after Atalla showed that a Si/SiO2 interface of good quality and stability
was attainable with his oxidation recipe. The oxide of germanium, on the contrary,
dissolves in water and the germanium oxide was found to be of insufficient quality.
Together with the plentiful supply of silicon this explains why today CMOS ICs are
made of silicon. With the recent development of well functioning high-κ dielectrics
with low EOT the traditional concern against Ge MOSFETs has been partially al-
leviated. The stable high quality SiO2 is no longer sufficient for Si MOSFETs for
further scaling and needs to be replaced by a high-κ dielectric putting Ge and Si
MOSFETs at a more equal footing. This is not entirely so since high-κ MOSFETs
still use a Si/SiO2 interfacial layer and, as is shown in this thesis, inserting a Si/SiO2
layer into a Ge/high-κ gate stack does not lead to the excellent Si/SiO2 interfacial
characteristics.
The most important reason driving Ge MOSFET research is the promising drive
current perspective. For Ge MOSFETs the long-channel drive current is in theory
higher than for Si MOSFETs due to the higher Ge mobility. The mobility, µ, deter-
mines the relationship between the driving electric field (E) and the carrier velocity
(ν) at sufficiently low fields (ν = µE). Ge, however, will not be used for long channel
transistors, where mobility determines the drive current or for those short channel
devices where the high field saturation velocity (see figure 1.5) influences the drive
current. Ge will be used in very short channel MOSFETs (beyond or at the 22 nm
node) exhibiting (quasi-)ballistic transport. According to Lundstrom et al. [9] in
this case the drive current is determined by the carrier injection probability. This
probability is related to the mobility at low field. This relationship (explained in the
4
1.2 Ge/III-V CMOS: A Promising Route or the Holy Grail?
Figure 1.5: Carrier velocities as a function of field for Ge, Si and GaAs. The
mobility is the proportion of the drift velocity of the carriers to the electric field.
next paragraph) shows why the very short channel Ge MOSFETs are expected to
have a higher drive current than Si MOSFETs. It is because of Ge’s higher low field
drift mobility (see figure 1.5). The relationship between injection velocity and long
channel mobility is supported by experimental data ( see figure 1.6).
The injection probability tc , discussed in the theory of Lundstrom[9] is given by:
λ 2µ0 E0
tc = = (1.1)
l+λ νT + 2µ0 E0
where l is de distance from the source to the location where the potential has decreased
with kT/q for a source electrical field of ε0 . The mean free path is λ ∝ µ0 , where µ0
is the mobility at low field. νT is the thermal velocity. The drive current becomes:
tc 1
IDS = QW νT = QW 1 (1.2)
2 − tc νT + µ01E0
where W is de width of the MOSFET and Q the inversion charge.

An important difference between the development of high-κ and Ge technology is
that the physical mechanism leading to the advantage for Ge technology, the increased
drive current compared to Si, is still subject of debate. The theory by Lundstrom et
al. [9] has been cited frequently to show the potential advantage of Ge at the relevant
technology nodes. Early simulations by Fischetti et al. showed a status quo between
Si, Ge and GaAs [10] considering drive current performance for sub-100nm channel
lengths. Simulations by Shinichi Takagi et al., Low et al. Rahman et al. and Tejas
Krishnamohan et al. showed Ge to be superior to Si ([11][12][13][14][15]). Recent full
band Monte Carlo simulations by Terrance O’Regan and Max Fischetti [16] also show
an advantage for Ge. Marc Lundstrom recently commented that at very short channel
length Si is likely to be the best material because of it’s high density of states [17].
5
1. INTRODUCTION
Figure 1.6: Change in source injection velocity as a function of change in

long channel mobility in different published short channel devices. From J.A. del
Alamo and D. Antoniadis [8].
He also stated that there might be a channel length window where Ge will show an
advantage compared to Si [17]. Hence a large part of the involved authors agree that
Ge will provide a performance benefit. In order to provide a significant performance
benefit to leapfrog strained Si, it is most likely necessary to strain germanium [15].
The second advantage of Ge is that it’s lattice constant matches the GaAs lattice
constant opening up possibilities for monolithical integration with GaAs MOSFETs
and components which have optical and RF possibilities. With germanium by itself
interesting optical components can be built, because the wavelength of the light cor-
responding to the Ge bandgap coincides with a standard wavelength in fiber optics
communication.
A first disadvantage and one of the largest of Ge MOSFETs is the high defect
density at the Ge-dielectric interface. These interface states have played a crucial role
since the very beginning of transistor research [18][19] when focus was on the “field ef-
fect” which eventually led to the MOSFET. Interface passivation has not been shown
to be a fundamental problem and progress has been made in passivating the Ge in-
terface. Initial pioneering work aimed for Ge MOS without an interfacial layer for
passivation in contradiction to Si/high-κ[20]. Such an interfacial layer increases the
EOT which one wants to avoid. However, in further research an interfacial layer ap-
peared to be needed. Surface treatments using ammonia [21][22] have been evaluated,
as well as CeO2 dielectrics [23] and many others [24][25][26][27][28]. Currently GeON
[29][30][31][32][33] and GeO2 interfacial layers [34][35] or Si-passivation [36][37][38]
before high-κ deposition are considered the most promising route to improve the
interface passivation. The passivation of the interface trap defects is important be-
cause these defects degrade drive current, alter the threshold voltage, and increase
the leakage currents.
A second disadvantage of Ge MOSFETs is its higher leakage current than an
equivalent Si MOSFET. This relative leakage increase is not necessarily a problem
because different device architectures (such as GOI) allow to decrease leakage to
6
1.3 Problem Statement and Objectives of the Thesis
comply with device specs. The junctions show more leakage compared to Si due to
the smaller bandgap and defects in the space charge layer of the junction increase
the leakage currents further. In shallow highly doped junctions high activated doping
levels are more difficult to obtain. After implantation the dopants are incorporated
into the Ge lattice during an activation anneal. The activation for Ge MOSFETs
occurs at lower temperatures than for Si which is an advantage. The low junction
activation temperature potentially allows 3D stacked ICs by processing Ge MOSFETs
on top of Si MOSFETs. Apart from junction leakage also gate induced drain leakage
is expected to be a problem. This is band-to-band tunneling exacerbated by the gate
field. Because of the smaller bandgap of Ge this leakage will be larger than for Si.
It has been shown that it is possible to modify the Ge MOSFET device structure to
decrease this type of leakage [39][40].
A third issue is the availability of Ge. It will be necessary to use and develop GOI
(Germanium-On-Insulator) substrates or GOS (Germanium-on-Silicon) substrates of
sufficient quality. This will allow the fabrication of competitive germanium MOSFETs
on reasonably priced wafers. Also the weight and the breakability of the wafers is
reduced.
A last important issue is the necessity to develop an entirely new technology. Dur-
ing the development of the germanium technology emphasis is placed on keeping the
Ge development compatible with Si processing so the production of Ge MOSFETs can
be introduced with as few as possible modifications in existing fabrication facilities.
Although all these issues are present the previously mentioned benefits outweigh
the disadvantages and Ge has gained sufficient interest from major CMOS manufac-
turers to investigate its potential.
1.3 Problem Statement and Objectives of the Thesis

This work focusses on the electrical characterization and analysis of interface passiva-
tion of germanium (and III-V) MOSFETs. Barely any work had been done focussing
on the analysis of electrical characterization techniques for Ge and III-V MOSFET
interface quality. These electrical characterization techniques are necessary to ac-
curately evaluate the success or failure of passivation techniques and are crucial to
provide accurate feedback about Ge MOSFETs since improving interface passiva-
tion is the key Ge and III-V MOSFET challenge. Designing such a technique is not
straightforward due to the potentially highly deformed Ge/III-V admittance char-
acteristics. The work done on Ge MOS provides the insight to design a thorough
electrical interface characterization technique capable of characterizing the interface
trap density throughout the bandgap for both Ge and III-V MOS.
No model exists for the Si-passivated Ge interface and the consequences of limited
interface passivation for this promising interface passivation scheme have not been
studied.
The general objective of this thesis is to map the perspectives for the IMEC Ge
Si-passivated MOSFETs with a focus on interface passivation by means of electrical
characterization and modeling. Is the Si-passivated Ge MOSFET a viable technology
choice for investment in continued research or possible introduction into the develop-
ment phase for a manufactured CMOS process? The need for input to answer this
question is translated into obtaining insight in the interface passivation by means of
7
1. INTRODUCTION
characterization and modeling. Understanding of the IMEC Si-passivated Ge MOS-

FET will serve as feedback for further improvement of processes and devices. The
following objectives are formulated:
The characterization of Ge MOSFETs and capacitors: to evaluate the appli-

cability of existing methodologies for Si MOSFETs and capacitors for charac-
terizing the interface quality on Ge. If deemed necessary, new methods will be
developed specifically for Ge issues or in case the Si methods are found to fail
for Ge.
Modeling of Ge devices: Models will be composed based on experimental data

from the characterization techniques to evaluate the applicability of Ge MOS-
FETs for future CMOS. Modeling will also be used to develop appropriate
characterization techniques.
1.4 Devices Used in the Work

pMOS devices are fabricated with a Si-compatible process flow using 200 mm (100)
Ge-on-Si wafers from ASM as starting material. The process flow is summarized in
table 1.1. The Ge-on-Si wafers have a threading dislocation density of approximately
1×108 cm−2 . The epitaxial Ge is nominally undoped. The wafers first receive 31 P
implants to form the n-well, through a 30-nm deposited SiO2 layer. Wafers receive
deep well and shallow well implants, and a 90-keV threshold voltage adjust (VTA)
implant. Next the SiO2 box isolation is formed.
In the gate stack sequence the Ge surface is first cleaned in an SC1 solution and HF
solution consecutively. The Ge surface is passivated with an epitaxial Si layer (∼0.8
nm) after a 650◦ C pre-epi bake. The Si layer is partially oxidized with aqueous ozone,
resulting in a 0.4 nm layer of SiO2 . To avoid further oxidation, this Si-passivation
layer is immediately capped by a 4 nm ALD HfO2 gate dielectric from an ASM Pulsar
2000 reactor, followed by 10 nm TaN and 80 nm TiN PVD depositions. After dry
metal gate etch, the As halo implant and a boron extension are implanted. Then
the formation of spacers is followed by pre-amorphization and highly doped drain
(HDD) implants. A junction anneal at 550 ◦ C for 5 minutes in nitrogen is done
prior to the nickel germanidation of the active areas using a 5nm thick layer of Ni.
TiN/Ti/Al/TiN was used as backend metallization. The final step is a 350 ◦ C, 20
minute anneal in hydrogen [37].
A TEM cross section and the I-V characteristics of the Ge pMOSFET are shown
in figure 1.7 [38]. A comparison of the evolution of the main characteristics as the
short channel devices were optimized and scaled down is shown in table 1.2. The Ge
MOSFETs outperform their ITRS Si pMOS counterparts. Figure 1.8 compares the
IMEC Ge MOSFETs with other results in literature in October 2004 at the start of
this work and figure 1.9 compares the most recent IMEC Si-passivated Ge MOSFETs
with the best short channel results in literature.
8
1.4 Devices Used in the Work
1. 2µm epi-Ge-on-Si substrates

31
2. P well implants: 90 keV VTA, 180keV shallow, 570keV
deep and 600◦ C 5’ N2 anneal
3. Box isolation 200 nm SiO2 45◦ angle
4. 1/10/5000 NH4 OH:H2 O2 :H2 O 15” SC1 and 40” 0.5% HF
Ge surface clean
5. 10’ 650◦ C H2 bake
6. Epitaxy of Si-passivation layer at 500 ◦ C using Silane
7. 1 ppm 1’ aqueous ozone oxidation of Si, 0.4nm of SiO2
8. 4nm 300 ◦ C ALD HfO2 HfCl4 /H2 O based
9. 10 nm TaN/80 nm TiN gate electrode deposition
10. Dry etch of metal gate
11. Boron extension implant, As halo implant
12. Spacer formation
13. PAI and HDD Implant
14. 550 ◦ C 5’ N2 Activation Anneal
15. NiGe S/D 5 nm
16. Back end dielectric
17. TiN/Ti/Al/TiN metallization
18. 350 ◦ C H2 anneal with cooldown in H2
Table 1.1: Summary of the Si-compatible process flow for IMEC Si-passivated
Ge pMOSFETs.
10-2
Vd = -1V Set of devices
10-4
Vd = -20mV Drain
10-6
I (A/µm)
Hard Source
mask 10-8
10-10 Lg = 65nm Source
Gate
NiGe TiN/ NiGe 10-12
TaN
Ge subtrate -1 0 1
on Si Vg (V)
Figure 1.7: TEM picture of 65nm Ge-pMOSFET (left). Full I-V curves at low
and high Vds of several 65nm Ge pFETs (right).
9
1. INTRODUCTION
April 2007 Oct 2007 April 2008 Intel 45nm

node
Si Ge Si Ge Si Ge
L [nm] 120 125 100 100 65 ∼ 70 35
EOT [nm] 1.9 1.3 1.5 1.2 1.3-1.6 1.4 1
Vdd [V] 1.5 1.5 1.2 1.2 1.2 1.2 1
Ion 350 722 350 425 400- 622 1.07 × 103
[µA/µm] 450
Iof f 7 11 8 11 24 21 100
[nA/µm]
Table 1.2: Evolution of the characteristics of IMEC Si-passivated Ge pMOS-

FETs compared with Si pMOS targets from the ITRS and with the latest 45 nm
node Intel technology in production. Off current is measured at the source for
the IMEC Ge MOSFETs.
100
IBM 2004 HfO2 atomic nitrogen nitridation
SNDL 2003 HfON

SNDL 2003 HfO2
MIT 2003 s-Ge 1.6nm bulk Ge 1.8 nm, both NH3
10 SNDL 2004
HfO2 plasma PH3 Stanford 2002
L [ mm ]
IBM 2004 SGOI s-Ge Si cap SiO2 ZrO2

SNDL 2004 IBM 1991
HfO2 silane pass. GeON 21 nm
1 IMEC 2004
Stanford 2004
HfO2Si-pass.
GeON / SiO2
IBM 1991 2.6 nm
melt growth GeOI
GeON 20 nm
IMEC 2004 HfO2, NH3 2.1 nm

0.1
0.1 1 10 100 1000
I [ mA/ mm]
Figure 1.8: Overview of Ge pMOSFETs from literature at the beginning of

this work in October 2004. The EOT of the devices is indicated as the size of
the circles. The EOT is sometimes indicated in nm in text.
10
1.5 Organization of the Thesis
Ge bulk 60nm Vdd = -1V
Ioff [A/µm] @VTH-Vdd/3

-5
10
70nm
GeOI IMEC
MIRAI
-7 IEDM 2007 65nm Ge pFET
10
CEA-LETI
ESSDERC 2008
-9
10
10-11
0 100 200 300 400 500
Ion [µA/µm] @VTH+Vdd.2/3
Figure 1.9: Comparison of the current 65 nm Si-passivated Ge MOSFETs with

best short channel results from other groups [38].
1.5 Organization of the Thesis

The thesis is organized in the following chapters involving the theory of the admittance
of Ge/III-V MOS structures, admittance based interface trap extraction techniques,
pulsed signal analysis techniques and a treatment of the Si-passivated germanium
MOSFET.
Chapter 2 The admittance behavior of Ge/III-V MOS capacitors is elaborated. The

admittance is shown to be strongly affected in several ways when the substrate and the
interface passivation is changed. Correct interpretation of the routinely used admit-
tance characteristics is of high importance for Ge/III-V technology since frequently
used interface trap density extraction methods are dependent on the admittance be-
havior. Several possible artifacts in the extraction of interface trap densities are
demonstrated.
Chapter 3 In this chapter it will be shown which issues affect the extraction of
interface trap density in Ge/III-V MOS structures based on the developed admittance
theory. The focus is on the conductance method. It is shown that applying the
conductance method on non-Si/SiO2 interfaces can lead to large errors in interface
trap density extraction. These issues can be resolved by modifying the conductance
method to a full conductance method. Another method was developed which is able to
distinguish weak Fermi-level pinning due to a dominant amount of interface traps from
other sources of large frequency dispersion. A method was also co-developed which
evaluates the relative severity of Fermi-level pinning to study the passivation quality of
non-ideal capacitors, usually GaAs or InGaAs MOS. Finally other admittance based
methods are evaluated.
11
1. INTRODUCTION
Chapter 4 In this chapter pulsed signal analysis techniques such as pulsed C-V/Q-
V, DLTS and charge pumping are elaborated. In a first part a pulsed Q-V/C-V
technique is introduced which solves the issues the conventional pulsed C-V and RF
C-V methods have when dealing with sub-nm EOT gate stacks. Secondly, deep level
transient spectroscopy is applied on Ge capacitors to study the technique’s value
for Ge MOS development. Finally, charge pumping is reviewed for the use on Ge
MOSFETs and modifications of the technique are proposed to deal with the charge
pumping characterization issues for Ge MOS.
Chapter 5 This chapter analyzes the Si-passivated Ge interface and its impact on
MOSFET characteristics. The nature of the interface trap defects involved is elab-
orated. A host of MOSFET parameters affected by surface passivation and their
importance are evaluated. The question is answered what the maximum allowed
interface trap density can be without affecting device performance and quality and
which parameters play a role in this maximum allowed density. Conclusions are drawn
on the quality limiting properties of Si-passivated Ge MOSFETs which are caused by
a lack of surface passivation and perspectives are also given for further progress for
the Si-passivated Ge MOSFET.
Chapter 6 In this chapter the general conclusions and suggestions for future work
are given.
12
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15
BIBLIOGRAPHY
16
Chapter 2
Admittance Behavior of
Ge/III-V MOS Capacitors
2.1 Introduction
Admittance characteristics, such as C-V and conductance characteristics, are fre-
quently used in CMOS R&D to characterize crucial parameters of Si MOS capacitors
such as the flatband voltage, fixed charge, work function, effective oxide thickness,
doping level, and last but not least, the semiconductor-dielectric interface passivation
quality. C-V and especially conductance characteristics are the means of choice to
extensively study the interface passivation because of the inherent sensitivity of the
electrical measurements, the ease-of-use of the involved methods, wide availability of
the concerned measurement equipment, and the relative ease of producing capacitor
structures.
Interface passivation is a key challenge for realizing Ge/III-V CMOS. It is therefore
essential that the interface quality is evaluated correctly. For example, poor interface
passivation (presently a non-issue in Si-based technology) can cause major distortions
of the admittance characteristics and can result in far-reaching misinterpretations in
Dit (E) and other parameters perfunctorily extracted from these measurements. The
bandgap of Ge and III-V substrates also affects the admittance characteristics in sev-
eral ways that do not have to be considered in Si-based devices. Correct interpretation
of the routinely used admittance characteristics therefore becomes of paramount im-
portance in Ge/III-V technology.
Thorough understanding of the admittance characteristics will allow the proper
extraction of the interface trap density across the bandgap and of the other MOS
capacitor parameters. Trap density extraction is elaborated in the next chapter. In
this chapter the understanding of the behavior of typical Ge and III-V MOS capaci-
tors with different interface trap distributions is provided based on firmly established
Si/SiO2 MOS capacitor theory [1][2][3][4][5][6][7][8][9] · · ·
The chapter starts by introducing the measurement setup and the ideal MOS ca-
pacitor behavior in section 2.2, after which the influence of series resistance (section
2.3) and gate leakage (section 2.4) on the MOS admittance are discussed. The contri-
bution of interface traps to the MOS admittance is discussed in section 2.5 and that
17
2. ADMITTANCE BEHAVIOR OF GE/III-V MOS CAPACITORS
Figure 2.1: Configuration of the admittance measurement setup (left). A DC

voltage and an AC test voltage is applied over the DUT and an analyzer deter-
mines the admittance as a capacitance and a conductance in parallel. The ideal
MOS capacitor is modeled as an oxide capacitance and semiconductor capaci-
tance in series (right).
of inversion generation in section 2.6. In section 2.7 further MOS admittance effects
are discussed. Finally, in section 2.8 misleadingly similar admittance characteristics
due to different effects are discussed.
2.2 Measurement Setup and Ideal MOS Admittance

Behavior
The admittance of an MOS structure is measured as a function of DC gate volt-
age and frequency by applying a small AC probing signal and DC bias voltage over
the MOS capacitor. The phase and magnitude of the resulting AC current are
analyzed to obtain the admittance as shown in figure 2.1. The MOS admittance
(Ymeas = Gmeas + jωCmeas ) is conventionally represented as a parallel capacitance
(Cmeas ) and conductance (Gmeas ). The magnitude of the AC test signal is typically
chosen in the 10-50 mVrms range. The practical frequency range using conventional
probes and structures and a four terminal pair setup[10] is 100Hz-1MHz. Capaci-
tance measurements in this frequency range are often referred to as HF capacitance
dQ
measurements. Capacitance is defined as C = dV . In this work the 1kHz-1MHz
range is preferred for accurate measurements of small capacitors (2-5 pF). Typical
instruments for measuring the admittance of MOS structures are the Agilent 4294
and 4284 impedance analyzers. They are also used in this work.
The MOS capacitor has four regimes of operation depending on the bias voltage:
accumulation, depletion, weak inversion and inversion (see figure 2.2). The bias volt-
age determines the difference in Fermi level energy between the gate electrode and
the semiconductor. This induces a potential drop in the dielectric and in the semi-
conductor (see lefthand diagrams in figure 2.2). In contrast to a metal electrode the
semiconductor will show band bending in order to accommodate charge. Since the
Fermi level does not change with depth for a semiconductor in equilibrium, the posi-
tion of the Fermi level at the MOS interface relative to the bands is directly related
to the band bending.
For an n-type capacitor as shown in figure 2.2 accumulation will occur for volt-
ages higher than the flatband voltage, the voltage at which the semiconductor
bands are flat. In accumulation majority carriers accumulate at the MOS in-
18
2.3 Series Resistance
terface.
When the interface Fermi level is positioned in between its flatband position
and the intrinsic level (∼midgap) the semiconductor is in depletion: majority
carriers are depleted and the ionized donor charge forms the semiconductor
electrode charge.
For a Fermi level in between midgap and the threshold position the MOS ca-
pacitor is in the weak inversion regime and a weak density of minority carriers
contributes to the semiconductor electrode charge.
Once the threshold voltage is crossed minority carrier density becomes compa-
rable or exceeds the doping density. This is inversion.
The straightforward ideal MOS capacitance description is usually sufficient to

perform the characterization tasks for silicon MOS. The “ideal” MOS capacitance
is defined as the capacitance expected theoretically from free charges in the semi-
conductor and metal/poly electrodes separated by the dielectric. The ideal MOS
capacitor is assumed defect-free apart from fixed charges in the dielectric. The ideal
MOS capacitance is described by an oxide capacitance (Cox ) and a voltage depen-
dent semiconductor capacitance (Cs ) in series [9]. The two capacitances represent
the voltage drop changes (dV /dQ)−1 = C over the oxide and semiconductor related
to charge fluctuation in the electrodes. The equivalent circuit and band diagram are
shown in figure 2.1.
Three main features of the ideal MOS capacitance are used to extract parame-
ters. The maximum capacitance of an MOS capacitor measured as a function of gate
voltage is determined by the oxide capacitance Cox = εSiO2 /tox . This property is
used to extract the oxide thickness or EOT of MOS capacitors. √The MOS capaci-
tance in depletion is dependent on the doping: Cs ≈ εs /wdep ∝ εs qN . This feature
can be utilized to determine the doping taking note that the capacitance in deple-
tion also depends on the band bending which is approximately fixed in inversion.
Finally, fixed charge and the work function, which determine the flatband voltage
(Vf b = Φms − Qf /Cox ), are also routinely extracted from MOS measurements. These
features are illustrated in figure 2.3 with simulations. Note that mostly HF capac-
itance measurements on Si MOS at room temperature do not show the inversion
capacitance (see figure 2.3) due to insufficient availability of minority carriers (inver-
sion generation will be treated in section 2.6). From the three main features it is clear
that, in case of ideal behavior, the EOT, Vf b , and N can be comfortably extracted
by means of C-V fitting.
2.3 Impact of Series Resistance on MOS Admittance

Behavior
Series resistance is a common parasitic affecting MOS C-V measurements. The series
resistance is due to the resistance of the bulk semiconductor material and/or the gate
electrode material, as well as the contact resistances.
19
M O S
(a) (b)
Ionized donors
Q
(c) (d)
Holes
(e) (f)
Holes
Ionized donors
Q
(g) (h)
Figure 2.2: The accumulation regime (a-b), the depletion regime (c-d), the
weak inversion regime (e-f) and the inversion regime (g-h) of an MOS capacitor
represented schematically. Taken from [11].
20
2.3 Series Resistance
-6 -6
1.0x10 3 1.0x10 Vfb= 0.222 V
EOT [nm]:
4 EOT = 3 nm
0.8 0.8
C [F/cm ]
C [F/cm ]
2
2
Vfb= 0.222 V 5 -3
N [cm ] :
0.6 16 -3 0.6
N = 1x10 cm
18
0.4 6 0.4 1x10
17
0.2 0.2 1x10
16
1x10
-1.0 0.0 1.0 -1.0 0.0 1.0
Vg [V] Vg [V]
Figure 2.3: Basic properties of the ideal MOS C-V include the variation of
maximum capacitance with EOT (top left), the variation of the depletion capac-
itance with doping density (top right), and the shifting of the C-V with flatband
voltage (bottom). The simulations show an ideal n-type Ge MOS capacitor.
21
The frequency dependent MOS admittance behavior of an ideal MOS capacitor

with series resistance (see figure 2.4, left) can be comprehended by investigating the
following equations which describe its behavior:
Cox Cs /(Cox + Cs )
C= (2.1)
1 + (ωτRC )2
G Cox Cs /(Cox + Cs )ωτRC

= (2.2)
ω 1 + (ωτRC )2
Where the RC time constant τRC = RC = RCox Cs /(Cox + Cs ).

Equations 2.1 and 2.2 have a particular form which describes a frequency behavior
which will return in different types of MOS admittance behavior:
α
C= +β (2.3)
1 + (ωτ )2
G αωτ
= (2.4)
ω 1 + (ωτ )2
This form includes the time constant τ . The term β represents an offset capacitance
or an approximation for a depletion capacitance for example. Behavior satisfying
this form will be referred to as τ -behavior. τ -behavior has several typical character-
istics. First of all the time constant indicates the frequency, 1/(2τ π), at which the
capacitance is reduced to (Cmax + Cmin )/2. (Cmax and Cmin are the maximum and
minimum capacitance as a function of frequency resp.) At the same frequency G/ω
will peak as a function of frequency. For different types of MOS admittance behavior
the time constant characteristic as a function of voltage will be different.
The typical C-V and G/ω characteristics due to series resistance are shown in
figure 2.5. At each voltage the admittance shows τ -behavior as a function of fre-
quency. The capacitance reduces from the oxide capacitance to half of it around the
frequency of 1/(2τRC π). At the same frequency G/ω peaks. The RC time constant
will decrease when the voltage is swept from accumulation to depletion because the
MOS capacitance decreases (see figure 2.5). The time constant will change in the or-
der of the capacitance change which depends on the doping level of the substrate and
EOT (see figure 2.5). The C-V characteristic shifts down with increasing frequency
around 1/(2τRC π) and the shift occurs evenly throughout most of the accumulation
voltage range.
Due to the reduction in capacitance, the series resistance effect can result in the
overestimation of EOT or CET. The extraction of other parameters among which the
interface trap density (see section 2.5) can also be gravely affected by series resistance.
The presence of series resistance should hence be considered when measuring admit-
tance. The effect can be recognized by the typical frequency dependence shown in
figure 2.5. It is best to simply avoid the presence of the series resistance effect in the
used frequency range by choosing small capacitor areas and optimizing the fabricated
structures.
22
2.4 Gate Leakage
Figure 2.4: The equivalent circuit of the ideal MOS capacitor with an addi-
tional series resistance (left), and the equivalent circuit of an ideal MOS capacitor
with both gate leakage and series resistance added (right).
2.4 Impact of Gate Leakage on MOS Admittance Be-

havior
Ultra-thin EOT gate dielectrics in current and future technologies give rise to sub-
stantial gate leakage due to tunneling. In this section it is elaborated how excessive
gate leakage seriously affects admittance measurements and their interpretation.
The effect of the gate leakage can be understood again by means of the equivalent
circuit shown in figure 2.4. The conductance G = dI/dV represents the leakage
through the gate dielectric. An expected series resistance is also included. The
admittance of an MOS capacitor showing gate leakage (and series resistance) can be
described by the following equations:
G G/ω(RG + 1) + C 0 ωτRG (RG + 1)

= (2.5)
ω 1 + (ωτRG )2
C0
C= (2.6)
1 + (ωτRG )2
RC C
Where τRG = 1+RG , and C 0 = (1+RG) 2 and C = Cox Cs /(Cox + Cs ). From
equations 2.5 and 2.6 it is clear that an increase in gate leakage (G) results in the
decrease of measured capacitance because of the dependence on G in C 0 . The common
extractions from C-V measurements will be prevented by gate leakage in excess of ∼
100mA/cm2 . RF C-V (∼ 100MHz - 1GHz) measurements can be used to overcome
high gate leakage currents [12][13][14] for doping, EOT and Vf b extractions.
Apart from the gate leakage term in the numerator of equation 2.5 and the
(RG + 1)-factor, the equations 2.5 and 2.6 show τ -behavior. For high gate leak-
age the gate leakage term will dominate the conductance. Conductance due to gate
leakage will prevent the use of the interface trap conductance contribution (See sec-
tion 2.5) to characterize interface traps. Sufficiently thick dielectrics are needed to
allow admittance based interface trap extractions to avoid gate leakage effects.
23
-7 -7
5x10 2.5x10
4 2.0 1.5 - 0.3 V
G/w [F/cm ]
2
C [F/cm ]
0.2 V
2
3 1.5 0.1 V
0V
-0.1 V
2 1.0 -0.2 V
-0.3 V
1 -0.4 - -1.5 V
0.5
0 0.0
2 4 6 2 4 6 2 4 6 2 4 6 2 4 6 2 4 6
3 4 5 6 3 4 5 6
10 10 10 10 10 10 10 10
-7
5x10 1-32 kHz
52 kHz
Capacitance [F/cm ]
2
4 85 kHz
139 kHz 228 kHz
3
373 kHz
2
611 kHz
1
1 MHz
-2 -1 0 1 2
Gate Voltage [V]
Figure 2.5: The simulation of the capacitance characteristic as a function of
frequency of an n-type Ge MOS capacitor with series resistance (top left) at a
gate voltage of 1.5 V. The capacitance reduces at higher frequencies and reaches
half its DC value at 1/(2τRC π), in which τRC is the RC time constant. The series
resistance is 3 kΩ and the area of the capacitor is 173x173 µm2 . The simulation
of G/ω − f characteristics of the Ge MOS capacitor is shown for several voltages
(top right). The G/ω −f characteristic shows a peak at the frequency 1/(2τRC π).
This frequency decreases toward accumulation. The C-V characteristic (bottom)
shifts vertically with frequency and the shift occurs evenly throughout most of
the accumulation voltage range.
24
2.5 Impact of Interface Traps
2.5 Impact of Interface Traps on MOS Admittance Be-

havior
For state-of-the-art Si/SiO2 , Si/SiON and even Si/SiO2 /high-κ MOS capacitors in-
terface traps have a negligible contribution to the C-V characteristic. Hence interface
traps do not interfere with the common parameter extraction. This is no longer the
case for Ge/III-V MOS capacitors for which the “heart” of CMOS, the Si/SiO2 in-
terface, has been truly transplanted. Interface traps in Ge/III-V MOS capacitors can
have a large impact on MOS admittance characteristics as will be elaborated in this
section.
Interface traps alter the admittance characteristic in two ways. Firstly, the inter-
face traps cause so-called stretch-out of the C-V characteristic (see figure 2.6)[1][3].
Stretch-out is a DC effect which modifies the relationship between gate voltage and
interface Fermi level position (also simply referred to as energy). The interface Fermi
level position is directly related to semiconductor band bending which is caused by
charges in the semiconductor. As more interface traps are present, more MOS capac-
itor charge will be in the traps at the interface itself instead of in the semiconductor.
Less charge in the semiconductor means less band bending and hence, directly related,
less Fermi level movement. Interface traps cause a decrease in change in energy with
gate voltage change. Since capacitance is directly determined by band bending (band
bending determines Cs ), a stretch-out of the C-V results (see figure 2.6).
Secondly, the interface traps contribute admittance to the MOS admittance [15][5].
The discussion of the admittance contribution of the interface traps is more intricate
and is split in subsections contributed to the depletion and weak inversion regimes.
The temperature dependence of the MOS admittance contribution due to interface
traps is treated in a final subsection. The different impacts of Ge/III-V substrate
materials on the admittance will be discussed in each of these subsections. Note
that we do not include the gate leakage and series resistance effects to maintain a
comprehensive explanation of the interface state phenomena. However, these gate
leakage and series resistance effects should be kept in mind when doing practical
measurements and should be avoided to allow a clear interpretation of the admittance
according to the theory put forward in the following sections.
2.5.1 Depletion Regime

On Si/SiO2 MOS capacitors the interface trap admittance contribution is solely ob-
served in the depletion regime in conventional circumstances (at room temperature,
and within the 1kHz - 1MHz measurement range)[9]. The MOS admittance in de-
pletion is used by most interface trap extraction methods for silicon MOS capacitors
[16] and can be explained relatively straightforward. The contribution of interface
traps to the depletion MOS admittance will now be introduced. The effects of –for
Si/SiO2 – unusually large interface trap densities as encountered in Ge/III-V MOS
capacitors will be developed as well. The contribution of the work described in this
section consists of the introduction of the concept of weak Fermi-level pinning [17]
linking Fermi-level pinning with the conventional MOS admittance theory [18] and
of the simulations of this section based on conventional MOS theory in agreement
with experiments confirming the role of increasing interface trap density in the often
25
Figure 2.6: Illustration of stretch-out resulting from the presence of interface

traps. The top left hand graph shows the capacitance as a function of the valence
band offset of the interface Fermi level position. This relationship is fixed and
does not depend on the interface trap density. The top righthand graph shows
the relationship of Fermi level position with voltage modulated by the interface
trap density. The bottom graph shows the resulting stretch-out of the C-V due
to interface traps.
26
observed Ge/III-V MOS admittance characteristics with typical frequency dispersion.

The admittance contribution of interface traps results from the charging and dis-
charging of traps due to the AC gate bias. The DC bias determines which traps in the
bandgap will be charged and discharged by the AC bias (see figure 2.7). The behavior
of an MOS capacitor with interface traps in the depletion regime is described by the
equivalent circuit shown in figure 2.7 (middle) [7][5]. It consists of the oxide capaci-
tance, the semiconductor capacitance, and the capacitance CT which represents the
charge storage in the trap. The capture and emission of carriers by interface traps is
an energy dissipating process due to the time lag of the interface trap occupation com-
pared to the required equilibrium trap occupation. This dissipation is represented by
the conductance Gn . This small signal equivalent circuit is converted to the righthand
side circuit in figure 2.7 introducing the interface trap capacitance and conductance,
Cit and Git . For the single level trap case Cit and Git are expressed by [7]:
qDit
Cit = (2.7)
1 + (ωτit )2
Git qDit ωτit

= (2.8)
ω 1 + (ωτit )2
Figure 2.7: Band diagram showing the electron capture and emission taking
place near the Fermi level during the application of an AC-voltage (left). Equiva-
lent circuit model of a single interface trap (middle) related to the band diagram
and the transformed equivalent circuit commonly used to model interface traps
in an MOS capacitor (right).
We also define GP = Git and CP = Cit + Cs . These symbols will be used quite
frequently in this work. The measured admittance becomes Ymeas = ((jωCox )−1 +
(GP + jωCP )−1 )−1 (note that no other additional phenomena are considered apart
from the interface states in this deduction). The measured conductance is only due
to interface traps and is easier to use to interpret Dit than the measured capacitance.
The measured capacitance also shows the Cs contribution which has to be separated.
Series resistance and gate leakage can contribute to the measured conductance and
should be avoided if one wants to make use of the conductance to characterize interface
traps.
Equations 2.7 and 2.8 forming the interface trap admittance show τ -behavior.
GP /ω has a maximum at f = 1/2πτit and at that maximum Dit = 2GP /(ωq). The
27
interface trap time constant has a different behavior as a function of gate voltage than
the RC time constant [2]:
τit = [vth σNef f exp(−q∆E/kT )]−1 (2.9)
The hole or electron interface trap time constant is a measure of the time needed to
exchange charge between the trap and respectively the valence or conduction bands.
The gate voltage determines which trap is addressed by setting the interface Fermi
level position at a certain trap position. The energy distance of the trap to the
majority carrier band edge, ∆E, exponentially determines τit . The interface trap
time constant decreases toward accumulation over several orders of magnitude as the
Fermi level sweeps traps at different locations in the bandgap. The time constant
varies exponentially with temperature and also varies inversely proportional to the
capture cross section.
The time constant corresponds to the frequency (1/2πτit ) at which the traps in a
certain position in the bandgap dissipate the most energy per cycle. The equation de-
termining the time constant is derived from the compensation at thermal equilibrium
of emission with capture, known as detailed balance [2]. Capture is described by a
capture cross section combined with the density of free carriers and thermal velocity
of the free carriers subject to capture by traps [2]. For Si/SiO2 interface trap capture
cross sections of 1×10−12 - 1×10−17 cm−2 are observed [9].
-6
1.0x10
Frequency
Capacitance [Fcm ]
-2
0.8 1kHz → 1MHz
0.6
0.4
0.2
-1.0 0.0 1.0

Gate Voltage [V]
Figure 2.8: Simulation of an n-type Si MOS capacitor with a single energy

interface trap with a density of 2.4×1012 cm−2 and at an energy 0.78 eV above
the valence band edge. The capture cross section is 1×10−15 cm−2 . The density
corresponds to the density of the traps in half the bandgap of figure 2.9 (left).
Equations 2.7 and 2.8 are for interface traps with a single energy level in the
bandgap. A C-V due to a single energy level trap is shown in figure 2.8. Interface
traps at a semiconductor-dielectric interface, however, are continuously distributed in
energy throughout the semiconductor bandgap. This results in a modified description
by a convolution:
Dit
Cit = g(E) ⊗ (2.10)
1 + (ωτit )2
28
Git Dit ωτit

= g(E) ⊗ (2.11)
ω 1 + (ωτit )2
R +∞
where ⊗ denotes the convolution ([f ⊗ g](x) = −∞ f (y)g(x − y)dy), where g(E) =
q 2 f0 (1 − f0 )/kT and f0 (E) is the Fermi-Dirac function (1 + exp( E−E
kT ))
F −1
.
-6 -6
1.0x10 Frequency 1.0x10 Frequency
Capacitance [F/cm ]
Capacitance [F/cm ]
2
2
0.8 1kHz → 1MHz 0.8 1kHz → 1MHz
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-1.0 0.0 1.0 -1.0 0.0 1.0
Gate Voltage [V] Gate Voltage [V]
-6
1.0x10 Frequency
Capacitance [F/cm ]
1kHz → 1MHz
2
0.8
0.6
0.4
0.2
0.0
-1.0 0.0 1.0
Gate Voltage [V]
Figure 2.9: Simulation of an n-type Si MOS capacitor showing the in-

fluence of interface trap capacitance on the C-V. A constant interface trap
density across the bandgap is used. As the interface trap density is de-
creased from 4×1012 cm−2 eV−1 (top left) to 1×1012 cm−2 eV−1 (top right) and to
1×1011 cm−2 eV−1 (bottom) the interface trap capacitance contribution decreases.
Interface trap capacitance becomes indistinguishable for smaller densities. The
interface trap capacitance decreases for higher frequencies.
For the MOS C-V, the behavior described by equation 2.10 is illustrated in figure
2.9. The interface traps contribute a frequency dispersive capacitance to the MOS
capacitance which decreases to zero for higher frequencies. As the interface trap
density is decreased the capacitance contribution also decreases. For small interface
trap densities the capacitance contribution can no longer be distinguished. This is
due to the Cs contribution to the MOS capacitance which dominates the interface
trap contribution for low Dit . The conductance properties as described by equation
2.11 are illustrated in figure 2.10. The Gmeas /ω shows a peak determined by the
interface trap time constant. The peak magnitude is proportional to the interface
trap density. For small interface trap densities the peak remains distinguishable,
because the interface traps are the only contribution.
The peaks due to a constant continuous distribution of interface traps across the
bandgap shown in figure 2.10 show a certain peak width, which was found to be too
narrow compared to experiments. Note that in figure 2.10 the peaks seem broad
due to the large range on the vertical axis. Further illustrations can be found in
[9][7]. A phenomenon known as the surface potential fluctuation was introduced to
explain the difference [7]. Surface potential fluctuation is the fluctuation of the band
29
bending due to varying oxide or interface charges across the interface of an MOS
capacitor. As a result the surface potential fluctuation broadens the Gp /ω peak
explaining the experiments [7]. In the simulations shown in this chapter the surface
potential fluctuation is not used, since we aim to explain the general trends in the
observed characteristics and do not wish to go into such detail. For extracting the
interface trap density the surface potential fluctuation was taken into account (see
next chapter).
Figure 2.10: Simulation of G/ω − f for different Dit levels. The peak value
of G/ω is proportional to the interface trap density. Due to the absence of
a conductance contribution from the ideal MOS capacitor small interface trap
densities can be distinguished.
For the Si/SiO2 interface one is used to low trap densities ( < 1×1010 cm−2 ) since
the successful FGA passivation saturates the Pb -type dangling bonds with elemental
hydrogen. This effectively means that a mere ∼ 1 of 100000 surface atoms gives rise
to an interface trap. Even for Si/SiO2 devices without FGA passivation and with
relatively thin oxides (2-10 nm) the impact on C-V of the interface traps will be
limited due to a lower density of interface traps [ Si(100) ∼1×1012 cm−2 and Si(111)
∼5×1012 cm−2 ] than the accumulation layer density ( ∼0.2-1×1013 cm−2 ). This means
that the interface trapped charge will not manage to dominate the free charge in the
C-V characteristics. When studying non-Si/SiO2 semiconductor-dielectric interfaces
one will be confronted with devices with a much higher interface trap density. When
the interface trap density dominates the C-V, the extraction methods based on ideal
C-V behavior become completely inapplicable.
To deal with such high trap densities, the concept of weak Fermi level pinning
is introduced to bridge the gap between the concept of MOS interface Fermi-level
pinning known to occur mainly for III-V MOS structures [19][20][21] and the MOS
admittance theory, developed on Si MOS. Weak Fermi level pinning is defined to
occur when Dit > Cox /q. For weak Fermi level pinning the interface trap capacitance
is larger than the oxide capacitance and the interface traps will dominate the C-V
behavior. When Dit > Cox /q the movement of the Fermi level will be impeded by
interface traps, but it will still be able to move. This is in contrast to the “strong”
Fermi level pinning case in which one assumes that the Fermi level is completely
30
-2
-2
Energy (E-Ev) [eV]

Trap density [cm ] 1.5
-1
14 11
10 3.8x10
12
3.0x10
13 13 1.0 11
10 1.5x10 3.8x10
14 12
3.0x10 3.0x10
12 13
10 0.5 1.5x10
14
3.0x10
11 -2
10 0.0 Trap density [cm ]
0.0 0.4 0.8 1.2 -3 -2 -1 0 1 2 3

E-Ev Valence band offset [eV] Gate Voltage [V]
Figure 2.11: Interface trap distributions (left) used for simulations of the
effect of high interface trap density on GaAs MOS capacitors in figure 2.12.
Energy-Voltage characteristics (right) are shown corresponding to the interface
trap distributions. As the trap density becomes higher the Fermi level shifts less
with voltage resulting, for the highest densities, in weak Fermi level pinning.
fixed at a certain position in the bandgap. Weak Fermi level pinning is illustrated in
figure 2.11 in which E-Vs are shown for increasing interface trap densities. For higher
densities the energy changes less and less with voltage in the high trap density region
of the bandgap. Fermi level pinning is a concern for developing non-Si/SiO2 MOS.
Fermi level pinning has mainly been studied for GaAs-insulator interfaces [22][20][19].
The introduction of the weak Fermi level pinning concept, allows the description of
C-V and G-V characteristics of “pinned” devices with a large amount of interface
traps by the established Si/SiO2 MOS theory.
The effect of increasing interface trap density on the admittance is illustrated by
means of simulations based on equations 2.10 and 2.11 in figure 2.12. The correspond-
ing interface trap densities and the E-V characteristics are plotted in figure 2.11. As
trap density is increased, more frequency dispersion occurs in the MOS C-V charac-
teristic. When Dit > Cox /q a “frequency dependent flatband shift” starts to occur
in the C-V. Such a “frequency dependent flatband shift” is observed on GaAs MOS
samples and is sometimes associated with interface traps in literature [23]. At even
higher densities the C-V also starts to shift vertically down with frequency. In figure
2.13 the impact of the traps on the capacitance at 2V is illustrated. As the interface
traps start to dominate the C-V, the capacitance rises because the interface traps are
located at the interface while the center of charge of the accumulation layer is located
slightly away from the interface.
In figure 2.14 measurements of C-Vs show the same trends with increasing interface
trap density for Si, Ge and GaAs resp. A typical characteristic expected for non-
passivated Si(100)/SiO2 interfaces is shown in figure 2.14, top left. When the SiO2
becomes thicker Dit > Cox /q becomes true and weak Fermi level pinning will occur.
Interface traps dominate the C-V behavior and a “frequency dependent flatband shift”
occurs. For the GaAs sample with the highest trap density the presence of a higher
amount of traps leads to a vertical shift in C-V with frequency in addition to a
“frequency dependent flatband shift.” Evidently, it was ensured that there was no
31
-7 -7
5x10 Trap density 5x10 Trap density
12 -2
]
Capacitance [F/cm ]
2
11 -2 3.0x10 cm
2
3.8x10 cm
Capacitance [F/cm
4 4
1 kHz
3 3 2.7 kHz
7.2 kHz
1 kHz
19 kHz
2 7.2 kHz 2 52 kHz
51.8 kHz
139 kHz
1 373 kHz 1 373 kHz
1 MHz
1 MHz
0 0
-0.5 0.0 0.5 1.0 1.5 2.0 -0.5 0.0 0.5 1.0 1.5 2.0
-7
5x10
-7
1.5x10 cm
13 -2
5x10 Trap density
14 -2
Trap Capacitance [F/cm ] 3.0x10 cm
2
Capacitance [F/cm ]
2
4 density 4 1 kHz
1 kHz 2.7 kHz
2.7 kHz 7.2 kHz
3 3 11.8 kHz
7.2 kHz 19.3 kHz
19 kHz 31.6 kHz
2 2 51.8 kHz
52 kHz 84.8 kHz
139 kHz 139 kHz
1 373 kHz 1 228 kHz
1 MHz
1 MHz
0 0
-0.5 0.0 0.5 1.0 1.5 2.0 -2 -1 0 1 2
Figure 2.12: Simulated C-V curves at room temperature in the 1kHz - 1MHz
measurement range of a GaAs MOS capacitor with interface trap distributions
plotted in figure 2.11. Oxide thickness is 6.1 nm (∼3.5×1012 cm−2 accumulation
charge density at 1 V overdrive) and doping is 1×1016 cm−3 . For higher trap
densities a “frequency dependent flatband shift” is present, a sign of weak Fermi
level pinning. For even higher trap densities the C-V also shows vertical shifts
with changing frequency.
-7
5x10
Capacitance [Fcm ]
-2
0
10 11 12 13 14
10 10 10 10 10
-2
Interface trap density [cm ]
Figure 2.13: Capacitance at 2 V gate voltage as a function of interface trap

density corresponding to figure 2.12.
32
gate leakage or series resistance influence in these measurements. This clearly shows
that regular MOS theory successfully explains the C-V characteristics of devices with
unpassivated interfaces on different semiconductor materials.
-8
7x10 300 K
3.0x10
-7 300 K Frequency
Capacitance [F/cm ]
[Hz]
2
6
Capacitance [F/cm ]
2
2.5 Frequency 3400

[Hz] 5 7800
3
2.0 1000 18x10
3400 4 40x10
3
3 3
1.5 12x10 3 92x10
3 3
40x10 208x10
3 3
1.0 125x10 2 473x10
3 6
480x10 1.3x10
0.5 1
-2.0 -1.5 -1.0 -0.5 0.0 0.5 -2 -1 0 1 2
-6
2.5x10
-7
8x10 300 K
Capacitance [F/cm ]
2
2.0 Frequency
Capacitance [F/cm ]
2
3
1x10
3
1.5 6 3x10
3
10x10
3
30x10
1.0 3
80 K 4 100x10
3
Frequencies 300x10
0.5 6
8k ® 1.6M 1x10
2
0.0
0.4 0.6 0.8 1.0 1.2 1.4 -2 -1 0 1 2
Figure 2.14: A series of experimental C-V characteristics corroborating the

findings of the simulations in figure 2.12. Frequency dependent C-V characteristic
at 300 K of a p-type Si/SiO2 capacitor with a ∼10 nm SiO2 dielectric (top
left) is shown. No FGA was done. Interface trap density is ∼1×1012 cm−2 .
300K characteristic of a Si(100)/SiO2 capacitor with a 20 nm SiO2 dielectric
(top right). Interface trap density is ∼×1012 cm−2 . C-V characteristic at 80 K of
a Ge/Si/SiO2 /HfO2 capacitor with an EOT of 1.4 nm (bottom left). Interface
trap density is 1.6×1013 cm−2 . C-V characteristic at 300 K of a GaAs/GdO2
capacitor with an EOT of 3.8 nm. Interface trap density is > 1×1013 cm−2 .
The measured admittance will show approximate τ -behavior when the interface
trap contribution is significantly larger than the Cs contribution. The Cs will pre-
vent the occurrence of τ -behavior for small trap densities due to its position in the
equivalent circuit. This means that for high interface trap densities not only the in-
terface trap admittance but also the measured admittance will show τ -behavior. The
measured admittance can be approximated by:
qDit Cox /(Cox + qDit )

C∼
= (2.12)
1 + (ωτit,Cox )2
33
G ∼ qDit Cox /(Cox + qDit )ωτit,Cox

= (2.13)
ω 1 + (ωτit,Cox )2
Where τit,Cox = τit CoxC+qD

ox
it
.
When weak Fermi level pinning takes place a“frequency dependent flatband shift”
occurs (as shown in figures 2.12,2.14 and also in [24][25][23]). In this case, the MOS
capacitance is dominated by the interface trap capacitance which is frequency disper-
sive as described by equation 2.12. When only measuring at one frequency the C-V is
very similar to an ideal C-V, but is in fact nearly completely determined by interface
traps. When a C-V showing interface trap behavior is measured at a certain frequency
the interface trap time constant and frequency determine the voltage position of the
C-V flank where the capacitance changes significantly with voltage. For an ideal C-V
the voltage position of this C-V flank is associated with the flatband voltage. The
MOS capacitance with dominant interface traps though will reach approximately half
the maximum value at the voltage or energy where the trap time constant corresponds
to the frequency (ω −1 ∼ τit,Cox , see equation 2.12). If the frequency is increased traps
further away from the bands will no longer be able to respond and the C-V will shift
leading to the “frequency dependent flatband shift”.
The additional vertical frequency dispersion for the highest interface trap density
in figure 2.12 can be explained by extreme stretch-out. As the density increases the
stretch-out increases and, as a result the interface trap time constant will only change
little with voltage for the highest density (see figure 2.11). The typical capacitance
frequency characteristic obeying τ -behavior is nearly “frozen” across the highest volt-
ages where the Fermi level barely moves with voltage. This can be seen as weak
Fermi-level pinning starting to lean toward strong Fermi-level pinning. This explains
the additional decrease in capacitance with frequency for the highest densities.
Large contributions of interface traps to the C-V prevent the extraction of Vf b ,
EOT and N. The root cause is that C-Vs of weakly Fermi level pinned MOS capaci-
tors at a certain frequency have the appearance of an ideal C-V curve - although one
is measuring mostly interface trap capacitance. Frequency dependent measurements
verify whether interface traps jeopardize the correctness of the extraction. Dop-
ing extraction is very sensitive to the presence of traps since it depends on the low
depletion capacitance which is modified even for small interface trap contributions
(qDit & Cox /10). Doping extractions should be avoided when a significant amount
of interface traps are present. EOT extraction can be invalidated because the mea-
sured maximum capacitance in a trappy capacitor is higher than for an ideal MOS
capacitor with the same EOT. Interface traps are located at the interface while the
accumulation charge is located slightly away from the interface due to band bending
and quantum confinement. The difference in location of the charge changes the max-
imum observed capacitance levels and will cause EOT and Cox misinterpretations. In
case of large Dit and “frequency dependent flatband shifts” it is clear that flatband
voltage extractions are out of the question.
We have shown that the occurrence of a high density of traps (qDit > Cox ) sig-
nificantly modifies the MOS admittance characteristics and that these characteristics
are explained by Si/SiO2 MOS theory[9]. One needs to take these characteristics into
account when extracting parameters from the C-V characteristics.
34
2.5.2 Weak Inversion Regime

The influence of the interface traps on the MOS admittance in the weak inversion
regime becomes important and must be considered when interpreting the admittance
of non-Si/SiO2 MOS capacitors. The weak inversion interface trap admittance will
become significant depending on the bandgap and the nature of the traps in non-
Si/SiO2 MOS. In this subsection first MOS admittance behavior due to interface
traps in the weak inversion regime will be elaborated theoretically. This theory will
be shown to explain the Ge MOS experiments by means of modeling. This work [26]
demonstrates the presence of the weak inversion response in Ge capacitors. This pres-
ence had not been demonstrated before (an independent study on the weak inversion
response was done by [27]). The influence of temperature and capture cross section
will be elaborated as well. The impact of bandgap on weak inversion interface trap
behavior will also be discussed for Ge as well as for III-V substrates such as GaAs.
In the weak inversion regime the C-V and conductance behavior due to interface
traps becomes more complex. In the weak inversion regime interface traps can com-
municate with both the majority and minority carrier bands, as shown on the band
diagram of figure 2.15 (left). The traps can communicate with the minority carrier
band due to the proximity of the Fermi level to this band. Due to their resulting
small minority carrier time constant the traps being filled and emptied by the ac
voltage near the Fermi level can communicate with the minority band sufficiently fast
and provide minority carriers to the band. The communication of the trap with the
majority carrier band provides the electrical link of the trap to the substrate contact.
When this dual communication occurs it leads to a larger conductance response than
the typical depletion response, which is typical for Si MOS capacitors.
We will refer to the interface trap admittance contribution due to this dual commu-
nication effect as the “weak inversion response”. The presence of the weak inversion
response within the typical 1kHz - 1MHz measurement frequency window depends on
the bandgap energy, the capture cross section and the temperature. For the Si/SiO2
-interface this effect does not occur at room temperature in the 1kHz - 1MHz fre-
quency window. The effect has been shown to be present at lower frequencies for
Si [8]. For small bandgap materials, like germanium, however, the weak inversion
response will be shown to be present in the 1kHz - 1MHz window.
The contribution of an interface trap to the MOS admittance is more correctly de-
scribed by the Y-circuit shown in figure 2.15 [7][5] (center left) than by the depletion
regime circuit shown in figure 2.7. The Y-circuit description stems from the estab-
lished MOS capacitor description based on Shockley-Read-Hall theory [5][9]. The
Y-circuit description is valid in all regimes. This equivalent circuit takes into account
the communication of the trap with both the valence band (Gp ) and the conduction
band (Gn ). Expressions for the capacitance CT , the hole trap conductance Gp and
the electron trap conductance Gn are:
q2
CT = Nit f0 (1 − f0 ) (2.14)
kT
q 2 Nit f0 (1 − f0 )
Gp = (2.15)
kT τp
35
Figure 2.15: A band diagram showing the weak inversion response (top left)
and the general equivalent circuits used to model the MOS capacitor C-V and
G-V characteristics across the bandgap for an n-type capacitor. The first cir-
cuit (top right) models one trap only: Cox is the oxide capacitance, Cinv the
inversion capacitance, Cdep the depletion (and accumulation) capacitance, CT
the trap capacitance and Gn and Gp electron and hole trap conductances. For a
distribution a series of Y-circuits is used (bottom left). The third circuit (bottom
right) shows the ∆-circuit conversion of the Y-circuit (center left).
36
q 2 Nit f0 (1 − f0 )
Gn = (2.16)
kT τn
To model a distribution of traps in the bandgap Y-circuits corresponding to traps
located in energy thoughout the bandgap are added in parallel (see Figure 2.15). To
calculate the resulting MOS admittance these Y-circuits are converted to ∆-circuits
(see figure 2.15 (right)) consisting of the following elements:
Gn Gp
Ggr = (2.17)
D
CT Gp
CT n = (2.18)
D
CT Gn
CT p = (2.19)
D
Where Ggr is the generation-recombination conductance, CT n the electron trap ca-
pacitance and CT p the hole trap capacitance, D = jωCT + Gn + Gp . Note that
these are not real number capacitances and conductances but are complex (all the
other capacitance and conductances used in this work are real). For the simulations
a continuous distribution in energy of the interface traps is approximated by a set of
discrete interface trap energies. This results in a summation of Ggr , CT n and CT p :
X
Ggr,it = Ggr (2.20)
X
CT n,it = GT n (2.21)
X
CT p,it = GT p (2.22)
These admittances can then be converted to the parallel admittance YP :

(Ggr,it )jω(Cinv + Cit,T p )
YP = jω(Cit,T n + Cb ) + (2.23)
Ggr,it + jω(Cinv + Cit,T p )
To finalize, oxide capacitance is added in series to YP to obtain the MOS admittance:
(jωCox )YP
Y = (2.24)
YP + jωCox
The equations leading to equation 2.24 making use of the parallel Y-circuits are used
for the simulations of the MOS capacitors in this chapter.
Now that we have developed a theory and modeling approach it will be shown
that this theory can explain experimental Ge MOS capacitor data. A weak inversion
response shows a particular C-V and G-V characteristic as a function of frequency,
voltage and temperature. One of the typical characteristics is the frequency dispersive
”C-V-bump” shown in figure 2.16(left). This will be used to identify the nature of a
measured Ge/GeOx Ny MOS capacitor admittance as shown in figure 2.16(left). The
measurement can be modeled by a weak inversion response of a relatively low and
constant Dit (7×1011 cm−2 eV−1 ) as shown in figure 2.16 (right). At temperatures
above 300K the observed “true” inversion C-V characteristic due to inversion layer
37
“True inversion C-V

due to inversion
generation
True inversion C-V
due to inversion
midgap generation
Weak
inversion
bump
Figure 2.16: The temperature and frequency dependence of the measured n-

type Ge/GeOx Ny C-V curve (left) shows a “bump” at low frequency at lower
temperature mainly due to a weak inversion response. The curve is not corrected
for offset capacitance. Inversion generation can also be recognized, especially at
higher temperature where the “full” inversion C-V characteristic due to inversion
generation is present. This shows that the “bump” occurs in the weak inversion
and is a weak inversion response. The simulated frequency dependence of a
Ge MOS capacitor with a constant Dit (= 7×1011 cm−2 eV−1 ) at 300K (right)
and including diffusion-induced inversion generation. The simulation corresponds
to the measurement showing that the “bumps” can be explained by the weak
inversion response.
38
generation (see figure 2.16, left) clearly indicates the position of the weak inversion
regime and shows that the “C-V bump” at 300K in the measurements is located in
this regime. Moreover, the model explains the conductance as a function of frequency
and voltage at 80K and 300K (see figure 2.17, top left and right). The large difference
between the 300K and 80K G/ω is explained by the occurrence of a weak inversion
response at 300K and not at 80K. The difference between model and measurement at
80K at higher frequency is explained by series resistance which was not included in the
model. Furthermore, the model explains the temperature and frequency dependence
of G/ω (see figure 2.17, bottom). It is clear that a weak inversion response is present
in the Ge/GeOx Ny MOS capacitors.
The presence of the weak inversion response in Ge MOS capacitors has indepen-
dently been studied by another group [27] by investigating room temperature C-Vs.
However, in a next section it will be shown that the admittance characteristics of a
weak inversion and depletion response can be similar at the same temperature ne-
cessitating additional measurements other than regular C-Vs at room temperature to
assess the presence of a weak inversion response. Such additional measurements to
correctly prove the presence of the weak inversion response can be high temperature
measurements as described in the previous paragraph.
At this point we will take a more detailed look at the temperature and capture cross
section dependence of the weak inversion response. The weak inversion response is
expected to increase with increasing temperature and increasing capture cross section
because both facilitate the communication between the trap and both bands. Figure
2.18 shows a simulation of the conductance characteristic of an n-type Ge capacitor
at 300K using both the complete model adequately simulating the weak inversion
regime ( see figure 2.15) and the depletion model ( see figure 2.7). One clearly sees
that the weak inversion response induces a much larger conductance in the simulation
shown in figure 2.18 (top left). The weak inversion response conductance can be up
to an order of magnitude higher. Figure 2.18 (top right) shows the same Ge capacitor
simulated at 250K. Here one observes that the weak inversion response has become
weaker. At this temperature one can see that the weak inversion response has an
impact on the conductance around midgap. The presence of the “weak inversion
response”, the effect due to the dual communication of traps, is hence not strictly
limited to the weak inversion regime. When the temperature is further lowered to
200K the weak inversion response almost disappears. See figure 2.18 (bottom left).
Note that a midgap G/ω-peak can no longer be observed and that a weak inversion
response is still present. It has been shown that lowering the temperature reduces
the weak inversion response but also shifts the energy range of the traps observed by
their peak G/ω.
The capture cross section of traps has a large impact on the weak inversion re-
sponse. Figure 2.18 (bottom right) shows a simulation of the conductance at 300K
with a smaller capture cross section. The weak inversion response has weakened com-
pared to the 300K simulation with larger capture cross section in figure 2.18 (top
left). Influence of the weak inversion response around midgap is clear. This shows
that smaller capture cross sections induce smaller weak inversion responses. These
smaller responses can still affect G/ω characteristics of MOS capacitors with smaller
interface trap densities.
The bandgap plays a main role in the weak inversion response. Enlarging the
39
Figure 2.17: Measured parallel Gmeas /ω as a function of frequency at differ-

ent voltages at 80K and 300K for a Ge/GeOx Ny capacitor (top left). The large
Gmeas /ω peaks correspond to the C-V bumps at the same voltages. Simulation
(top right) corresponding to C-Vs of figure 2.16 explains Gmeas /ω at 80K and
300K. The measured parallel peak value of Gmeas /ω taken as a function of volt-
age and plotted as a function of temperature and frequency of the Ge/GeOx Ny
capacitor compared with simulations corresponding to the simulations in figure
2.16 (bottom). The major trends for model and measurement are the same show-
ing the consistency of the measurement data with a weak inversion response.
40
WI / no WI response Voltage [V] E-Ev [eV]

/ -0.72 0.065 2 WI / no WI response Voltage [V] E-E v [eV]
/ -0.60 0.104
/ -0.52 0.139
/ -0.42 0.223
2 -7 / -0.34 0.266
/ -0.44 0.180 10 8 / -0.26 0.309
-7 / -0.36 0.222
10 / -0.28 0.265 6 / -0.18 0.352
G/w [F/cm ]
2
/ -0.22 0.297 / -0.14 0.373
G/w [F/cm ]
6 4
2
/ -0.1 0.394
4
2
2
-8
-8 10 8
10 6
6 300 K 11 -1 -2
Dit = 3x10 eV cm 4
4 11 -1 -2 -14 -2
-14 -2 250 K Dit = 3x10 eV cm s = 4x10 cm
s = 4x10 cm
2
2 2 4 6 2 4 6 2 4 6
4 5 6 3 4 5 6
10 10 10 10 10 10 10
WI / no WI response Voltage [V] E-Ev [eV]
WI response Voltage [V] E-E v [eV] / -0.28 0.276
/ -0.24 0.351 / -0.2 0.320
/ -0.22 0.362 / -0.12 0.364
/ -0.2 0.373 2 / -0.04 0.407
/ -0.16 0.394 / 0 0.427
/ -0.12 0.415 / 0.04 0.448
G/w [F/cm ]
2
/ -0.08 0.436 -9 / 0.08 0.467

10
G/w [F/cm ]
2
/ -0.04 0.457 8
/ 0 0.478
-8 6
10
4
9
8 2
-1 -2 -14 -2 10 -1 -2 -17 -2
200 K Dit = 3x1011 eV cm s = 4x10 cm 300 K Dit= 2x10 eV cm s = 5x10 cm
-10
7
2 4 6 2 4 6 2 4 6
10 2 4 6 2 4 6 2 4 6
3 4 5 6 3 4 5 6
10 10 10 10 10 10 10 10
Frequency [Hz] Frequency [V]
Figure 2.18: Simulation of an n-type Ge MOS capacitor conductance charac-

teristic at 300K (top left) with an interface trap density of 3×1011 cm−2 eV−1 and
a capture cross section of 4×10−14 cm2 . Thick lines represent simulations using
the complete model including the weak inversion response and thin lines repre-
sent simulations using the depletion model. Simulation of the same Ge MOS
capacitor at 250K (top right). Simulation of the Ge MOS capacitor at 200K
(bottom left). Simulation of a Ge MOS capacitor conductance characteristic at
300K (bottom right) with an interface trap density of 2×1010 cm−2 eV−1 and a
small capture cross section of 5×10−17 cm2 .
41
bandgap implies weakened dual communication of a trap with both minority and
majority carrier bands resulting in a reduced weak inversion response. That is why
the weak inversion response is observed regularly for germanium capacitors (as shown
in figure 2.16, left) [28][29][30] and not at all visible for Si/SiO2 capacitors[9]. However,
the weak inversion response can in principle also occur for large bandgap materials
such as GaAs or Si for example in the 1kHz-1MHz window for lower frequencies or at
elevated temperature at which the communication between the traps and the bands
is increased. This is shown by means of a simulation of a GaAs MOS capacitor at
600K showing a weak inversion response. This simulation uses a capture cross section
of 2.1×10−13 cm2 and an interface trap density of 1.5×1012 cm−2 eV−1 . To obtain a
similar response at, for example 450K, an unrealistically high capture cross section
must be assumed. However, in special circumstances GaAs can also show such a weak
inversion response at lower temperatures than 600K. This will be treated in secion
2.8.
-7
6x10 -7
228x10
3 2.5x10 600 K
Capacitance [F/cm ]
3
2
5 373x10
3 600 K
610x10
1x10
6 Frequency [Hz] 2.0
G/w [F/cm ]
4 1000
2
1600
2700
4400
1.5 Voltage [V]
3 7200 -2
3 -1.92
12x10 -1.84
19x10
3 1.0 -1.76 -1.28
3 -1.2
2 32x10
3
-1.68
-1.6 -1.12
52x10 -1.52 -1.04
85x10
3
0.5 -1.44 -0.96
1 139x10
3
-1.36 -0.88
-0.8
0.0 2 4 6 8 2 4 6 8 2 4 6 8
-2 -1 0 1 2 10
3
10
4
10
5
10
6
Gate Voltage [V] Frequency [Hz]
Figure 2.19: A simulation of a GaAs MOS capacitor with a constant interface

trap density of 1.5×1012 cm−2 eV−1 and a capture cross section 2.1×10−13 cm2 at
600K. The typical C-V bump (left) and conductance (right) is due to a weak
inversion response.
The reduced bandgap compared to Si of materials such as Ge and InGaAs means

that the weak inversion response becomes important for 1kHz-1MHz room temper-
ature admittance measurements on MOS capacitors based on those materials. It is
now clear that the weak inversion response needs to be considered when investigating
non-Si/SiO2 interfaces and that the well established interface trap MOS admittance
model [9] explains the observed experimental characteristics of Ge MOS capacitors.
2.5.3 Interface Trap Time Constant and MOS Admittance Tem-

perature Dependence
The behavior of the interface trap time constant as a function of temperature deter-
mines in which part of the bandgap the interface traps are observable in the MOS
admittance characteristic for a specific temperature. As a result, changing the temper-
ature changes which defects in the bandgap are observable. For Si/SiO2 the interface
42
trap peaks happen to be observable at room temperature. For non-Si/SiO2 interfaces

this is not necessarily the case and the effect of the interface trap time constant should
be taken into account if one aims to characterize the interface trap density correctly.
In this section the interface trap time constant behavior and its effect on the MOS
admittance is discussed. The energy window in which traps are observable is dis-
cussed for different temperatures and bandgaps. Experimental results are explained
and used to demonstrate the importance of time constant behavior. By means of sim-
ulations the effect of the time constant on wide bandgap GaAs MOS is elaborated.
Finally the influence of the capture cross section is discussed. The contribution of the
work in this section, apart from giving an instructive overview of the implications of
the known trap time constant phenomenon [7][31], consists out of the experimental
demonstration of the possible dramatic and misleading changes in MOS admittance
behavior as a function of temperature which have not been observed before and are
caused by the time constant effect [26].
The interface trap time constant was introduced in section 2.5.1 and equation
2.9. The concrete consequences of the exponential increase of the time constant with
decreasing temperature and increasing trap to majority-carrier-band energy will be
elaborated.
In section 2.5.1 it was shown that the interface trap admittance (Git + jωCit )
shows τ -behavior. In figure 2.20 interface trap admittance is shown as a function of
frequency (left) together with the interface trap time constant characteristic (right)
represented as the interface trap time frequency (fit = 1/2πτit ) as a function of
energy in the bandgap. The vertical line shows the position of the Fermi level bias
used for the interface trap admittance plot. The interface trap frequency causes the
peak frequency of G/ω (= fit ) and the capacitance slope to be located within the
1kHz-1MHz window. One is hence able to measure the peak conductance and the
frequency dispersion in the capacitance. These tell-tale signs of traps will be used to
consider a trap observable. The observable range is also indicated in the interface trap
frequency characteristic (right). For a different position in the bandgap (see figure
2.21) the interface trap frequency shifts out of the observable range due to the strong
trap energy dependence of the time constant and the peak G/ω and capacitance
frequency dispersion are no longer measurable. One observes little conductance and
the capacitance shows no frequency dispersion. If one changes the temperature the
interface trap frequency changes exponentially. In figure 2.22 the temperature has
been lowered to 210K and the interface trap frequency has decreased and is within
the observable range. It is clear that trap energy and temperature have a strong
influence on which traps are observable and which are not.
As a result of the strong temperature and energy dependence of the interface trap
time constant only traps in a certain part of the bandgap are observable at a specific
temperature. This is shown in figure 2.23 which shows the interface trap frequency
as a function of energy at different temperatures. At each temperature the interface
trap frequency is within observable range for only a limited energy span for holes
and electrons. As the temperature is decreased the interface trap frequency decreases
and the observable energy windows shift toward the band edges. The observable
energy window for Ge and GaAs is shown in figure 2.24. For materials with a larger
bandgap than Ge, like GaAs, a wider temperature range is needed to shift the window
across the bandgap. For higher temperatures traps located nearer to midgap become
43

9
-7 10
G/w or Capacitance [F/cm ]
8x10
2
8
10
7 300 K 300 K
6 Cit 10
6
10
+ -
5
10 h e
4
4 Fermi-level bias
10
Git/w 3
2 10
2
10
1
0 10
10
1
10
3
10
5
10
7
10
9 0.0 0.2 0.4 0.6
Frequency [Hz] Valence band offset E-E v [eV]
Figure 2.20: Calculated interface trap admittance characteristic (left) corre-

sponding to the interface trap frequency (right) at the indicated Fermi level posi-
tion (vertical line). The hole and electron interface trap frequency (= 1/(2πτit ))
depend exponentially on trap energy (right). The non-shaded zones (left and
right) indicate the measurable range: 1kHz-1MHz. For the Fermi level posi-
tion represented in these two plots the G/ω-peak and capacitance dispersion fall
within the observable range and the traps are considered observable. The lightly
shaded areas in the interface trap frequency characteristic show the part of the
bandgap in which interface traps are observable at 300K.
9
-7 10
2
8x10
8
10
Cit 7 300 K 300 K
6 10
6
10
+ - Fermi-level bias
4
5
10 h e
4
10
3
2 Git/w 10
2
10
1
0 10
10
1
10
3
10
5 7
10
9
10 0.0 0.2 0.4 0.6
Figure 2.21: Calculated interface trap admittance (left) corresponding to the

interface trap frequency (right) at the indicated Fermi level position closer to
the band edge (vertical line). For this changed Fermi level position compared to
figure 2.20 the G/ω-peak and capacitance dispersion fall outside the observable
range and the traps are considered unobservable at 300K.
44

9
-7 10
8x10
2
8
10
7
6 Cit 10
210 K 210 K
6
10
5
4 10
+ -
4
10 h e
Git/w 3
2 10
2
10
1
0 10
10
1
10
3
10
5
10
7 9
10 0.0 0.2 0.4 0.6
Figure 2.22: Same plot as in figure 2.21 but at a lower temperature. The
interface trap frequencies have decreased and the traps at the Fermi level position
have become observable again.
observable while for lower temperature traps more located toward the band edges
become observable.
Note that for similar capture cross sections as in figure 2.24 the distance of the
window to the band edges is similar for Si and GaAs at each temperature. This
is because traps located at the same energy distance from a band, and with similar
capture cross section but for different semiconductors have time constants not differing
by more than an order of magnitude. This is because the effective density of states
does not vary significantly from semiconductor to semiconductor. The temperature
at which traps near midgap are observable becomes higher with increasing bandgap
value.
Experiments on Si-passivated germanium samples with a SiO2 /HfO2 dielectric
stack clearly show that the interface trap time constant behavior can give rise to
dramatic effects. These experiments show the importance of the awareness of these
effects for assessing interface trap density. Figure 2.25 shows C-V measurements of
Si-passivated Ge MOS structures at 80K (top left) and 300K (top right). At 300K, the
C-V characteristics barely show any frequency dispersion and one could erroneously
conclude that the interface is of an excellent quality. At 80K, however, the measure-
ments show a totally different picture. A large amount of frequency dispersion is
visible in the form of a “frequency dependent flatband shift” showing the presence of
large amounts of interface traps. The simulations in figure 2.25 (middle and bottom)
show that this effect can be explained by interface trap MOS theory using a dominant
density of interface traps near the conduction band edge. This effect occurs because
only the trap time constant of near-midgap traps lays within the observable range
at room temperature while at 80K the trap time constant of the band edge traps
with a much higher density lays within the observable range. The interface trap time
constant is very important and needs to be taken into account. When the interface
traps are dominant and unobservable the C-V can be free of frequency dispersion and
be very similar to an ideal C-V, while in fact most of the capacitance can be due to
interface traps.
For wide bandgap semiconductors such as GaAs the same effects can occur as
45

9
10
8
10
7 300 K 300 K
10
210 K 210 K
6
10
5 140 K 140 K
10
+ -
4
10 h e
3
10
2
80 K 80 K
10
1
10
0.0 0.2 0.4 0.6
Figure 2.23: Calculated interface trap frequency as a function of energy in
the bandgap for different temperatures for Ge. The capture cross section is
1×1015 cm2 . The darkly shaded areas indicate the unobservable range. The
lightly shaded areas indicate which part of the bandgap is observable at each
temperature.
Figure 2.24: The calculated energy ranges at which traps are visible as a
function of temperature for Ge(left) and GaAs (right).
46
-6 -6
2.5x10 2.5x10
]
Capacitance [F/cm ]
2
2
Capacitance [F/cm
2.0 2.0
1.5 1.5
1.0 1.0
Frequencies
Frequencies
0.5 0.5 8k ® 1.6M
8k ® 1.6M
300 K
80 K
0.0 0.0
0.4 0.6 0.8 1.0 1.2 1.4 0.4 0.8 1.2
-6
2.5x10 -6
Frequencies 2.5x10
Capacitance [F/cm ]
2
2.0 1k ® 1M Frequencies
80 K
Capacitance [F/cm ]
2.0
2
1k ® 1M
1.5 300 K
1.5
1.0
1.0
0.5 0.5
0.0 0.0
-0.5 0.0 0.5 1.0 1.5 -0.5 0.0 0.5 1.0 1.5
-6 -6
10 10
300 K
-7 -7
10 10
G/w [F/cm ]
2
G/w [F/cm ]
2
-8 -8
10 accumulation 10
-9 -9
10 10
80 K midgap
-10 -10
10 2 4 6 2 4 6 2 4 6 10 2 4 6 2 4 6 2 4 6
3 4 5 6 3 4 5 6
10 10 10 10 10 10 10 10
Figure 2.25: Experimental C-V of an n-type Si-passivated Ge MOS structure at

80K (top left) and at 300K (top right). A large frequency dispersion is observed
at 80K while not at 300K. Simulations of C-V at 80K (middle left) and at 300K
(middle right) and G/ω at 80K (bottom left) and 300K (bottom right) reproduce
the observed behavior. The simulation makes use of a large, dominant density of
interface traps causing weak Fermi level pinning near the conduction band edge.
It is clear that the large density of interface traps is observable only at 80K and
the 300K data can be easily mistaken for a C-V of a nearly ideal MOS capacitor.
The “pseudo-accumulation capacitance” at 300K is in fact due to interface traps.
47
for Ge at low temperature. This is illustrated in figure 2.26. At 300K (right) no

frequency dispersion in the C-V is observed while at 80K (left) a very large frequency
dispersion is visible. This can be the case for all semiconductors. For interface traps
with a capture cross section of 1×10−15 cm2 traps closer than ∼200meV to the band
edges are unobservable at room temperature for most semiconductors.
-7
6x10 Frequencies: -7
Frequencies:
6x10
Capacitance [F/cm ]
2
1k ®1MHz 1k ®1MHz
Capacitance [F/cm ]
2
5 80K 5 300K
4 4
3 3
2 2
1 1
-2 -1 0 1 2 -2 -1 0 1 2
Figure 2.26: A simulation of an n-type GaAs MOS capacitor C-V with a

large density of interface traps near the conduction band at 80K (left) and 300K
(right). At 300K the C-V can be easily mistaken for an ideal C-V.
For materials with a wide bandgap, such as GaAs, midgap traps are expected
to be unobservable at room temperature [32]. In figure 2.27 the effect of the time
constant on the observability of midgap traps is illustrated by means of simulations.
For this GaAs case, interface traps near midgap cannot be observed in the C-V (top
left) and G/ω (top right) at 300K because of the large trap time constants for midgap
traps in the large bandgap. At higher temperatures (600K) the traps near midgap
become observable both in the capacitance (bottom left) and conductance character-
istics (bottom right). Midgap traps can clearly be “cloaked” by the interface trap
time constant effect too.
The observability of the interface traps does not only depend on the temperature,
and the energy and bandgap but also on the capture cross section. The capture
cross section of traps can vary over orders of magnitude and is important. The
capture cross section can vary with changing temperature. One will have to take this
effect into account when varying the temperature to extract interface trap density
across the bandgap (see next chapter). The following relation is used for temperature
dependence:
∆Eb −∆Eb
σ = σ300K exp exp (2.25)
k300 kT
Where ∆Eb is the “barrier to thermal capture” which describes the temperature
dependence. σ300K is the capture cross section at 300K. In figure 2.28 the influence
of the capture cross section on the observability of the traps is shown for GaAs
MOS. First of all, the magnitude of the capture cross section clearly has a large
influence on which traps are observable at which temperature. Midgap traps are
observable at 350K for a capture cross section of 1×10−12 cm2 (figure 2.28, top left)
48
-8
-7 300 K 4x10
5x10
Frequency [Hz]
Capacitance [F/cm ]
2
1000 3
4 2700
G/w [F/cm ]
300 K
2
7200 Voltage [V]
3
19x10 -0.280
3 52x10
3
2 -0.200
3 -0.120
139x10
3 -0.040
2 373x10
6 0.040
1x10 1 0.120
0.200
1
0
2 4 6 2 4 6 2 4 6
-2 -1 0 1 2 3 4 5 6
10 10 10 10
-7
6x10 -7
2.5x10 600 K
600 K
Capacitance [F/cm ]
Voltage [V]
2
5 Frequency [Hz] -2
1k 2.0 -1.84
G/w [F/cm ]
-1.68
2
1.6k -1.52
4 2.7k -1.36
4.4k
7.2k 1.5 -1.2
-1.04
12k -0.96
3 19k -0.88
32k 1.0
52k -0.8
85k -0.72
2 139k -0.64
228k 0.5 -0.56
373k -0.48
611k -0.4
1 1M
0.0
2 4 6 2 4 6 2 4 6
3 4 5 6
-2 -1 0 1 2 10 10 10 10
Figure 2.27: Simulation of an n-type GaAs MOS C-V (top left) and G/ω
(top right) are shown at 300K. The large interface trap peak near midgap is not
observable as no frequency dispersive capacitance nor conductance is observable
near midgap. A peaked interface trap density of 2.2×1013 cm−2 eV−1 is located
0.45 eV above the valence band. At 600K, C-V (bottom left) and G/ω (bottom
right) are shown. The large interface trap peak near midgap is now observable
as a frequency dispersive capacitance.
49
and are only observable at temperatures larger than 600K for a capture cross section
of 1×10−18 cm2 (figure 2.28 top right). The influence of the temperature dependence
of the capture cross section is most pronounced at low temperatures. A negative
Eb (figure 2.28, bottom right) shifts the windows toward midgap, which can make
observing the traps closest to the band edges impossible. The window shifts toward
the band edges for positive Eb (figure 2.28 bottom left). The effect of the capture cross
section can be significant and should be kept in mind when interpreting admittance.
Valence band offset E-E v [eV] Valence band offset E-E v [eV]
1.4 1.4
-12
1.2 s=1x10 1.2
-18
s=1x10
1.0 electrons 1.0
e- min. E
min. E
0.8 max. E 0.8 max. E
holes h+ max. E
0.6 max. E 0.6 min. E
min. E bandgap
0.4 bandgap 0.4
0.2 0.2
0.0 0.0
100 200 300 400 500 600 100 200 300 400 500 600
Temperature [K] Temperature [K]
1.4
1.4
1.2 -15
1.2 -15 s=1x10
s=1x10 1.0 Eb= -100 meV
1.0 Eb= 200 meV e- min. E
e- min. E 0.8 max. E
0.8
max. E 0.6
h+ max. E
0.6 h+ max. E min. E
min. E 0.4 bandgap
0.4 bandgap
0.2
0.2
0.0
100 200 300 400 500 600 100 200 300 400 500 600
Temperature [K] Temperature [K]
Figure 2.28: Energy windows in which the interface traps are observable de-
pending on capture cross section and its energy dependence for GaAs. The
window for a large capture cross section (top left) shows large differences with
the window of a small capture cross section (top right). The window for a cap-
ture cross section with a temperature dependence described by Eb = 200meV
(bottom left) is mainly different from a window with Eb = −100meV (bottom
right) at low temperature.
The dependence of the interface trap admittance contribution on the interface

trap time constant can have a large effect on parameters extracted from the MOS ad-
mittance. Obviously the interface quality evaluation will be affected as only a certain
fraction of the traps at a certain temperature are observable. The capacitance due to
interface traps can have the appearance of a plausible regular accumulation MOS C-V
without any frequency dispersion. The occurrence of such a “quasi-accumulation” C-
V can lead to erroneous flatband, EOT and doping extractions from C-V. One needs
to measure at lower temperatures to verify if this effect is present since no frequency
50
2.6 Inversion Generation
dispersion will be present at room temperature.
2.6 Impact of Inversion Generation on MOS Admit-

tance Behavior
The generation of inversion layers in MOS capacitors during an HF admittance mea-
surement has a significant effect on the MOS admittance characteristics and should
be taken into account.
In order for inversion layers to respond to the ac signal of the admittance mea-
surement equipment minority carriers need to be supplied to the inversion layer. This
can occur by means of several mechanisms: by diffusion, by generation-recombination,
and induced by a nearby source of minority carriers such as an inversion layer induced
by semiconductor surface charge surrounding the measured structure [9]. Sufficient
presence of inversion generation will make the “true” inversion C-V characteristic
become visible. Typical C-V and G-V characteristics where inversion generation is
present are shown in figure 2.29 (top left and right). The characteristic shows τ -
behavior. Note that the time constant decreases away from accumulation, similar as
for series resistance behavior. The trap time constant shifts by the same amount as
the inversion capacitance changes, similar as for series resistance.
For smaller bandgap semiconductors or higher temperatures the diffusion-induced
inversion generation component becomes more important. In the diffusion case mi-
nority carriers diffuse from the bulk generating charges for surface inversion at the
MOS interface (for Ge, see [33]). The admittance contribution associated with this
effect is referred to as the “diffusion-induced inversion response”. This response in-
creases with increasing intrinsic carrier concentration (ni ), which is much larger for
Ge as compared to Si. In general the admittance contribution due to inversion gen-
eration, not only due to diffusion [9], will be referred to as the “strong inversion
response”. The diffusion-induced inversion response is modeled by inserting a con-
qµ n2
ductance, Gd = (LppNDi ) into the circuit modeling the MOS capacitor [9](see figure
2.29, bottom left). Gd models the temperature dependent supply of carriers to the
inversion layer. Other sources of inversion generation can be modeled by adding
admittance in parallel to Gd [9].
The generation-recombination induced inversion response occurs because of gen-
eration of minority carriers through bulk semiconductor traps in the depletion layer.
This type of generation is more prominent at lower temperatures than the diffusion-
induced generation. Inversion generation can also be caused by an inversion layer
surrounding the MOS capacitor, which can be present at low temperatures. The in-
version response can hence occur in a wide temperature range. The diffusion-induced
inversion response is shown to be present in the Ge/GeOx Ny capacitors by mak-
ing use of an Arrhenius plot [33] of the conductance (figure 2.29, bottom right).
Diffusion induced inversion response gives rise to an activation energy (Ea ) of Eg ,
while for generation-recombination induced inversion Ea = Eg /2. The presence of
diffusion-induced inversion generation is indicated by Ea = 0.42eV > Eg /2 in figure
2.29 (bottom right). A mixture of diffusion induced and generation-recombination
induced responses is present.
Inversion generation can have a large influence on MOS admittance characteristics
51
-7
-7 2.5x10
5x10 300 K
300 K
Capacitance [F/cm ]
2
Gate voltage [V]

2.0 -2
4 Frequency [Hz]
G/w [F/cm ]
-1.2
2
1000 -1
12x10
3 -0.88
3 1.5 -0.76
3 19x10
3
-0.64
32x10 -0.52
3 -0.44
52x10 1.0
3 -0.36
2 85x10
4
-0.28
14x10
4
23x10
37x10
4 0.5
1 1x10
6
0.0
2 4 6 2 4 6 2 4 6
3 4 5 6
-2 -1 0 1 2 10 10 10 10
0.001
9 n-type Ea = 0.423
8 p-type Ea = 0.436
G [S/cm ]
7
2
Cox CT Cs 6
Cinv Gn
Gp 3
-3
2.8 3.0 3.2x10
Gd 1/T [1/K]
Figure 2.29: Simulation of C-V (top left) and G/ω of an n-type Ge MOS
capacitor without interface traps and series resistance but with diffusion-induced
inversion generation added. Frequency dispersion is observed in the inversion
and weak inversion regime. Equivalent circuit modeling the diffusion-induced
inversion response with Gd (bottom left). Arrhenius plot (bottom right) of the
measured conductance at 100kHz and -1.4 V (300-378K) of a Ge/GeOx Ny MOS
capacitor and the extracted activation energies showing the presence of both
diffusion-induced inversion and generation-recombination induced inversion.
52
2.7 Other Contributions
in the weak and strong inversion regimes by adding additional conductance and should
be taken into account when determining the interface trap density.
2.7 Impact of Other Contributions on MOS Admittance

In this section several effects will be elaborated which can also affect the MOS ad-
mittance and related parameter extraction. The Maxwell-Wagner effect, the quasi-
accumulation layer effect, interface dipoles, semiconductor bulk traps, oxide bulk
traps, and the steady state non equilibrium deep depletion effect will be treated.
In literature “exotic” sources of frequency dispersion can be found such as the
Maxwell-Wagner [34], the quasi-accumulation [35] and the interface dipole effect [9].
These “exotic” effects, which have not been observed in Ge/III-V capacitors in this
work, show that frequency dispersion in a Ge/III-V MOS C-V does not necessarily
mean that series resistance, inversion generation or an interface trap issue is present.
The latter is usually the case for silicon MOS. In the next chapter a technique will
be introduced to separate interface traps from other sources of frequency dispersion
in MOS capacitors.
2.7.1 Dielectric Effects

The dielectric constant of the insulator is not expected to show dispersive behavior
in the frequency range used for HF C-V measurements (1kHz - 1MHz) nor for higher
frequencies [36]. Some dispersive phenomena in dielectrics, though, can be observed
in that same frequency range. The Maxwell-Wagner effect [37] is an interfacial po-
larization effect and can occur when an interface between two different dielectrics
is present in the gate insulator. It has been observed for Ga2 O3 - Gdx Ga0.4−x O0.6
dielectrics [34] and influences parameter extractions from admittance measurements.
To describe the Maxwell-Wagner effect the oxide capacitance is replaced by an
oxide admittance (Gox +jωCox ) with the following components (see figure 2.30, center
left):
· ¸
ε0 κ0s + κ0∞ 0
Cox (ω) = + κ∞ (2.26)
d (τM W ω)2 + 1
· ¸
Gox (ω) ε0 (κ0s + κ0∞ )ωτM W σ
= + (2.27)
ω d (ωτM W )2 + 1 ω
ε0 ε0 σ
Where κ0∞ = ( d1 /εd/ε 0
1 +d2 /ε2
), σ = ( d1 /σd/ε 0
1 +d2 /σ2
), and τM W = ( κ0 1σ11 σ2 ). κ0s is the static
∞
0
dielectric constant and κ∞ is the optical dielectric constant of the two layer dielectric
stack of which the thicknesses are d1 and d2 , of which the conductivities are σ1 and
σ2 and of which the dielectric constants are ε1 , and ε2 . d is the total thickness of the
stack. Apart from the conductivity term in equation 2.27 the frequency dispersion is
described by τ -behavior. The time constant, τM W , is independent of voltage. The
Maxwell-Wagner effect results in a change of maximum measured MOS capacitance
with frequency and in a conductance contribution. This effect is rarely observed in
MOS capacitors but can influence parameter extraction from MOS admittance.
53
Cox( ) Cox Cox

G( )
Cdip( )
Cp( )
Gox( )
C( ) Cs
Gp( ) Gdip( )
Cs
Figure 2.30: Equivalent circuits for the as measured MOS capacitance (left),
of an MOS capacitor showing the Maxwell-Wagner effect (center left), of an
MOS capacitor showing a quasi-accumulation layer (center right) and of an MOS
capacitor with dipoles at the oxide-semiconductor interface(right).
2.7.2 Quasi-Accumulation Layer and Dipoles

Some authors have proposed other effects to explain frequency dispersion observed in
GaAs MOS capacitors. Quast [35] showed that the occurrence of a quasi-accumulation
layer can cause frequency dispersion. The quasi-accumulation layer and the occur-
rence of a potential barrier near the interface is due to deep-lying acceptor like impu-
rity levels near the GaAs-insulator interface (n-type is considered in this case) which
induce the potential barrier. The quasi-accumulation layer effect can be described by
the following equations for an n-type capacitor [35]:
qµnm 1
Cp (ω) = Cs + A √ √ (2.28)
2Dn ω
Gp (ω) qµnm √
= A√ ω (2.29)
ω 2Dn
Where nm is the equilibrium electron density at the potential barrier, and Dn is the
electron diffusivity. The conductance behavior with the oxide capacitance added is
given by (see figure 2.30, center right):
√ 2
G(ω) ωCox a
= √ (2.30)
ω ω(Cox + Cs ) + 2(Cox + Cs )a ω + 2a2
2
qµnm
where a = A sqrt2D n
. Unlike the previous Gmeas /ω characteristics this effect does not
show a maximum of G/ω as a function of frequency. When a conductance peak is
observed the dominance of this effect can be excluded.
Another possibility for the occurrence of frequency dispersion in MOS capacitance
measurements is the presence of dipoles at the GaAs-insulator interface [9]. This leads
to a dipole admittance (Gdip + jωCdip ) showing τ -behavior [9] (see figure 2.30, right).
If the dipole density is relatively low the oxide capacitance in series with the parallel
semiconductor capacitance and dipole admittance results in a partial τ -behavior, no
longer described by equations 2.3 and 2.4. In general the time constant τdip will
decrease little (less than an order of magnitude) when the bias is swept from inversion
to accumulation.
54
2.7 Other Contributions
2.7.3 Semiconductor Bulk Traps
Semiconductor bulk traps are also known to cause a frequency dispersive capacitance
and a conductance contribution [9]. Bulk traps are present in very small quantities
in today’s semiconductor substrates (<1×1012 cm−3 ) and hence the admittance con-
tribution is negligible in an MOS admittance measurement. When introducing new
processing, like the deposition of films, the presence of introduced bulk traps can
be suspected. The possible presence of this effect can be checked by doing DLTS
measurements (see chapter 4). The bulk traps are also responsible for the generation-
recombination leading to inversion generation (see section 2.6).
2.7.4 Oxide Charge Trapping
Oxide bulk traps are too slow to be observed in the conductance of HF admittance
measurements (1kHz - 1MHz) discussed here. Trapping in the oxide is known to cause
hysteresis or flatband instabilities and stretch-out in C-V characteristics with high-κ
materials [38]. The influence of charge trapping in the dielectric on the frequency
dependence of HF conductance and capacitance can be ruled out by making sure
that the amount of charge trapped in the oxide at each voltage does not vary from
sweep to sweep when varying the frequency. This can be verified easily by repeating
(not reversing) the same sweep without changing the frequency. Verifying that the
stretch-out due to charge trapping stays the same from sweep to sweep reduces the
influence of the oxide charge trapping to an additional stretch-out of the C-V.
2.7.5 Steady State Non-Equilibrium Deep Depletion
An effect called steady state non equilibrium deep depletion (SSDD) has been re-
ported for GaAs MOS capacitors [39]. It occurs when the gate leakage is sufficiently
large. High gate leakage can occur either due to the limited bandgap of the insulator,
tunneling currents or by defect assisted leakage currents. To accommodate for the
leakage while the Fermi level is pinned the bands have to bend and the semiconductor
is forced into a non-equilibrium deep depletion. SSDD occurs as a result of a com-
bination of gate leakage and Fermi level pinning which results in a modulated C-V
instead of a nearly constant C-V, typical for (strong) Fermi level pinning.
This effect will not affect the investigation of weak Fermi level pinning. The often
observed frequency dependent flatband shift, typical for weak Fermi level pinning,
can only be observed if the capacitor is not strongly pinned and if the capacitance is
dominated by carriers emitted from and captured by interface traps. For weak Fermi
level pinning the interface trap capacitance dominates the depletion capacitance so
the occurrence of deep depletion will not have a large influence on the observed
capacitance.
55
2.8 Similarities in Admittance Characteristics of MOS

Capacitors with Different Interface Trap Distribu-
tions
Two MOS capacitors with different interface trap distributions can have similar ad-
mittance characteristics as a function of frequency and voltage. This is an important
issue when interpreting admittance characteristics to determine the interface trap
density.
A weak inversion response of interface traps can be very similar to a depletion re-
sponse of a larger peaked interface trap density near midgap. The potential similarity
between an admittance characteristic as a function of both voltage and frequency [26]
has not been demonstrated before. The similarity is shown by comparing the sim-
ulations in figure 2.31 with simulations corresponding to the measurements of the
Ge/GeOx Ny MOS capacitor shown in figures 2.16 and 2.17. On the left hand side
of figure 2.31 C-V (top), G/ω(middle) and Dit (E) (bottom) are shown of a weak
inversion response and on the right hand side C-V (top), G/ω(middle) and Dit (E)
(bottom) are shown of a depletion response of a peaked and higher trap density.
It is clear that C-V and conductance characteristics are similar and can easily be
confused. The similarity stems from the larger conductance contribution of a weak
inversion response then of a depletion response for the same amount of traps. The
similarity also stems from the stretch-out due to the midgap interface trap peak for
the depletion response case. Stretch-out makes a depletion response of a midgap
trap peak occur at similar voltages as a weak inversion response. One can notice a
difference in the sharpness of the capacitance peak in the simulations. Introducing
stretch-out and surface potential fluctuations into the simulations can make the char-
acteristics even more similar. We emphasize that the similarity is qualitative and can
lead to quantitative large errors in the extraction of Dit with the conductance method
by erroneously misinterpreting the weak inversion response as a depletion response.
The stretch-out in combination with the similar admittance contribution explains the
possible misinterpretation of the weak inversion response as a depletion response and
vice versa.
The similar characteristics due to the different trap densities in figure 2.31 at 300K
can be distinguished by measuring at higher temperature (see figure 2.32). By raising
the temperature to 380K inversion generation becomes stronger and the inversion C-
V characteristics, nearly free of frequency dispersion, appear for the weak inversion
case (figure 2.32, left). For the depletion response case the frequency dispersive C-V
“bump” remains visible (figure 2.32, right).
One could wonder if the similar characteristics of figure 2.31 could be separated
by measuring at lower temperature. Low temperature simulations are shown in figure
2.33. It is observed that the qualitative similarity remains. Both the weak inversion
response and the depletion response weaken. By measuring at lower temperature (or
at higher temperature) one shifts the energy window in which the traps are observ-
able. This also explains the weakened depletion response at low temperature. At low
temperature one cannot measure the midgap interface trap peak clearly observed at
300K and at 300K it is indistinguishable from a weak inversion response. The simi-
larity is an issue for the interpretation of the MOS admittance in terms of interface
56
2.8 Similarities in Admittance
-7 -7
5x10 Frequencies 5x10 Frequencies:
Capacitance [F/cm ]
1kHz ® 1MHz 1kHz ® 1MHz

2
Capacitance [F/cm ]
2
4 300K 4 300 K
3 3
2 2
1 1
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 -1.0 0.0 1.0
-7 -7
1.4x10 1.2x10
-0.7 V 300K 300 K
Conductance [F/cm ]
1.2
2
1.0
G/w [F/cm ]
1.0 -0.88 V
2
0.8
0.8 -0.25 V 0.6
0.6 0V
0.4
0.4
0.2 0.2
0.0 0.0
2 4 6 2 4 6 2 4 6 2 4 6 2 4 6 2 4 6
3 4 5 6 3 4 5 6
10 10 10 10 10 10 10 10
13
1.0x10 1.0x10
13
0.8
Dit [eV cm ]
Dit [eV cm ]
0.8
-2
-2
0.6 0.6
0.4 0.4
-1
-1
0.2 0.2
0.0 0.0
0.0 0.6 0.0 0.6
Figure 2.31: Simulation of the C-V (top left) and conductance (middle left) at
300K of a weak inversion response of interface traps for a Ge MOS capacitor with
a constant interface trap density of 7×1011 cm−2 eV−1 (left bottom). Simulation
of the C-V (top right) and conductance (middle right) at 300K of a depletion re-
sponse of a peaked interface trap distribution for a Ge MOS capacitor with a peak
density of 8×1012 cm−2 eV−1 (bottom right). Left and right hand characteristics
are clearly similar.
57
-7
-7
5x10 5x10
Capacitance [F/cm ]
Capacitance [F/cm ]
380 K
2
2
4 4 Frequency [Hz]
1000
2700
3 380 K 3 7200
3
Frequency [Hz] 19x10
1000
2 4 2 52x10
3
37x10 4
4 14x10
61x10 4
1 1x10
6 1 37x10
6
1x10
0 0
-1.0 0.0 1.0 -1.0 0.0 1.0
Figure 2.32: Simulation of the C-V at 380K at different frequencies (left)

corresponding to the 300K simulation shown in figure 2.31 (left). The weak
inversion interface trap response disappears at this temperature and is replaced
by a strong inversion response. This shows that the frequency dispersive “bump”
in the C-V at room temperature is due to a weak inversion response. Simulation
of the C-V at 380K at different frequencies (right) corresponding to the 300K
simulation shown in figure 2.31 (right). The frequency dispersive capacitance
due to the interface trap peak remains observable at this temperature.
trap density.
The issue of MOS admittance similarity with different interface trap distributions
also occurs for wider bandgap materials like GaAs. When the bandgap becomes
wider, the weak inversion response occurs at higher temperatures or for larger capture
cross sections. An example is given in figure 2.19 which shows the capacitance and
conductance characteristics of a weak inversion response of traps at 600K which is
similar to the depletion response admittance characteristics of a peaked interface trap
density represented in figure 2.27 at 600K.
Another example for GaAs is given in figure 2.34 in which measurements are
shown of a GaAs MOS C-V at 300K (left) and 423K (right). The additional feature
appearing at 150C could be attributed to a depletion response of traps near midgap.
Since these traps are too slow at room temperature one needs to heat the sample up
to be able to observe the traps in the C-V due to the time constant effect. Could this
also be a weak inversion response?
To obtain a weak inversion response at 423K similar in magnitude to the one
in figure 2.19 at 600K one needs unrealistically large capture cross sections. Most
likely a weak inversion response is not present but a weak inversion response cannot
be completely excluded. For GaAs a defect band [24] near the conduction band
can effectively raise the perceived capture cross section to such large dimensions by
effectively lowering the conduction band edge. In this case the trap is communicating
with the defect band instead of the conduction band which decreases the energy
difference between trap and “band edge” (see figure 2.35). This in turn decreases the
interface trap time constant. When situating the trap in the bandgap, without taking
into account the defect band, the effective capture cross section is perceived to be
unrealistically large. The following equations, derived from equation 2.9 describe the
58
-7 -7
5x10 Frequencies 5x10 Frequencies
1kHz ® 1MHz 1kHz ® 1MHz
Capacitance [F/cm ]
Capacitance [F/cm ]
2
2
4 250K 4 250K
3 3
2 2
1 1
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
-0.475 V 250K -8
-0.45 V 250 K
-8 2.5x10 -0.15 V
4x10
-0.125 V 2.0
G/w [F/cm ]
3
2
G/w [F/cm ]
2
1.5
2
1.0
1 0.5
0 0.0 2 4 6 8 2 4 6 8 2 4 6 8
2 4 6 8 2 4 6 8 2 4 6 8
3 4 5 6 3 4 5 6
10 10 10 10 10 10 10 10
Figure 2.33: Simulation of the C-V (top left) and conductance (bottom left)
at 250K of a weak inversion response of interface traps for the Ge MOS capacitor
with a constant interface trap density of 7×1011 cm−2 eV−1 . Simulation of the
C-V (top right) and conductance (bottom right) at 250K of a depletion response
of a peaked interface trap distribution for the Ge MOS capacitor with a peak
density of 8×1012 cm−2 eV−1 . Left and right hand characteristics clearly remain
qualitatively similar.
-7 -7
7x10 8x10 Frequencies 1kHz → 1 MHz
Capacitance [F/cm ]
Frequencies 1kHz → 1 MHz

2
Capacitance [F/cm ]
2
6 7
6
5
5
4
4
3
3
2
2
-1.0 0.0 1.0 -1.0 0.0 1.0
Figure 2.34: Measured C-V at 300K (left) and at 423K (right) of an n-type
GaAs MOS capacitor. Logarithmically plotted frequencies are chosen in the
1kHz-1MHz range.
59
interface trap time constant in case of a defect band:

τit = [vth σNef f exp(−q∆Etrap−db /kT )]−1 (2.31)
This can be reworked as:
τit = [vth σef f Nef f exp(−q(∆Etrap−db + Edb )/kT )]−1 (2.32)
where the effective capture cross section σef f = σ exp qE

kT and depends on tempera-
db
ture. Edb is the defect band width , and Etrap−db the trap to defect-band distance.
σ is the true capture cross section of the trap. It is clear that the effective capture
cross section can be much larger than the true capture cross section.
Defect band
Edb
e- DEtrap-db e-
Fermi-level Fermi-level
traps traps
Figure 2.35: Illustration of the effect of a defect band on the interface trap time
constant. In the situation without defect band (left) the energy gap between the
trap and the conduction band is large and consequently the interface trap time
constant is large. In the situation with defect band (right) the trap communicates
with the defect band instead of the conduction band. The energy gap between
the trap and the defect band is smaller and as a result the interface trap time
constant is also significantly smaller.
The use of the defect band concept gives rise to the simulated characteristics shown
in figure 2.36. On the left hand side of the figure one sees the 300K C-V (top) and
450K C-V (middle) of a weak inversion response (responsible for the frequency disper-
sive capacitance at low voltages at high temperature) and a depletion response of a
large acceptor trap peak (responsible for the frequency dispersive capacitance at high
voltages). The large peak communicates with a 0.48 eV wide defect band extending
to the conduction band. The Fermi level is forced to energies below the acceptor
peak. The true capture cross section is 1×10−14 cm2 . At 450K the effective capture
cross section is 2×10−8 cm2 . On the right hand side of the figure one sees a 300K C-V
(top) and 450K C-V of a depletion response of a large donor trap peak (responsible
for the frequency dispersive capacitance at low voltages at high temperature) and a
large acceptor trap peak (responsible for the frequency dispersive capacitance at high
voltages). The Fermi level is forced in between the donor and acceptor peaks. In this
case a defect band was used to allow the peaks to be in the lower half of the bandgap
but the peaks can be shifted up in energy simultaneously while adjusting capture
cross section to obtain the same result since the minority carrier band does not play
60
a role. The modeled admittance characteristics are qualitatively similar and resemble
the measured characteristics (see figure 2.34). The modeled characteristics are due
to entirely different trap distributions. This shows that it is theoretically possible
that weak inversion-depletion similarity issues occur for GaAs MOS at temperatures
of 450K.
Frequencies 1kHz ® 1 MHz

-7 -7 300K
6x10 6x10
300 K
Capacitance [F/cm ]
Capacitance [F/cm ]
2
2
4 4
2 2
-1.0 0.0 1.0 -1.0 0.0 1.0
-7
-7 7x10
7x10
Capacitance [F/cm ]
2
Capacitance [F/cm ]
6
2
6
5 5
4 4
3 3
450K
2 450 K 2
1 1 Frequencies 1kHz ® 1 Mhz
-1.0 0.0 1.0 -1.0 0.0 1.0
14 14
2.0x10 4x10
Dit [cm eV ]
-1
Dit [cm eV ]
-1
1.5 3
-2
1.0 2
-2
0.5 1
0.0 0
0.0 0.4 0.8 1.2 1.6 0.0 0.4 0.8 1.2 1.6
Figure 2.36: Simulation of the C-V at 300K (top left) and at 450K (middle left)
of an n-type GaAs MOS capacitor with a single peak interface trap distribution
(left bottom). A weak inversion response occurs at 450K. Simulation of the C-V
at 300K (top right) and at 450K (middle right) of an n-type GaAs MOS capacitor
with a double peaked interface trap distribution (bottom right). Left and right
hand characteristics are clearly qualitatively similar. Five frequencies are plotted
chosen logarithmically in the 1kHz-1MHz range.
Further possible similarities are illustrated in figure 2.37. Simulations of InGaAs

MOS capacitors with different interface trap distributions are shown. Figure 2.37e,
which shows a weak inversion interface trap response, is clearly similar to figure 2.37c
and 2.37d which show depletion interface trap responses and to a lesser extent to
figure 2.37f which shows an inversion response. The InAs example in figures 2.37a
61
and 2.37b shows that a strong inversion response (figure 2.37b), which does not show
a maximum as a function of voltage in the frequency dispersive C-V part, can be
qualitatively similar to an interface trap response (figure 2.37a).
It is demonstrated that similarities between the admittance characteristics of the
depletion and weak inversion responses of traps and the inversion generation can lead
to misinterpretations of the interface trap density. It will be shown how to resolve
this issue in the next chapter.
2.9 Conclusions: The Influence of Trap Density, Trap

Energy Distribution, Bandgap and Temperature on
Admittance Characteristics of Non-Si/SiO2 MOS
capacitors
Several parameters of the MOS capacitor admittance characteristic change when leav-
ing the trodden Si/SiO2 path: the bandgap, the trap densities, the trap energy dis-
tribution and the trap capture cross sections. For a novel semiconductor-dielectric
interface only the bandgap is well known, all the other parameters need to be deter-
mined and no assumptions can be made. The influence of all of these parameters on
the admittance characteristic needs to be well described in order to be able to deter-
mine these parameters. We confirm that the admittance characteristics are described
by the - for Si/SiO2 - firmly established MOS theory [9].
The trap density can be much higher in non-Si/SiO2 interfaces. These high densi-
ties can lead to large frequency dispersion in MOS capacitance and often give rise to
a “frequency dependent flatband voltage shift.” Large densities give rise to so-called
weak Fermi level pinning (qDit > Cox ), which implies that substantially larger voltage
changes are needed to change the interface Fermi level position. When weak Fermi
level pinning occurs the classical MOS theory still describes the MOS characteristics.
We have shown that the interface trap time constant plays an important role in
MOS admittance behavior. The interface trap time constant gives rise to an energy
window in the bandgap which depends on temperature. Interface traps can only be
recognized by their conductance and capacitance frequency dispersion when they are
located inside the window. The window shifts toward the band edges when temper-
ature is decreased. One needs to be aware of this phenomenon in order to avoid
significant errors in interface trap density extraction.
For higher temperatures, smaller bandgaps, and larger capture cross sections the
weak inversion response of interface traps becomes more prominent in the frequency
range of 1kHz - 1MHz. This weak inversion response can easily be confused with a
depletion response of a much larger amount of traps since these two responses can
have similar admittance characteristics. Inversion generation can also give rise to
confusion with interface trap responses due to similar admittance characteristics. It
is clear that confusing these similar admittance characteristics can lead to interface
trap characterization errors.
In this chapter these phenomena were worked out to provide proper understanding
of the admittance behavior in order to enable the correct extraction of interface trap
density based on admittance measurements. The extraction methodology itself is
62
2.9 Conclusions
Figure 2.37: Simulations illustrate the qualitative similarities of alternative

MOS capacitor C-Vs with different interface trap distributions which can lead
to misinterpretations (Dit indicated underneath graphs. Energy is relative to
valence band edge). The presence of a weak inversion response from a relatively
small background Dit (c) or strong inversion response in (b) and (f) can lead to
confusion with distributions with more traps. Such issues are analogously present
for G-V. Note that pseudo-accumulation occurs for (c) and (e).
63
worked out in the next chapter.
64
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68
Chapter 3
Admittance Based Interface

Trap Extraction Methods for
Ge/III-V MOS devices
3.1 Introduction
In this chapter we treat the use of admittance measurements for extracting the inter-
face trap density of dielectric-semiconductor interfaces for any semiconductor/dielectric
combination.
Admittance based methods to extract interface trap density have a very good sen-
sitivity. A defect density of ∼ 1×109 cm−2 can be detected using conductance measure-
ments. Most material characterization techniques are not this sensitive. Detecting a
density of 1×1013 cm−2 of chemically bonded atoms potentially causing the interface
defects (the occurrence of germanium monoxide for example) is currently practically
impossible using ARXPS (Angle Resolved X-ray Photoelectron Spectroscopy) on a
Ge/Si/SiO2 /HfO2 MOS stack consisting of 0.2 - 1 nm thick layers. Also Electron Spin
Resonance (ESR) measurements, the most versatile technique to identify defects, can
only detect dangling bonds down to a density of ∼2-5×1010 cm−2 for Si Pb1 dangling
bonds. In contradiction to conventional SIMS (Secondary Ion Mass Spectroscopy),
low energy SIMS can potentially be used to detect the presence of indiffused Ge in
a Si layer of a few monolayers thick [1]. Compared to photoluminescence measure-
ments, which can provide a relative evaluation of interface quality [2], conductance
measurements offer the advantage that one does not need a direct bandgap semicon-
ductor and that a direct quantification of trap density is possible. Deep level transient
spectroscopy measurements have a very good sensitivity but are more involved and
quantification of high trap densities is difficult. Charge pumping measurements (see
next chapter) also offer a high sensitivity and a direct measurement but it requires the
availability of high quality MOSFETs instead of capacitors. Issues related to junction
leakage or contact resistance dependent on temperature can occur for experimental
MOSFETs.
In this chapter it will be shown which issues affect the extraction of interface
69
3. GE/III-V INTERFACE TRAP EXTRACTION METHODS
trap density in non-Si/SiO2 MOS structures. We focus on the conductance method

because it is known to be the most accurate admittance based method [3]. It is shown
that applying the conductance method on non-Si/SiO2 interfaces can lead to large
errors in interface trap density extraction. These issues can be resolved by modifying
the conductance method to the full conductance method.
When the samples to be analyzed are far from ideal, the full conductance method
can no longer be applied and different methods can be applied to gain insight into
the passivation properties. A first method was developed which is able to distinguish
weak Fermi level pinning due to the dominant amount of interface traps from other
sources of large frequency dispersion. We also propose a method which evaluates the
relative severity of Fermi level pinning to study the passivation quality of non-ideal
capacitors, usually GaAs or InGaAs MOS.
Numerous other methods are available in the literature to extract interface trap
density from MOS capacitor admittance which were developed for Si/SiO2 . An anal-
ysis is given which shows the impact of changing to a non-Si/SiO2 MOS structure on
the most important of these methods. For non-Si/SiO2 interfaces the (full) conduc-
tance technique remains the most accurate.
3.2 Conventional Conductance Method and Full Con-

ductance Method
In this section the conductance method[4][5][6][7] will be treated. First the con-
ventional conductance method will be introduced, followed by the issues posed by
non-Si/SiO2 interfaces and then finally the full conductance method is introduced as
a solution for these issues.
3.2.1 Principles of the Conductance Method

The conductance method makes use of the linear relation between the interface trap
density and the peak GP /ω value as a function of frequency to determine the interface
trap density (see section 2.5 of the previous chapter). The conductance method uses
equations based on an integral to approximate a continuous interface trap density
[4][8] which is equivalent to the convolution shown in equations 2.10 and 2.11 of
the previous chapter. Surface potential fluctuation (σs , see previous chapter) which
determines the width of the G/ω peak is also included. The following equations valid
in the depletion regime are used to extract the interface trap density [3]:
Z ∞
Dit
Cp = Cs + q arctan(ωτ )P (σs , E)dE (3.1)
−∞ ωτ
Z ∞
GP q Dit
= ln(1 + ω 2 τ 2 )P (σs , E)dE (3.2)
ω 2 −∞ ωτ
in which P is a Gaussian distribution with variance σs2 , describing the surface potential
fluctuations (σs is expressed in units of kT /q).
70
3.2 Conventional Conductance Method and Full Conductance Method
The Dit can be extracted from GP based on equation 3.2. The interface trap
density can be derived from the equation:
µ ¶
Gp
Dit = [fD (σs )q] (3.3)
ω fp
³ ´
G
in which ωp is the peak G/ω value at a certain voltage, and fD is a universal
function of the surface potential fluctuation ([9], p.217). Gp can be determined from
the measurement (Gmeas and Cmeas ) by “subtracting” the oxide capacitance using
the equation:
2
GP ωCox Gm
= 2 (3.4)
ω Gm + ω 2 (Cox − Cm )2
Apart from taking into account the oxide capacitance one should also ensure that
series resistance does not influence the measurements. This can be verified in practice
by checking the area scaling (series resistance does not scale with area while interface
trap characteristics do) and by looking for tell-tale signs of series resistance (the
typical horizontal shift in the C-V with frequency in accumulation and associated
time constant behavior versus voltage, see previous chapter). Gate leakage issues can
occur as well as more rare phenomena influencing conductance as discussed in the
previous chapter. These phenomena should also be avoided. The energy position of
the trap in the bandgap corresponding to the voltage at which Dit is determined can
be found using a flatband voltage extracted from a C-V fit.
The conductance method provides a straightforward, direct and accurate mea-
surement of the interface trap density.
3.2.2 Issues of the Conductance Method Applied to Ge/III-V MOS

and Solutions
In this subsection several issues are treated which can affect the conductance method’s
results negatively when applied to non-Si/SiO2 interfaces. Under- and overestimations
of more than an order of magnitude in extracted interface trap density can result. It
has not been shown before that such dramatic errors can be made using the con-
ductance method [10]. These extraction methodology issues are shortly introduced
and are based on the theory developed in the previous chapter. The focus in this
section is on the practical conductance method extractions. Solutions for the issues
are proposed in this work leading to the full conductance method [10].
3.2.2.1 Influence of the Time Constant

Issue The influence of the interface trap time constant has important implications
on MOS admittance as discussed in the previous chapter. Because of the interface
trap time constant’s dependence on energy and temperature, only traps in a certain
part of the bandgap are observable at a certain temperature.
¡ ¢ A trap is considered
observable by means of the conductance method when GωP fp is within the measure-
ment equipment’s frequency range (usually 1kHz-1MHz). This is illustrated in figure
3.1.
71
Solution The conductance method is typically used at room temperature. In this

case only traps in part of the bandgap are measured and usually a large amount of
traps in the non-observable parts of the bandgap are missed. For Si/SiO2 the trap
peaks happen to be largely observable at room temperature. For novel interfaces
this cannot be assumed to be the case. We emphasize that it should be made sure
that an as large as possible part of the bandgap is covered systematically with the
measurements. We show that this can be done by selecting a range of temperatures
which allows measuring traps across the entire bandgap (this is illustrated in figure
3.1 by the vertical lines). Note that one needs to take into account the capture
cross section and it’s dependence on temperature (see figure 2.28). Since the capture
cross section is unknown beforehand for a new interface, the choice of measurement
temperature range must be wide enough or adapted on the fly to determine Dit
across the bandgap. We propose to measure conductance at selected temperatures to
allow the measurement of Dit across the bandgap. High temperature measurements
have been proposed before to measure traps more toward midgap for Si (for example
[11]) and III-V [12]. We have also done work on high temperature measurements on
III-V MOS [13]. However, the essential need to measure an array of temperatures
(both higher and lower than room temperature) to systemically cover traps across
the bandgap of any semiconductor-dielectric combination has not been demonstrated
nor has an adaptation of the conductance method been proposed which is proven
to be able to accurately and completely characterize Dit (E) for a broad range of
semiconductor-dielectric MOS combinations.
1.0 bandgap
1MHz
0.8 -
1kHz e
0.6
+
0.4 1kHz h
0.2
1MHz
0.0
100 200 300 400 500
Temperature [K]
Figure 3.1: The calculated energy ranges at which traps are visible as a function
of temperature for Si for a constant capture cross section of 1×10−15 cm−2 . The
vertical lines indicate a possible choice of measurement temperatures to extract
interface trap density across the bandgap. The Ge and GaAs cases can be found
in figure 2.24.
3.2.2.2 Indistinguishability of the Weak Inversion and Depletion Response

Issue The possible similarity in the admittance characteristic of a depletion and
weak inversion response of interface traps, as discussed in the previous chapter, forms
72
another considerable issue for the conductance method. The conductance method
assumes the presence of a depletion response. Two samples can have very different
interface trap densities and yet can have similar admittance characteristics due to a
weak inversion and a depletion response. A G/ω-peak caused by a weak inversion
response can be due to a much smaller amount of traps than a G/ω-peak of the same
magnitude but caused by a depletion response. In the case that one interprets the
characteristic as a depletion response, as in the conductance method, while it is really
due to a weak inversion response, a large overestimation of the trap density will result.
The error can be up to an order of magnitude.
The measurements and corresponding simulations and analysis of the GeOx Ny
capacitor of which conductance is shown in figure 2.17 show that the interface trap
density is 7×1011 cm−2 eV−1 Ȧ naive extraction at room temperature on the weak
inversion response would lead one to think that the trap density is 8.5×1012 cm−2 eV−1 ,
more than an order of magnitude higher. The possible similarity of the weak inversion
and depletion responses can result in large errors when applying the conductance
technique which inherently assumes depletion bias.
Also the inversion response can be confused with a depletion response in some
cases. Clearly a solution is needed to reliably measure the trap density at any tem-
perature in the presence of a weak inversion or inversion response.
Solution: Full Conductance Measurement It is not possible to solve this issue

and to distinguish a weak inversion response from a depletion response by look-
ing at the voltages for which the response occurs. A depletion response of similar
G/ω-magnitude will show more interface traps and hence more stretch-out will occur.
This stretch-out will make the peaked response occur at similar voltages as a weak
inversion response. It was also shown that the weak inversion response can influence
the conductance around midgap (see figure 2.18).
Since the weak inversion response decreases at lower temperatures one could try
to eliminate the weak inversion response by lowering the temperature to measure Dit
more accurately. However, the temperature needed to completely eliminate the weak
inversion response is unknown since one does not know the capture cross section of
the traps one is going to measure. It is also not feasible to make assumptions about
the capture cross section since the cross section can attain values varying orders of
magnitude (1×10−12 - 1×10−18 cm2 ). Hence one is never sure whether one still has a
weak inversion response when lowering the temperature to measure Dit of a newly
made experimental device. By lowering the temperature one also changes the energy
range of the measured traps in the bandgap toward the band edge and hence one is no
longer able to measure traps located more toward midgap. The weak inversion and the
depletion response also remain relatively similar when lowering the temperature (see
figure 2.18). Lowering the temperature is not a solution to avoid the weak inversion
response.
By increasing the temperature it was possible to show that a particular response
was a weak inversion response by inducing a strong diffusion-induced inversion re-
sponse (see section 2.5.2 in the previous chapter). Increasing the temperature again
changes the range of traps measured by the conductance method and the induced in-
version response contributes large amounts of conductance which will most likely dom-
inate any contribution from interface traps and inhibit a good Dit -characterization.
73
Increasing the temperature is also not a solution. One should be able to resolve
the weak inversion and inversion response issue at any given temperature to enable
the extraction of the interface traps across the bandgap by measuring at different
temperatures as shown in the previous subsection.
In literature [14] the fitting of a complete model has been used to determine the
interface trap density in the weak inversion regime on Si/SiO2 capacitors. It is clear
that the potential similarity of a weak inversion and depletion response prevents such
a method from being effective. The conductance also shows a decreased sensitivity
to the interface trap density in the weak inversion regime compared to the depletion
regime for capacitors. Moreover, a fitting based method is needed which is more
complicated, less easy-to-use and less transparent than the conductance method.
Figure 3.2: (a) Measured parallel G/ω on a Si-passivated Ge n-type capaci-

tor with HfO2 at 300K (b) Full conductance measurement on a pMOS with the
same gate stack. The (weak) inversion capacitor response is absent in the full
conductance at 300K. The small τ at 300 K causes a large part of Dit (E) to be
unobservable. At 80K the traps near the band edges are observable.
The weak inversion response and strong inversion response dominate the conduc-
tance at 300K for Si-passivated Ge MOSFETs (as shown in figure 3.2). We show
by means of this example and equivalent circuit models that a so-called full conduc-
tance measurement solves the weak inversion and strong inversion response issues and
avoids misinterpretations at any temperature.
“Full conductance” is measured on a MOSFET or gated diode with the bulk and
source and drain shorted (see figure 3.3b). The capacitance measured is referred to
as “full capacitance” and the admittance as “full admittance”. Inversion carriers are
provided deliberately at a very high rate via the source/drain avoiding the dissipation
and conductance when carriers are provided in (weak) inversion through traps or dif-
74
fusion. Any conductance contribution due to the strong inversion and weak inversion
responses will be avoided.
s s
P P
P P
s
Figure 3.3: (a) Equivalent circuit of an MOS capacitor. In a full conductance

(or full capacitance) measurement the conductance (capacitance) is measured
between the gate of a MOSFET or gated diode and the shorted source/drain
and bulk (b) This results in a simplified equivalent circuit. For a single trap
this simplified circuit is represented by a Git and Cit pair (c). A distribution of
traps consists of a series of such pairs (d). Circuit d is the same as the one on
which the conductance method is based (see [9] for more details) but for a full
conductance measurement it is valid across the bandgap. Gp is used to extract
Dit in the conductance method [9] (e). Gp is obtained by “subtracting” Cox from
the measured conductance and capacitance (f).
Applying the short (Fig. 3.3b) on the MOS capacitor circuit model (Fig. 3.3a)
results in a simplified circuit which is the same as the one used for the conventional
conductance method (figure 3.3c) in which
Cit = gNit /((ωτit )2 + 1) (3.5)
Git /ω = gNit ωτit /((ωτit )2 + 1) (3.6)
where Nit [cm−2 ] is the density of the single level interface traps, and g(E) = q 2 f0 (1−
f0 )/kT .
The simplified full conductance equivalent circuit, though, is valid across the
bandgap while that for the conventional conductance method is only valid in deple-
tion. The electrical contact to the minority carrier band allows to probe the traps in
75
the minority carrier half of the bandgap while this is not possible with the conventional
conductance method. For full conductance the time constant is τf c = τn τp /(τn + τp ).
A continuous trap distribution can again be approximated by a series of discrete
states modeled by adding corresponding Git and Cit elements in parallel for each trap
level (figure 3.3d).
The conductance method uses the equations based on an integral instead of a sum-
mation (figure 3.3d) to approximate a continuous interface trap distribution. Equa-
tions 3.1 and 3.2 are valid across the bandgap for full conductance and one can apply
the normal conductance method on a full conductance measurement to extract the
interface trap density without weak inversion and strong inversion response issues
across the bandgap.
Figure 3.2 shows the full conductance and the conventional conductance mea-
surement of the Si-passivated Ge devices. At 300K the weak inversion response and
inversion response in the conventional conductance shows a peak G/ω increasing
sharply toward lower voltage (as in figure 3.2a). This is no longer present for a 300K
full conductance measurement (figure 3.2b) confirming the effectiveness of the full
conductance solution. The full conductance measurement at 80K shows that the
characteristic of τ (V ) shows a maximum near midgap. τ determines the maximum in
G/ω at each voltage (fmax ≈ 1/(2πτit )). Note that conductance measurements have
been done before on MOSFETs with source/drain and bulk shorted on Si/SiO2 MOS
[15]. However, their value for avoiding the similarity issues seen in MOS capacitors for
a broad range of semiconductor-dielectric MOS combinations was never recognized
nor was it realized that the depletion equivalent circuit becomes valid across the entire
bandgap with an adapted τf c . We show that by doing a conductance measurement
on a MOSFET or gated diode with S/D and bulk terminals shorted (see figure 3.3),
dubbed a full conductance measurement, the weak inversion and inversion similarity
issues are solved at any temperature.
3.2.2.3 Influence of Large Stretch-out and the E-V Relationship Extraction

Issues More issues for alternative substrates are caused by the potentially much
larger Dit than for Si/SiO2 . For high Dit (> Cox /q) the energy-voltage relationship
(E-V) can be difficult to extract because an apparent “frequency dependent flatband
shift” or “frequency dependent threshold voltage (VT ) shift” will occur in C-Vs which
prevents threshold voltage or flatband voltage extraction. Making use of an extracted
Dit (V ) one needs to extract Vf b or VT to anchor E-V.
Apart from the possible infeasibility of extracting Vf b or VT to position Dit (V ) in
energy it is also possible that a very large stretch-out Rprevents the extraction of Dit
over a sufficiently large energy range. Very high Dit ( qDit (E)/Cox dE > 5 − 10V )
leads to a very large stretch-out (the extreme is strong Fermi level pinning) and then
only Dit in a small part of the bandgap can be extracted. Oxide breakdown limits
the energy range that can be assessed. The latter issue is fundamental.
Solution We show (see figure 3.4) that for an n-type MOS capacitor with asymmetric
high Dit as in some Ge MOS the E-V problem can be solved by using a full capacitance
measurement (see figure 3.4b). The asymmetric Dit causes a frequency dependent
flatband voltage shift to be present in n-type capacitors. This is not the case for p-
76
type capacitors because Dit is low near the bottom of the bandgap. Full capacitance
is a capacitance measurement of a MOSFET with drain/source and bulk terminals
shorted (see figure 3.3b). The full capacitance measurement allows extracting VT
instead of Vf b when a “frequency dependent flatband shift” occurs. Due to the low
Dit in the bottom of the bandgap a “frequency dependent threshold voltage shift” does
not occur. For a Dit (E) in which the Fermi level (Ef ) is trapped between acceptor
and donor densities neither Vf b nor VT can be extracted (figure 3.4c) because one is
confronted with both a “frequency dependent flatband and threshold voltage shift”.
We show this is the case for a typical GaAs MOS capacitor (figure 3.5, [16][17][18]).
In this case it is not possible to extract E-V and to position Dit in the bandgap.
Figure 3.4: Schematic showing the effect of asymmetric and symmetric high
Dit (> Cox /q) on capacitor and full capacitance characteristics. Temperature is
chosen so the traps are visible. It shows when a “frequency dependent flatband
voltage shift” or “frequency dependent threshold voltage shift” will occur. These
two phenomena, typical for high Dit , prevent the extraction of Vf b and VT resp.
At least either VT or Vf b should be extractable to determine the E-V relation
and hence for the symmetric case it is not possible to determine E-V.
3.2.2.4 High Trap Density Influence on the Conductance

We show that at high Dit (qDit > Cox ) the conductance method becomes insensitive
to the trap density, as illustrated in figure 3.6 [19]. G/ω starts saturating when
Dit > Cox /q. The onset of the saturation occurs earlier for thicker dielectric layers.
77
Figure 3.5: N-type and p-type capacitor GaAs MOS C-V characteristics at
300K. A “frequency dependent flatband shift” occurs for both substrate types
showing the relevance of the symmetric case in figure 3.4 for MOS admittance
measurements in general. In this case it is hence not possible to extract E-V.
This insensitivity is caused by the dominating 1/(jωCox ) in the MOS admittance.

The saturation means that if the extracted qDit > 4Cox (G/ω reaches ∼ 80% of
saturation value) the extracted value of Dit is only a lower bound of possible values.
The insensitivity at higher Dit is a fundamental issue of the conductance method and
can lead to the underestimation of the interface trap density for non-Si/SiO2 MOS.
3.2.2.5 Measuring Traps Across the Entire Bandgap

The conductance technique is known to only measure traps in the depletion half of the
bandgap while a complete extraction is needed across the bandgap on a single device.
N-type combined with p-type measurements are not the best option because one
cannot necessarily assume that the substrate type has no influence on the unknown
non-Si/SiO2 interfaces under investigation [20]. Full bandgap measurements on a
single sample also avoid double work both in measurement and processing. The full
conductance measurement proposed is able to measure in both bandhalves and allows
to measure Dit across the bandgap.
3.2.3 The Full Conductance Method

We have mapped the issues of the conventional conductance method and provided
solutions. A method, the full conductance method (FCM), can now be composed to
correctly determine interface trap density in non-Si/SiO2 MOS structures.
78
-6
10
G/w [F/cm ]
2
-7
10
qDit > Cox
-8
10
-6 2
Cox= 2.5x10 F/cm 1.4 nm EOT
-7 2
Cox = 3x10 F/cm 12 nm EOT
-8 2
Cox= 4.5x10 /cm 100 nm EOT
-9
10
10 11 12 13 14
10 10 10 10 10
2
Interface state density [1/eV/cm ]
Figure 3.6: Theoretical measured G/ω (figure 3.3f) as a function of Dit . G/ω
starts saturating when qDit > Cox . This means that the extracted Dit value
using the conductance technique becomes a lower bound of the sample Dit when
the extracted Dit > 4Cox /q (G/ω reaches ∼80% of saturation value).
1. To extract Dit across the bandgap measurements are needed in a temperature

range which becomes larger with bandgap because of the trap time constant
effect (see figure 3.1). A minimal set of temperatures is selected in this range to
cover the bandgap of the semiconductor. Temperatures below 300K are required
to extract near the band edges and temperatures above 300K can be required
to be able to extract midgap Dit .
2. At each of these temperatures a full conductance measurement is done as a
function of voltage and frequency. Full conductance avoids jeopardizing the
conventional conductance method by the weak inversion response, the diffusion-
induced inversion response, the G-R-induced and surrounding surface charge
induced inversion response. Full conductance also enables extractions across
the bandgap. On the full conductance measurement the conductance method
is applied:
(a) The oxide capacitance is subtracted from the measured admittance to de-
rive GP .
(b) At each voltage the peak GP /ω is determined. This value is converted to
a Dit -value at each voltage using equation 3.2 or 3.3 and using a surface
potential fluctuation parameter σs extracted by means of fitting.
3. The E-V relationship is calculated by using the extracted Dit (V ) combined with
a VT or Vf b extracted from the full capacitance characteristic. The full capaci-
tance characteristic is the capacitance component obtained when measuring full
conductance. If the Fermi level is positioned in between two high (Dit > Cox /q)
interface trap peaks it is no longer possible to position Dit in energy. At very
high Dit , stretch-out will prevent extracting Dit across the bandgap.
79
4. If the extracted Dit is larger than ∼ 4Cox /q the extracted Dit should be marked
as a lower bound to the true Dit .
The full conductance method expands the conductance method for use on a broad
range of semiconductor-dielectric combinations. The extracted interface trap density
by means of the FCM of a Si-passivated Ge MOSFET is shown in figure 3.7. The entire
bandgap is covered and time constant effect is taken into account by measuring at
different temperatures. The full conductance measurement avoids weak inversion and
inversion response artifacts and allows extracting Dit in both halves of the bandgap.
In the extraction shown in figure 3.7 the threshold at which the extracted Dit becomes
a lower bound is reached at ∼ 0.5 eV. The interface trap density shows an outspoken
asymmetry and the density is high compared to Si/SiO2 . The interface trap densities
of silicon passivated Ge MOSFETs will be discussed in chapter 5.
The full conductance method requires the availability of gated diodes or MOS-
FETs. Gated diodes can be obtained from capacitors with only two additional pro-
cess steps: an implant and anneal. A full MOSFET process is hence not necessary.
MOSFETs, however, offer characterization advantages because also drive current,
Ion − Iof f and mobility become available.
Figure 3.7: Extracted Dit using the full conductance method at 77K, 153K,
228K, and 300K for the Si-passivated Ge pMOSFETs. As the temperature is
lowered interface traps nearer to the band edges are extracted and a large asym-
metry in Dit over the bandgap becomes evident.
In figure 3.8 an overview is given of the time constant and weak inversion response
issues affecting Ge/III-V admittance behavior and solved by the full conductance
method. The temperature needed to observe midgap traps increases with increasing
Eg. The weak inversion and diffusion-induced inversion response occurs at increasing
temperature with increasing bandgap. Weak inversion and diffusion-induced inversion
response were defined to occur when their peak G/ω contribution was larger than a
peak G/ω from a 1×1012 cm−2 eV−1 depletion response. Generation-Recombination
induced inversion as well as inversion induced by surrounding inversion layers occur
80
3.3 Qualitative Interface Trap Density Analysis Methods
at lower temperatures than diffusion-induced inversion and are not indicated in figure
3.8.
Temperature range which Issues for capacitor measurements
guarantees covering all traps a full conductance measurement solves:
in bandgap more than Weak inversion Diffusion-induced
60 meV from band edges response present inversion response
using full conductance present
Thigh Only midgap traps are

visible. No traps visible 1 kHz -1MHz
using full conductance range assumed
above this temperature.
n-type
Tlow Traps 60 meV from
band edges are visible.
Lowering temperature
will show traps closer
to band edges
InSb InAs Ge Si GaAs GaN

In0.53Ga0.47As
Figure 3.8: Overview of the properties affecting the admittance behavior for
different semiconductors.
3.3 Qualitative Methods to Analyze Effect of Large In-

terface Trap Densities and Fermi level Pinning for
Ge/III-V Devices
3.3.1 Introduction
When samples with very high trap density need to be analyzed, the full conductance
method may no longer be applicable. The method can no longer be applied when
severe stretch-out occurs or when the position of the Fermi level in between two
trap peaks makes it unfeasible to derive the E-V relationship and situate Dit in the
bandgap. More importantly, Dit itself may no longer be extracted accurately when
G/ω saturates for Dit & 4Cox /q at high Dit . When the conductance method can
no longer be applied we propose methods that still provide useful information on the
MOS structures which do not attempt to determine Dit (E) anymore. A first method
distinguishes weak Fermi level pinning due to a dominant amount of interface traps
from other effects causing similar admittance characteristics. A second method [21]
81
evaluates the Fermi level movement efficiency to study the passivation quality of non-
ideal capacitors, usually GaAs or InGaAs MOS. The first method makes sure that one
is indeed dealing with interface traps and the second method can be used for relative
comparison of samples with very high trap density.
3.3.2 Fermi Level Pinning Detection Method (FLPDM)
A straightforward, qualitative methodology is proposed able to distinguish the pres-

ence of weak Fermi level pinning due to interface traps from other effects based on
capacitance and conductance measurements on capacitor structures.
Fermi level pinning has been investigated based on photoluminescence measure-
ments [22][2], capacitance analysis [23] [24] [25], or DLTS-like techniques [23][25][16].
DLTS measurements are much more involved than an admittance measurement to
determine the presence of Fermi level pinning. The capacitance based analysis tech-
niques reported do not intend to provide a straightforward technique to conclude the
presence of pinning and to separate it from other effects. Different observed phenom-
ena were reported and described in detail [23][24][16][26] [27]. Some concluded that
to affirm that accumulation or inversion is reached [28] MOSFET or MISFET current
measurements would have to be made. It was also concluded [28] that one has to
revert to surface conductivity measurements which are less reliable than admittance
measurements. Yet others propose photoluminescence. Photoluminescence measure-
ments can only be used on direct bandgap materials, are easy-to-use and compare
semiconductor-dielectric interfaces with heteroepitixial semiconductor interfaces of
high quality [2]. The method proposed here is complementary to PL-measurements
for the evaluation of MOS capacitors based on alternative semiconductors.
The proposed methodology is based on the simultaneous analysis of frequency dis-
persion in capacitance and conductance versus voltage in the depletion-accumulation
regime. Frequency dispersion in capacitance is often reported in GaAs capacitors
(for example [29] [28] [16] [18] [17] [30] [31] [32]). Some articles report the dispersion
in particular devices to be caused by interface traps (for example [16] [18] [17] [32])
while others report the obtained characteristics to be due to a space charge layer
[26] [31] or due to a dielectric effect [27]. The often observed frequency dependent
flatband shift [17] is associated with weak Fermi level pinning (see section 2.5 of the
previous chapter). The characteristic time constant versus voltage derived from the
capacitance-voltage (C-V) and frequency normalized conductance-voltage (G/ω-V)
characteristics is used to determine the presence of weak pinning and separate it from
other effects.
As a rule of thumb, weak Fermi level pinning is defined to occur when the majority
of MOS charges are located in interface traps over a voltage range larger than half the
bandgap. When charges are dominated by interface traps in the weak inversion or
inversion regime for more than half the bandgap in voltage it is clear that MOSFET
functionality will be strongly degraded. In practice the relevant weak inversion or
inversion regime for MOSFETs will be evaluated using capacitor C-V measurements
of the opposite doping type in the depletion-accumulation regime.
82
3.3.2.1 Methodology
To conclude the presence of weak pinning, the extracted time constant is introduced
and investigated versus voltage. The extracted time constant is derived as a function
of voltage for both C-V and G-V measurements separately. Finally a criterium is
formulated to conclude weak Fermi level pinning.
G/ω or Capacitance [F/cm ]
-7
2
8x10 Cmax
6
τ =1/2πf
C1/2
4
Cmin
0
2 4 6 2 4 6 2 4 6
3 4 5 6
10 10 10 10
Frequency [Hz]
Figure 3.9: Demonstration of the extraction of a time constant from the capac-
itance and conductance separately. A theoretical capacitance and admittance is
shown when the MOS capacitor is entirely determined by interface traps (Cs = 0,
Cof f set = 0). Cmin , Cmax , and C1/2 are indicated by the full horizontal lines,
in this case Cmin = 0. The full vertical line indicates the frequency belonging
to the extracted time constants. In this case the time constants coincide. The
dashed horizontal line indicates a C1/2 position in the case that the interface
traps are not dominant. In this case the capacitance and conductance shown
need to interpreted as the contribution due to interface traps only.
For the C-V measurements the average is taken of the minimum and maximum ob-
served capacitance over all voltages and frequencies(C1/2 = (Cmax,f,Vg +Cmin,f,Vg )/2).
For each voltage the frequency for which C1/2 occurs is noted resulting in a time con-
stant (τ = 1/2πf ) as a function of voltage (see figure 3.9). The minimum capacitance
is included to comprise the case in which the depletion capacitance is not completely
negligible compared to the interface trap capacitance (the effect of the depletion ca-
pacitance is approximated as a capacitance added to Cit ) or to comprise the case in
which an offset capacitance is present (see figure 3.10). The definition of C1/2 assumes
that the theoretical maximum capacitance value is measured. When using a measured
maximum capacitance it should be made sure that toward higher voltages and lower
frequencies the capacitance approximately saturates to the value expected for the
oxide capacitance. If measured maximum capacitance is not adequate, C1/2 can be
corrected by using the expected oxide capacitance as the maximum capacitance.
For the G-V measurement the frequency is noted at each voltage where the max-
imum G/ω occurs, similarly resulting in a time constant versus voltage (see figure
3.9). This is a semi-quantitative technique and the extracted time constants should
83
offset
Figure 3.10: Equivalent circuit of an MOS capacitor with a large interface

trap density.
not be regarded as a highly accurate extraction of numerical values.

Next, the following rule of thumb is applied on the extracted time constants: the
voltage range is taken where both extracted time constants approximately match, are
not approximately constant with voltage and decrease toward accumulation. If the
change in time constant with voltage in this range is more than an order of magnitude
and if this voltage range is larger than half the bandgap of the semiconductor under
consideration weak Fermi level pinning is concluded.
3.3.2.2 Discussion
In this section it is discussed why the FLPDM is able to distinguish weak Fermi-
level pinning from other effects. In table 3.1 the behavior is given for a number of
effects discussed in the previous chapter. It is given to which degree a certain be-
havior obeys τ -behavior and the equations 2.3 and 2.4. When the admittance can be
described completely by τ -behavior this is marked in the table as “Fully τ ”. When
only a component in the equivalent circuit can be described by τ -behavior this is
marked “Partly τ ”. The trend of the time constant toward accumulation and the
magnitude of the time constant change with voltage is also given. Interface trap be-
havior is the only phenomenon of the ones considered in table 3.1 showing a decrease
in time constant over several orders of magnitude when approaching accumulation.
Matching extracted time constants will result if the equation for the capacitance and
conductance contain a τ -behavior admittance term, which is due to the definition of
τ -behavior by equations 2.3 and 2.4 and the choice of extracted parameters. Match-
ing time constants is the case for dominant interface traps. Approximately, a small
depletion capacitance can be considered as a constant term added to the τ -behavior
admittance. The method will hence remain valid if a small depletion capacitance
contribution is present. The FLPDM rule of thumb demands matching time con-
stants and time constants decreasing toward accumulation over more than an order
of magnitude because this will only be the case for dominant interface trap behavior.
We will elaborate on why the matching time constants criterion and the definition
of C1/2 allow the exclusion of the case in which the interface traps are not dominant.
In the non-dominant case the maximum interface trap capacitance ∼ qDit will be
smaller than the oxide capacitance, which is approximately the maximum measured
capacitance. Because Cmax and the maximum interface trap capacitance contribution
as a function of frequency at a particular voltage no longer coincide, the time constant
84
Effect Series re- Gate leak- Maxwell- Dipole ef-

present sistance age and se- Wagner fect
ries resis- effect
tance
τ -behavior? Fully τ τ term τ term Non-τ
Partly τ
time con- Increasing Increasing, Constant Decreasing
stant trend if gate leak-
toward ac- age is high τ
cumulation term will be
negligible
Magnitude In order of In order of Constant less than
of change of ideal capaci- ideal capaci- an order of
time con- tance change tance change magnitude
stant with
voltage
Effect Quasiaccu- Interface Dominant Semicon-
present mulation traps interface ductor
layer traps bulk traps
τ -behavior? Partly τ Partly τ Fully τ τ
time con- / Decreasing Decreasing Constant
stant trend
toward ac-
cumulation
Magnitude / Several Several Constant
of change of orders of orders of
time con- magnitude magnitude
stant with
voltage
Table 3.1: Summary of the different effects and the presence of a τ -behavior
in the capacitance and conductance behavior. Time constant change is given for
the effects showing τ -behavior. Dominant interface trap behavior is distinguished
from the other effects which gives rise to the FLPDM.
85
extracted from the capacitance will no longer match the true time constant. This is
illustrated in figure 3.9 by the dashed lines where we now have to interpret the shown
capacitance as the interface trap capacitance contribution as a function of frequency
at a particular voltage and the horizontal dashed line as the C1/2 position. The time
constant extracted from the conductance, however, will still correspond to the true
time constant explaining the non-matching time constants in the non-dominant case.
So C1/2 will no longer correspond to half the maximum capacitance of the interface
trap admittance contribution determined by equations 2.3 and 2.4 and this causes
a disparity between the time constant extracted from the capacitance and the one
extracted from the conductance which allows excluding the non-dominant case.
The FLPDM rule of thumb requires that the voltage range over which the time
constant changes is larger than half the bandgap. This is to make sure that weak Fermi
level pinning is present, according to the rule of thumb definition of weak Fermi level
pinning. A rule of thumb voltage change of half the bandgap was chosen for relatively
small EOTs instead of the exact voltage-surface potential relation dependent on the
Effective Oxide Thickness and doping to maintain a straightforward and fast method.
When stretch-out occurs due to oxide bulk traps the half bandgap criterion will be
reached sooner. This can be avoided by subtracting the estimated amount of stretch-
out due to oxide bulk traps from the voltage range which is compared with the half
bandgap value.
This typical time constant signature of dominant interface trap behavior can be
masked or hidden by other effects. This masking can make a conclusion of weak
pinning impossible even though weak pinning is present. One problem is that when the
interface trap density increases sufficiently toward the majority carrier band the time
constant will become much less dependent on voltage eventually becoming constant
toward accumulation due to very large stretch-out. In that case it is not possible to
distinguish the weak pinning from other effects. More often than not, though, the
time constant will vary sufficiently with voltage before the time constant becomes
voltage independent to be able to conclude weak pinning.
Another effect which can lead to masking is series resistance. The change in the
MOS admittance due to series resistance can prevent FLPDM from concluding Fermi
level pinning. It should be ensured that no series resistance effect is present. To
eliminate a series resistance effect the area of the device can be chosen smaller so
1/(2πτRC ) is shifted out of the measured frequency range. This will eliminate the
possibility of the common series resistance effect which can prevent concluding the
presence of weak Fermi level pinning.
3.3.2.3 Illustration
The G/ω-V curves versus frequency of an n-type GaAs/Al2 O3 -sample [33] are shown
in figure 3.11 (top left) while the C-V curves versus frequency are shown in 3.11 (top
right). The G/ω of a p-type GaAs/GdO2 [33] sample is shown in figure 3.11 (bottom
left) while the capacitance is shown in figure 3.11 (bottom right). For both samples
a similar large frequency dispersion of the capacitance can be observed as well as
a similar conductance behavior. For the examples used in this section to illustrate
the method the gate leakage was found low enough ( < 0.1Acm−2 ) to rule out any
influence on the characteristics. The extracted time constants are plotted in figure
86
3.12. Both the time constant derived from the capacitance and the one derived from
the conductance match. The time constants clearly decrease toward accumulation
over several orders of magnitude and over more than 1.42 V for each case. As a result
weak Fermi level pinning can be concluded for both samples.
-7
6x10
-6 2 Gate Voltage [V]
Area = 2.04x10 cm 1.96 Frequency [kHz]
1.72 -6 17.7
1.48 1.2x10
5 1.23 26.7
10.3
]
0.99
2
G/w [ Ss/rad/cm ]
0.747
2
60.7
Capacitance [F/cm
0.505
4 0.263 1.0 91.5
0.020 138
-0.222
-0.465 208
3
-0.707 314
-0.949
-1.19 0.8 473
-1.43 713
-1.68
-1.92
1070
2
1990
0.6 -6 2
Area = 2.04x10 cm
1
0
0.4
2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9
4 5 6
10 10 10 -2 -1 0 1 2
Frequency [Hz] Gate voltage [V]
Frequency [kHz]
1
-7 -7
1.4x10 8x10 1.51
5.17
Capacitance [F/cm ]
12.7
2
1.2 60.7
G/w [ Ss/rad/cm ]
208
2
1.0 Gate voltage [V] 6 385

-1.84
713
-1.60
2440
0.8 -1.35
No symbol Measured
-1.11
4 R extrap.
0.6 -0.869
-0.626
-0.384
0.4 -0.141
-1.01 2
0.2 0.343
-5 2 0.586
Area = 4.85x10 cm
0.0
3 4 5 6
10 10 10 10 -2.0 -1.0 0.0 1.0
Frequency [Hz] Vg [V]
Figure 3.11: G/ω characteristics vs. frequency for the Al2 O3 GaAs sam-
ple (top left) showing the peaks versus frequency due to interface traps. C-V
characteristics vs. frequency for an Al2 O3 GaAs sample (top right) showing the
typical frequency dependent flatband shift. G/ω characteristics vs. frequency
for the GdO2 GaAs sample (bottom left) showing the peaks versus frequency
due to interface traps. C-V characteristics vs. frequency for a GdO2 GaAs sam-
ple (bottom right) also showing the typical frequency dependent flatband shift.
The additional traces marked with circles (R extrap.) are an extrapolation of
a low frequency capacitance trace toward higher frequencies assuming frequency
dispersion is only due to a 2 kΩ resistance in series.
To illustrate the difference of the typical capacitance behavior dominated by in-

terface traps compared to an RC-effect a second series of C-V traces versus frequency
was added to figure 3.11 (bottom right). In this series it was assumed that the fre-
quency dispersion was due to only an RC-effect with a series resistance of 2 kΩ and
the frequency dispersion due to the resistance was extrapolated from a low frequency
trace. This is in clear contrast with the original measurement clearly showing that the
dispersion in the original measurement is not due to series resistance. The different
87
time constant behavior due to series resistance becomes clear too in figure 3.12.
Ga2O3 Conductance
-4
10 Ga2O3 Capacitance
Ga2O3 Capacitance
Series Resistance
extrapolation
Time constant [s]
Ga2O3 Conductance
Series R extrap.
-5 Al 2O3 Conductance
10 Al 2O3 Capacitance
-6
10
-7
10
-2 -1 0 1 2
Gate Voltage [V]
Figure 3.12: Plot of the time constant extracted from conductance and ca-
pacitance separately vs. voltage of the Al2 O3 on GaAs sample and the GdO2 on
GaAs sample. Also the time constant due to a series resistance effect is plotted vs.
voltage. The latter was derived from a low frequency GdO2 trace extrapolated
to high frequencies only assuming a series resistance (2 kΩ) to be present.
In figure 3.13 one can find several non-GaAs examples on which the method was
applied. A Ge/HfO2 capacitor is included with an EOT of 1.6 nm showing weak
Fermi level pinning as determined by the proposed method and as determined quan-
titatively before by fitting [34]. In addition, unpassivated (Dit ∼1×1012 cm−2 eV−1 )
Si/SiO2 capacitors of thicknesses 10 nm and 20 nm are also shown. When applying
the method to the 10 nm case (Dit < Cox /q ∼ 2 × 1012 cm−2 eV−1 ) weak Fermi level
pinning is not concluded due to the non-matching time constants whereas for the 20
nm case (Dit ≈ Cox /q ∼ 1 × 1012 cm−2 eV−1 ) weak Fermi level pinning is concluded.
As the oxide becomes thicker the interface traps in the Si/SiO2 interface can domi-
nate the semiconductor charges more easily. For the 10nm case the influence of the
interface traps is restricted to a large “bump” on the ideal C-V. For the 20nm case
the interface traps dominate the C-V which shows the typical frequency dependent
flatband shift. This shows clearly that the rule of thumb method can distinguish
between the dominant and non-dominant interface trap densities.
3.3.2.4 Conclusion
To conclude the presence of weak Fermi level pinning, a time constant is introduced
and investigated versus voltage. The time constant behavior of several phenomena is
considered: series resistance, gate leakage, the Maxwell-Wagner effect, dipole effects,
quasiaccumulation layer effects, interface traps, oxide or semiconductor bulk traps.
Whichever of those phenomena is present, if the extracted time constants for the C-V
88
-4
10
Time constant [s]
-5
10
n-type
pinned Ge MOS Conductance
-6
10
pinned Ge MOS Capacitance
10 nm Si/SiO2 Conductance
10 nm Si/SiO2 Capacitance
p-type
20 nm Si/SiO2 Conductance
20 nm Si/SiO2 Capacitance
-7
10
0.0 0.5 1.0 1.5 2.0 2.5

Gate Voltage [V]
Figure 3.13: Plot of the time constant vs. voltage of a weak Fermi level pinned
Ge/HfO2 capacitor measured at 80K with a Ge surface passivated epitaxially
with Si. The high amount of defects in the Ge capacitor allows the Fermi level
to be pinned at an EOT of 1.6 nm. Additionally a 10 nm Si/SiO2 and a 20 nm
Si/SiO2 without passivated interface are shown. As the oxide is taken thicker
the interface state defects in the Si/SiO2 interface can dominate the depletion or
accumulation charge more easily resulting in a weakly pinned interface for the 20
nm case.
89
and the G-V approximately match, are not constant and decrease more than an order
of magnitude toward accumulation over a voltage range larger than half the bandgap
of the semiconductor the presence of weak Fermi level pinning by interface traps can
be concluded. Using this method on capacitor structures it will be straightforward to
qualitatively and quickly conclude the presence of weak pinning in most cases.
3.3.3 Fermi Level Pinning Severity Analysis Method

3.3.3.1 Methodology
In order to properly evaluate the less-than-ideal oxide-semiconductor interfaces, a new
approach focusing on the interface Fermi level is proposed[21]. This work has been
co-developed with Dennis Lin, who led the work. The evaluation of the efficiency with
which the Fermi level shifts when changing the voltage can be used as a measure of
the severity of Fermi level pinning. It will be useful to compare samples showing very
large amounts of interface traps, which is often the case for III-V MOS capacitors.
Similar to the conductance method, the Fermi level efficiency (FLE) method is
based on the equivalent parallel conductance of the interface traps (Gp ). But the
location of the conductance curve peak in frequency, instead of the magnitude, is
the feature we focus on. The frequency at which the conductance peak occurs is
associated with the trap energy level and hence Fermi level using the interface trap
time constant repeated here (see section 2.5.1):
τit = [vth σNef f exp(−q∆E/kT )]−1 (3.7)
By extracting the interface trap time constant one can trace the movement of the
Fermi level as a function of gate bias. The amount of Fermi level movement with
respect to a certain gate bias change reflects the trap density level at the oxide-
semiconductor interface. High trap density hinders Fermi level movement. We define
Fermi Level Efficiency (FLE) as the ratio of dEf over q · dV g which can be expressed
as the following:
µ ¶
dEf ∼ ∆E1 − ∆E2 f2 kT /q
= = ln · × 100(%) (3.8)
q · dV g q(V1 − V2 ) f1 (V1 − V2 )
where ∆E1 and ∆E2 are the Fermi level positions from equation 3.7 while f1 and
f2 are the frequency at which the conductance peak occurs under bias V1 and V2 ,
respectively.
The amount of band-bending or interface Fermi level displacement under gate
bias Vg at a near perfect oxide-semiconductor interface can be estimated, using the
depletion width approximation:
s
Qsc qN 2εs Φs
Vg = Φ s + = Φs + (3.9)
Cox Cox qN
where Φs , Qsc are the total semiconductor band-bending, total space charge in the
depletion region. If we solve for Φs numerically we can determine the ratio ∆Φs /∆Vg
which is the FLE for an ideal MOS capacitor. This ratio ∆Φs /∆Vg is very close
to unity when the substrate doping is low ( ∼ 1×1015 cm−3 ) and Cox high ( ∼ 1
µF/cm2 ), as in the case of the silicon reference sample. For a moderately doped (
90
∼ 1×1017 cm−3 ) GaAs sample with similar Cox the ideal ∆Φs /∆Vg ratio decreases
to around 85%. This ratio represents the theoretical upper bound of FLE. Other
parameters such as the oxide capacitance and the substrate dielectric constant will
also have minor effects on the ratio. This ∆Φs /∆Vg ratio for ideal MOS system should
be used as a reference or calibration when comparing the FLE results from different
oxide-semiconductor combinations. The FLE method allows to compare FLE figures
between samples with different interface passivation and to compare to the expected
ideal FLE figure.
3.3.3.2 Applicability
Certain criteria regarding the application of the FLE method and equation 3.8 are
discussed in the following section.
Energy dependence of trap state interaction cross section The trap capture or
emission cross section in equation 3.7 could depend on the energy level of the trap
states, and can be described by the relation:
σ = σ0 exp(−α∆E/kT ) (3.10)
The coefficient α is the energy dependence coefficient of the cross section. The ex-
tracted amount of Fermi level movement becomes (1 + α) · (∆E1 − ∆E2 ) when the
above situation is taken into account. The depth of the measured trap energy level as
well as the Fermi level travel can be significantly overestimated if the coefficient α is
comparable to unity or larger. It is assumed that the coefficient α is much less than
unity.
Applicability in Depletion Region The applicable range of the Fermi level efficiency
technique falls within the depletion region. Inversion generation, the weak inversion
response of interface traps can produce high conductance readings which completely
overtake the typical depletion conductance response from the interface traps. Because
of these effects, the measured conductance results in the weak inversion and inversion
regions cannot be properly interpreted and should not be taken into account for
analysis. Note that the occurrence of a series resistance effect will also jeopardize the
applicability of this technique.
3.3.3.3 Experimental
MOS capacitors with p-type In0.15 Ga0.85 As and p-type In0.53 Ga0.47 As substrates were
fabricated and studied. The In0.15 Ga0.85 As samples consist of a CVD grown 20nm
strained buffer layer on a GaAs wafer, while the In0.53 Ga0.47 As samples have a lattice
matched MBE grown In0.53 Ga0.47 As layer on an InP wafer. A 10nm aluminum oxide
layer was deposited on all the InGaAs samples inside an ASM Pulsar 2000 ALD
reactor at 300◦ C after ex situ ammonium hydroxide surface treatment. Samples were
annealed at different temperatures from 400◦ C ∼ 700◦ C in RTA. Ohmic contacts and
palladium metal gates are deposited by e-beam evaporation. A Si reference sample
with 1nm native oxide and 10nm MBE grown aluminum oxide and similar MOS
structure was also fabricated. The In0.15 Ga0.85 As MOS samples were measured at
150◦ C in order to have access to the traps near midgap.
91
The FLE curves in figures 3.14 and 3.15 clearly demonstrate the difference in oxide
interface quality between silicon and InGaAs MOS devices. The silicon-oxide FLE is
near 100 percent at the mid-bandgap region where a trap density of 2×1011 cm−2 eV−1
was estimated by the conductance method. In contrast, the InGaAs MOS samples
have FLE figures between 0.5 and 23 percent in which the magnitude of the conduc-
tance peaks are too high to properly conclude Dit levels by the conductance method.
In figure 3.15, more information is revealed comparing the InGaAs samples. Post
deposition anneals (PDA) can modify the FLE profile. In the In0.53 Ga0.47 As sam-
ple, degradation of the interface due to high temperature PDA was confirmed by
the observed 10 percent drop in peak FLE. The effect of Indium percentage can be
investigated with this technique. The In0.53 Ga0.47 As samples show higher efficiency
and broader range in Fermi level movement in comparison with the In0.15 Ga0.85 As
samples.
3.3.3.4 Conclusion
The FLE method proposed is based on the surface Fermi level movement as a function
of applied gate bias. This method demonstrates its effectiveness in evaluating high
trap density interfaces which the conventional conductance method cannot deal with
properly. The applicable bias range, doping and EOT need to be carefully addressed
when applying the FLE method.
3.4 Investigation of Different Capacitance Based Inter-

face Trap Extraction Methods for Ge/III-V
In this section frequently used conventional interface trap extraction methods based
on capacitance are evaluated for non-Si/SiO2 interfaces. The influence of the different
effects mapped out in the previous chapter is discussed.
3.4.1 Low frequency (Quasi-static) Method

Principle of the Method The low frequency method [3] determines the interface
trap density versus energy by means of a low frequency C-V measurement, a so-called
quasi-static measurement. In a quasi-static measurement a voltage slope is applied
on the gate of an MOS capacitor structure and the displacement current is measured
from which the capacitance is derived. The slew rate of the voltage is taken sufficiently
low so the interface traps can be charged in a quasi-static fashion. This means that
the interface traps can be considered in equilibrium when one is applying the voltage
slope. The interface trap capacitance measured during a quasistatic measurement is
Cit = qDit . This can be deduced from the equation 2.7 of the previous chapter when
f → 0 . The low frequency property Cit = qDit is the main feature on which the low
frequency or quasi-static method is based.
In order to estimate Dit by means of Cit = qDit one needs to separate Cit from
the Cs and Cox contribution in the MOS capacitance (see section 2.5 in the previous
chapter). In order to do this one needs an estimate of Cox and Cs . These values will
92
3.4 Investigation of Dit Extraction Methods
Figure 3.14: Extracted Fermi level efficiency numbers from the Gp /ω plot of
a Si MOS sample. The inset shows the range of trap energy levels within Si
bandgap measurable between 100Hz and 1MHz at room temperature assuming
constant capture cross section of 1×10−15 cm−2 . The efficiency decreases as the
Fermi level moves toward the valence band, reflecting the well known parabolic
distribution of Si interface traps. The FLE drop off at 0.42eV and below is due
to series resistance.
93
Figure 3.15: Fermi level efficiency plots for p-type InGaAs MOS samples. For
15% indium samples the measurements were carried out at 423K in order to reach
the midgap traps. The others were measured at room temperature. The FLE
numbers were calculated accordingly.
then be “subtracted” from the measured MOS capacitance value as follows:

µ ¶
Cit 1 Cox Clf
Dit = = − Cs (3.11)
q q Cox + Clf
where Clf is the measured low frequency or quasi-static capacitance, and Cs is
the semiconductor capacitance. Cox is obtained by means of a C-V fit. There
are two different methods to obtain the Cs term. A first method, the hf model/lf
method makes use of a modeled Cs . A second method, the hf/lf method (Castagné-
Vapaille method), uses a high frequency (hf, lower case) measurement to estimate
Cs = Cox Chf /(Cox − Chf ). For an hf measurement it is assumed that the frequency
is sufficiently high in order to prevent the traps from contributing to the capacitance.
This will be referred to as the hf condition. Usually a frequency of 1MHz is used.
Cit = 0 for f → ∞ in equation 2.7 of the previous chapter. By reducing the Cit
contribution to the MOS capacitance to zero one is able to obtain an estimate of Cs .
These two different methods enable one to extract Dit as a function of voltage.
To determine Dit as a function of energy within the bandgap one makes use of
the Berglund integral [3]:
Z Vg1 µ ¶
Clf
E= 1− dVg + ∆ (3.12)
Vg2 Cox
where E is the Fermi level energy position relative to the bandedges at the interface
and ∆ is an integration constant. The integration constant ∆ is determined by as-
suming that at sufficiently high or low voltage the flatband condition or threshold
94
condition is reached where the interface Fermi level energy position varies little with
voltage and hence one can determine the Fermi level energy at these voltages to corre-
spond to the Fermi level energy at flatband/threshold. Note that this holds for thick
oxides but less so for thinner oxides which are properly described by Fermi-Dirac
statistics instead of Boltzman statistics. For thin oxides the Fermi level position will
vary quite significantly when the flatband condition has been passed.
The low frequency method is used frequently for Si/SiO2 capacitors with large
Dit (unpassivated or partially passivated) with rather thick oxides ( ∼ 10nm) [35].
The method works very well for the stacks involved in the aforementioned cases.
Note that the ∼ 10 nm oxide thickness and Dit -values of ∼ 1×1012 cm−2 imply that
∼ Cox /[20 → 100] < Cit < Cox (Cit larger than 1-5 % of Cox and smaller than
Cox ). In this case stretch-out is not severe enough to prohibit determining the
energy by means of the Berglund integral (condition: ∼ Cit < Cox ). In case of large
stretch-out accumulation is not reached and accumulation is needed to fix ∆E for the
Berglund integral. For Cox /[20 → 100] < Cit , Cit is also large enough compared to
the ideal C-V in depletion to allow a good sensitivity to determine Dit (condition:
∼ Cit > Cox /[20 → 100]). The quasi-static method was applied for GaAs MOS with
the GGO oxide [27] ( ∼ 10 nm EOT, 6×1011 cm−2 interface traps). The potential
issues of the low frequency technique will be elaborated further in the next paragraph.
Issues of the Low Frequency or Quasi-static Method The main issue with the
low frequency (lf) technique is it’s lack of sensitivity for low trap densities. As the
Cit becomes significantly smaller than Cox the sensitivity drops. The Cit is “added”
to the larger contribution of Cs and this larger contribution needs to be subtracted
from the measured MOS capacitance. The error related to this subtraction and the
measurement error limit the sensitivity. In practice Cit can be determined when
∼ (20 → 100) × Cit > Cox (Cit 1-5% of maximum measured capacitance). This
stems from the fact that the Cit component sits on a much large MOS capacitance
component for low Dit which limits sensitivity. The conductance technique does not
have this issue [3] since the conductance is not “added” to a conductance contribution
from the MOS capacitance. Sensitivity issues also occur when qDit > Cox . Similarly
as for the conductance the oxide capacitance causes a saturation of the observed
additional capacitance due to interface traps (Clf − Chf ) when qDit > Cox .
The use of the Berglund integral also has it’s limits for high trap densities. In the
case of a large amount of interface traps and hence large amounts of stretch-out the
flatband or threshold condition might not be reached in the measured voltage range
and hence it becomes impossible to anchor the E-V relationship obtained by the
Berglund integral. Note that in case the large density of traps is only present on one
side of the bandgap one is still not able to determine the E-V by for example switching
from a flatband to a threshold side determination of ∆. Since one is measuring quasi-
static C-V which shows both inversion and accumulation C-V, one can switch but one
can also not tell on which side of the bandgap the traps are located with quasi-static
measurements since the trap capacitance can be very similar to an accumulation or
inversion capacitance in combination with potentially present effects which deform
the C-V shape, stretch-out, surface potential fluctuation, etc.
Stretch-out due to oxide bulk traps (which does not occur for Si/SiO2 ) affects the
low frequency method as well. This oxide bulk trapping is present in high-κ oxides
95
and also in GeOx Ny and GeO2 based stacks. The stretch-out affects the Berglund
integral and can lead to incorrectly determined E-V characteristics.
Apart from the issues treated above there are more issues related to the way Cs
is obtained. When the Cs is obtained from a modeled curve the following issues are
present:
1. The (model hf)/lf method is sensitive to offset capacitance. A small change in

offset capacitance can affect the extracted Dit (especially for Cit < Cox /10 and
for small area capacitors like used in the Si-passivation case).
2. One depends on theoretical C-Vs which tend to be inaccurate for ultra-thin

oxides because of quantum mechanical effects not accurately taken into account
in the models (even for Si/SiO2 there is a lot of difference between different
quantum mechanical simulators) [36]. This is certainly an issue if one is looking
for features around or less than 10% of the maximum C-V capacitance. Interface
trap free C-Vs of the Si-passivated Ge MOS structures are not straightforward
to simulate. Detailed quantum mechanical simulations are needed to explain
certain asymmetries [37] and these simulations would depend on parameters
of ultra-thin semiconductor layers which are not established. This considers
effective masses for ultra-thin layers of semiconductors.
3. Surface potential fluctuations also modify C-V characteristics and will blur dis-
tinct peaks or dip shapes which are used in the low frequency methods. These
need to be well modeled.
4. Note that also depth dependent doping concentration can influence C-V curves
significantly and thus affects the Dit -extraction [9]. It should therefore be in-
cluded in the modeling. The doping for the Si-passivated devices depends on
depth (same doping as for sub-micron devices).
All these factors make it very difficult to use a modeled Cs to yield sufficiently accurate
results with the low frequency technique, if not practically impossible.
When the Cs is determined from a measured hf C-V curve the frequency needs
to be sufficiently high. The frequency is sufficiently high when it is well above the
interface trap frequency determined by the interface trap time constant (see previous
chapter). High frequency C-V is usually measured around 1MHz which is not high
enough for traps near the band edges. As a consequence a large part of the traps are
still responding to the ac signal of the C-V measurement equipment at 1MHz and
the hf frequency C-V curve cannot be used to determine traps across the bandgap.
This limits it’s use to determine trap densities further away from the band edges.
For the particular Si-passivated Ge MOS case even the traps at midgap still respond
at 1MHz. The conductance peak is still visible (within 1kHz-1MHz) for these traps.
For materials such as Si and GaAs midgap traps are generally expected to no longer
respond to 1MHz signals at room temperature and hence this method can be used to
determine the trap density in these materials for traps sufficiently far from the band
edges as was done in [27].
Illustrations If the quasi-accumulation capacitance i.e. the interface trap capac-

itance which looks like accumulation capacitance because of absence of frequency
96
Interface trap peak

Only background interface traps
Interface trap peak and bulk traps
-7
6x10
Capacitance [F/cm ]
2
5
4
3
Quasi-Static
2
1 1 MHz
0
-2.0 -1.0 0.0 1.0
Gate Voltage [V]
Figure 3.16: Simulation of n-type GaAs Quasistatic and hf (1 MHz) C-V curves
for different conditions. One shows the C-V curves of a characteristic with only
the background interface trap density of 1×1012 cm−2 eV−1 . A second character-
istic has an interface trap peak near the conduction band of 1×1014 cm−2 added
to the background concentration. A last characteristic is with interface trap peak
and bulk oxide trapping added.
dispersion, as seen in Si-passivated germanium at 300K, is combined with sufficient

stretch-out due to oxide bulk trapping the hf/lf method (Castagné-Vapaille method)
can lead to the wrong conclusion that one has a low interface trap density. This oc-
curs because the method is not sensitive to a trap density near one of the band edges.
Also the Berglund integral can lead one to think that it is possible to move the Fermi
level across the bandgap while this is not the case. This faulty interpretation results
from the oxide bulk trapping causing stretch-out. This also shows that interpreting
C-V dips can be risky because they are related to the Berglund integral. C-V dips are
interpreted as follows: “The smaller a C-V dip is the more limited is the movement
of the Fermi level and hence the more traps there are.” But this dip can be stretched
by oxide bulk trapping and can lead to the impression that trap density is lower than
it actually is.
As an example, simulations of GaAs Quasi-static and hf (1MHz) C-V curves for
different conditions are shown in figure 3.16. For the C-V curves with only the back-
ground interface trap density of 1×1012 cm−2 eV−1 , the traps are clearly visible in
the difference between the Quasi-static and hf C-V curves between -1V and 0V. This
background density can be measured nicely with the lf/hf technique. A second char-
acteristic has an interface trap peak of 1×1014 cm−2 near the conduction band added
to the background concentration. This very large density trap peak does not show up
in the difference between hf and lf traces and is hence not measurable with the hf/lf
technique. This is because the hf frequency is not sufficiently high, which means that
there is still an interface trap contribution to the capacitance at the used frequency
of 1MHz. A last characteristic is with interface trap peak and bulk oxide trapping
97
added. This has as a result that the reduction in C-V “dip width” due to the trap
peak has disappeared due to the oxide bulk trapping.
Berglund integrals ( see equation 3.12) of the three C-V characteristics are shown
in figure 3.17. One can see that the modulation of the interface Fermi-level position
with voltage between accumulation and inversion is reduced in case the large interface
trap peak is present. However, for the case that the large interface trap peak and oxide
bulk trapping is present the modulation is similar to what one observes in case just
a background interface trap density is present. This shows that oxide bulk trapping
can mask the presence of a large trap density when using the Berglund integral. Bulk
oxide trapping is common in experimental MOS capacitors using high-κ dielectrics.
One can still observe a difference between the curve with only background interface
traps and the one with large peak and oxide bulk trapping. For the characteristic
without peak there is an increase of energy with voltage stronger than for the other
case in accumulation (high voltages). This is due to the fact that the Fermi-Dirac dis-
tribution is used in the simulations. This would not have been the case for a Boltzman
distribution. The difference in slope in an extraction is due to the different values
of capacitance in “accumulation.” The characteristics due to the peaked interface
traps have a higher capacitance in “accumulation” than the simulation with low trap
density and give rise to a lower slope compared to a C-V using Fermi-Dirac statistics.
Note that “accumulation” values of the capacitance change depending on how
quantum mechanical effects are taken into account. Also passivation layers, strain
etc. influence the C-V characteristic and these effects are not well known. In addition
quantum mechanical modeling results in differing capacitance values for different sim-
ulators [36]. The slope of the Berglund integral in accumulation (or inversion) which
is determined by the “accumulation” capacitance can hence not be used to distinguish
between the trap peak case and the one without trap peak.
2.0
Berglund integral energy [eV]
1.5
1.0
0.5 Interface trap peak

Only background interface traps
Interface trap peak and bulk traps
0.0
-2.0 -1.0 0.0 1.0
Gate Voltage [V]
Figure 3.17: Berglund integrals of the three C-V characteristics shown in

figure 3.16. One sees that the reduction in observed interface Fermi-level swing
due to the peak of interface traps can be masked by bulk oxide trapping which
is common in experimental capacitors.
98
Conclusions All of the above considerations make it risky to interpret C-Vs of novel,
experimental devices quantitatively based on the low frequency method, especially
when qDit . Cox /[20 → 100]. It is hence important to be aware of the limits of the
method. For experimental non-Si/SiO2 devices the quasi-static method can be used
in conjunction with a 1MHz C-V trace to determine trap densities near midgap as
was done in [27]. The extraction of interface trap density (not the trap energy) for
the hf/lf method is immune to oxide bulk trapping. The Berglund integral can be
used to double check the results of the Dit extractions. This is a quick and convenient
method but has limited sensitivity and cannot measure traps near the band edges and
hence can lead to large underestimations of trap densities.
3.4.2 Terman Method

The Terman method determines the interface trap density by looking at the stretch-
out of an hf C-V curve. The method assumes the absence of interface trap capacitance
in the C-V [3]. Since more traps mean more stretch-out one can determine the amount
of traps by comparing the measured hf C-V curve with the ideal curve without stretch-
out [3].
The limitations of the Terman method are well-known. First of all the frequency
needs to be high enough to ensure a true hf C-V curve is measured. For the Si-
passivated Ge case all traps still respond at the usual 1MHz frequency. This means
that the Terman method cannot be applied. The Terman method cannot be used for
traps near the band edges which have interface trap frequencies which are too high
too allow the hf C-V condition.
In case the traps around midgap are sufficiently slow one has a sensitivity prob-
lem since dC/dVg is low around midgap and this reduces sensitivity to stretch-out.
Stretch-out is difficult to measure when the C-V is flat. Especially the occurrence of
a quasi-accumulation capacitance and the additional presence of oxide bulk trapping
make this method unsuitable for practical analysis of experimental non-Si/SiO2 MOS
capacitors. The sensitivity of the method for low trap densities is also an issue since
very little stretch-out will be present for these trap densities. On top of that there
are also the ultra-thin EOT modeling issues. This method is of no use for evaluating
Dit of experimental non-Si/SiO2 MOS capacitors.
3.4.3 Gray-Brown Method

For the Gray-Brown method [3] the flatband voltage is measured as a function of tem-
perature. As the flatband Fermi level position shifts in energy toward the band edges
at lower temperature more traps are filled and the flatband voltage shifts compared
to the ideal value. These shifts are used to determine the trap density as a function
of energy.
The precise extraction of the flatband assumes an hf C-V curve. For traps in
proximity to the band edges, which contribute Cit (certainly at high temperature),
the method is not valid. For non-Si/SiO2 cases which can show a quasi-accumulation
capacitance the Gray-Brown method is clearly unapplicable because it is simply not
possible to derive the flatband voltage since one is looking at trap capacitance instead
of accumulation capacitance. In some cases a frequency dependent flatband voltage
99
is present, and again, for this case it is obviously not possible to derive the flatband
voltage properly. Issues such as bulk oxide trapping and limited sensitivity for low
trap densities further exacerbate the issues of the Gray-Brown method. The Gray-
Brown method is not applicable to determine interface trap density in experimental
non-Si/SiO2 MOS capacitors.
3.5 Conclusions
In this chapter admittance based interface trap extraction methods were reviewed
and a toolset is provided for the use on non-Si/SiO2 experimental MOS structures.
The conductance method is adapted for the use on non-Si/SiO2 MOS by changing
it into a full conductance method with simple modifications only: one measures MOS
conductance of MOSFETs or gated diodes with drain/source and bulk shorted, and
one measures at a series of temperatures guaranteeing coverage of the entire bandgap.
On these measurements the original conductance extraction methods can still be
applied. The full conductance method provides the most accurate and complete
admittance based measurement of the interface trap density for experimental feedback
or proving the passivation of the interface.
For experimental devices with very high interface trap density ∼ qDit > 4Cox the
conductance method can no longer be used to evaluate MOS structures. In this case
the weak Fermi level pinning rule of thumb can be used to assess whether frequency
dispersion and conductance characteristics are indeed due to interface traps. The
Fermi level efficiency technique can be used to relatively evaluate experimental MOS
structures with very high trap density. These two techniques complement photolumi-
nescence measurements [2] [38] which also provide a means to relatively evaluate trap
density (compared to a heteroepitaxial interface of two semiconductors and among
different samples) on direct semiconductors.
Admittance based methods such as the Terman and Gray-Brown methods become
unapplicable for experimental non-Si/SiO2 MOS capacitors. The low frequency C-V
method is a quick and easy-to-use method but can miss out on trap densities near
the band edges and has limited accuracy.
The conductance method is preferred over the low frequency method mainly be-
cause of its higher sensitivity to lower trap densities. It is more practical to use
peak G/ω, which shows a direct, linear relationship with the trap density without the
need for detailed modeling or an hf C-V curve. This makes the conductance much
more robust and insensitive to issues such as oxide bulk trapping and approximations
such as the hf C-V assumption. The standard conductance method procedure takes
into account surface potential fluctuations, most other considerations that influence
capacitance based methods mentioned above do not influence conductance.
After extracting Dit vs. voltage by means of the conductance method one has
to obtain the energy. For the conductance method energy was extracted using C-V
based methods and hence energy has a relatively large error bar ( ∼ 50-100 meV for
large trap densities). The full conductance method is therefore the most fit (among
admittance based methods) to provide an accurate and complete Dit (E) for feedback
to processing and to accurately prove that a certain interface is completely passivated.
In future work, the full conductance method could be implemented with a model
and a fitting routine to provide more accurate extractions as was done for a specific
100
3.5 Conclusion
case in my work [34]. Such a method would make the extraction method more valid
for rapidly changing Dit with energy and would provide more accurate extraction of
the energy position of traps.
101
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104
Chapter 4
Pulsed Signal Electrical Analysis

Techniques
4.1 Introduction
The use of pulsed signal electrical analysis techniques offers some particular advan-
tages compared to ac analysis techniques like admittance measurements with a small
test signal amplitude. The use of pulsed signal analysis with large signal amplitudes
allows to study hysteresis with pulsed I-V and pulsed C-V/Q-V methods. The use
of deep level transient spectroscopy which is based on the measurement of capac-
itance transients after the application of a pulse allows sensitive measurements of
semiconductor bulk trap densities. Finally, charge pumping, which also makes use of
pulses in combination with DC current measurements, allows interface trap density
measurements with high sensitivity.
In this chapter these techniques are elaborated. In the first part a pulsed Q-V/C-
V technique is introduced which solves the issues of the conventional pulsed C-V and
RF C-V methods when dealing with sub-nm EOT gate stacks. Secondly, deep level
transient spectroscopy is applied on Ge capacitors to study the technique’s value
for Ge MOS development. Finally, charge pumping is reviewed for the use on Ge
MOSFETs and modifications of the technique are proposed to deal with the charge
pumping characterization issues for Ge MOS.
4.2 Measuring C-V and Hysteresis in Ultra-Thin EOT

MOS: Pulsed Q-V
4.2.1 Introduction
Sub-nm EOT high-κ dielectrics [1] on Si or on alternative substrates such as Ge
[2] show the combined presence of high leakage and charge trapping in the high-
κ dielectric. Both a high gate leakage [3] (see also section 2.4) and oxide charge
trapping [4] are characteristics known to prevent the accurate determination of the
capacitance versus voltage or, equivalently, the charge versus voltage characteristic
105
4. PULSED SIGNAL TECHNIQUES
of an MOS structure. The influence of both effects on the C-V is depicted in figure
4.1. Leakage causes warping of the C-V at high voltages and oxide charge trapping
causes stretch-out and hysteresis. Methods have been developed to deal with each
of the phenomena separately. No method to date has addressed the determination
of the C-V or Q-V when both phenomena are present simultaneously. First the two
methods addressing each issue separately are introduced: the RF C-V technique and
the Inversion Charge Pumping technique (ICP).
C
C
Vg Vg Vg
Figure 4.1: Schematics showing the effects of leakage and charge trapping on
C-V characteristics. An ideal C-V is shown (left). Leakage causes warping of the
C-V at high voltages (center) and oxide charge trapping causes stretch-out and
hysteresis (right).
RF C-V [3] or specially designed RF-IV C-V measurements [5] on RF structures

are used as a solution for the C-V warping at high gate leakages up to 1000 Acm−2 (see
section 2.4). RF structures require more processing, time, and die space than regular
MOSFET structures. For gate leakage up to ∼10 Acm−2 we show that RF structures
are not needed to accurately determine the C-V if the pulsed Q-V method proposed
here is used. Pulsed Q-V is also less difficult to interpret and to measure than RF
C-V measurements.
Just like regular C-V measurements, RF C-V measurements will be deformed
when oxide charge trapping occurs. In figure 4.2 the involved mechanism is illustrated.
Charge is trapped in the oxide during the DC steps which are sufficiently long (∆tm >
1 − 10µs [6]) for charge trapping to occur. The charge trapping causes stretch-out
and asymmetry between charging and discharging causes hysteresis.
Also Time Domain Reflectometry has been proposed [7][8] to measure the C-V of
MOS devices with high gate leakage. This work also does not deal with the hysteresis
issue present in high-κ dielectrics.
The inversion charge pumping technique (ICP) [9] is used to measure the inversion
charge without charge trapping influence of high-κ dielectrics. The technique is based
on the geometric component in charge pumping measurements (see section 4.4). When
a gate voltage pulse train is applied with sufficiently short rise and fall times on a
sufficiently large channel length MOSFET with a negligible amount of interface traps
[10] a bulk current arises proportional to the inversion charge: I = qNinv /Tpulse in
which Tpulse is the pulse period. When inversion is induced the inversion carriers
are supplied through the source and drain. When the device is switched back to
accumulation or depletion the source and drain are pinched off and the inversion
charge recombines in the bulk and induces a net current between bulk and S/D
integrated over time. Part of the charge still escapes through the source and drain
106
4.2 Measuring C-V and Hysteresis in Ultra-Thin EOT MOS: Pulsed Q-V
Vg
Dtm e-
oxide
t trap
Qot
t
Figure 4.2: Schematic showing the influence of charge trapping on the regular
C-V measurement (top and bottom left, also applies for RF C-V). During the
DC voltage steps the admittance is measured using a small ac signal (see section
2.2). During these DC voltage steps charge trapping occurs since the step time
∆ts > 1 − 10µs [6]. This is indicated in the bottom schematic in which the
oxide trapped charge is shown as a function of time. This charging mechanism
is responsible for stretch-out in the C-V. This is similar to the stretch-out due to
interface traps (see section 2.5). Asymmetry in charging and discharging rates
for oxide traps causes hysteresis. A banddiagram showing the basic oxide charge
trapping mechanism is shown on the right.
though. By making use of the device symmetry the results can be corrected for
this escaping charge when extracting the inversion charge density. The inversion
charge density is derived using a measurement with only one implant connected and
a measurement with both connected (see figure 4.3): Ninv = 2 · NICP b − NICP a .
Using this technique one can keep the pulse length below 1-10µs and avoid charge
trapping when measuring C-V/Q-V. However, it is also not resistant to gate leakage
because the gate leakage rapidly becomes larger than the charge pumping current as
the EOT of the device is reduced.
The Q-V technique proposed here can measure the total or inversion Q-V directly
without influence of charge trapping and with gate leakage up to ∼ 10 Acm−2 . The
technique is also capable of characterizing the charge trapping induced flatband volt-
age shift versus charging time and voltage on capacitor structures, as is possible with
the pulsed I-V method [11][12]. Low interface trap density is assumed for this tech-
nique. This means the technique will only be applicable on Ge/III-V technologies
in an advanced stage of development showing good surface passivation and sub-nm
EOT. The development of the technique and the demonstration of characterization
with a quasi-RF 1GHz bandwidth system opened avenues for further work on charge
pumping on devices with high interface trap density (see section 4.4.2) and opens pos-
sibilities for work on quasi-RF conductance method applications on non-RF structures
and memory characterization. The proposed pulsed Q-V method does not require RF
structures and is suited for measuring Q-V or C-V of experimental devices showing
high gate leakage and charge trapping.
107
NS/D NS/D NS/D
Nicp,a Nicp,b
A A
Figure 4.3: Schematics of the ICP setup used to extract the inversion charge
density [4]. The device symmetry was exploited to compensate for the inversion
charge escaping through source and drain (NS/D ).
Vg
DV
Dts
Dtp t
Ig
Figure 4.4: Schematic showing the principle of the pulsed C-V method. A volt-
age pulse (top) is applied to the MOS capacitor and the resulting displacement
current I = C(V ) dV
dt (bottom) is used to derive the MOS capacitance.
108
The pulsed Q-V technique we introduce is based on the pulsed C-V technique
which can theoretically be used to avoid the effect of hysteresis (see figure 4.4) on the
C-V. We shortly introduce the pulsed C-V technique. When applying a gate voltage
pulse (see figure 4.4, top) with a constant slew rate (∆V /∆ts ) for the rising and falling
edge the capacitance can be determined from the resulting displacement current (see
figure 4.4, bottom). The following equation shows how the capacitance can be derived
dQ
from the capacitor displacement current based on C = dV and I = dQ dt :
µ ¶−1
dV
C(Vg ) = I(t(Vg )) (4.1)
dt
By keeping the length of the pulse (∆tp ) shorter than 1-10 µ s charge trapping can be
minimized. However, this method is sensitive to gate leakage, because the displace-
ment current for a step time of 1µs rapidly becomes smaller than the gate leakage
current when the latter is raised to ultra-thin EOT levels (0.1-10 Acm−2 ) (see figure
4.5 ). However, in practice the slew rate is limited to 10 kV/s because of instrumen-
tation reasons[13] and hence the pulse width cannot be kept below 1-10µs for pulsed
C-V measurements to avoid hysteresis.
3 -6 2
10 C = 2x10 F/cm
1 ∆V = 1 V
Current [A/cm ]
10
2
scale factor
-1
100%
10 10%
1%
-3
10
-5
10
-7
10
-9
10
-10 -8 -6 -4 -2 0
10 10 10 10 10 10
∆ts [s]
Figure 4.5: Graph showing the displacement current of a 2×10−6 Fcm−2

capacitor subject to a 1V pulse as a function of step time (∆ts , see figure 4.4).
10 % and 1% of the displacement current are also indicated.
In this section first the pulsed Q-V technique and measurement setup will be
elaborated. After that the pulsed Q-V technique is demonstrated on leaky Si/SiON
MOSFETs and oxide charge trapping high-κ capacitors consecutively. Finally the
technique is demonstrated on leaky and oxide charge trapping high-κ capacitors.
4.2.2 Measurement Principle and Setup

In order to create a technique which can deal with the gate leakage and hysteresis
simultaneously the pulsed C-V technique, which can deal with hysteresis, is taken as
the starting point. The rise and fall times of the pulsed C-V technique are shortened
in order to make the gate leakage small compared to the displacement current (see
109
figure 4.5). To enable this the pulsed C-V measurement setup has to be modified and
changed into a pulsed Q-V technique.
The very short (25ns) transition time chosen for the proposed technique is real-
ized by modifying the measurement system to have a 1GHz bandwidth. This 1GHz
bandwidth measurement system (see figure 4.6, top) consists of a 50Ω terminated
pulse generator and a high bandwidth 50Ω terminated oscilloscope. The 1GHz band-
width system is divided conceptually in a distributed part, consisting of the cables,
the pulse generator and the oscilloscope, and a lumped part. The lumped part con-
sists of the area where the DUT, an MOS device on a die, is contacted. The area
modeled as a lumped circuit has a diameter of 3-5 cm, small compared to the 1GHz
vacuum wavelength, justifying it’s lumped modeling in the 1GHz system. Since the
wiring and probes are surrounded by air the vacuum wavelength can be used as an
approximation. The lumped area contains, apart from the DUT, the probes on which
the cables are directly mounted and the grounding wires connecting the shields of
all the cables. The grounding wires of length around 3 cm are no problem for the
bandwidth of the proposed measurements. Since the surrounding dielectric is air, the
wavelength is 30cm at 1GHz making the wire length ∼ 10% of the wavelength. This
is sufficient to represent the electrical circuit between the cables as a lumped circuit
in which the inductance of the wire (∼ 60 nH) is of no influence on the measurements
(LC/∆t2 = V ).
Probing area
modeled as lumped circuit
voltage monitoring
transmission line
current monitoring transmission line
Scope 50
V 50 Scope
V A A
50
pulse generator tranmission line
Pulse
generator
Si
gn
50 al pulse generator tranmission line
Pulse pr
op
CDUT Rseries generator ag
at
ion
current monitoring transmission line
50 Coffset 50 CDUT and

Rseries DUT 50
Cpara Cpara Scope
Signal propagation
n
io
at
ag
op
voltage monitoring transmission line

pr
Scope 50
al
gn
Si
Figure 4.6: General setup for the pulsed C-V measurement (top left). High
bandwidth setup used for the pulsed Q-V method (top right). Schematic of
the impedance as “seen” by the pulse generator transmission line (bottom left).
Diagram showing signal propagation trajectories and the points where reflections
are avoided (bottom right).
The RC-delay is mainly determined by the DUT capacitance (CDU T ) and the
110
series resistance (Rseries ). As shown on figure 4.6, bottom left. To limit RC-delay
the DUT capacitance should be kept small (1-10 pF), taking into consideration that
up to 1-2 kΩ substrate series resistances can be present. Gate voltage pulse signal
reflections are avoided by the high series resistance or by keeping the DUT capacitance
small (1-3 pF). Reflections would warp the applied gate voltage pulse. The reflection
coefficient (Γ) at the DUT end of the pulse generator tranmission line is given by:
Z − Zc 75 + Rseries + j/ωCDU T
Γ= = −25 2 (4.2)
Z + Zc (75 + Rseries )2 + 1/ω 2 CDU T
This equation corresponds to figure 4.6, bottom left, in which the circuit representa-
tion of the impedance (Z) connected to the pulse generator transmission line at the
DUT end is shown. Zc is the characteristic impedance of the transmission line, 50Ω.
In this equation the parasitic capacitances and the offset capacitance were not incor-
porated. In case the series resistance is low, the capacitance needs to be kept low in
order to maintain the 50Ω termination of the transmission line. The 50Ω termination
element in the circuit originates from the voltage monitoring transmission line (see
left hand 50Ω element in figure 4.6 bottom left). There is no need to maintain a
50Ω termination at the DUT end of the current monitoring transmission line. The
signal leaves the DUT and no reflections will occur at the 50Ω terminated scope. No
signals originate from the scope. Hence signals only travel away from the DUT and
no reflections need to be avoided at the DUT end of the line. An overall scheme of
the reflections avoided in the system and signal travel are shown in figure 4.6, bottom
right.
Any capacitance between signal and ground or other parasitic element in the
lumped part has a negligible contribution to the measured displacement charge. The
net charge displaced by the parasitic capacitors (Cpara ) into the current monitoring
line is zero, since the right hand parasitic capacitor in figure 4.6 which is connected to
the current monitoring line is simply uncharged when no current is flowing through the
transmission line in between pulse edges. The voltage drop due to gate leakage across
the transmission line (the right hand 50Ω in bottom left of figure 4.6) is considered
negligible.
No de-embedding is needed to derive the displacement charge of the MOS device:
the displacement charge of the DUT is directly drained into the current monitoring
line. Only a correction for the offset capacitance (∆Qof f set = Cof f set ∆V ) due to the
bond pad is needed, as is also needed in a regular C-V measurement.
The quality of the pulses of the system is demonstrated in figure 4.7. No re-
flections are observed for the transition time considered. Experimentally, the 25ns
transition time resulted in the best leakage robustness and SNR for this setup. A
4GHz bandwidth 10Gsamples/s oscilloscope was used. Leakage robustness can be
further increased by changing to a setup that makes use of RF probes and structures
and by decreasing the transition time further.
The numerical integration of the transient current response of the MOS capacitor
to a rising or falling edge of a gate voltage pulse is used to obtain the displacement
charge for a certain pulse base level and amplitude. The Q-V is derived from a
series of displacement charge (Qd ) measurements using gate voltage pulses of varying
amplitude as illustrated in figure 4.8. A measured Q-V curve is shown in figure
4.9. The setup used is similar to Singh et al’s setup [14], but the difference is in
111
-6
15x10
2.0 2.0
0 10
Applied Voltage [V]

Applied Voltage [V]
1.5 1.5
Current [A]
Current [A]
5
-50
1.0 0 1.0
-100
0.5 -5 0.5
-6 -10
-150x10 0.0 0.0
-9 -9
0 50 100 150 200x10 0 50 100 150 200x10
Time [s] Time [s]
Figure 4.7: Voltage-time (25 ns fall time) and current-time trace of a leaky 1.7
nm Si/SiON stack illustrating the characteristics obtained with the setup (left).
Detail taken from the left hand figure of the voltage-time and current-time trace
(right). 3.3 % of peak current is leakage at 2.5 V. 4 µA or 14 A/cm−2 for this
3×10µm2 capacitor.
the integration used. Singh et al’s setup uses analog current integration instead of
numerical integration of the sampled current. In the setup of Singh et al., however,
obtaining good signal-to-noise ratio with proper matching is more difficult. To further
increase the leakage robustness, the numerical integration is corrected for leakage:
Z
Q = (I(t) − Ig (V (t))) dt (4.3)
where the gate leakage characteristic Ig (V ) is determined from the pulsed measure-
ment. By combining the Q-V methodology with the 1GHz bandwidth setup Q-V or
C-V can be determined for leaky and oxide charge trapping MOS structures.
The Q-V is converted to a C-V by fitting a convexity-constrained spline function
through the Q-V [15] and evaluating the derivative of the spline function. The simple
numerical derivative ( xy22 −y
−x1 ) delivers very noisy results since taking the derivative
1
is a numerically badly conditioned operation. This can be avoided by spline fitting.

Dierckx’ convexity constrained spline fitting algorithm was adapted to add constraints
on the third derivative by changing the Quadratic Programming (QP) algorithm used
(the Theil-Van De Panne procedure) to a general QP solver to which the additional
constraints were added while maintaining the rest of the algorithm. Asserting these
extra constraints on the third derivative allows a smoother fit. C-V characteristics
are clearly convex-concave and this property can be exploited to improve the spline
fitting.
Apart from allowing the calculation of the C-V, the spline fit is also used to denoise
the Q-V measurement. The uncertainty on the denoised Q-V measurement is smaller
than the uncertainty on the C-V derived from the Q-V due to the sensitivity of the
derivative operation. For evaluating flatband voltage shifts due to charge trapping
the use of the denoised Q-V is more accurate. It is also preferred to derive EOT, flat
band voltage and doping by fitting a model to the Q-V directly for the same reasons.
112
Q
Qd
Vg
Figure 4.8: Schematic showing the principle of a Q-V measurement. A Q-V

of a MOSFET is shown and a series of pulses with different amplitudes and a
constant base level. For each amplitude a displacement charge (Qd ) is obtained
and with a series of amplitudes the Q-V can be determined.
-12
25x10
100kHz C-V
20 pulsed Q-V
Charge [C]
15
10
-2 -1 0 1 2
Voltage amplitude [V]
Figure 4.9: Q-V curve of a 20 nm Si/SiO2 capacitor nicely matching an inte-

grated 100 kHz conventional C-V curve.
113
In the following sections the pulsed Q-V technique will be demonstrated. First its
effectiveness on Si/SiON MOS structures with high gate leakage but no oxide trapping
is demonstrated, then its usefulness on oxide trapping high-κ structures without gate
leakage is proven. Finally the Q-V technique is demonstrated on oxide charge trapping
MOS structures with high gate leakage.
4.2.3 Experimental Q-V and C-V Measurements of Leaky Devices
In this section the Q-V technique will be demonstrated on Si/SiON MOS structures
to show the leakage resistance of the introduced pulsed Q-V technique.
-12
1.8x10 pulsed Q-V
2
on regular 10x10 mm
1.6 RF C-V 100 MHz
on RF structure
Capacitance [F]
1.4 RF-IV C-V 100 MHz

on RF structure
regular C-V 100 kHz
1.2 on regular 10x10 mm
2
1.0
100
2
0.8 1
0.01
0.6
0.0001
-2 0 2
0.4 Gate Voltage [V]
-2.0 -1.6 -1.2 -0.8 -0.4

Gate Voltage [V]
Figure 4.10: A comparison of regular C-V, RF C-V, RF-IV C-V and pulsed
Q-V measurements on a 1.7 nm EOT Si/SiON nMOSFET with 5 Acm−2 leakage
at -2 V, demonstrating the leakage resistance of the Q-V method. Base level is
0.7 V.
Pulsed Q-V measurements were performed on 1.7 nm EOT Si/SiON nMOSFETs

with a gate leakage of 5 Acm−2 at -2.0 V (see inset of figure 4.10). Well and
source/drain were shorted for the measurement. To demonstrate the validity of the
method a comparison is made with an RF C-V measurement using a vector network
analyzer (VNA) [3] and an RF-IV C-V [5]. As can be seen in figure 4.10, the C-V
determined by the Q-V method on a regular structure matches to within 5% the C-V
determined with the VNA on an RF structure. The leakage resistance of the pulsed
Q-V method up to ∼10 Acm−2 is demonstrated.
114
4.2.4 Q-V Measurement and Characteristics of Charge-Trapping

Devices
In this section the ability of the pulsed Q-V technique to be immune to oxide charge
trapping and to investigate charge trapping characteristics is investigated. The im-
munity of the Q-V technique to the influence of charge trapping is ensured by the
very short time in which the displacement charge measurement is done (25-50 ns).
This is much shorter than the onset of oxide charge trapping for high-κ which has
been observed to occur at times of ∼ 1-10µs [12]. By keeping the width of the pulse
below 1µs the charges measured at the rising and falling edges will be identical and
free of influence of charge trapping.
For longer pulse widths (> 1 µs) the displacement charges at rising and falling
pulse edges (measured over 25-50 ns) start to differ. The charge trapping process is
investigated by looking at the pulse width dependence of the difference. To demon-
strate this, a 1.0 nm SiO2 / 10 nm HfO2 10×10 µm2 nMOSFET (3.8 nm EOT) was
investigated. The Q-Vs for different pulse widths from starting and ending edges are
shown in figure 4.11. With “starting and ending edges” the onset, first edge and
final, second edge of the voltage pulse shape are meant. The used pulse shapes are
shown in figure 4.12. The Q-Vs at the starting and ending edges obtained by means
of an amplitude scan allows the evaluation of charge trapping at different voltages,
while changing the pulse width for the Q-V allows investigating the charging and
discharging of traps in time.
Starting edge:
200 Ending edge:
pulse width
1 µs
Charge [pC]
10 µ s
150 100 µ s
1 ms
10 ms
100
50
1.0 2.0 3.0 4.0
Amplitude [V]
Figure 4.11: Application of the pulsed Q-V method to a thick high-κ nMOS.
The measured displacement charge (Qd ) is shown as a function of amplitude. The
difference in displacement charge between starting edge (no influence of trapping,
see figure 4.12) and the ending edge with different pulse widths was used to derive
the flatband voltage shift versus pulse width and voltage.
To understand the influence of oxide charge trapping on the Q-V we will intro-
115
Width
inversion 2V 2V
Amplitude 0.7V
accumulation
Pulse level Pulse level
Figure 4.12: Schematic of pulse shapes used for a regular ( see figure 4.11)
and virtual pulsed Q-V measurement ( see figure 4.15).
duce a simplified theory. For small flatband voltage shifts the difference in measured
displacement charge between the rising edge and the falling edge of the pulse due to
oxide charge trapping at a certain amplitude and pulse width is given by:
∆Qd = (Cbase − Cpulse )(∆Vf b ) (4.4)
in which Cpulse is the capacitance of the MOS capacitor at the pulse voltage and
Cbase is the capacitance at the base voltage. ∆Vf b is the flatband voltage shift caused
by the charge trapping between the starting and ending edges. This equation can
be understood by locally approximating the Q-V linearly with the capacitance as
coefficient (see figure 4.13). The starting edge displacement charge before the flatband
voltage shift takes place is:
Qd = Qpulse − Qbase (4.5)
where Qbase and Qpulse are the charges in the MOS capacitor at the base and pulse
voltages. When the flatband voltage shift is introduced this becomes:
Q0d = (Qpulse − Cpulse ∆Vf b ) − (Qbase − Cbase ∆Vf b ) (4.6)
and hence ∆Qd = Q0d −Qd returns equation 4.4. Equation 4.4 can be used to calculate
small flatband voltage shifts based on ∆Q − d. To calculate the large flatband voltage
shifts in the following experiments the linear approximation of the Q-V was not used
as in equation 4.4, but the measured trapping-free starting-edge Q-V was used instead
to calculate the flatband voltage shift.
Equation 4.4 shows that if capacitances are equal at the base and pulse voltages
no difference in charge will be seen even though a flatband voltage shift is present. In
figure 4.11 the upper set of Q-Vs were obtained by using a base level in inversion and
by scanning the pulse level from inversion to accumulation, as indicated in the left
schematic in figure 4.12. As the capacitance at the two levels becomes more equal for
increasing pulse voltages the flatband voltage shift can no longer be detected.
To detect a flatband voltage shift when capacitances are equal at base and pulse
voltage we introduce a virtual base level corresponding to a capacitance different from
the base level (see the schematic in figure 4.12). Before switching from the base level
to the pulse level the voltage is kept at the virtual base level for a short time (500ns
- 1 µs ). This time is kept shorter than the known onset time of oxide charging (1-10
µs) to avoid any trapping or detrapping at the virtual base level. The virtual charge,
which is the displacement charge when switching from virtual base level to the pulse
level, is monitored to obtain the Q-V.
116
Dvfb
Q
Dvfb DQ pulse= CpulseDVfb
Qd Qd’
Vbase Vpulse
Dvfb
DQ base = CbaseDVfb
Figure 4.13: Schematic showing the influence of a flatband voltage shift on the
Q-V and on the displacement charges near the base voltage and pulse voltage.
The Q-V can be linearly approximated locally with the capacitance as coefficient,
which allows to describe the displacement charge changes in case of a small
flatband voltage shift.
200
Starting edge:
Ending edges:
Virtual charge [pC]
pulse width
150 1 µs
10 µ s
100 µ s
1 ms
100 10 ms
50
0.5 1.0 1.5 2.0 2.5 3.0 3.5

Virtual amplitude [V]
Figure 4.14: Application of the pulsed Q-V method to a thick high-κ nMOS.
The measured “virtual” charge (Qd ) is shown. The difference in charge between
starting edge (no influence of trapping) and ending edge (∆Qd ) with different
pulse widths was used to derive the flatband voltage shift versus pulse width and
voltage. Curves with the use of a virtual base level (0.7 V) are shown.
117
Regular / Virtual
0.0 1 µs
Flatband shift [V]

/ 100 µ s
/ 1 ms
-0.1
-0.2
-0.3
-1.0 0.0 1.0

Gate Voltage [V]
Figure 4.15: Flatband voltage shifts derived from regular and virtual pulsed
Q-V measurements (shown in figures 4.11 and 4.14).
Figure 4.14 shows that, by using a virtual base level, the charge trapping charac-
teristics can be revealed which remain hidden for the case without virtual base level.
The starting edge Q-V curves do not depend on pulse width and are not influenced
by charge trapping. This is because all traps are charged after the base voltage is
applied, as in the case without virtual base level. The use of a virtual base level
allows deriving the flatband voltage shift when pulsing between voltages with similar
capacitance. Note that the change in virtual charge with increasing pulse width is of
the opposite polarity as for the non-virtual measurement. This is explained by the
change in capacitance at the different levels in the simplified case of equation 4.4. In
figure 4.15 the combination of the flatband voltage shifts calculated with and without
the use of a virtual base level is shown. The charge detrapping onset occurs around
10 µs, which is similar to that in [12]. By using the virtual base level charge trapping
can be monitored in an unrestricted voltage range. This cannot be done with pulsed
I-V [11][12]. For pulsed I-V weak inversion or inversion has to be part of the voltage
range since one obviously needs MOSFET source-drain current for this technique.
4.2.5 Q-V and Trapping Characteristic Measurement of Leaky Oxide-

Charge-Trapping Devices
In this section we show that the pulsed Q-V can be applied on devices showing both
high gate leakage and charge trapping. The method was applied on a 0.4nm SiO2 /
2nm HfO2 10×10 µm2 pMOS (1.27 nm EOT) with a leakage of 3 Acm−2 at 2 V
and 0.01 Acm−2 at -3 V. As can be seen in figure 4.16 and 4.17 it is possible to
derive the charge trapping characteristics of such dielectrics. The onset of significant
trapping is found to occur between 10 µs and 100 µs corresponding to what is found in
literature[12]. No further detailed investigation of the trapping mechanism was done.
The accuracy of the flatband voltage shift determination is about 10 mV, sufficient
to determine relevant charge trapping characteristics in thin high-κ dielectrics.
We also demonstrate the trapping free determination of the inversion capacitance.
118
0
Starting edge
-1 Ending edge
pulse width
1 µs
Charge [C]
-2 11 µs
1 ms
-3
-4
-5
-12
-6x10
-2.0 -1.5 -1.0 -0.5 0.0
Gate Voltage [V]
Figure 4.16: Hysteresis is seen in the Q-Vs on a 1.27nm EOT HfO2 pMOS
and for which the virtual base level is 0.5V and the base level is 2V.
0.00 0
Flatband shift [V]
10
Substrate
2
Source/Drain
-0.02
-2
10
-0.04
Width -4
10
-0.06 1 µs
11 µs
-6
-0.08 100 µs 10
1 ms
-0.10 -8
10
0.8 1.2 1.6 2.0 -3 -2 -1 0 1 2
Amplitude [V] Gate Voltage [V]
Figure 4.17: Shows the derived flatband voltage voltage shifts versus pulse
width and amplitude (left) of the stack investigated in figures 4.16 and 4.18.
Gate leakage characteristic of the involved gate stack is shown on the right.
119
This is done by determining the full Q-V using the starting edge only, guaranteeing
the absence of the influence of charge trapping. The inversion charge is determined
by fitting a depletion and accumulation Q-V model to the full Q-V and using the
difference between the full Q-V and the model Q-V as the charge trapping free inver-
sion Q-V. The pulsed Q-V technique can be used to obtain the C-V of leaky charge
trapping samples and also the inversion charge for mobility extractions without the
distortions caused by leakage and charge trapping.
0
-12
Inversion charge [C]

6x10
-1
Charge [C]
4
-2
2
0 -3
-2 -4
-4 total QV
fitted depl. QV -5
-6 Inversion QV
-12
-6x10
-3 -2 -1 0 1 2
Gate voltage [V]
Figure 4.18: Inversion charge characteristics free of trapping and leakage in-
fluence were obtained by means of the pulsed Q-V technique on a 1.27nm EOT
HfO2 pMOS. By fitting a depletion and accumulation Q-V model (upward trian-
gles) to the measured full Q-V at the falling edge (squares), the inversion Q-V is
obtained (downward triangles).
4.2.6 Conclusions
A pulsed Q-V method enabling charge or capacitance measurements versus gate volt-
age of aggressively scaled, leaky (up to ∼10 Acm−2 ) and charge trapping high-κ MOS
devices is introduced. The method does not require RF structures and can be used
on MOS capacitors or MOSFETs with an oxide capacitance of 1-10 pF. The method
enables the measurement of charge trapping characteristics in leaky MOS devices and
allows the accurate measurement of the inversion charge without influence of trapping
for the determination of mobility in leaky charge trapping MOS devices.
4.3 Deep Level Transient Spectroscopy Study of Ge

MOS Capacitors
4.3.1 Introduction
Deep Level Transient Spectroscopy (DLTS) has been applied on high-κ Ge capacitors
to investigate bulk traps and interface traps in Si-passivated HfO2 germanium MOS
120
4.3 Deep Level Transient Spectroscopy Study of Ge MOS Capacitors
capacitors. DLTS is particularly suited to investigate semiconductor bulk traps.

The main intention of the DLTS work was to evaluate the use of the DLTS tech-
nique for Ge capacitors. First the DLTS principle will be elaborated after which DLTS
measurements of the samples are analyzed. Then the use of the DLTS technique for
interface trap extraction is evaluated.
4.3.2 Theory of DLTS and Fourier Transform DLTS, Devices and

Measurement Setup
Theory Deep level transient spectroscopy [16] makes use of gate voltage pulses in
combination with gate capacitance measurements as a function of time. These mea-
surements are done as a function of temperature in a liquid Helium cryostat to study
interface traps and semiconductor bulk traps.
V Vpulse
Vquiescent
t
C DLTS transient
t
Figure 4.19: The voltage pulse shape used in DLTS measurements showing
the pulse voltage and the quiescent voltage (top). The corresponding capacitance
transient is shown in the bottom.
The principle of DLTS is illustrated in figures 4.19 and 4.20. The quiescent voltage
(see figure 4.19) is chosen so the bands show more bending than at the pulse voltage
(see figure 4.19). At the quiescent voltage less bulk traps will be charged than at the
pulse voltage. When the pulse voltage is applied bulk traps will be filled very rapidly
by means of capture (the pulse voltage is chosen so there are sufficient majority carriers
for fast capture). The capture occurs nearly instantaneously. When the voltage is
returned to the quiescent voltage level the filled bulk traps are discharged by means
of the much slower emission process and the MOS capacitor returns more slowly to
its equilibrium state. As a result the capacitance will show a transient back to the
quiescent voltage level capacitance:
C(t) = C0 − ∆C exp(−t/τe ) (4.7)
The emission time constant, τe , determining this transient is given by:
τe = [vth σNef f exp(−q∆E/kT )]−1 (4.8)
121
The time constant behavior as a function of temperature is used to determine the bulk
trap’s energy level and ∆C can be used to determine the trap’s density which will be
treated in a later subsection. The influence of gate leakage and oxide trapping will
not be treated here. Gate leakage in the considered samples was low and hysteresis
due to oxide charge trapping was limited.
E E E
Ec Ec
Ef Ef
ET ET
X X X
Figure 4.20: Band diagrams showing the principle of DLTS measurements. At

the quiescent voltage the most band bending occurs and a lot of bulk traps are
empty (left). When the pulse voltage is applied bulk traps are rapidly filled by
means of capture (middle). When the voltage is switched back to the quiescent
voltage the carriers in the bulk traps are slowly emitted to the majority carrier
band.
In conventional DLTS [16] the capacitance difference is measured between two

fixed times t1 and t2 : ∆Cc = C(t2 ) − C(t1 ). This difference shows a peak as a
function of temperature as illustrated in figure 4.21. At the peak the τe of the trap
level is identical to the rate window τe = tw = (t2 − t1 )/ ln(t2 /t1 ). When one varies
the rate window one obtains a relation τe (T ) from which the trap energy level can be
obtained via an Arrhenius plot.
In Fourier transform DLTS the entire transient is recorded digitally and a Fourier
transform is used to obtain the time constant. The Fourier transform is taken of the
following function:
t + t0
f (t) = At exp(− )+B (4.9)
τ
where A is the amplitude, B the offset, τ the time constant, and t0 a time offset. For
this function the following Fourier coefficients are obtained:
2At
a0 = exp(t0 /τ )(1 − exp(−TW /τ ))τ + 2B (4.10)
TW
1
2At
an = exp(t0 /τ )(1 − exp(−TW /τ )) 1 τ 2 2 (4.11)
TW τ 2 + n ω0
2At nω0
bn = exp(t0 /τ )(1 − exp(−TW /τ )) 1 (4.12)
TW τ 2 + n2 ω02
where TW is the period of the pulse signal and ω0 is 2π/TW . Based on these coefficients
the amplitude and time constant of the transient can be obtained:
1 2 2
TW exp(t0 /τ ) τ 2 + n ω0
At = bn (4.13)
2nω0 1 − exp(−TW /τ )
122
1 bn
τ= (4.14)
nω0 an
The application of the Fourier transform on the measured capacitance transients

allows to obtain the time constant at different temperatures and without the need to
make use of different rate windows as in conventional DLTS.
t
t1 t2
Figure 4.21: Schematic of the capacitance transient temperature dependence.
As the temperature increases the time constant becomes shorter and the exponen-
tial decays faster. As the temperature is increased the difference in capacitance
between t1 and t2 will show a maximum.
Devices and Setup The devices considered were fabricated on p-type bulk Ge sub-
strates with a doping level of 1×1014 cm−3 [17]. After cleaning, 4 monolayers of Si
were grown followed by oxidation. Then 4 nm of HfO2 was deposited using Atomic
Layer Deposition (ALD). No O2 Post Deposition Anneal (PDA) at 400◦ C for 1’ was
given for the samples in this experiment. The effective oxide thickness (EOT) of the
capacitors is 1.4 nm. Transistors corresponding to this gate stack with PDA (devices
not measured with DLTS) were made with EOT of 2.6 nm. The 0.18 µm pMOSFET
drive current is 300 A/µm at 1 V gate overdrive with a drain-to-source voltage of -1
V. For a 0.15 µm nMOSFET the drive current is 45 µA/µm at the corresponding
voltages.
FTDLTS measurements were performed for the p-type sample pulsing from deple-
tion to an accumulation gate voltage of -2 V. Four simultaneous DLTS measurements
had quiescent gate voltages of 0.5, 1, 1.5, and 2 V. The period of the measurement
was set to 51.2 ms and the pulse time to 1 ms. Capacitance transients were mea-
sured at the frequency of 1MHz. The Capacitance-Voltage characteristics at different
temperatures at 1MHz can be seen in figure 4.22. The area of the p-type sample was
3.7×10−4 cm2 .
4.3.3 Analysis of DLTS Measurements

The obtained DLTS spectrum, the b1 coefficient versus temperature [18], is shown in
figure 4.23 for a quiescent voltage of 1 V. The spectrum shows a peaked response. A
rule of thumb [19] says that the peak temperature of the b1 coefficient corresponds
123
120
100
Capacitance [pF]
80 Temperature [K]
5
13
21
60 36
53
76
111
40 134
161
192
223
20 253
-2 -1 0 1 2
Gate voltage [V]
Figure 4.22: Capacitance-Voltage characteristics of the p-type Si-passivated

HfO2 Ge MOS capacitor at different temperatures. The large voltage shift in the
C-V as a function of temperature indicates a large interface trap density.
roughly to a trap energy of 2Tpeak meV relative to the majority carrier band. The
spectrum indicates a trap near midgap.
The b1 coefficients of the different quiescent voltages are shown in figure 4.24.
Arrhenius plots corresponding to the main peak at the different quiescent voltages of
0.5, 1, and 1.5 V yielded energy levels of 170 meV, 180 meV, and 210 meV above the
valence band, resp. This shows a defect peak to be present at about 0.2 eV above
the valence band. The shoulder evolving into a side peak as the quiescent voltage is
increased shows energy levels of 320 meV, 290 meV and 310 meV for the quiescent
voltages of 1, 1.5 and 2 V. This shows a side defect peak level to be present at about
0.3 eV above the valence band.
Semiconductor bulk traps were suspected to be present possibly due to Hf indiffu-
sion in germanium during the HfO2 deposition. For bulk traps the peak temperature
is known to be constant when varying the quiescent voltage. In this case the peak tem-
perature clearly varies with quiescent voltage, which is an indication of the presence
of interface traps and not bulk traps.
It is however possible that a bulk trap signal is dominated by the interface trap
contribution since these Ge MOS capacitors have a high interface trap density. Hence
the investigation of MOS capacitors for semiconductor bulk traps with DLTS is not
ideal.
DLTS has however shown to be suitable to investigate semiconductor bulk traps
induced by Ni indiffusion in NiGe Schottky junctions[20].
The experiments presented here were carried out on early experimental Si-passivated
Ge capacitors which were unoptimized. Most likely extra interface defects were
124
0.5
0.4
0.3
b1 [pF]
0.2
0.1
0.0
-4 2
p-type A = 3.7x10 cm
-0.1
-0.2
50 100 150 200 250
T [K]
Figure 4.23: DLTS spectrum of the p-type Si-passivated HfO2 Ge MOS-

capacitor. It shows the b1 coefficient of the Fourier transform DLTS [18]. There
is a trap level at midgap. Arrhenius analysis shows the trap level to be at 180
meV above the valence band.
0.6
Quiesce nt vo ltage
0.5 0.5 V
1V
0.4 1.5 V
2V
b1 [pF]
0.3
0.2
0.1
0.0
-0.1
80 100 120 140 160 180 200 220
T [K]
Figure 4.24: The DLTS spectrum (b1 coefficient as proposed by Weiss et al.
[18]) for different quiescent voltages indicating the traps to be interface traps.
125
present due to for example the incomplete knowledge of the critical timing of the
processing of the gate stack. The most important factor is the exposure of the grown
Si layer to clean room air. Hence these experiments are not used to draw conclusions
on the properties of Si-passivated Ge MOSFETs in general. No signature of semicon-
ductor bulk traps was found in the samples but DLTS is not an ideal tool to analyze
bulk trap behavior in Ge MOS capacitors due to the high interface trap density.
4.3.4 Evaluation of DLTS Applicability for Ge MOS Capacitors

In this subsection the feasibility of interface trap density extraction with DLTS will
be treated. Interface trap density was extracted using the following equation [21][22]
:
∆C
Dit (E) = εs Cox N kT ln(t2 /t1 ) (4.15)
C03
in which C0 is the capacitance measured at the quiescent voltage. ∆C is the cor-
relation signal or (C(t1 ) − C(t2 )) in which C(t) is the capacitance transient versus
time and t1 and t2 are the chosen sampling times for conventional DLTS [16]. ∆C
can be obtained from the Fourier transform DLTS coefficients a1 and b1 given by the
following equations :
∆C = At (exp(−t1 /τ ) − exp(−t2 /τ )) (4.16)

1 2
TW τ 2 + ω0
At = b1 (4.17)
2ω0 1 − exp(−TW /τ )
1 b1
τ= (4.18)
ω0 a1
t1 and t2 were chosen within TW and the extracted density was found insensitive
to the choice of these parameters as expected. The energy was derived using the
following equation for p-type germanium :
µ ¶
ep
E = −kT ln (4.19)
gσp T 2 1.05 × 1021
In which ep = 1/τp and τp =22.127 ms = TW /2, the capture cross section σp was
assumed to be 1×10−15 cm2 , g is the degeneracy factor and was taken to be 4.
Combining equations 4.17,4.18,4.16 with equation 4.15 converts equation 4.15 to
be usable for Fourier Transform DLTS measurements. The result is shown in figure
4.25. For the quiescent voltages of 0.5 and 1 V a tail appears toward the valence band
edge. The tail disappears at the higher quiescent voltages. Near midgap the extrac-
tions from the DLTS measurements at the different voltages do not agree indicating
the lack of validity of the used method. The energy of the peak and side peak are
higher by about 0.01-0.06 eV than deduced from the Arrhenius plots and vary with
quiescent voltage. Equation 4.15 assumes the interface trap capacitance to be small
compared to the oxide capacitance [21] which is clearly not the case, judging by the
very large temperature dependent C-V shifts in figure 4.22. The presence of large
amounts of interface trap densities prevent the extraction of interface trap density
126
4.4 Charge Pumping Applicability on Ge MOS
with the relatively straightforward equation 4.15. It is clear that no consistent ex-
tractions can be made with this technique from the measurements. Precise interface
trap density extractions with DLTS are not possible using the proposed easy-to-use
formula for high trap densities.
1
Extractred interface state density [a.u.]
Quiescent voltage
0.5 V
0.1
1V
1.5 V
2V
0.01
0.001
0.0001
0.1 0.2 0.3 0.4 0.5 0.6
Valence band offset [eV]
Figure 4.25: Interface trap density versus energy extracted from the DLTS
measurements separately derived for each quiescent voltage. The large disagree-
ment and the presence of the tail near the valence band indicate the invalidity of
the used method.
4.3.5 Conclusions
Using DLTS measurements the existence of a midgap interface trap peak for Si-
passivated HfO2 Ge capacitors was shown for unoptimized samples. More impor-
tantly it is clear that the extraction of the interface trap density is not feasible with
a relatively straightforward method for large interface trap densities. No signature of
semiconductor bulk traps was found with DLTS measurements in the samples inves-
tigated. However, in the presence of high Dit also DLTS’ asset, the characterization
of semiconductor bulk traps, is jeopardized. It is clear that DLTS measurements
are not preferable to conductance measurements for Dit (E) measurements of typical
Ge/III-V samples.

4.4.1 Introduction
Charge pumping, one of the most reliable and sensitive techniques for analyzing the
electrical properties of a semiconductor-dielectric interface, is evaluated for germa-
nium. When charge pumping is used on Ge as it is used on Si/SiO2 (300K, 100ns
transition times) the method can underestimate the total interface trap density be-
cause interface traps near the band edges are not measured.
These devices show performance benefits compared to Si MOSFETs [23] and an
interface trap distribution deviating significantly from Si/SiO2 MOS [24]. This makes
127
the devices interesting and relevant to study how, and if, charge pumping can be
applied on Ge MOSFETs to extract Dit (E).
In this section charge pumping is introduced and the consequences of switching
from a Si substrate to a Ge substrate will be investigated. On the basis of this theory
issues of charge pumping on Ge MOS are analyzed. Modified charge pumping meth-
ods are proposed for germanium MOS to deal with the involved issues. Afterwards
experimental results at room temperature on Ge MOSFETs will be discussed. Finally
the proposed charge pumping methods at low temperature and for short transition
times will be discussed experimentally.
4.4.2 Charge Pumping Theory and Devices

4.4.2.1 Basics
A charge pumping current arises in a MOSFET between bulk terminal and S/D
due to the interface traps when a gate voltage pulse train is applied [25] (for the
setup see figure 4.26, left and center). The charge pumping phenomenon occurs
when charging and discharging of interface traps during a gate voltage ramp cannot
maintain the equilibrium Fermi-Dirac distribution of trapped carriers dictated by the
Fermi level (charge pumping only occurs in non quasi-static conditions)[26]. The
direct relation of the charge pumping current to the interface traps allows a reliable
and straightforward characterization of the interface traps. The charge pumping
current is measured with a DC ammeter and hence charge pumping measurements are
very sensitive and allow the characterization of sub-micron devices and trap densities
down to 1×108 cm−2 eV−1 which is not possible with the conductance method.
A standard charge pumping setup (see figure 4.26, left) was used for measurements
with transition times down to 100ns. Charge pumping measurements with rise and fall
time down to 6ns without making use of RF structures were carried out by making
use of a system with ∼ 1GHz bandwidth similar to the setup used for fast Q-V
measurements [27] (see figure 4.26, right). The oscilloscope and pulse generator are
50Ω terminated and cables with 1GHz bandwidth are used. The shields of the probes
are connected in the probing area, which is kept within an area with a 2.5cm radius.
The bulk terminal is linked to the parameter analyzer terminal while the source and
drain terminals are grounded to the shield.
The first order charge pumping theory [25] explains the charge pumping effect as
follows: When a pMOSFET is pulled into accumulation electrons will flow from the
substrate into the channel region where a fraction of them will fill the interface traps.
When the device is pulled back into inversion the electrons in the channel region
drift back into the substrate but the electrons in the interface traps will recombine
with the holes coming from the S/D. This gives rise to a net flow of negative charge
from substrate to S/D. This charge pumping phenomenon gives rise to a current
proportional to the frequency of pulses (f):
Icp = qAf Dit ∆E (4.20)
where Dit is the mean interface trap density over the energy range ∆E = EF,inv −
EF,acc , where EF,inv is the Fermi level position in inversion and EF,acc the position
in accumulation.
128
scope pulse
generator Vpulse
VA
tr tf Vbase
A DC ammeter
Figure 4.26: Charge pumping setup (left). A gate voltage pulse train is applied
with source and drain grounded and the resulting bulk current is measured. The
charge pumping pulse shape is shown (middle) indicating the transition times:
the fall time (tf ) and the rise time (tr ) and also the amplitude (VA ), pulse voltage
(Vpulse ) and base voltage (Vbase )(middle). High frequency setup used for charge
pumping with transition times down to 6ns (right).
In the first order theory all electrons in the interface traps between the inversion
Fermi level position and the accumulation Fermi level position are provided from the
substrate during the switch from inversion to accumulation and recombine with holes
from S/D when switching from accumulation to inversion in a pMOSFET. However,
this is only the case for tr , tf → 0 (see figure 4.26, center, for the pulse shape). The
finite time taken to switch to accumulation allows holes to flow from traps to S/D
instead of the substrate. The finite switching time also allows part of the trapped
electrons to flow back into the substrate instead of recombining with holes from S/D
during the switch to inversion.
What happens during a charge pumping pulse is depicted in figure 4.27, top. When
a pMOSFET is switched from inversion to accumulation at first holes are emitted
from the traps to the valence band to accommodate for the Fermi level change. This
emission can keep up with the rate of change in the Fermi level. At a certain point
the emission process is no longer capable of evacuating carriers sufficiently fast from
the traps to keep up with the changing Fermi level and the equilibrium distribution
of carriers in the traps can no longer be maintained (a non quasi-static condition
occurs). This continues until the flatband voltage is reached and electron capture
is turned on. The fill level of the traps right before the capture turns on is called
the hole emission level (Eem,h ). When switching from accumulation to inversion the
inverse process occurs. At first electron emission can keep up with the Fermi level
movement in time and at a certain point emission can no longer keep up. The fill level
of the traps right before hole capture is turned on (at the threshold voltage) is called
the electron emission level(Eem,e ). The net current flowing between source/drain and
substrate is a result of the difference between carriers drained from the traps to a
particular band by capture and emission (see figure 4.27, bottom).
With these physical processes at the heart of the charge pumping phenomenon
in mind the charge pumping current can be understood to be proportional to the
129
Emission Capture Emission Capture
Ec
Vfb Eem,e
-
+
- - Ef
+ - -
+ -
+ -
Ev +
Eem,h
-
+
+
VT
Equilibrium Non-equilibrium Equilibrium Equilibrium Non-equilibrium Equilibrium
-
Eem,e
-
net
Eem,h current
+ +
Figure 4.27: Schematic of the processes occurring during charge pumping.
130
amount of interface traps located in between the electron and hole emission levels
(Eem,e and Eem,h resp.) [26]:
Z Eem,e
Icp = qAf Dit (E)dE (4.21)
Eem,h
The emission levels for germanium are shown in figure 4.28 for a capture cross sec-
tion of 5×10−17 cm−2 . The expressions generally used for charge pumping using the
Boltzmann distribution are given by[26]:
dt ni
Eem,h = Ei + Vt ln(vth,h σh ni |Vf b − VT | + ) (4.22)
dV N
dt ni
Eem,e = Ei − Vt ln(vth,e σe ni |Vf b − VT | + ) (4.23)
dV N
Where dt/dV is the inverse rate of change of gate voltage which is directly related to
the transition time. The emission levels depend on the transition time as shown in
figure 4.28. When the transition is shorter more traps will be measured with charge
pumping.
Figure 4.28: Electron and hole emission levels calculated with Boltzmann
[26] and Fermi-Dirac statistics as a function of pulse edge slew rate at different
temperatures for germanium. Equivalent emission levels derived from detailed
simulations are also shown.
Charge pumping measurements are usually done by means of a base level sweep.
This is illustrated in figure 4.29. The amplitude of the pulse is maintained while the
base level is swept. The charge pumping current as a function of base level has the
typical hat shape. For a pMOSFET the current is negative and the hat inverted.
131
Icp
VT - VA Vfb Vbase
VT
Vfb
Vpulse
VA
Vbase
Figure 4.29: Schematic of a base-level scan in charge pumping for an nMOS-

FET. For a pMOSFET the current is negative. A charge pumping current occurs
when the pulse voltage sweeps through both the threshold and flatband voltages.
4.4.2.2 Review of Charge Pumping Theory for Germanium MOSFETs

The validity of the emission level charge pumping theory [26] was checked for germa-
nium MOSFETs. Previously, it was shown that the conductance method is jeopar-
dized by germanium’s small bandgap compared to silicon [24][28]. Here it is inves-
tigated whether germanium’s small bandgap also jeopardizes charge pumping mea-
surements.
In the emission level approximation [26] it is assumed that at any time during the
application of a gate voltage pulse only one type of communication (either emission
or capture) with one of the bands is dominant. Simulations which take into account
all four mechanisms at any time during a charge pumping cycle are done to verify
whether this approximation still holds for germanium. The capture and emission rate
equation is integrated over time. The integrated equation is:
df
= −ce,em f + ce,cap (1 − f )n + ch,em (1 − f ) − ch,cap fp (4.24)
dt
Where f (E) is the fraction of traps filled, ce,em the electron emission probability, ce,cap
the electron capture probability, ch,em the hole emission probability, ch,cap the hole
capture probability, n the electron density and p the hole density. The transition times
were varied and a simulated curve showing the fraction of traps contributing to Icp
across the bandgap is shown in the figure 4.30. A constant Dit of 1×1012 cm−2 eV−1 ,
a capture cross section of 5×10−17 cm−2 and an amplitude (VA ) of 1.3 V is used at
300K.
Equivalent emission levels can be defined as those levels that give rise to the same
measured integrated interface trap density [cm−2 ] as the profiles in the figure 4.30. It
is clear that the equivalent emission levels from simulation and from the emission level
132
1.0
Fraction of traps pumped

0.8
0.6
0.4 1 µs/V
320 ns/V
100 ns/V
0.2 32 ns/V
0.0
0.1 0.2 0.3 0.4 0.5
E-Ev Energy [eV]
Figure 4.30: Simulation of the fraction of traps giving rise to charge pump-
ing current taking into account all emission and capture processes at 300K for
different edge slew rates.
approximation are in good agreement (see figure 4.28) showing that the emission level
approximation holds for charge pumping on MOSFETs with small bandgap materials
like germanium.
At 300K, only a small portion of the Ge bandgap is scanned and a too small
part of the bandgap is scanned. The interface trap distribution can be characterized
across a wider portion of the bandgap for germanium MOSFETs by measuring at
lower temperature. This is possible because the electron and hole emission levels
move closer to the band edges (figure 4.28) as a result a monotonous increase in Icp
is expected when lowering the temperature [29].
An alternative method to characterize the interface trap distribution across a
wider portion of the bandgap is to measure with shorter transition times. According
to emission level theory based on Boltzmann statistics [26] lowering the transition
times below 100ns at 300K will not make much difference because of the saturation
of the emission levels near flatband and threshold voltage (see figure 4.28). Using
Fermi-Dirac statistics, appropriate for ultra-thin dielectrics and high fields, one sees
that it is possible to scan further into the gap using charge pumping with shorter
transition times at 300K (figure 4.28).
4.4.2.3 Devices
The devices considered are Si-passivated Ge pMOSFETs [23] with TaN-gates fabri-
cated on n-type Ge-on-Si substrates (a 2 µm thick epitaxially grown and fully relaxed
Ge layer on a p-type Si substrate) with a doping level of 3×1016 cm−3 defined by
implantation. After appropriate surface cleaning, a ∼ 6 ML Si layer is deposited fol-
lowed by an ozone oxidation forming 0.4nm of silicon oxide. Then an ALD 4nm HfO2
layer is deposited. The EOT of these MOSFETs is 1.4nm as determined by split-CV.
133
4.4.3 Characteristics
4.4.3.1 Room Temperature
300K base level sweep charge pumping characteristics of Si-passivated germanium
MOSFETs are shown in figure 4.31. A typical charge pumping hat is observed (neg-
ative currents for pMOS) which shows proper frequency scaling. Sufficiently high
frequencies (500kHz- 2MHz) were chosen to avoid the influence of traps in the high-κ
oxide [6] in order to study the interface traps at the Ge-Oxide interface only.
Charge pumping current [A/cm ]
2
0.0
-0.2
-0.4
Transition time
100 ns
-0.6 1.3 V amplitude
2 MHz
1 MHz
-0.8 500 kHz
-1.0 -0.5 0.0 0.5

Base Level Voltage [V]
Figure 4.31: Ge MOSFET charge pumping characteristics at 300K show the

typical hat shape and frequency scaling.
The magnitude of the charge pumping signal shows an integrated interface trap
density of 2×1012 cm−2 at a transition time of 100ns while the total interface trap
density was previously determined to be ∼ 1-2×1013 cm−2 across the bandgap using
full conductance measurements [24]. The experiment is hence in agreement with
emission level theory since only the interface traps near midgap are measured with a
regular charge pumping measurement.
Transition time sweep measurements were done (see figure 4.32) in which the tran-
sition time is varied and all other parameters of the charge pumping pulse shape were
kept constant. The measurements show that the charge pumping current becomes
zero for a specific transition time. This specific transition time corresponds to the
transition time at which the hole and electron emission levels coincide (see figure
4.28) and confirm the capture cross section value of ∼ 5×10−17 cm−2 assumed in our
simulations. The capture cross section is obtained by equating equation 4.22 and 4.22
and solving for the capture cross section.
4.4.3.2 Temperature Dependence

Measurements below 300K are done to characterize the interface trap distribution
across a wider portion of the bandgap for germanium MOSFETs (see figure 4.33). A
100ns transition time and 1.3V amplitude are used. The current is found to increase
continuously in magnitude with decreasing temperature. At 80K an integrated inter-
134
Figure 4.32: 300K transition time sweep showing the point at which the charge
pumping current becomes zero. This corresponds to the time at which the hole
and electron emission levels coincide in figure 4.28.
0.0
-0.2
Icp [Acm ]
-2
-0.4
-0.6
-0.8
100 150 200 250 300

Temperature [T]
Figure 4.33: Charge pumping current versus temperature increases in magni-

tude with decreasing temperature.
135
face trap density of 6×1012 cm−2 is extracted showing that interface traps located
closer to the band edges are measured at low temperature. Low temperature mea-
surements yield a more accurate and complete extraction of interface trap density
than possible at 300K.
The temperature dependence of the charge pumping current is given by the fol-
lowing equation:
Icp (T ) = −aT − bT ln(T ) + c (4.25)
" r #
√ 3k |VT − Vf b | p
a = 2qkf Ag Dit ln σn σp Ki tr tf (4.26)
m ∆Vg
b = 4qkf Ag Dit (4.27)
c = qf Ag Dit Eg (4.28)
√
where Dit , the average interface trap density, and σn σp , the geometrical average of
the electron and hole capture cross section are assumed independent of temperature.
Ki is a temperature-independent constant originating from the expression for ni (T ),
m is the appropriate effective mass.
4.4.3.3 Short Pulse Times

Another approach enabling characterization of the interface trap density across a
wider portion of the bandgap is reduction of charge pumping transition times (see
figure 4.28). For this purpose a high frequency setup (see figure 4.26) is used with a
∼ 1GHz bandwidth enabling transition times down to 6ns.
Figure 4.34: Charge pumping current as a function of rise or fall time down to
6ns. Only the rise or fall time was changed, the other transition time was kept
to 6ns.
Experiments show that indeed trap densities closer to the band edges can be ex-
tracted using charge pumping (see figure 4.34) at 300K. A clear increase in Icp is
evident when decreasing the fall time. Changing the fall time changes the electron
136
Figure 4.35: The extracted characteristics using a least squares linear fit are
shown in this figure compared with an extraction using the full conductance
method. The slight difference might be due the fact that these measurements
were done on different samples of different lots. The Si thickness shows variations
of ± 1 ML from lot to lot.
emission level which is located near the conduction band where trap density is high.
The high density results in large changes in Icp with changing emission level. Extrac-
tions of interface trap density were done from the charge pumping transition time
sweeps. A line is fitted to the charge pumping current as a function of energy, which
is related to the logarithm of the transition time (figure 4.34). The linear fit guaran-
tees a robust extraction. The extracted interface trap density from the rise and fall
time sweeps corresponding to the valence and conduction band side are indicated in
figure 4.35. The extractions (figure 4.35) from charge pumping measurements clearly
confirm the asymmetric nature of the interface trap density as previously found using
the full conductance method, which is the method resolving the issues of the conduc-
tance method [24]. Moreover, the correspondence with the full conductance method
results proves that using short transition times down to 6ns indeed allows probing the
interface traps closer to the band edges at 300K.
4.4.3.4 Limitations
A disadvantage of the use of charge pumping with experimental structures is that

junction leakage and noise can jeopardize charge pumping measurements. Especially
large and defective junctions are a problem as was encountered with early Ge MOS-
FETs. The small voltage difference between the ground of S/D and bulk can be
sufficient to cause leakage currents to dominate charge pumping currents. For charge
pumping measurements to be effective it is preferable to have well optimized and
small junctions. This is not a requisite for full conductance measurements.
At low temperatures issues can occur for charge pumping related to the electrical
contacts. Charge pumping measurements are sensitive to excessive series resistance
since the measured DC currents are the result of the integration of pulsed currents of
high magnitude during the transition times. The series resistance might increase at
137
low temperature due to freeze-out of Schottky contacts and defect related junction
currents in the Ge-on-Si substrates used. For some samples a decrease in charge
pumping current with temperature was measured.
4.5 Conclusions
In this chapter large signal analysis techniques are treated and the toolset is expanded
to evaluate MOS properties beyond admittance based techniques. The broader toolset
allows for complementary characterization and confirmation of results by using multi-
ple techniques. A pulsed Q-V/C-V technique is introduced which solves the issues the
conventional pulsed C-V and RF C-V methods have when dealing with sub-nm EOT
gate stacks. For DLTS, it is clarified that the extraction of the interface trap density
is not feasible with a relatively straightforward method for large interface trap den-
sities. No signature of semiconductor bulk traps is found with DLTS measurements
in the samples investigated. However, in the presence of high Dit DLTS’ asset, the
characterization of semiconductor bulk traps, is jeopardized.
Charge pumping characteristics of germanium MOSFETs are investigated and
the validity of emission level theory is confirmed for Ge MOSFETs. From theory and
experiment it is clear that 300K charge pumping with transition times down to 100ns,
as used for Si/SiO2 can only quantify the amount of interface traps in a fraction of the
bandgap near midgap for Ge. This explains why Si/SiO2 charge pumping practices
can lead to an underestimation of the actual total trap density in Ge.
To increase the measured fraction of the bandgap low temperature measurements
can be used. By using transition times down to 6ns the interface trap density is
extracted closer to the band edges on germanium MOSFETs at 300K. This enables a
convenient 300K evaluation of interface trap density across a large part of the bandgap
for process and reliability evaluation purposes. The obtained results are found to be
in agreement with full conductance method results.
138
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142
Chapter 5
Interface Passivation and

Characteristics of Si-passivated
Ge MOSFETs
5.1 Introduction
This chapter analyzes the Si-passivated Ge interface and its impact on MOSFET
characteristics. The nature of the interface trap defects involved is elaborated. A
host of MOSFET parameters affected by surface passivation and their importance
are evaluated. The question is answered what the maximum allowed interface trap
density can be without affecting device performance and quality and which parameters
play a role in this maximum allowed density.
Interface trap extractions were done on Si-passivated Ge MOSFETs for different
Si-layer thicknesses and for different precursors. In a second section the proposed
interface trap density model is elaborated in detail. Then the threshold voltage tuning
possibilities are elaborated for the Si-passivated Ge MOSFET followed by a discussion
of mobility extraction and characteristics. The mobility limiting properties of the
interface passivation are discussed. The cause of the strongly degraded nMOS mobility
for the Si-passivation is also worked out. Further properties which are considered and
discussed are the parameter variability (such as the threshold voltage variability),
EOT and leakage issues of the Si-passivated MOSFETs. Finally some reliability
properties are worked out and conclusions are drawn on the quality limiting properties
of Si-passivated Ge MOSFETs which are caused by a lack of surface passivation.
Perspectives are given for further progress for the Si-passivated Ge MOSFET.
5.2 Influence of Processing Conditions on Si-Passivation

5.2.1 Introduction
In this first section interface trap density distributions are determined for Si-passivated
Ge/high-κ pMOSFETs for different Si thicknesses and for Si growth at low temper-
143
5. SI-PASSIVATION OF GE MOSFETS
ature and high temperature. Based on the extracted interface trap densities and
other extracted device parameters such as threshold voltage, CET, drive current and
mobility important conclusions can be drawn which corroborate a first model of the
Si-passivated Ge MOS interface.
As it was shown in chapters 2 and 3, applying conventional interface trap extrac-
tion techniques on alternative substrates can lead to incorrect conclusions. We showed
[1] how the conductance method can be adapted and made reliable for novel semi-
conductor/dielectric interfaces. In this chapter we use the full conductance method
to extract the interface trap density distributions accross the Ge bandgap.
In this section first the Si-passivation and the influence of the Si-passivation pro-
cessing on the interface trap density is discussed followed by an analysis of drive
current, mobility and threshold voltage trends correlated with the interface trap den-
sity. Finally, we investigate the influence of the post metallization anneal on the
interface passivation.
5.2.2 Si-Passivation
Germanium pMOSFETs were investigated with Si-passivation (3 to 8 monolayers),
∼ 0.4 nm of oxide, and 4 nm ALD HfO2 [2]. The intention of the Si-passivation
is to insert a Si/SiO2 interface into a Ge/high-κ gate stack to bypass the interface
passivation issues of growing or depositing a dielectric directly on germanium.
In the gate stack sequence the Ge surface is first cleaned in an SC1 solution and HF
solution consecutively, followed by a pre-epi H2 bake at 650◦ C in the epi-reactor. The
Ge surface is passivated with an epitaxial Si layer of varying thickness using the silane
precursor at 500 ◦ C. The nominal thickness, which is used throughout this work, can
be different from the actual Si thickness because variations from lot-to-lot in the
Si thickness exist for fixed processing parameters. These processing parameters are
expected to result, on average, in the nominal thickness. Low temperature (350◦ C) Si
growth with a more reactive trisilane precursor (SilcoreT M ) is used as an alternative
to silane at 500 ◦ C to lower the Ge surface segregation in the Si layer [3], [4].
The Si layer is partially oxidized with aqueous ozone, resulting in a 0.4 nm layer of
SiO2 . To avoid further oxidation, this Si-passivation layer is immediately capped by a
4 nm ALD HfO2 gate dielectric from an ASM Pulsar 2000 reactor, followed by 10 nm
TaN and 80 nm TiN PVD depositions. At the very end of the MOSFET processing
a post metallization anneal is done at 350 ◦ C, 20 min anneal in hydrogen[2].
5.2.3 Influence of Si Thickness and Precursor: Relation of Interface

Traps with Mobility, Drive Current and Threshold Voltage
Interface trap density extractions on Si-passivated Ge pMOSFETs with different sili-
con thicknesses grown using the silane and SilcoreT M precursor are shown in figure 5.1.
In figure 5.2 interface trap densities of Si-passivated pMOSFETs using the silane pre-
cursor are shown in detail for more thicknesses. It is clear that the Ge/Si/SiO2 /HfO2
gate stack does not show the excellent Si/SiO2 gate stack passivation properties. One
is hence not able to obtain the excellent Si/SiO2 passivation properties by simply
inserting a Si/SiO2 layer into a Ge/high-κ gate stack. Interface trap density is higher
than for the Si/SiO2 gate stack interface. Figure 5.3 shows Dit (E) integrated over
144

-2
-1
14
10 14 TM
-1
3 ML Silcore
-2
6 10
4
3ML silane
2
77 K 10
13
13 153 K 80 K
10 150 K
6
228 K
300 K 230 K
4
12 300 K
10
0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6
-2
-1
14 5ML silane 5 ML Silcore

TM
10
77 K 14
-2
-1
6 10 80 K
153 K 150 K
4
228 K 230 K
2 300 K 300 K
13
13
10
10
6
4
12
10
0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6

-1
-2
14 7ML Silane 7 ML Silcore

TM
10
-2
77 K 14
-1
6 10 80 K
153 K 150 K
4
228 K 230 K
2 300 K 300 K
13
10
13
10
6
4 12
10
0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6
Figure 5.1: Extracted interface trap distributions of Si-passivated Ge pMOS-

FETs with different Si thicknesses (in monolayers, ML) and precursor using the
full conductance method done at 4 temperatures from 77K to 300K to cover the
entire bandgap.
145
the valence band half (Nit,val ) and the conduction band half of the bandgap (Nit,con ).
Several trends are apparent. Nit,val decreases with increasing silicon thickness. Nit,con
initially decreases with increasing silicon thickness but increases again significantly
for thicker silicon layers. Nit,val is lower for the low temperature SilcoreT M precursor.
The good reproducibility of these characteristics is illustrated in figure 5.4. One has
to keep in mind that variations of ± 1 ML of the actual thickness as compared to the
(plotted) nominal thickness can occur from lot to lot.
3ML
4ML
5ML 6ML
7ML 8ML
Figure 5.2: Complete set of extracted interface trap distributions of Si-

passivated Ge pMOSFETs using Silane precursor with different Si thicknesses
expressed in monolayers (ML) using the full conductance method. Full conduc-
tance measurements were done at 4 temperatures from 77K to 300K.
The device performance as a function of silicon thickness and precursor is shown

in figure 5.5. The mobility increases with increasing silicon thickness. The SilcoreT M
mobility is higher than the silane mobility for lower silicon thicknesses. For the
146
4 Effective Charged Traps

nMOS inversion
2
13
10
Nit [cm ]
-2
6
4
12
10 SiH4 Silcore
TM
6
Valence band half
4
Conduction band half
3 4 5 6 7 8
Grown ML
Figure 5.3: Integrated extracted interface trap distributions as a function

of grown Si thickness and precursor. Integration was done separately over the
valence band half (0 - 0.33 eV) and conduction band half (0.33 - 0.66 eV) of the
Ge bandgap. Effective charge for nMOS in inversion is also shown(see later in
this chapter).
Conduction band side Nit [cm ]
2 4
-2
Silcore MG08005 (1)

Silcore MG08005 (2)
Valence side Nit [cm-2]
13 2
10 Silane MG07039 (1)
Silane MG08005 (2) 13
6 10
5 8
4 6
3 4
2
2
12 Silcore MG08005 (1)

10 12
Silcore MG08005 (2)
10
8
6 6
Silane MG07039 (1)
5 Silane MG08005 (2)
4 4
3 4 5 6 7 8 3 4 5 6 7 8
Grown Si ML Grown Si ML
Figure 5.4: Nit characteristics are shown to be reproducible from lot to lot
(MG07039 and MG08005)and from measurement to measurement [(1) and (2)].
The different lots were measured approximately three months apart while differ-
ent measurements on MG08005 were done one week apart.
147
SilcoreT M precursor the improved mobility and CET translate into better drive cur-
rent at low silicon thickness. The low temperature Si-passivation is hence more ad-
vantageous for EOT scaling while maintaining high drive current and mobility.
600
←µ 2.4
Drive current [µA/µm]

500
Mobility [cm /Vs]
150
2.2
400
CET [nm]
2
100 2.0
300
Ion→
200 1.8
50 Empty: SiH4 CET→
Filled: Silcore
TM
100 1.6
0 0 1.4
3 4 5 6 7 8
Grown Si ML
Figure 5.5: Mobility, 100nm MOSFET drive current, and CET of Si-passivated
Ge pMOSFETs with varying Si thickness and different precursors.
The hole mobility trends correlate well with and can be explained by Nit,val (see
figure 5.4 and 5.5). These charged interface traps will scatter free carriers and reduce
mobility in inversion. Briefly, decreasing Nit,val results in increasing mobility when
the silicon layer is thickened, and Nit,val decreases resulting in a mobility increase
when switching to the low temperature precursor. Physically these trends correspond
to the Ge segregation. Thicker silicon layers and lower temperature growth will yield
less Ge at the Si/SiO2 interface [3] and result in less Nit,val and higher mobility. This
corroborates that a large part of Nit in the valence band half is located near the
Si/SiO2 interface and is caused by the presence of Ge at that interface. If the traps
were located near the Ge/Si interface such Si thickness dependence and precursor
dependence cannot be explained.
Nit,con does not show the same trends with thickness as Nit,val . The mobility
does not correlate with Nit,con . The increase of Nit,con should induce a mobility
decrease for thicker layers and this is clearly not the case. This suggests that the
conduction side traps are uncharged when the pMOS is biased in inversion, which
points to the acceptor nature of Nit,con . These acceptor traps will be neutral for
pMOSFETs at inversion bias and will not be affecting mobility significantly. Nit,con
also does not show a correlation with Ge segregation in the trends of Nit,con as a
function of thickness and precursor.
Threshold voltage behavior as a function of silicon thickness and growth temper-
ature for pMOS and nMOS is explained by the interface trap density. The electrical
properties are investigated by dividing the traps in the conduction band half traps
and valence band half traps. Each of these halves can be assigned a donor, accep-
tor or double acceptor nature (see figure 5.6). This is inspired on the Si/SiO2 case
where the conduction band half of the traps are acceptor traps and the valence band
half are donor traps. The acceptor/double acceptor/donor nature of these traps will
have a profound impact on the interface trapped charge and on the threshold voltage.
148
Si/SiO2 Ge/Si/SiO2 Ge/Si/SiO2

Dit Dit Dit
double
donor acceptor ? ? acceptor acceptor
Ev Ec Ev Ec Ev Ec
double
acceptor donor acceptor
Ec
Ef Ef Ef
- 0 0 + -- -
Ef Ef Ef
Ev
Figure 5.6: Schematic showing the division of the bandgap in the two halves
(top) inspired on the Si/SiO2 case where the conduction band half of the interface
traps are acceptors and the valence band half are donors. For the Si-passivated
case a double acceptor/acceptor configuration is found. A schematic is shown of
acceptor, donor and double acceptor trap charge states depending on the relative
Fermi level position(bottom).
149
Different configurations (acceptor, donor, etc.) for the valence and conduction half
interface trap density were selected and the resulting threshold voltages for pMOS
are calculated with the following equation:
³R RE ´
E
q EVgT ς(E)Dit (E)dE + 0 V T (ς(E) − 1)Dit (E)dE
VT = VT 0 − (5.1)
Cox
where VT 0 is the threshold voltage without the presence of interface traps, EV T is the
interface Fermi level position relative to the valence band at the threshold voltage.
ς(E) is -1 for double acceptors, 0 for acceptors and 1 for donors. These threshold
voltages were calculated making use of the extracted pMOSFET interface trap density
assuming a metal gate work function of 4.4 eV known from the corresponding Si
MOSFETs [5], and the oxide fixed charge was assumed ∼ 0 Ccm−2 as is approximately
the case for Si/SiO2 /HfO2 gate stacks [5]. The equation for nMOS is analogous.
These calculated threshold voltages are compared with the measured threshold voltage
(figure 5.7). Double acceptors (negatively charged traps when empty) in the valence
half and acceptors in the conduction half result in approximately matching pMOS
threshold voltages.
PMOS Vt calculated from

NMOS Vt calculated from
2.0 Dbl. Acc./Acc. 0.8
3.5 Acc./Donor
Threshold voltage [V]
Acc./Dbl. Acc.
Donor/Acc.
Dbl. Acc./Dbl. Acc.
3.0 Dbl. Acc./Acc.
1.5 Val. Half / Con. Half 0.6 Val. Half / Con. Half
Measured Vt 2.5 Measured
0.4 nMOS Vt
1.0
2.0
0.2
0.5 1.5
0.0 1.0
0.0 Silane TM
Silane
Silcore
3 4 5 6 7 8 9 3 4 5 6 7 3 4 5 6 7 8
Grown Si ML Grown Si ML Grown Si ML
Figure 5.7: Measured VT vs. grown Si thickness for pMOS silane (left),
pMOS silcoreT M (middle) and silane nMOS (right). The VT is shown which
was calculated based on the extracted interface trap densities for different
Donor/Acceptor/Double Acceptor configurations of traps in each bandgap half.
This configuration is also consistent with the pMOS mobility observations. In

inversion for pMOS, the acceptor and conduction band half traps will be neutral
and the double acceptor valence band half traps will be single negatively charged,
explaining why the mobility correlates with Nit,val and not with Nit,con . nMOS
threshold voltage also matches for this configuration (figure 5.7, right) for tSi < 7ML.
For tSi ∼ 7ML the conduction mechanism changes: electrons are most likely located
inside the silicon layer resulting in a downward threshold voltage shift induced by
the conduction band offset of the silicon layer. Electrons can be contained in the
Si layer for thicker thicknesses because only then quantum mechanical confinement
allows electrons to be situated in the Si layer. Because the Si layer shows a conduction
band offset with Ge the switching of conduction from the Ge to the Si layer induces
a threshold shift.
150
Finally, silane Si-passivated nMOS mobility increases with silicon thickness and
is smaller than 35 cm2 V −1 s−1 . This can also be explained by the trap density.
The interface trapped charge in inversion for nMOS (see figure 5.3 and the effective
trap density for nMOS, 2Nit,val + Nit,con due to resp. the double charged double
acceptor Nit,val and the single charged acceptor Nit,con ) decreases with increasing
silicon thickness and is much higher than the pMOS interface trapped charge (see
Nit,val in figure 5.3).
Mobility and threshold voltage behavior of Si-passivated Ge MOSFETs are ex-
plained by interface passivation and based on these observations an investigation of
the nature of the interface traps in the Si-passivated germanium interface was done.
A large part of the interface traps in the valence band half are located at the Si/SiO2
interface and are double acceptors. Note that these traps are denominated as dou-
ble acceptors based on their electrical characteristics and abstraction is made of the
physical structure of the trap sites. These valence side traps are caused by Ge at
the Si/SiO2 interface, present because of Ge surface segregation in the Si-layer. The
interface traps near the conduction band are found to be acceptors and not related
to Ge at the Si/SiO2 interface. This model of the Si-passivated interface obtained
experimentally will be worked out further in the next section 5.3.
5.2.4 Influence of N2 and H2 Anneal

After the introduction of a metallization step into the process flow of the Si-passivated
Ge MOSFETs considerable variations in drive current were found to be present linked
to an increased interface trap density. These variations and the related interface trap
density could be reduced by doing either a H2 anneal or N2 anneal[6] as post met-
allization anneals. The H2 anneal was chosen and was always used in the following
lots (among which the samples discussed earlier). Most likely these were extra inter-
face trap defects introduced by a process step which damages the Ge/Si/SiO2 /HfO2
interface.
The investigated pMOSFETs were made by epitaxially growing 4 monolayers of Si
on Ge, oxidizing the uppermost Si layer resulting in ∼ 0.4nm of oxide and depositing
4nm HfO2 with ALD [7]. The resulting EOT is 1.2 nm. Activation anneals were given
in N2 for 5’ at 500◦ C. After metallization N2 (400◦ C, 5’) and H2 (420◦ C, 20’, 5 h.
cool down in H2 ) anneals were given separately.
Investigation of the influence of N2 and H2 anneals shows that the ideal Si/SiO2
interface for the Si-passivated Ge with HfO2 is not present. Charge pumping mea-
surements and conductance measurements were performed on samples with no anneal,
separate H2 anneal, and N2 anneals and an H2 anneal after an N2 anneal.
Charge pumping measurements were done at a frequency of 4MHz and 1MHz,
with a transition time of 50ns and an amplitude of 1V. Proper frequency scaling of
the charge pumping current was observed on all samples. The interface trap density
was extracted using Nit = f Icp /q where q is the elementary charge. It is clear that
the extracted Nit does not correspond to all traps but only to traps near midgap.
The results of the charge pumping measurements are shown in figure 5.8. The
unannealed samples show a large spread. N2 and H2 annealed samples show a similar
reduction in interface trap density and reduction of spread on the interface trap
density.
151
12
3.5x10 300
Interface state density [1/cm ]

2 3.0
Peak mobility [cm /Vs]

2.5 250
2.0
200
1.5
1.0
2
150
0.5
0.0 100
no anneal N2 H2
Figure 5.8: Mobilities and interface trap density derived from charge pumping
measurements showing a comparable reduction in Nit due to N2 and H2 anneals.
-7
2.5x10
No anneal -7
H2 anneal
G/w [Ss/rad/cm ]
G/w [Ss/rad/cm ]
2.5x10
2
2
2.0
2.0
1.5
1.5
1.0 1.0
0.5 0.5
0.0
0.0 0.4 0.8 0.0 0.4 0.8
-7
2.5x10 N2 anneal
3.5 MHz
G/w [Ss/rad/cm ]
2
2.0 2 MHz
500 kHz
1.5 100 kHz
1.0
0.5
0.0 0.4 0.8

Gate Voltage [V]
Figure 5.9: G/ω for annealing treatments. Without anneal there are two
peaks, of which one or both are reduced by annealing.
152
5.3 Origin of Interface Traps in Si-passivated Germanium MOS
Conductance analysis was done using full conductance measurements. The ex-
tracted Dit will also represent the interface trap density near midgap. The averaged
conductance curves are shown in figure 5.9 for the four samples with different anneals.
In this figure it becomes clear that the valence band side peak seen at lower voltages
decreases in magnitude for all annealing treatments. Also the conductance at lower
frequencies decreases with all the annealing treatments. In fact, no peak is visible for
the annealed samples at 100kHz.
maximum vs. V
12
at 3.5 MHz
4x10 maximum vs. V
at 2 MHz
2.5G/w/q [eV cm ]
side peak vs. V

-2
at 3.5 MHz
3 maximum vs. V
-1
at 500 kHz
0
no anneal H2 N2
Figure 5.10: Summary of the G/ω data showing that the effect of the H2 and
N2 anneal is due to reduction of the side peak.
A summary of the G/ω results is given in figure 5.10. An extraction of interface

trap density by using Dit = 2.5G/ω/q shows that the Dit values are in the same
range as the charge pumping Nit values considering the different units. Figure 5.10
shows that the conductance measurements confirm the charge pumping results. The
decrease in Nit by the N2 and H2 anneals is attained by reduction of the interface
trap density near the valence band and by reducing the slower traps near midgap.
In figure 5.8 it is shown that annealing leads to an increased peak hole mobil-
ity. Conductance and charge pumping measurements (see figures 5.10 and 5.8) show
decreased midgap interface trap densities down to 5×1011 cm−2 using anneals. The
measurements show that N2 and H2 anneals provide a significant reduction in Nit .
The similar result for the H2 anneal as for the N2 anneal indicates that the defect
affected by the anneals is not a Pb type defect as found in Si/SiO2 . We speculate that
the variations in mobility or drive current associated with part of the interface trap
density are process induced damage to the interface which can be mended by N2 or
H2 anneals.
5.3 Origin of Interface Traps in Si-passivated Germa-

nium MOS
In this section the basic model for the interface traps in Si-passivated Ge MOSFETs is
elaborated further. The physical origins of the interface trap density are elaborated.
It is investigated why this interface does not behave like a Si/SiO2 interface as was
originally intended when inserting a Si/SiO2 layer into a Ge gate stack. Three main
153
contributions to the interface trap density are outlined: Ge diffusion and segregation,
quantization effects and dangling bonds.
5.3.1 Ge Diffusion and Segregation

The double acceptor interface trap density in the valence band half correlates strongly
with the Ge concentration at the Si/SiO2 interface as shown in section 5.2.3. This
indicates that the physical origin of these valence band side traps is related to the Ge
at the Si/SiO2 interface. The Ge reaches the Si/SiO2 interface during the epitaxial
growth of the Si layer by means of surface segregation and/or diffusion.
180000 6 ML 6000
160000 5 ML
4 ML 5000
140000
3 ML
120000 1 ML 4000
Intensity
100000
3000
80000
60000 2000
40000
TOFSIMS
Xe 350 eV 1000
20000
0 0
0 5000 10000 15000 20000
Depth (a.u.)
Figure 5.11: Ge (lower set of curves) and Si (upper set of curves) TOFSIMS
depth profiles. It is clear that the Ge concentration at the surface decreases with
increasing thickness. The grown Si thickness on a SiGe substrate is indicated in
monolayers.
TOFSIMS measurements show the effects of the different Si thicknesses and the
precursor on the Ge concentration throughout the Si layer. In figure 5.11 TOFSIMS
measurements are shown for different Si thicknesses for the silane precursor (500 ◦ C
growth temperature). As the thickness decreases the measured Ge concentration at
the Si surface increases. The peak on the left hand side of the graph could be the Ge
accumulated at the surface because of surface segregation. If we assume the absence
of SIMS artifacts then the measurements are in agreement with the presence of Ge
surface segregation.
In figure 5.12 TOFSIMS measurements are shown of a Si layer grown with the
SilcoreT M precursor at 350◦ C. The increased reactivity of this trisilane precursor
allows growth at lower temperature at which surface segregation and diffusion will
be reduced. The resulting TOFSIMS spectra suggest that the peak concentration
at the surface has decreased by switching to the SilcoreT M precursor. However, the
TOFSIMS profiles could be significantly modified by changing the SIMS conditions.
The slope of the Ge profiles is around 1nm/dec which is close to the SIMS limit
154
Figure 5.12: TOFSIMS Ge concentration profile measurements of a Si layer

grown with silane (500 ◦ C) and one grown with SilcoreT M (350 ◦ C). Ge concen-
tration at the surface of the silicon is lower for the SilcoreT M case.
as well and hence the apparent outdiffusion might not be real [8]. The TOFSIMS
measurements suggest that the Ge concentration at the Si/SiO2 interface decreases
with increasing thickness and that the concentration decreases when switching to the
SilcoreT M low temperature precursor.
Bulk interdiffusion of Ge and Si cannot account for the surface concentration of
Ge found in the Si-passivation layers. Interdiffusion profiles were calculated making
use of the concentration dependent interdiffusion coefficient determined by Xia et al.
[9] by means of Boltzmann-Matano analysis which is given by:
µ ¶
4.66eV
D̄ = 310 exp − exp(8.1xGe )[cm2 /s] (5.2)
kT
This interdiffusion coefficient was determined for a Si layer grown on a SiGe substrate.
Extrapolation of the relation is used for high xGe values. For xGe = 0 the coefficient
is reduced to the coefficient found by Zangenberg et al. [10] for the diffusion of Ge in
Si. Simulations were done making use of Fick’s second equation:
µ ¶
∂C ∂ ∂C
= D(C) (5.3)
∂t ∂x ∂x
The results are shown in figure 5.13. High temperatures(600-700 ◦ C) are needed to
cause any diffusion and this diffusion stays limited to ∼ 0.1nm at these temperatures.
This shows that bulk diffusion cannot account for the Ge present at the Si surface. Ge
surface segregation plays an important role and is driven by the reduction of surface
energy by segregating Ge to the Si surface.
The presence of Ge at the semiconductor-dielectric interface causes the interface
to be different from a regular Si/SiO2 interface, which does not have a double acceptor
nature near the valence band half of the bandgap. Note that it is not assumed that
the interface trap density in the conduction band half is due to the same physical
155
0
10
10 minute time period
-1
10
Germanium fraction
727ºC
-2
10 677ºC
527ºC
-3
10 427ºC
627ºC 327ºC
initial profile
-4
10
-5
10
-22 -21 -20 -19 -18
Position [Å]
Figure 5.13: Simulations of concentration enhanced interdiffusion of Ge in a
Si layer for different temperatures for a duration of 10’.
trap site as the one which contributes to the valence band half trap density. Linking
the densities in both halves to the same trap site would imply a negative U trap.
A negative U trap can show two levels in the bandgap with the upper level less
negatively charged than the lower level when filled. In Si/SiO2 the same Pb traps
contribute donor trap density to the valence band half and acceptor trap density to
the conduction band half of the Si bandgap. The double acceptor Ge concentration
related traps in the valence band halves can be potentially reduced by using a low
temperature precursor like SilcoreT M or by further lowering the growth temperature.
Surface treatments or surfactants could possibly be used to reduce the amount of
surface segregated Ge.
5.3.2 Band Structure Effects

The Ge/strained Si/SiO2 has a fundamentally different band structure than Si/SiO2 .
A Si layer shows band offsets with Ge which make the band structure outspokenly
asymmetric for holes and electrons compared to the Si/SiO2 case. The conduction
band edge in the strained Si layer will be lowered in electron energy compared to
the Ge conduction band while the valence band edge will be increased in hole energy
compared to the Ge valence band edge (see figure 5.14). For free holes the Si layer will
form a barrier while this is not the case for free electrons. Electrons can potentially
be trapped in the Si layer while holes will not be able to be trapped in the Si layer.
We formulate a hypothesis on the origin of the interface traps as a result of con-
finement. Electrons can be confined in the Si layer only when it is sufficiently thick.
If the layer is too thin it will not be able to confine an electron because the ground
state will be higher than the height of the confining energy barrier for thin Si layers.
For this confinement effect to give rise to an electron trap behavior the electron must
be confined in three dimensions, otherwise a confined 2D electron gas will be present.
We speculate that this can be possible due to the stepped and slightly angled nature
156
n(x) n(x)
Ge Ge
Si Si
Figure 5.14: Schematic of the band offsets and confinement behavior of elec-
trons for two different Si thicknesses. The electron can be confined in the Si layer
if the layer is sufficiently thick.
of the terraced interfaces of the Ge/Si/SiO2 structure. At certain points in such a

structure as shown in figure 5.15 confinement will be possible and at other points the
layer will be too thin and confinement will not be possible. This type of layer gives
rise to 3D confinement of electrons.
Oxide
Si
Ge
too thin for confinement
Oxide
Si
Ge
trapped sufficiently thick
for confinement
electron
Figure 5.15: Schematic of how an electron can be trapped in a terraced Si layer
for thicker Si-layers (bottom) and not for thinner layers (top) because confinement
is only possible when the layer is sufficiently thick.
The considered trap will be of an acceptor nature and located near to the con-
duction band edge. It will be an acceptor because it is uncharged when no electron
is captured and it is negatively charged when filled. The proximity to the conduc-
tion band edge results from the band structure (see figure 5.14 ). We speculate that
confinement in a terraced Si layer explains the appearance of the large interface trap
157
density near the conduction band edge for thicker Si layers. This large density appears
both for the silane and SilcoreT M precursor ( see figure 5.1) and is independent of Ge
concentration at the Si/SiO2 interface and is hence consistent with this confinement
phenomenon. If the hypothesis is confirmed, these surface states might be reduced by
engineering the terrace structure of the Si layer. Detailed simulation and an analysis
of the terrace structure (do the quantity of possible traps match to what is electrically
observed?) should allow one to test this hypothesis further.
5.3.3 Si and Ge Dangling Bonds

Dangling bonds or Pb -type defects are the interface trap defects responsible for the
electrical interface trap density in Si/SiO2 interfaces. These same defects are expected
to be present in Ge/GeO2 MOS interfaces but have not been shown to be present
yet with ESR measurements. The cause of their absence in ESR measurements on
Ge/GeO2 structure might simply be because their density is not sufficiently high for
detection with ESR ([11]). Houssa et al. predicted the interface trap density due to
Ge Pb defects to be present as two peaks in the Ge bandgap ([11]). Similar to Si, one
donor is predicted to be located near the valence band and one acceptor peak located
near the conduction band.
The group of Van de Walle [12] predicted that the donor peak would be located
beneath the valence band edge of germanium. As a result of this, the dangling bond
trap would be occupied since the Fermi level is positioned above it and the two
electrons in the bond would result in an absent ESR signal. The charging of the trap
would also prevent passivation with H2 in the Van de Walle case.
Dangling bonds have been observed in the Si-passivated germanium MOSFETs
with ESR measurements[13]. The surface Ge concentration dependence of the valence
side interface traps for the Si-passivated Ge MOSFETs indicates that this trap density
is not explained by a Pb trap presence. The appearance of the trap density peak near
the conduction band edge for thicker Si layers without an accompanying peak near
the valence band edge indicates that the conduction band half trap density is not a
Pb type trap either. We conclude that, most likely, Pb type traps are present but
that they are either passivated by the hydrogen based anneals during processing or
non-dominant.
5.4 Threshold Voltage Control

The control of the threshold voltage was one of the main issues to be solved for
the successful development of the high-κ metal gate MOSFET. In this section the
threshold voltage control issue is examined for the Si-passivated Ge MOSFET. During
the development of high-κ gate dielectrics, which was driven by the need to reduce
gate leakage while maintaining electrical channel control, one was confronted with
threshold voltages for high-κ-poly MOSFETs which could not be set to the target
values. This is ascribed to Fermi level pinning at the high-κ-poly interface caused
by the replacement of SiO2 or SiON with a high-κ dielectric [14]. The Fermi level
pinning was believed to be due to interaction between Si and HfO2 creating defects
at the interface. To solve the issue the poly-Si gate was replaced by a metal gate.
The challenge became the setting of the metal gate work function to the n+ and
158
p+ poly-Si values: most CMOS integrable metals are known to have mid-gap work
functions.
Several methods to engineer the metal gate work function in order to control the
threshold voltage were put forward[15]. The effective work function of the metal in
an MOS stack is determined not only by the bulk work function of the metal but also
by the dipole present at the metal-dielectric interface [15].
φm,ef f = φm,vac + D (5.4)
where D is the dipole contribution to the effective work function.

A first method to change the metal gate work function makes use of the im-
plantation of a well chosen species into the metal gate. The implanted species induce
interface dipoles modifying the effective work function dependent on the implant dose.
Aluminum can be used to modify the effective work function toward PMOS values.
For a TiN/HfO2 structure the work function was modified by 150 meV (from 4.7
to 4.85 eV)[15]. Arsenic can be used for nMOSFETs for which a threshold shift of
600mV was demonstrated [15]. An advantage of the implantation method is that it
is very viable for integration: only one extra implantation step is needed in combi-
nation with a resist mask to discriminate between nMOS and pMOS. Disadvantages
are that the implant can counter dope the channel and also degrade the interface
quality. A second method makes use of dielectric capping to modify the interface
dipole and the effective work function. Al2 O3 can be used for pMOS (340 mV shift
for a poly-Si/TiN/Al2 O3 /SiON stack compared to without cap) and Dy2 O3 (290mV
flatband shift for a poly-Si/TaN/Dy2 O3 /SiON stack) can be used for nMOS work
functions [15]. The dielectric capping methods avoid the damage done by implants
but the dielectric cap adds slightly to the EOT or can cause integration issues[15].
Now that the threshold voltage control issue has been introduced for high-κ metal
gate MOSFETs the issues for the Si-passivated Ge MOSFETs will be discussed. A
host of possibilities to modify the work function can be taken over from high-κ metal
gate work to adjust the threshold voltage of metal gated high-κ Ge MOSFETs. In
figure 5.16 the threshold voltages are shown of TaN-gated Si-passivated HfO2 Ge
MOSFETs with different Si thicknesses, different precursors and also for pMOS and
nMOS. As shown in section 5.2.3 the VT trends as a function of Si thickness and
precursor can be explained by the interface trapped charge. Generally the threshold
voltage decreases for thicker Si layers. In the pMOS case for higher thicknesses the
threshold voltage is relatively close to the -0.11 V high performance ITRS [16] target
for the 22 nm node. The nMOS, on the other hand, is very far off. Threshold voltage
engineering is a major problem for nMOS. The threshold voltage issue for nMOS is
caused by the high interface trapped charge for nMOS near or in inversion (see section
5.2.3).
Controlling the Ge pMOS threshold voltage is distinctly advantageous compared to
controlling the Si pMOS threshold voltage due to the band alignment of Ge compared
to Si (see figure 5.17). The TaN work function is much closer to the valence band of
Ge than to the Si valence band and the TiN work function (4.7 eV) is approximately
aligned to the Ge valence band (4.66 eV). Note that the metal gate work function
also depends on the processing used and specific examples are used here. The work
function will have to be shifted much less to attain the proper threshold value for Ge
pMOSFETs compared to Si pMOSFETs.
159
1.5
Threshold Voltage [V]
1.0
pMOS Silane
TM
pMOS Silcore
nMOS Silane
0.5
nMOS target
pMOS target
0.0
2 4 6 8
Grown Si thickness [ML]

Figure 5.16: Measured pMOS and nMOS threshold voltages for differ-
ent Si-passivation thicknesses expressed in monolayers (ML) for the silane and
SilcoreT M precursors. A TaN gate is used.
160
Vacuum potential
Metal gate Semiconductor
Si nMOS target
Si Ge
TaN
Si pMOS target
Figure 5.17: Diagram showing the TaN metal gate work function and the ideal
metal gate workfunction for Si pMOS and nMOS. The bandgaps of Si and Ge
are also indicated. For Si TaN is almost a midgap work function. For Ge the
TaN work function is much closer to the valence band edge.
To control the threshold voltage of the Si-passivated Ge MOSFETs several param-

eters can be tuned: the Si thickness and hence the interface trap density, the doping
concentration (see figure 5.18) and the effective metal gate work function. It is prefer-
able to use the doping concentration to control short channel effects and cope with
variability issues instead of using it to adjust the threshold voltage with hundreds
of millivolts. Doping concentration might be chosen low in the case of multiple gate
MOSFETs, which will most likely be needed at the 22 nm and beyond, to control
short channel effects and variability simultaneously. Doping concentration might be
chosen high to control sub-100 nm short channel effects in planar MOSFETs [4], in
case planar MOSFETs are preferred. Small variations in doping concentration by
means of a VT -adjust implant are used to fine tune the threshold voltage. Also the
Si thickness choice is not a preferable parameter to tune the threshold voltage first
and foremost because it affects interface passivation which affects other important pa-
rameters of the MOSFET such as mobility, drive current,. . . Obviously the interface
trap density should be reduced further for improvement and is no option to tune the
threshold voltage, implying that Si thickness, which is strongly correlated to interface
trap density in the Silane case cannot be used either. EOT considerations also prevail
for the Si thickness choice.
The fortunate valence band position of Ge results in a pMOS VT of -0.26 V for
a TaN gate, and no interface traps and fixed charge, and a doping of 2×1017 cm−3 .
For low interface trap density (as in the case of higher Si thickness or SilcoreT M
precursor) VT can be adjusted by choosing the proper mid-gap (for Si) metal gate
material and by fine tuning with VT adjust implants. High-κ metal gate work function
control techniques remain available. It has been proposed that dipoles induced by the
Si layer induce an additional work function shift for Si-passivated Ge MOSFETs[17].
This possible phenomenon which might explain the threshold voltage behavior as a
function of Si thickness in more detail can be compensated by VT -adjust implants,
161
metal choice and WF engineering techniques. Thanks to the fortunate Ge pMOS

metal gate threshold voltage and the plethora of work on high-κ metal gate threshold
voltage control Si-passivated Ge pMOS threshold voltage control is not a major issue.
To control threshold voltage properly for nMOS interface trapped charge near or in
inversion needs to be reduced strongly. To reduce the threshold voltage shift due to
interface trapped charge for pMOSFETs below 30 mV the interface density in the
valence band half should be reduced below 7×1011 cm−2 for a CET of 1.6 nm and
below 16×1011 for a CET of 0.7 nm (see figure 5.18, right).
0.0 1
10
Threshold Voltage [V]
-0.11 V
Threshold shift [V]

0
10
-0.5
-1
10
-2
-1.0 10 30 mV
-3
10 CET
-1.5 -4 1.6 nm
10 0.7 nm
-5
10
-2.0
13 14 15 16 17 18 8 9 10 11 12 13 14
10 10 10 10 10 10 10 10 10 10 10 10 10
-3 -2
Doping [cm ] Interface trap density [cm ]
Figure 5.18: Threshold voltage as a function of doping density for a TiN gated
Ge pMOSFET (left) without interface traps and with an oxide capacitance of
2.3×10−6 Fcm−2 and a fixed oxide charge density of zero. Threshold voltage shift
as a function of interface trapped charge (right).
5.5 Impact of Interface Passivation on Variability, Leak-

age and EOT
5.5.1 Variability
Variability in device parameters (threshold voltage, drive current, mobility, . . . ) is
known to be a major concern for sub-100 nm node devices. For Si MOSFETs pa-
rameter variability can be physically explained by the grain structure of the gate
material (for poly Si gated MOSFETs), fluctuations in channel doping and gate dop-
ing, fluctuations in fixed oxide charge, surface roughness scattering, and fluctuations
in channel length and width[18]. In this section the additional parameter variability
is analyzed for Ge MOSFETs. The focus in this section is on the main additional
issue for Ge/III-V MOSFETs, the interface passivation, and more specifically the
Si-passivation.
For Si-passivation two major causes of variability are discerned. First of all, the
large changes in interface trap density with monolayer changes in silicon thickness
imply a major issue. Because of this strong dependence minute variations in thickness
will lead to large interface trapped charge variations and hence to significant MOSFET
parameter fluctuations. This is of concern from a device-to-device scale to a lot-to-
lot scale. A second cause of variability is the stochastic nature √ of the distribution
of the traps across a Si/SiO2 interface[19]. Because of the 1/ area scaling law for
162
5.5 Impact of Interface Passivation on Variability, Leakage and EOT
the variability due interface traps only, variability becomes an issue for scaled Si-
passivated Ge devices.
5.5.1.1 Parameter Variations due to the Spatial Arrangement of Interface Traps

The Poisson distribution which is used to express the stochastics of the interface trap
spatial arrangement, describes the probability of a number of occurrences on a fixed
area with a known average density and with occurrences independent from each other.
The Poisson distribution is given by:
λn e−λ
f (n) = (5.5)
n!
Where n is the number of occurences, and λ the expected√number of ocurrences on a
specific area. The standard deviation is given by: σn = λ. For an MOS interface
trap distribution λ is given by Nit A and the standard
√ deviation of the number of traps
on a particular MOS interface area becomes Nit A. p Normalizing the occurrences to
area the standard deviation on these becomes: σNit = Nit /A. The threshold voltage
shift due to a certain trap density is:
−qNit,VT
∆VT = (5.6)
Cox
Where Nit,VT is the total number of charged traps at the threshold voltage per unit
area. The standard deviation of VT becomes:
qσNit,VT
σVT = (5.7)
Cox
p
where σNit,VT = Nit,VT /A.
The mobility is described by:
1
µ=( + αNit )−1 (5.8)
µ0
see [20] of which the standard deviation becomes:
α
σµ = 1 σN (5.9)
( µ0 + αNit )2 it
p
where σNit is once again given by Nit /A.
Based on these equations an analysis can be done of the threshold voltage and
mobility variability due to interface traps. In figure 5.19 a Poisson distribution of in-
terface traps and induced threshold shifts is shown. For a 81 nm2 MOSFET with an
interface trap density of 1×1012 cm−2 the discrete nature of interface traps manifests
itself as discrete threshold shifts from device to device as described by the Poisson
distribution. As the interface trap density is increased the variability of the thresh-
old voltage increases significantly (see figure 5.20). Reducing the CET results in a
decreased variability. To keep the standard deviation on the threshold voltage below
5mV the interface trap density needs to be reduced below 5×109 cm−2 for a CET of
1.5nm and below 2×1010 cm−2 for a CET of 0.7nm.
The mobility fluctuations induced by the Poisson distribution of interface traps is
illustrated in figure 5.21. The standard deviation peaks around 14 % of the average
163
Threshold voltage shift [V]

0.0 0.2 0.4 0.6 0.8
0.4 2
81 nm MOSFET
Probability
CET = 0.7 nm
0.3 12 -2
Nit = 1x10 cm
0.2
0.1
0.0
0 5 10 15 20
Number of charged traps
Figure 5.19: Poisson distribution of interface traps for a 81 nm2 MOSFET
and associated threshold voltage shifts.
1.5 nm 0.7 nm CET

0 sV
10 T
VT shift
2
Voltage [V]
-1 81nm MOSFET
10
-2
10
-3
10
-4
10
9 10 11 12 13 14
10 10 10 10 10 10
-2
Figure 5.20: Threshold voltage shift and standard deviation of the threshold
voltage as a function of interface trap density for a 81nm 2 MOSFET with a CET
of 1.5 and 0.7 nm.
164
mobility value. For higher trap densities the variation is reduced due to the mobility
degradation ascribed to the traps. For a mobility reduction of 5% the standard
deviation is ∼ 6% of the average mobility.
300
Standard deviation [% of average]

Mobility 12
250
Mobility [cm /Vs]
2
σµ [cm /Vs] 10
200 σµ [% of average]
2
8
150
6
100
4
50 2
0
9 10 11 12 13 14
10 10 10 10 10 10
-2
Figure 5.21: Mobility and standard deviation on the mobility as a function

of interface trap density for a 81 nm 2 MOSFET with CET of 1.5 nm. µ0 was
taken to be 300 cm−2 eV−1 and α was taken to be 2×10−16 .
It is the down scaling of the MOSFET devices which induces the appearance of
the variability issue due to the stochastic placement of√interface traps. The standard
deviation indeed increases with decreasing area (the 1/ area law). This is illustrated
in figure 5.22 in which the standard deviation as a function of device dimension is
given.
0.1
CET = 1.5 nm
4 12 -2
Nit=1x10 cm
2
σV [V]
0.01
T
0.001
4
2
6 8 2 4 6 8 2 4 6 8 2
10 100 1000
Physical gate length and width [nm]
Figure 5.22: Standard deviation on threshold voltage as a function of MOSFET
dimensions. The CET is 1.5 nm and the interface trap density is 1×1012 cm−2 .
It is clear that the variability due to interface traps is one of the most impor-
tant reasons why interface trap density has to be reduced significantly to at least
165
5-50×109 cm−2 levels. Variation induced by interface traps is one of the most impor-
tant passivation related issues.
5.5.1.2 Parameter Variations due to Si Thickness Variations

Variations in the thickness of the Si-passivation layer give rise to variations in the
interface trap density and hence threshold voltage via:
dNit,VT
qσNit,VT q dtSi σtSi
σVT = = (5.10)
Cox Cox
Note that in this treatment only the influence of the Si thickness is incorporated.
Other contributions (like the one treated in the previous subsection) are not included.
In figure 5.23 the effect of the Si thickness variations on threshold voltage variability
is shown. Data is plotted for both the silane and SilcoreT M precursors. A standard
deviation of 1 ML was assumed for the calculations. It is clear that because of the
steep change in interface passivation with varying Si thickness the variability of the Si
thickness gives rise to a very high threshold voltage variability. The threshold voltage
variability should be strongly reduced by improving passivation and processing.
The SilcoreT M precursor gives rise to less threshold voltage variability than the
silane precursor and variability is higher for thinner Si layers. The higher the Ge
content at the Si/SiO2 interface the higher the variability becomes. The Ge content
is responsible for a large part of the interface traps in the valence band half and also
for the change in interface trap density with silicon thickness and growth temperature.
Most likely decreasing or eliminating the Ge at the Si/SiO2 interface decreases the
dependence of the interface trap density on thickness as is apparent in the Nit,val
dependence on thickness for SilcoreT M . The reduced dependence of the interface trap
density on thickness for SilcoreT M reduces the threshold voltage variability. If the
surface segregation can be avoided, or further reduced the threshold voltage variability
can be reduced toward acceptable levels.
The variation in the Si thickness also causes variations in the mobility as in equa-
tion 5.10 with σNit = dNdtSi σtSi . Similar conclusions as for the threshold variability can
it
be drawn. Reducing the Ge content in the Si-passivation layer reduces the variability
of the mobility.
5.5.2 Leakage
Interface passivation has an influence on MOSFET leakage characteristics. Leakage
is a critical issue for Ge MOSFETs since the smaller bandgap leads to enhanced gate
induced drain leakage [21][22][23] and junction leakage. The interface passivation has
an impact on subthreshold drain-to-source leakage, which will be the focus of this
subsection.
The influence of the interface trap density on the subthreshold slope becomes
apparent in the following equation for the long channel MOSFET subthreshold slope:
S = ln(10)nkT /q where n = 1+(Cdep +qDit )/Cox . The effect of the interface traps on
the subthreshold slope is illustrated in figure 5.24 (left). Also the factor with which the
current reduces between a threshold voltage of 110 mV and 0V is shown. This factor
is reduced by more than 5% for interface trap densities higher than 4×1011 cm−2 eV−1
166
σN σV 0.30
12 it T
4x10 Silane
TM 0.25
Silcore
σN [V]
3
σV [V]
0.20
T
it
0.15
2
0.10
1
0.05
4 5 6 7 8
Grown Si thickness [ML]
Figure 5.23: Standard deviation on interface trap density and threshold voltage
as a function of Si thickness caused by the variability of the Si thickness. σtSi =
1M L was assumed.
for a CET of 0.7 nm and 2×1011 cm−2 eV−1 for a CET of 1.6 nm. Reducing oxide
thickness reduces the effect of the interface traps on the subthreshold slope. To limit
the impact of the interface trap density on the subthreshold slope it is recommended
to reduce the interface trap density below 8-20×1011 cm−2 eV−1 levels.
Subthreshold slope [mV/dec]
Subthreshold slope [mV/dec]
600 200
50 Measured SS
500 180 Calculated SS based on
extracted Dit
Current factor
40
400 160
30
300 CET 140
1.6 nm
200 0.7 nm 20
120
100 10 100
0 0
9 10 11 12 13 14
10 10 10 10 10 10 3 4 5 6 7 8
-1 -2
Interface trap density [eV cm ] Grown Si thickness [ML]
Figure 5.24: Subthreshold slope as a function of interface trap density (left).

Also the current reduction factor between 110 mV (projected threshold voltage
for the 22 nm node) and 0 mV is plotted. The measured and calculated sub-
threshold slope is shown for the Si-passivated Ge MOSFETs making use of the
silane precursor for the Si layer growth (right).
In figure 5.24 (right) the measured subthreshold slope of the Si-passivated Ge

MOSFETs is compared with the subthreshold slope calculated from the extracted
interface trap densities near the valence band as a function of Si thickness. Both
characteristics show corresponding trends and match well for higher Si thicknesses.
The effect of the improved surface passivation on the subthreshold slope and off
current by using the low temperature SilcoreT M precursor is illustrated in figure 5.25
167
[4]. Clearly the off currents and subthreshold slopes are reduced for the SilcoreT M
case. Note that also an EOT reduction for the SilcoreT M , which allows lower Dit at
lower EOT, plays a role in the reduced subthreshold slope and off currents.
-6
10
Ioff [A/µm] @VT +0.3V
Optimal T(Si-500C)
-7 8 Si ML (EOT = 1.3nm)
10
-8
10
Lg=100nm
-9
10
Optimal T(Si-350°C)
10-10 5Si ML(EOT = 1.05nm )
Obtained with 4nm Hf02
0 100 200 300 400 500
Ion [µA/µm] @VT -0.6V
Figure 5.25: Ion − Iof f plot for Si-passivated MOSFETs with the optimal
thicknesses for the silane (500 ◦ C) and SilcoreT M (350 ◦ C) case showing a clear
improvement in Iof f (left). Subthreshold slope as a function of channel length for
the silane and SilcoreT M case (right).
Interface traps also increase GIDL and gate leakage currents by means of a trap
assisted tunneling mechanism[24]. GIDL is band-to-band tunneling from drain to
bulk enhanced by high fields near the drain induced by the gate.
In this section we showed that the interface traps have a profound effect on the
subthreshold slope. One of the most important advantages of the introduction of the
SilcoreT M precursor which decreases the interface trap density and allows lower EOT
was the reduction of the off current by reducing the subthreshold slope. Reducing
the interface trap density below 2-4 ×1011 cm−2 eV−1 should avoid a significant effect
of interface traps on the subthreshold slope.
5.5.3 EOT
Reducing EOT is advantageous for short channel control, for a reduction of the nega-
tive impact of interface trap density on the subthreshold slope, for reducing variability
issues, for improving drive current, and for reducing the impact of interface trapped
and other charges on the threshold voltage. Reducing EOT, however, also increases
the gate tunneling current exponentially.
The introduction of the Si-passivation layer has increased EOT (see figure 5.26)
compared to the Si high-κ MOSFETs, but silicon’s relative dielectric constant of 11.9
limits the impact of the Si layer of a few monolayers thick. The remaining Si thickness
after oxidation is about 2.5 ML less than the grown Si thickness. As illustrated in
figure 5.26 with experimental data, reducing the Si layer thickness reduces the EOT.
By switching from a 4nm HfO2 layer (as used in the presented devices) to a 2nm HfO2
layer sub-nm EOTs can be reached. Using the low temperature SilcoreT M precursor
allows reducing the EOT, because of the lower trap densities at low silicon thickness
and EOT for this precursor.
168
5.6 Mobility in Si-passivated Ge MOSFETs
1.6 1.6
1.4 1.4
1.2 1.2
4 nm HfO2
EOT [nm]
1.0
EOT [nm]
1.0
0.8 Extracted EOT 2nm HfO2
0.8
0.6 0.6
0.4 0.4 nm SiO2 0.4 0.4 nm SiO2
0.2 0.2
Si Si
0.0
0.0
3 4 5 6 7 8 3 4 5 6 7 8
Grown Si thickness [ML] Grown Si thickness [ML]
Figure 5.26: Extracted and calculated EOT as a function of grown Si thickness

for 4 nm of HfO2 (left). The different full lines delineate the EOT contributions
for each layer of the gate stack. The different layers are marked by the vertical
arrows. Si layers were grown by silane. 0.4nm ozone oxidation was used. By
reducing HfO2 thickness from 4nm to 2nm sub-nm EOTs can be reached (right).

In this section a closer look will be taken at the influence of the Si-passivation on
the mobility characteristics of Ge pMOS and nMOS devices. First of all the mobility
extraction techniques are introduced, their weaknesses are exposed, and solutions
are proposed. A temperature dependent study of hole mobility was done to show the
presence of remote phonon scattering which was found to be present before in Si/high-
κ MOSFETs. Finally, the influence of Si-passivation on the mobility is evaluated for
pMOS and nMOS devices.
5.6.1 Mobility Extraction Technique

In this work the mobility is extracted as the effective mobility. The effective mobility
is the mobility obtained from the drain conductance in the linear regime (Vg − VT >>
Vds ). Other types of extracted mobility such as the field-effect mobility derived from
the transconductance in the linear regime and the saturation mobility are not as
accurate: they do not take into account the vertical surface electric field dependence
of the mobility and therefore underestimate the mobility [25]. The effective mobility
is extracted using the equation:
Lgd LIds
µef f = = (5.11)
W Qinv W Qinv Vds
where Qinv is the inversion charge density [Ccm−2 ]. The effective mobility is usually
plotted as a function of the effective field in order to obtain universal mobility curves
[26].
Qdep + ηQinv
Eef f = (5.12)
εs
where Qdep is the depletion charge density and η is taken 1/3 for holes. η takes into
account the averaging of the electric field over the inversion layer.
169
There are two methods to obtain Qinv . One can use Qinv = Cox (Vg − VT ) or one
can use C-V measurements to obtain Qinv as
Z ∞
Qinv = Cinv dVg (5.13)
Vg
where Cinv is obtained using a split C-V or full C-V measurement. The method mak-
ing use of the capacitance measurement is preferred because of its superior accuracy.
Similarly Cdep , used to determine the effective field, can be obtained from a split C-V
measurement.
The MOSFET parasitic series resistance (Rseries ) can be taken into account by
extracting the series resistance by means of one of the known methods such as the
shift and ratio method or the Terada and Muta et al. method [25] and by modifying
equation 5.11 to:
L
µef f = (5.14)
W Qinversion (1/gd − Rseries )
From Si high-κ MOSFETs it is known that oxide bulk trapping can lead to an un-
derestimation of mobility. This phenomenon explained part of the degraded mobility
encountered for Si high-κ MOSFETs [27]. The underestimation of mobility occurs
because the oxide trapping induced stretch-out leads to an overestimation of Qinv
when integrating the measured capacitance using the split C-V method. A difference
in stretch-out between the I-V and C-V measurement also leads to errors. A solution
was proposed for this problem by means of a method making use of pulsed I-V and
inversion charge pumping techniques [27]. A second solution was proposed by Zhu et
al. which counters the stretch-out by using a modeled curve to estimate Qinv more
properly [28].
For germanium MOSFETs an additional issue is present: interface traps. These
cause additional stretch-out and also additional interface trap capacitance on top of
the effect due to the oxide bulk trapping. Due to the wide spread in interface trap time
constants across the bandgap among which very short time constants, it is practically
impossible to measure faster than the response of the interface traps as is done with
the pulsed I-V and ICP techniques for high-κ oxide bulk trapping.
Hall mobility measurements [25] are the most optimal technique to measure mo-
bility in the presence of large interface trap densities since the inversion charge density
BIds
is measured directly by means of the Hall voltage (VH = Q inv
)[25]. The Hall voltage
only results from the mobile inversion carriers excluding the interface trapped charge.
Since one measures both VH and Ids simultaneously one can derive the mobility as a
function of Qinv even though stretch-out is present. These direct measurements are
the most optimal experimental method to measure Ge/III-V MOSFET mobilities.
T he work presented in the next sections makes use of the method by Zhu et
al. [28] in one particular case to demonstrate the impact of stretch-out. Basically
a C-V model is used to obtain Qinv by fitting the model to the measured C-V. The
mechanism behind this method, the effect of stretch-out due to interface traps, can
be understood by means of a few simplifications. When integrating the inversion
capacitance stretch-out is present which can be seen as:
dQit −qDit dE/dVg Cit
dVg → dVg − = dVg − dVg ≈ dVg (1 + δ) (5.15)
Cox Cox Cox
170
where Cit is the average value of qDit in the inversion voltage range investigated and δ
is the slope of the linear approximation of E(Vg ) in that same inversion voltage range.
By inserting this into the integral used to obtain the inversion charge one obtains:
µ ¶Z ∞ µ ¶
Cit Cit
Qinv,extracted ≈ 1 + δ Cinv dVg = 1 + δ Qinv (5.16)
Cox Vg Cox
One sees that stretch-out results in an overestimation of Qinv and hence an under-
estimation of the mobility. The stretch-out approximately results in the scaling of
the extracted inversion charge density and mobility with a constant factor. This in-
sight will be useful when studying the temperature dependence of mobility subject to
stretch-out effects.
It must be emphasized that using a model based correction procedure such as
the Zhu et al. method [28] will lead to inaccuracies. The models do not completely
capture the behavior of the relatively unknown devices and the parameters used for
the model are also subject to inaccuracies. A direct measurement procedure is always
better than a model-based one for which one needs to make assumptions. We argue
that Hall mobility measurements will do better and would make an excellent future
follow-up experiment for the work presented here. We have used the model-based
correction method in one particular case [28] to make clear that stretch-out effects
profoundly influence mobility extractions. For the remaining cases the regular split
C-V effective mobility extraction was used in this work.
As a final note it is also important to realize that split C-V mobility measurements
are very sensitive to the offset capacitance often subtracted from capacitance mea-
surements. This is particularly so at low effective fields and the sensitivity is due to
the position of Qinv in the denominator of equation 5.11. Therefore “peak” mobility
figures can be strongly biased (the “peak” often occurs at low field) and are avoided
in this work. The full mobility curve as a function of effective field or inversion charge
density is a much more reliable representation of mobility.
5.6.2 Temperature Dependence of Mobility

Two experiments were conducted to investigate the temperature dependence of mo-
bility. A first experiment was done on the first successful Si-passivated pMOSFETs
[6][2]. A second experiment was done on later Si-passivated pMOSFETs with dif-
ferent Si thicknesses (using the silane precursor) [29]. Investigating the temperature
dependence of mobility allows to draw conclusions on the presence of remote phonon
scattering [30]. Remote phonon scattering is found to be present for Si-passivated
high-κ Ge MOSFETs.
Remote phonon scattering is a scattering phenomenon associated with high-κ di-
electrics [31] which induces mobility degradation in MOSFETs with high-κ dielectrics[30].
The high-κ dielectrics thank their high permittivity to an increased ionic polarizabil-
ity. This increase is accompanied with an increased presence of soft optical phonons in
the dielectric which can cause scattering of carriers in the MOSFET channel. In SiO2
the bonds show less ionic polarizability. As a result optical phonons in the dielectric
show an increased energy content. Optical phonons in the dielectric with a higher
energy scatter carriers in the channel less than soft phonons with a lower energy as
found in high-κ dielectrics.
171
5.6.2.1 First Mobility vs. Temperature Experiment: Remote Phonon Scattering

and Stretch-out Correction
In the first experiment [6] hole mobility was extracted as a function of temperature for
Si-passivated HfO2 Ge pMOSFETs without a PMA H2 anneal (see figure 5.27). For
the mobility extraction the correction for stretch-out by Zhu et al.[28] in combination
with a quantum mechanical C-V model [32] was used yielding a significant increase in
extracted mobility compared to the uncorrected mobility (see figure 5.27, left). This
clearly shows that the presence of stretch-out due to interface traps and oxide charge
trapping can have a profound effect on mobility and make the mobility seem lower
than it actually is.
Since we are studying temperature dependence and will be looking at the exponent
a of the temperature dependence of mobility (µ ∝ T a ) we argue that the correction
for stretch-out will not have a profound influence on the evaluation of a. As shown in
the previous section the model based correction approximately leads to a correction
of the mobility with a constant factor which shows that there will not be a profound
effect of the stretch-out on a.
The mobility of the investigated Si-passivated MOSFETs show large temperature
dependence (see figure 5.27) whereas previous devices [7] showed a limited ∼ 20%
variation of mobility at 80 K compared to room temperature indicating a strong
Coulombic scattering mechanism in previous devices. Conventionally, the mobility
is made up of three scattering components: a Coulombic, a phonon and a surface
roughness scattering component. These are combined by Mathiessen’s rule to the
overall mobility:
−1
µ−1 = µphonon + µ−1 −1
Coulombic + µsurface roughness (5.17)
The phonon component shows a strong temperature dependence with the mobility
component increasing with decreasing temperature. Coulombic scattering is impor-
tant at low electric field and is caused by dopants, fixed oxide charge and interface
trapped charge. The Coulombic component shows a limited temperature dependence.
Surface roughness scattering is important at high electric field and also shows a limited
temperature dependence.
For high-κ dielectrics a fourth remote phonon component is added:
−1
µ−1 = µphonon + µ−1 −1 −1
remote phonon + µCoulombic + µsurface roughness (5.18)
Phonon mobility components dominate at medium field. For Si/SiO2 MOSFETs

the mobility at medium field shows a power law (T a ) temperature dependence with
exponent a = −1.5. It was shown before that the presence of remote phonon scattering
in high-κ dielectrics decreases this exponent to a = −0.95 [30].
We investigated the presence of the remote phonon phenomenon in Ge MOSFETs
in this straightforward way. When looking at the log-log plot of the mobility of the
devices as a function of temperature (figure 5.27, left) one sees -0.7 as the exponent of
temperature for the medium field of 0.3 MV/cm (corresponds to ∼ 0.5×1012 cm−2 in-
version density). The exponent of -0.7 is close to the earlier reported value of -0.95 for
remote phonon scattering in Si [30]. Probably a small Coulombic scattering compo-
nent is still present which accounts for the slightly decreased temperature dependence
at this field. The temperature dependence shows results similar to the ones obtained
172
1000 Temperature [K]

9
Effective field [MV/cm] T
a 8 100
0.2 a = -0.9 7 234
Mobility [cm /Vs]

0.3 a = -0.7 6 278
0.4 a = -0.6
5
Mobility [cm /Vs]
2
1000 4
2
9
8 3
7
6 2
5
Without correction
4 278 K
100
8 9 2 3 5 3 4 5 6 7 8
2x10
100
Temperature [K] Effective field [V/cm]
Figure 5.27: Mobility vs temperature and effective field showing similar be-
havior vs temperature as high-κ on silicon but dissimilar behavior vs Eef f .
for high-κ stacks on silicon. The dependence of the mobility on the effective field has
an exponent of −0.8 − −1.1 similar as in [33](see figure 5.27, right). Based on the
assessment of the similar temperature dependence of Si high-κ and Ge high-κ MOS-
FETs one can conclude the presence of remote phonon scattering in the Si-passivated
Ge MOSFETs.
The increased room temperature peak mobility of the devices in this experiment
(∼ 350cm2 V −1 s−1 ) [2] compared to the previous devices (∼ 250cm2 V −1 s−1 ) [7] (these
devices are not studied in this work) is ascribed to a reduction in defects. These peak
mobilities [2][7] were not corrected for stretch-out and are the mobilities of the best
device on the best wafer of the lot. For the temperature dependent measurements a
random device was measured on the best wafer. Compared to the previous devices
metallization was introduced and the critical timing of the gate stack growth and
deposition was improved. Temperature dependent mobility measurements showing
an increased dependence on temperature for the devices measured in this experiment
confirm the reduction of defects in the reported Ge/Si/HfO2 gate stack.
5.6.2.2 Second Mobility vs. Temperature Experiment: Remote Phonon Scat-

tering and Different Si Thicknesses
In the second experiment the conventional split C-V effective mobility extraction
technique was applied on Ge pMOSFETs with different silicon thicknesses grown
with silane [34]. The conventional split C-V is used here because the correction of the
mobility by means of a model is not deemed to be sufficiently accurate (see section
5.6.1). For a thickness of 7ML the measurement data and intermediate results are
shown. In figure 5.28 the source current measurements are shown as a function of
temperature, which clearly show a strong temperature dependence. The inversion
capacitance and derived inversion charge are shown in figure 5.29.
The mobility curves on a lin-lin scale and on a log-log scale are shown in figure
5.30. Error bars are shown indicating the error induced by the correction for the offset
capacitance on these 10x10 µm2 MOSFETs. The influence of the offset capacitance
173
Source Current [µA/µm] 1.5 77K

130K
1.0 170K
294K
0.5 220K
0.0
-2.0 -1.5 -1.0 -0.5 0.0 0.5
Gate Voltage [V]
Figure 5.28: Source current as a function of gate voltage and for a drain to
source voltage of 25mV for different temperatures of the Si-passivated Ge HfO2
pMOSFETs (7ML Si). Channel length is 10 µm.
-12 -12
2.0x10 3.0x10
Inversion charge [C]
2.5
Cinv [F]
1.5
2.0
77K
1.0 1.5 77K
130K
130K 294K
170K 294K 1.0
0.5 170K 220K
220K 0.5
0.0 0.0
-1.5 -1.0 -0.5 0.0 -2.0 -1.5 -1.0 -0.5 0.0 0.5
Gate voltage [V] Gate voltage [V]
Figure 5.29: Inversion capacitance curves (left) and inversion charge curves
(right) derived by integration of the Si-passivated Ge MOSFETs with 7ML of
grown Si at different temperature.
174
correction is most clear at low field where the error is substantially larger. The error
is given by:
Vint
σµ = µ σC (5.19)
Qinv of f
where Vint is the size of the integration interval used to determine Qinv which was
assumed to be 2.5 V and the standard deviation on the extracted offset capacitance
σCof f was assumed to be 10 fF.
500 5
4
77K 130K
77K
Mobility [cm V s ]
130K
Mobility [cm V s ]
2 -1 -1
2 -1 -1
400 3
170K
2 170K
300
220K
294K
200 100
7
220K
100 294K
6
5
4
0 12
5 6 7 8 2 3 4 5 6 7 8 2
12 13
5 10 15 20x10 10 10
-2 -2
Inversion charge [cm ] Inversion charge [cm ]
Figure 5.30: Mobility as a function of inversion charge density for different

temperatures of the Si-passivated devices with 7ML of grown silicon on a linear
(left) and a log-log (right) scale.
The mobility is shown as a function of temperature in figure 5.31. For a thinner

Si layer the mobilities are shown in figure 5.32. The exponent a of the mobility as a
function of temperature is for both cases relatively similar (-1.04 for thin silicon and
-0.8 for thick silicon) and confirms the reduced a obtained for Si-passivated high-κ
Ge MOSFETs compared to Si/SiO2 MOSFETs ascribed to remote phonon scatter-
ing. The similar exponent found in experiment 1, which used a correction method
also shows the relative immunity of the exponent extraction to stretch-out and to
corrections for it. The slope change of the mobility as a function of temperature
which occurs at lower temperatures indicates the transition to a different scattering
regime: when the temperature is reduced Coulomb scattering and surface roughness
scattering become more important.
5.6.3 Interface Passivation and Mobility in pMOS Devices

After investigating the role of remote phonon scattering we now turn our attention
to the impact of the interface passivation on the mobility of Si-passivated Ge MOS-
FETs. This will be done by comparing the mobility of MOSFETs with different Si
thicknesses, which correlates strongly with the charged interface trap density.
In section 5.2.3 a model was derived designating the valence side traps as double
acceptors and the conduction band side traps as acceptors based on an investigation of
threshold voltage and mobility. The mobility for pMOSFETs is shown to be correlated
with the valence band side traps as is shown in figure 5.33. This correlation can be
fitted with an approximate relation[20]:
µ = (1/µ0 + αNit )−1 (5.20)
175
Mobility [cm V s ]
2 -1 -1 5
Inversion charge
Measurement Linear interp. 130K-294K
12 -2
5x10 cm a = -0.79
2 12 -2
2x10 8x10 cm a = -0.73
13 -2
1x10 cm a = -0.68
7 8 9 2
100
Temperature [K]
Figure 5.31: Hole mobility as a function of temperature and for different

inversion charge densities for a Si-passivated high-κ Ge pMOSFET with 7ML of
grown silicon.
300 4
Mobility [cm V s ]
2 -1 -1
77K
Mobility [cm V s ]
250
2 -1 -1
3
130K
200
220K
2
150 260K
100 Inversion charge

300K Measurement Lin. Interp. 130-300K
13 -2
50 1x10 cm a=-0.90
100 12
8x10 cm
-2
a=-0.93
9 12 -2
0 5x10 cm a=-1.04
12
0 5 10 15 20x10 8 9 2 3
-2 100
Inversion charge [cm ] Temperature [K]
Figure 5.32: Hole mobility as a function of inversion charge density (left)

and mobility as a function of temperature (right) for a Si-passivated high-κ Ge
pMOSFET with 5ML of grown silicon.
176
190
Experiment
180
Mobility [cm /Vs]

Model fit
170
2 160
150
140
130
12
2 4 6 8 10x10
-2
Valence side traps [cm ]
Figure 5.33: Hole mobility as a function of valence band half trap density
(for different Si thicknesses and both precursors). A good correlation is found
between mobility and interface trap density. The mobilities were extracted using
the method by Ghibaudo[35].
where µ0 is the mobility without scattering by interface traps and theoretically α =

π 2 mq 3 /(16²2av hkT )[36][20]. Further, m is the carrier effective mass and εav = (εox +
εs )/2. Note that this is a semi-empirical model with alpha a fitting parameter. It
was found before that the theoretical value of α does not match to the experimental
value [36][20] due to the neglect of several effects in the equation such as screening,
position of the charges and the randomness of the distribution of the charges on
the interface. For Si nMOSFETs at room temperature the difference between the
theoretical value (4×10−14 Vs) and the experimental value ( 2.7×10−15 Vs) is a factor
of 20 [36]. No systematic study has been committed for the determination of α for
holes in Si pMOSFETs [36]. We will use the theoretical formula to scale the available
empirical values for Si nMOS to the Ge pMOS case.
A value for α of 2.6×10−16 Vs is obtained for the Si-passivated Ge pMOSFETs
by means of fitting (see figure 5.33). The value is a factor of 10 smaller then the
experimental value for Si electrons. The 10x factor can be explained in part ( factor
5) by the difference in εav to which α is strongly related. εav is about a factor of 5
different between Ge/high-κ and Si/SiO2 . We therefore assume that the experimental
values of α scale with εav as the theoretical values do. m is more or less similar for
Si electrons and Ge holes. Additional screening most likely explains the remainder of
the reduction in α. The difference in α can hence be accounted for. The reduction
in mobility due to the interface traps is of the magnitude expected for the amount of
charged interface traps present.
The α-factor gives an idea of the reduction in mobility due to a lack of surface pas-
sivation. In figure 5.34 a plot is shown reflecting the effect of interface trap density on
mobility. For the Ge pMOS value of α (2.6×10−16 Vs) the mobility is reduced by 5%
for an interface trap density of 7×1011 cm−2 . For the Si nMOS value of α (2.7×10−15
Vs) the mobility is reduced by 5% for an interface trap density of 7×1010 cm−2 . The
reduced α for Ge of 2.6×10−16 induces an improved robustness to mobility degrada-
tion due to interface traps. All in all the reduction of mobility due to interface traps
177
does not imply a very stringent requirement on the interface trap density. To avoid
mobility degradation the charged interface trap density in inversion should be reduced
to 5×1010 -5×1011 cm−2 levels from the current 1-2×1012 cm−2 levels for Si-passivated
Ge MOSFETs.
300 13
10
Mobility [cm V s ]
250
2 -1 -1
200 12
Nit,5% [cm ]
10
-2
150 α
-16
2.6x10 11
-16 10
100 8x10
-15
50 2.7x10
10
10
8 9 10 11 12 13 14 -17 -16 -15 -14

10 10 10 10 10 10 10 10 10 10 10
-2
α [Vs]
Figure 5.34: Mobility as a function of interface trap density for different values
of α (left). µ0 is assumed to be 300 cm2 V −1 s−1 . Nit,5% , the interface trap density
at which the mobility is reduced by 5%, as a function of α (right) with µ0 = 300
cm2 V −1 s−1 . The Ge pMOS value and Si nMOS value of α are indicated by the
vertical bars.
To corroborate the fact that a rather limited reduction in interface trap density
is needed to avoid mobility degradation due to interface traps the mobility model of
Villa et al can be utilized [37]. This semi-empirical model states that the Coulombic
part in the mobility can be given by:
µ00
µCoulombic = (5.21)
Nit α0 + N Lth
√
where µ00 is a fitting parameter and Lth the carrier thermal length (~/ 2mkT , ∼ 2.2
nm for Ge holes). The parameter α0 has values of the order of 10−2 . This means
that for a doping density of 2×1017 cm−3 both terms in the numerator of equation
5.21 become equal for a trap density of 4×1012 cm−2 which means that at that point
scattering due to dopants and due to interface traps are equally strong corroborating
that a reduction to 5×1010 -5×1011 cm−2 levels should be sufficient to limit mobility
degradation due to interface traps to reasonable bounds.
5.6.4 Interface Passivation and Mobility in nMOS Devices

In literature Ge nMOSFETs generally show strongly degraded mobility characteris-
tics, with mobilities usually lower than the mobility of their Ge pMOS counterparts
even though higher mobilities are expected. In this subsection the Si-passivated nMOS
case will be discussed and the cause of the degradation clarified.
In figures 5.35 and 5.36 drive current and extracted mobility characteristics at dif-
ferent temperatures are shown for Si-passivated nMOSFETs with grown Si thicknesses
of 5 and 8 ML respectively. One notices that the mobility as well as drive current
increase for thicker grown Si layers but the mobility is for both very degraded. The
178
extracted mobility characteristics are deformed, and show abnormal, rather constant
mobility as a function of extracted carrier density. This could be due to deformation
due to the higher conduction band side interface trap levels causing strong stretch-
out, especially for thicker Si layers. The deformed characteristics could also be due
to large changes in the present scattering phenomena compared to Ge pMOSFETs.
0.20
Source Current [µm/µA]
Extracted mobility [cm V s ]

2 -1 -1
0.15 Vds 75mV
80K
50mV 3 294K
25mV
0.10 80K
294K 2
75mV
0.05 1
50mV
0.00 25mV 0
12
1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 1 2 3 -24 5x10
Gate Voltage [V] Cox(VGS-VT)/q [cm ]
Figure 5.35: Drive current (left) and mobility (right) for different temperatures
for Si-passivated Ge MOSFETs with a grown Si thickness of 5ML.
Extracted mobility [cm V s ]
2 -1 -1
2.0 60
300 K 50
Source current [µA/µm]
200 mV
260K Vds
1.5 230K 40
170K
77K 30
1.0
20 77K
170K
0.5 260K
100 mV
10
300K
0
0.0 12
0.0 0.5 1.0 1.5 2.0 5 10 15x10
-2
Gate Voltage [V] Cox(VGS-VT)/q [cm ]
Figure 5.36: Drive current (left) and mobility (right) for different temperatures
for Si-passivated Ge MOSFETs with a grown Si thickness of 8ML.
Based on the extremely low values for the mobilities one could question whether
the observed drive currents are due to drift in an inversion layer. Perhaps they could
be due to a hopping transport mechanism through the interface traps. Indeed, if the
charge in the interface traps is much larger than the free charge the current could result
from hopping from trap to trap via the minority carrier band. However, the drive
current and mobility characteristic show a (limited) increase when the temperature
is decreased while for a hopping mechanism one would expect more current with
increasing temperature since hopping is thermally assisted. A hopping mechanism as
cause for the nMOS drive current is hence excluded. A tunneling mechanism remains
a possibility for trap-to-trap transport contributing to the drive current.
The limited temperature dependence of the mobility and drive currents in the Si-
passivated nMOSFETs show that phonon scattering, with its outspoken temperature
179
dependence is not an important scattering mechanism and that hence transport is

dominated by defects: either by Coulombic scattering due to charged interface traps
or due to tunneling from trap to trap. Considering the fact that the interface trap
density near the conduction band is more or less similar to the density near the valence
band for thinner Si layers, we do not expect stretch-out to be sufficient to prevent
the formation of an inversion layer and hence we expect an important drift transport
component.
Clearly, the mobility in the nMOS inversion layer is strongly degraded. This can be
ascribed to a much larger amount of charged interface traps for an nMOS in inversion
than for a pMOS in inversion (see figure 5.3). This difference is more or less an order
of magnitude and is ascribed to the double acceptor/acceptor nature of the traps.
This nature also partly explains the improved mobility for thicker layers since the
nMOS charged trapped density decreases with increasing thickness. The increased
interface trap charge for nMOS increases Coulombic scattering. Due to the absence
of the Si potential barrier for inversion carriers in an nMOS (see figure 5.14), the
scattering charges will be closer to the channel, explaining further mobility reduction.
5.6.5 Conclusion
The main reason for the study of the introduction of Ge into CMOS is the promise of
higher drive currents. For long channel MOSFETs higher drive currents are caused
by a higher mobility than for Si MOSFETs. For a Si-passivated HfO2 Ge pMOSFET
the extracted mobility is indeed a factor of 2.5x larger than for a Si pMOSFET (see
figure 5.37). In the figure the extracted mobility of the Ge MOSFET is compared
to the universal hole mobility in Si [26], which is only relevant for high effective field
since Coulomb scattering is not included in the universal mobility. Si-passivated Ge
pMOSFETs show an outspoken mobility advantage, much in contrast to the heavily
degraded mobility figures of their nMOSFET counterparts.
400
294 K Experimental Ge
Mobility [cm V s ]
2 -1 -1
Si universal
300 2.5x Si universal
200
100
0
6
0.2 0.4 0.6 0.8 1.0 1.2x10
Effective Field [V/cm]
Figure 5.37: The measured mobility of a Si-passivated Ge MOSFET with 7ML

of Si compared with the universal hole mobility of silicon.
The theoretically achievable possible mobility for Ge pMOSFETs is however sig-
180
500
Mobility [cm V s ]
2 -1 -1
400
300
200
100
294 K Experimental Ge
Calculated
0
12
0 5 10 15 20x10
-2
Inversion charge [cm ]
Figure 5.38: The measured mobility of a Si-passivated Ge MOSFET with 7ML

of Si compared with the theoretical hole mobility of germanium [38].
nificantly higher (500-600 cm2 V −1 s−1 )[38] than what is obtained experimentally for
Si-passivated Ge pMOSFETs as shown in figure 5.38. The calculated mobility is
due to phonon scattering and surface roughness and hence the calculated mobility is
similar to the universal mobility of Si, which also only contains phonon and surface
roughness scattering. The difference between experiment and theory can be explained
by three phenomena investigated. First of all the split C-V extraction methodology
contributes to an underestimation of the mobility caused by stretch-out due to in-
terface traps (estimated to be in the order of 20-50%). A second contribution is the
presence of remote phonon scattering, as shown in section 5.6.2. This phenomenon
contributes to a degradation of the mobility in the order of 20-50%. A third phe-
nomenon is associated with the interface traps (15-60% degradation, depending on
trap density). These three phenomena explain the hole mobilities of the Si-passivated
Ge MOSFETs observed in the 100 - 350cm2 V −1 s−1 range.
The remote phonon scattering in the Ge MOSFETs can be reduced by thickening
the interfacial oxide layer which distances the high-κ soft phonons from the interface
and by maintaining the metal gate which “screens” the remote phonon scattering.
Considering the interface passivation the thicker Si layers grown with the SilcoreT M
precursor with the lowest interface trap density for low EOT are preferable to minimize
Coulomb scattering and maximize performance. Further improvements in interface
passivation can be expected by further lowering the growth temperature to avoid Ge
surface segregation in the Si layer. A reduction of the charged interface trap density
down to 5×1010 -5×1011 cm−2 levels should reduce Coulomb scattering to reasonable
bounds.
Si-passivated Ge nMOSFETs show heavily degraded inversion layer mobility which
can be ascribed to the double-acceptor/acceptor nature of the interface traps. This
nature causes a large difference in interface trapped charge for nMOS and pMOS in
inversion causing significantly more Coulombic scattering for nMOS. A large improve-
ment in interface quality is most likely going to improve nMOS mobility, but at this
moment it is unclear how to achieve this.
181
5.7 Reliability
Deep-submicron Si-passivated pMOSFETs with a high-κ dielectric stack on unstrained
Ge achieved very high drive current with record peak mobility of ∼ 350 cm2 V −1 s−1
[2]. Addition of halo’s resulted in good control of short channel effects down to LG =
125 nm [39]. With these well behaving submicron devices free of gross extrinsic defects
it is possible to proceed to advanced reliability characterization of the gate stack. In
this section Time-Dependent Dielectric Breakdown and Negative Bias Temperature
Instability will be investigated. The reliability in terms of these characteristics for
Si-passivated HfO2 Ge pMOSFETs was found to be sufficient.
5.7.1 TDDB
Time dependent dielectric breakdown is the failure phenomenon taking place in the
gate dielectric subject to stress (an applied gate voltage) after a certain period of time.
Failure corresponds to the gate dielectric losing its electrical insulation properties and
gate leakage becoming intolerable. The breakdown times are described by a Weibull
distribution.
(µA)
3.0x10 3 -6
2.5 HBD
Ge substrate
current
22.0
(A)
1.5
gate Current
11.0
0.5
00.0 0 200 400 600 800 1000

0 200 400 Time600
(s) 800 1000
stress time (s)
-6
1.2
1.2x10
gate current (µA)
1.0 SBD
0.80.8
Current (A)
0.6
0.40.4
0.2
0.00.0620 630 640 650 660 670 680

stressTimetime
(s) (s)
Figure 5.39: : Typical Ig (t) trace observed during a TDDB measurement on a

Ge pMOSFET (top). Soft and hard breakdown events can be clearly observed.
Low noise on initial gate current allows for good detection of SBD (bottom).
Ge pMOSFET devices with 80 cycles of HfO2 (HfO2 EOT ∼ = 0.8nm) were studied.
The work described in this subsection has been led by Ben Kaczer [40]. Sub-micron
devices were stressed in accumulation to study dielectric breakdown (BD) in the
high-κ layer with the gate flux consisting of electrons only. Devices with sub-micron
dimensions were used to minimize the background gate current with respect to the
soft breakdown (SBD) path leakage.
182
5.7 Reliability
Observed Ig (t) traces show normal behavior (see figure 5.39) indicating gate di-
electric quality comparable to Si substrates. A robust algorithm set to trigger on a 50
nA Ig (t) jump was used as a SBD criterion. 115 devices were stressed at four differ-
ent voltages and the resulting TDDB data were corrected for wafer non-uniformities.
Data fitting yielded the Weibull spread parameter common for all voltages β= 1.28,
while the power-law voltage acceleration exponent was n = 37 [41]. Lifetime projec-
tion is shown in figure 5.40. BD position distributions are devoid of gate-to-extension
BDs [40] confirmed by measuring the ratio s ≡ Id /(Is + Id ) of post-BD pFET source
and drain currents.
108 10 years
tBD (s)
106
104 A = 3x10-9 cm2
Ge Si
102 A = 3x10 cm
-10 2
0.0 1.0 2.0 3.0

VG (V)
Figure 5.40: The 63% TDDB values for L = 180 - 350 nm pMOSFETs on
Ge (solid circles) and Si (open circles) substrates. Maximum allowed operating
voltage of ∼ 1.1V is projected for both samples after voltage (solid curves) area
(dashed curves) and percentile (dotted curves) scaling.
A direct comparison of the above data with the state-of-the-art high-κ gate stack
on Si proves difficult due to the different gate stack processing and subsequent lower
temperature budget. Reference TDDB data collected on a 40 cycle HfO2 (HfO2 EOT
∼
= 0.4) on a Si substrate with ∼ 0.9nm SiO2 interfacial layer result in β = 0.98 and n
= 38. A higher stress voltage is necessary to induce TDDB values similar to Ge.
All of these results are in good agreement with the Ge data. Due to the design
of the TDDB experiment, in both cases BD events originate in the high-κ layer. The
lower value of β on the Si substrate is due to the thinner HfO2 layer [42], while the
higher stress voltage is a consequence of the thicker interfacial layer, resulting in lower
voltage and hence lower damage in the HfO2 layer. Most importantly, the almost
identical voltage acceleration exponent n indicates similar quality and breakdown
mechanisms for both high-κ layers.
From the time-dependent dielectric breakdown (TDDB) analysis, we conclude that
the gate stack quality of the Ge/Si/SiO2 /high-κ devices is not significantly affected
by the Ge substrate.
5.7.2 NBTI
Negative Bias Temperature Instability is a degradation phenomenon which occurs
at high temperature and moderate bias. The phenomenon induces threshold volt-
183
age shifts, drive current and transconductance degradation and an increase in inter-
face trap density. For Si/SiO2 the phenomenon is linked to the depassivation of the
Si/SiO2 interface. Even though a high initial interface trap density is measured for
the Si-passivated germanium MOSFETs, we show here that the gate stack shows a
robustness toward NBTI stress, and the 10 year lifetime is ensured with a gate voltage
overdrive Vg -VT = -1.2V. The work described in this subsection has been led by Marc
Aoulaiche [43].
The threshold voltage shift was measured at different temperatures and for various
gate stress voltages. The threshold voltage shift has a power law time dependence, as is
shown in figure 5.41 (left). The time exponent is similar to what was already reported
for high-κ stacks (α=0.19±0.02). NBTI degradation shows a strong dependence on
the temperature. The extracted activation energy is about 0.2eV.
Figure 5.41: Threshold voltage shift as a function of stress time measured at

125 ◦ C (left). Nit generation as a function of the stress time measured by Icp at
3MHz and at 25 ◦ C(right).
The NBTI damage generated by the stress has a recoverable component [43]. Only
about 15% of the damage generated is recovered at 25◦ C for a 2000s recovery time.
This is consistent with a high interface trap contribution to the VT shift.
Charge pumping measurements at 3MHz were done as a function of bias stress.
The midgap Nit density extracted is plotted in figure 5.41 (right) as a function of
stress time and for different Vg stress. Nit generation during stress obeys a time
power law. Notice that a relatively high electric field was needed to generate Nit (Eox
is 13 to 17 MV/cm).
Finally, an NBTI lifetime comparison with Si-substrate pMOSFETs is made. The
reference Si-substrate TaN/TiN metal gated pMOS device measured has 60 cycles
HfO2 deposited by ALD on a 1nm SiO2 interfacial layer with an EOT of 1.43nm. Ge
pMOS lifetime is extrapolated to a threshold shift value of 30mV. Lifetime plots for
different Vg stresses and temperatures for the Si-passivated Ge pMOSFETs are shown
in figure 5.42.
Taking into account the EOT of the Si pMOS reference, 1.43nm, Vg − VT at 10
years for the Si pMOSFET is -1.46V and for the Ge pMOSFET is -1.41V. The NBTI
lifetime is more or less similar when comparing Si-substrate to Ge-substrate.
NBTI on Ge based pMOSFETs with a Si-passivated Ge interface has been studied
[43]. This interface is found to exhibit a high resistance to NBTI stress. Despite the
184
5.8 Conclusions
Figure 5.42: NBTI lifetime extrapolation for various temperatures for a 30mV
VT shift criterion.
fact that the initial interface trap density was about 2 orders of magnitude higher
than the typical values obtained on the Si/SiO2 interface, the degradation due to
NBTI stress remains within acceptable limits. Over 10 years lifetime is guaranteed
using the criterion of 30mV VT shift with Vg −VT = -1.2V, which is found to be similar
to an equivalent Si-based pMOSFET.
5.8 Conclusions
In this chapter the characteristics of the Si-passivated HfO2 germanium MOSFETs
related to interface passivation have been discussed and ways to improve these MOS-
FETs have been proposed.
The interface trap density was extracted for varying Si-passivation layer thick-
nesses and for the silane and SilcoreT M precursors. The Ge/Si/SiO2 /HfO2 gate stack
does not show the excellent Si/SiO2 gate stack passivation properties. Interface trap
density is higher than for the Si/SiO2 gate stack interface. It was found that the inter-
face trap density in the valence band half decreases with increasing Si thickness. The
density in the conduction band half first decreases with increasing Si thickness and
increases significantly for thicker Si layers. For the SilcoreT M precursor the interface
trap density in the valence band half is reduced.
An interface trap model is proposed for the Si-passivated germanium interface.
Traps in the valence band half are of a double acceptor nature and are believed to be
caused by the presence of surface segregated Ge at the Si/SiO2 interface. Traps in the
conduction band half are of an acceptor nature and it is speculated that the increase
in trap density for thicker Si layers is caused by a quantum mechanical confinement
effect. Dangling bond type traps are not found to be a dominant contribution to the
interface trap density. The reduction of Ge segregation leads to better passivated
interfaces as shown by the reduction of Ge content and improvement of the MOSFET
quality for thicker Si layers and for the low temperature SilcoreT M precursor. Further
reductions in the valence band side trap density could involve a further lowering of
185
the growth temperature, surface treatments of the Si layer to remove or prevent Ge

segregation or the use of surfactants during growth.
Threshold voltage behavior as a function of silicon thickness and precursor can be
explained by the interface trap density and the above model. It is found that threshold
control is not a significant issue for Si-passivated Ge pMOSFETs if the interface trap
density in the valence band half can be reduced sufficiently (< 7-16×1011 cm−2 ).
The presence of interface traps has a profound impact on the threshold variabil-
ity. This phenomenon requires an interface trap density in the valence band half of
at most 5-50×109 cm−2 which is one of the most stringent requirements for interface
trap density reduction. The variation of the Si-passivation thickness causes a major
threshold voltage variability issue due to the strong relation between Si-thickness and
interface trap density. Interface trap density also has a significant impact on the
subthreshold slope and densities in the subthreshold swing energy range should be
kept below 2-4×1011 cm−2 eV−1 . The Si-passivation layer increases the EOT of the
MOSFET by a limited amount and still allows sub-nm MOSFETs.
The Si-passivated pMOS and nMOS mobility has also been investigated. Three
phenomena cause the extracted mobility to be degraded. First of all the conventional
split C-V mobility extraction technique induces an underestimation of the mobility
caused by stretch-out due to interface traps. Remote phonon scattering is shown to
be present. Mobility degradation due to remote phonon scattering can be weakened
by thickening the interfacial SiO2 layer. A metal gate should be maintained. In-
terface traps are also shown to degrade the mobility. To avoid this degradation for
pMOSFETs interface trap density in the valence band half should be reduced below
5-50 ×1010 cm−2 . The interface trap model also explains the degraded nMOS perfor-
mance. Interface trap charge is much higher for the nMOS and the inversion layer
is closer to the interface causing severe mobility degradation. In order to obtain a
performing nMOS, interface trap density should be improved dramatically across the
entire bandgap.
Finally, TDDB and NBTI reliability were shown not to be an issue for Si-passivated
HfO2 germanium MOSFETs for a 10 year lifetime with a Vdd of ∼ 1.1 V in a first
investigation.
186
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Chapter 6
Conclusions, Future Work and

Outlook
6.1 Conclusions
In this section the conclusions of the work are synthesized. This work has addressed
the electrical characterization of Ge/III-V MOS interface passivation by investigating
and modifying a combination of techniques. Interface passivation is a key challenge in
Ge/III-V MOSFET development and accurate feedback is needed for passivating the
interface. The interface passivation and its impact on the properties of Si-passivated
Ge MOSFETs are investigated.
Chapter 2 We have demonstrated that the conventional MOS theory [1] explains
the admittance behavior of Ge and III-V MOS-capacitors which can deviate strongly
from Si/SiO2 admittance behavior. It is shown that Fermi level pinning and admit-
tance behavior of MOS capacitors with a high interface trap density can be linked
and understood with this MOS theory when introducing the concept of weak Fermi
level pinning. The impact of the interface trap time constant and of the weak inver-
sion response on the MOS admittance characteristics for different semiconductors is
demonstrated. The MOS admittance is shown to be affected strongly in several ways
when the substrate and the interface passivation is changed. Correct interpretation of
the routinely used admittance characteristics is of paramount importance in Ge/III-V
MOS development especially for interface trap density extraction methods.
Chapter 3 We have uncovered that the interface trap time constant behavior and
the weak inversion and inversion responses can severely affect interface trap density
extraction with the conductance method on Ge/III-V MOS structures. The con-
ductance method is considered as the most accurate admittance based method for
Si/SiO2 . These issues can be resolved by modifying the conductance method to a
full conductance method (FCM). A qualitative method was developed which is able
to distinguish weak Fermi level pinning due to a dominant amount of interface traps
from other sources of large C-V frequency dispersion (FLPDM). A method was also
191
6. CONCLUSIONS, FUTURE WORK AND OUTLOOK
co-developed which evaluates the relative severity of Fermi level pinning to study
the passivation quality of non-ideal capacitors, usually GaAs or InGaAs MOS (FLE
method). Among other admittance based techniques the Gray-Brown method and the
Terman method are not found to be useful for evaluating trap densities in experimen-
tal non-Si/SiO2 devices. The low frequency/ high frequency method is a relatively
quick and easy-to-use method but can result in missing a large trap density near
the band edges and the method also has limited sensitivity. The full conductance
method is found to be the most adequate admittance based method to characterize
experimental Ge/III-V MOS interfaces accurately across the bandgap.
Chapter 4 In this chapter large signal analysis techniques are treated and the toolset
is expanded to evaluate MOS properties beyond admittance based techniques. The
broader toolset allows for complementary characterization and confirmation of results
by using multiple techniques. A pulsed Q-V/C-V technique is introduced which solves
the issues the conventional pulsed C-V and RF C-V methods have when dealing
with sub-nm EOT gate stacks. For DLTS, it is clarified that the extraction of the
interface trap density is not feasible with a relatively straightforward method for
large interface trap densities. No signature of semiconductor bulk traps is found with
DLTS measurements in the samples investigated. However, in the presence of high
Dit DLTS’ asset, the characterization of semiconductor bulk traps, is jeopardized.
Charge pumping characteristics of germanium MOSFETs are investigated and
the validity of emission level theory is confirmed for Ge MOSFETs. From theory and
experiment it is clear that 300K charge pumping with transition times down to 100ns,
as used for Si/SiO2 , can only quantify the amount of interface traps in a fraction of the
bandgap near midgap for Ge. This explains why Si/SiO2 charge pumping practices
can lead to an underestimation of the actual total trap density in Ge. To increase
the measured fraction of the bandgap low temperature measurements can be used.
By using transition times down to 6ns the interface trap density is extracted closer to
the band edges on germanium MOSFETs at 300K. This enables a convenient 300K
evaluation of interface trap density across a large part of the bandgap for process and
reliability evaluation purposes. The obtained results are found to be in agreement
with full conductance method results.
Chapter 5 In this chapter the characteristics of the Si-passivated HfO2 germanium

MOSFETs related to interface passivation technology are investigated based on in-
terface trap density extractions developed earlier in the work.
The Ge/Si/SiO2 /HfO2 gate stack does not show the excellent Si/SiO2 gate stack
passivation properties. Interface trap density is higher than for the Si/SiO2 gate
stack interface. It was found that the interface trap density in the valence band
half decreases with increasing Si-passivation layer thickness. The trap density in
the conduction band half initially decreases with increasing Si thickness and this
increases significantly for thicker Si layers. For the SilcoreT M precursor the interface
trap density in the valence band half is reduced compared to the silane precursor.
An interface trap model is proposed for the Si-passivated germanium interface.
Traps in the valence band half are of a double acceptor nature and are caused by the
presence of surface segregated Ge at the Si/SiO2 interface. Traps in the conduction
band half are of an acceptor nature and it is speculated that the increase in trap
192
6.1 Conclusions
density for thicker Si layers is caused by a quantum mechanical confinement effect.

Dangling bond type traps are not found to be a dominant contribution to the interface
trap density. The reduction of Ge segregation leads to better passivated interfaces for
thicker Si layers and for the low temperature SilcoreT M precursor. Further reductions
in the valence band side trap density could involve a further lowering of the growth
temperature, surface treatments of the Si layer to remove or prevent Ge segregation
or the use of surfactants during growth.
Threshold voltage behavior as a function of silicon thickness and precursor can be
explained by the interface trap density and the above model. It is found that threshold
control is not a significant issue for Si-passivated Ge pMOSFETs if the interface trap
density in the valence band half can be reduced sufficiently (< 7-16×1011 cm−2 ).
The presence of interface traps has a profound impact on the threshold variability.
This phenomenon requires an interface trap density in the valence band half of at
most 5-50×109 cm−2 which is one of the most stringent requirements for interface
trap density reduction. The variation of the Si-passivation thickness causes another
major threshold variability issue due to the strong relation between thickness and
interface trap density. Interface trap density also has a significant impact on the
subthreshold slope and densities in the subthreshold swing energy range should be
kept below 2-4×1011 cm−2 eV−1 . The Si-passivation layer increases the EOT of the
MOSFET by a limited amount and still allows sub-nm MOSFETs.
The Si-passivated pMOS and nMOS mobility has also been investigated. The hole
mobility reaches up to 2.5x the universal Si hole mobility. Three phenomena inves-
tigated cause the extracted mobility to be degraded. First of all the conventional
split C-V mobility extraction technique induces an underestimation of the mobility
caused by stretch-out due to interface traps. Remote phonon scattering is shown to
be present. Mobility degradation due to remote phonon scattering can be weakened
by thickening the interfacial SiO2 or SiON layer. A metal gate should be maintained.
Finally interface traps are also shown to degrade the mobility. To avoid this degrada-
tion for pMOSFETs interface trap density in the valence band half should be reduced
below 5-50 ×1010 cm−2 . The Si-passivated Ge pMOSFET mobility can hence most
likely be increased even further by reducing remote phonon scattering and reducing
trap density. The interface trap model also explains the degraded nMOS performance.
Interface trap charge is much higher for the nMOS and the inversion layer is closer
to the interface causing severe mobility degradation. In order to obtain a perform-
ing nMOS, interface trap density should be improved dramatically across the entire
bandgap.
Some remarkable key insights with important consequences
Large C-V frequency dispersion is not necessarily a sign of a bad interface.

Example: GeOx Ny and GeO2 . See chapter 2.
An interface trap density which is high compared to Si/SiO2 does not need to
be avoided at all costs. Dit does not need to be as low as has been the case
for Si/SiO2 as shown in chapter 5. An important factor contributing to the
decreased importance of interface traps compared to the past is the scaled oxide
thickness which makes the subthreshold slope and the threshold voltage less
193
sensitive to interface traps. Considering the mobility the decreased oxide thick-
ness also increases the screening of interface charges by the increased inversion
layer density.
Not only interface trap density is important (for the subthreshold slope and
Ion − Iof f ) but the interface trap charge is important for the threshold voltage
and mobility. The difference between charge and density is determined by the
(double) acceptor or donor nature of the traps. A high trap density can be
tolerated for MOSFETs of either n-or p-type if it is located near the majority
carrier band and is not charged in inversion. For the opposite type of MOSFET
(resp. p- or n-type) the same trap density cannot be tolerated.
The difference between nMOS and pMOS performance and characteristics ob-
served for some Ge/III-V MOSFETs is caused by an asymmetry in the interface
trap characteristics across the bandgap. This can be an asymmetry in density
or an asymmetry caused by the (double) acceptor/donor nature of traps. This
has been shown to be the case for Si-passivated MOSFETs (see chapter 5) and
also is the case for InGaAs MOS.
MOSFETs are important to evaluate a certain interface passivation. Although

long channel MOSFETs (short channels are not necessarily required to evaluate
the interface) require more processing, they can deliver a much richer amount
of characterization data to analyze the interface and will avoid making wrong
decisions for further research. First of all MOSFETs deliver the most direct
data relevant for CMOS: Ion and Iof f and more indirectly: mobility. This is
important because with an extracted interface trap density (which in fact cannot
be extracted reliably from capacitors, especially for small bandgap materials,
see chapter 2 and 3) one still does not reliably know the (double) acceptor/donor
nature of the traps and hence the interface trapped charge and hence also the
predicted performance. An MOS interface with a very high Dit compared to
Si/SiO2 can in fact still deliver a record breaking MOSFET (InGaAs MOSFETs
for example). Apart from the direct and most relevant Ion and Iof f data,
MOSFETs also allow to extract a correct and complete interface trap density
extraction using the full conductance method (FCM) to provide correct insight
in the passivation and hence also more fruitful ideas for further improvements.
6.2 Future Work

In this section possible topics for future work stemming from this thesis are introduced.
Improvement of the full conductance method The full conductance method could
be implemented with a model and a fitting routine to provide more accurate extrac-
tions like in [2]. Such a method would make the extraction method more valid for
rapidly changing Dit with energy and would provide more accurate extraction of the
energy position of traps. Fully automated extraction would make the full conductance
technique more efficient.
194
6.2 Future Work
Investigate the applicability of RF admittance measurement techniques on Ge

MOSFETs Potentially RF admittance measurements can be used to extract the
interface trap density across a large part of the bandgap for Ge MOSFETs. By ex-
tending the frequency range from (1kHz-1MHz) to (1kHz-∼1GHz) one is able to probe
traps closer to the band edges with the conductance technique at room temperature.
Before investigation can be commenced appropriate RF MOSFET structures will be
needed.
Further investigation of charge pumping A room temperature charge pumping

technique can be developed further to extract interface trap density across a larger
part of the Ge bandgap. This will entail decreasing the used transition time and
increasing the system bandwidth of the proposed fast transition time charge pumping
technique or elaborating a sinusoidal waveform based RF charge pumping technique
[3]. A high frequency setup using RF structures serves this purpose. The features
hindering the efficiency of the charge pumping technique at low temperature on Ge
MOSFETs can be investigated further.
Application of pulsed measurements on Ge MOSFETs Threshold instabilities can

be studied on Ge MOSFETs using pulsed measurement techniques to investigate the
influence of interface traps on threshold instabilities at different frequencies.
Further elaboration of the pulsed Q-V technique Possibly the pulsed Q-V tech-
nique can be extended to shorter transition times allowing the use of the technique
at higher leakage levels. RF structures will be needed along with higher bandwidth
equipment to increase the bandwidth of the proposed system. The pulsed Q-V tech-
nique can be elaborated for the use on samples with a significant amount of interface
traps. Since the pulsed Q-V oxide bulk trap analysis technique is based on the fact
that bulk traps respond in times much longer than the pulse duration, much shorter
pulse durations will be needed to make the pulse duration shorter than the response
time of most of the interface traps.
Hall mobility investigation Hall mobility measurements are recommended for char-
acterizing the mobility of MOSFET samples with interface traps in this work. These
measurements will acquire a more accurate view of the electron and hole mobilities in
germanium MOSFETs. These measurements can be combined with detailed mobility
modeling including Coulomb scattering, phonon scattering, remote phonon scatter-
ing, and also surface roughness scattering. With this technique and with detailed
models the contributions of each scattering component to the mobility degradation in
germanium MOSFETs can be determined more precisely and more information can
be obtained regarding possible pathways for mobility improvement.
Interface trap modeling The interface defects in the Si-passivated Ge MOSFET

and their structure can be identified more precisely. To this end Density Functional
Theory simulations and more detailed Electron Spin Resonance measurements can be
done.
195
Further electrical interface characterization work on Si-passivated Ge MOSFETs

Several topics can be investigated further electrically. What happens to the interface
passivation when HfO2 is replaced by SiO2 ? What happens if intermediate anneals are
done in between the epitaxial growth of Si and the ozone oxidation (influence on Ge
segregation, roughness of surface, etc.)? What is the effect of reducing HfO2 thickness
on the interface passivation? To what extent can the SiO2 layer be thickened and
remote phonon scattering reduced? What is the effect of surface treatments (diluted
SC1 and HF for example) to eliminate surface segregated germanium? What is the
influence of the type of interfacial oxide used (plasma oxidation, aqueous ozone)?
Detailed investigation of the effects of interface traps on ultra-scaled devices

Detailed full quantum mechanical simulations of the effect of interface traps on ultra-
short channel MOSFETs can be done to study potential variability issues, the thresh-
old voltage behavior, scattering due to traps, switching speed, drive current and
leakage currents (trap assisted tunneling and subthreshold leakage for example).
Electrical interface characterization of Ge/III-V MOSFETs Semiconductor-dielectric

interfaces of Ge and III-V MOSFETs can be investigated accurately using the tech-
niques provided in this thesis and will provide a route to improving interface passi-
vation for different material combinations. InGaAs is a promising candidate material
to be investigated for III-V MOSFETs.
6.3 Outlook
During the course of this work Ge MOSFET technology has raised interest in a
broader group of companies and at the same time academic research is moving on
to the next step down the alternative semiconductor road: III-V MOSFETs. The
work presented here will provide a valuable contribution to the further development
of the Ge MOSFET and to the III-V MOSFET effort. The electrical interface char-
acterization learning from Ge MOSFETs already has found an application on III-V
MOSFETs.
The Ge MOSFET has lived up to its promise so far, most clearly demonstrated
by the IMEC short channel pMOS drive currents which outperform their Si ITRS
pMOSFET counterparts.
Si-passivated Ge MOSFETs show potential for further improvement in the pMOS-
FET case but are much less promising for the nMOSFET case. Tackling the Ge seg-
regation issue will open the door to better performance, less variability and reduced
leakage. For CMOS an appropriate nMOSFET compliment needs to be found.
A more accurate evaluation of interface traps on GeO2 , GeON and Ge3 N4 di-
electrics, made possible and supported by the electrical characterization work and
insight of this thesis, and comparison with other Ge gate stacks has learned that
GeO2 and Ge3 N4 were underappreciated. These dielectrics show promise for a fur-
ther reduced interface trap density (<1×1011 cm−2 ) and increased MOSFET quality.
Integration issues involving the water solubility of GeO2 will have to be addressed,
but high-κ capping layers and proper spacer insertion are seen as a candidate solution.
These dielectrics also show potential for the nMOSFET.
196
6.3 Outlook
Leakage issues due to GIDL and junction leakage will have to be addressed as
well. This can be done with dopant engineering to reduce drain fields, quantum well
structures, the use of low doped multiple gate FETs, ultra thin GOI, . . .
Finally, the Ge MOSFET will most likely have to be strained and have a multiple
gate structure to be inserted in future CMOS technologies.
197
BIBLIOGRAPHY
Bibliography
[1] Nicollian and Brews. MOS (Metal Oxide Semiconductor) Physics and Technology.
Wiley & Sons, New York, 1982.
[2] K. Martens, B. De Jaeger, R. Bonzom, M. Meuris, G. Groeseneken, and H. Maes.
A new interface state density extraction method applicable to peaked and high-
density distributions for Ge MOSFET development. IEEE Electron Device Letters,
27:405 – 408, 2006.
[3] G.T. Sasse and J. Schmitz. Application and evaluation of the RF charge pumping
technique. IEEE Transactions on Electron Devices, 55:881–889, 2008.
198
Curriculum Vitae
Koen Martens was born in Gent, Belgium, in 1981. He received the B.S. and M.S.
degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium,
in 2001 and 2004. He is currently working toward a PhD degree on the topic of
germanium MOSFETs at the Katholieke Universiteit Leuven, Belgium and at IMEC.
His PhD work is funded by a scholarship from the Institute for the Promotion of
Innovation by Science and Technology in Flanders (Belgium). In 2006 he was on
an internship at Stanford University working on the electrical characterization of
germanium MOSFETs. His current research interests include the characterization,
modeling, reliability and technology of germanium and III-V transistors.

PH DKoentotal

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KATHOLIEKE UNIVERSITEIT LEUVEN

FACULTEIT TOEGEPASTE WETENSCHAPPEN

ELECTRICAL CHARACTERIZATION AND MODELING

Promotoren : Proefschrift voorgedragen tot

Interuniversitair Micro-Elektronica Centrum vzw

ELECTRICAL CHARACTERIZATION AND MODELING

Examencommissie : Proefschrift voorgedragen tot

Interuniversitair Micro-Elektronica Centrum vzw

Wettelijke depotnummer: D/2009/7515/3

A combination of electrical characterization methods to evaluate MOS interface passi-

Symbol Unit Description

First Author Journal Papers

[2] K. Martens, B. De Jaeger, R. Bonzom, M. Meuris, G. Groeseneken, and H.

[3] K. Martens, W. Wang, K. De Keersmaecker, G. Borghs, G. Groeseneken, and

[4] K. Martens, M. Rosmeulen, B. Kaczer, G. Groeseneken, and H.E. Maes. Elec-

[5] K. Martens, W.F. Wang, A. Dimoulas, G. Borghs, M. Meuris, G. Groeseneken,

[6] K. Martens, C.O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Heyns, T.

[7] K. Martens, B. Kaczer, T. Grasser, B. De Jaeger, M. Meuris, H.E. Maes, and G.

First Author Conference Contributions

Elektrische karakterisering en modellering

Figuur 1: Illustratie van de performantiekloof tussen de geprojecteerde perfor-

CMOS schaling is hoofdzakelijk gedreven door geometrische schaling, maar een

de drive stroom beschreven als volgt:

waar W de breedte is van de MOSFET, Q de inversielading, µ0 de mobiliteit bij

Figuur 2: Ladingsdragersnelheden in functie van elektrisch veld voor Ge, Si en

De algemene doelstelling van dit werk is om de perspectieven voor IMEC Si-

Admittantiegedrag van Ge/III-V MOS capaciteiten

Figuur 3: Gesimuleerde C-V curve bij kamertemperatuur in het 1kHz - 1MHz

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Figuur 5: Berekende oppervlaktetoestandsfrequentie of conductantiepiekfre-

Extractiemethoden voor Ge/III-V oppervlaktetoestands-

We hebben aangetoond dat het gedrag van de oppervlaktetoestandstijdconstante

problemen kunnen opgelost worden door de conductantiemethode te modificeren in

Figuur 10: Plot van de tijdsconstante geëxtraheerd van de conductantie en ca-

1.4 RF-IV C-V 100 MHz

-2.0 -1.6 -1.2 -0.8 -0.4

schillende technieken te gebruiken. Een gepulste Q-V/C-V techniek wordt voorgesteld

Charge pumping karakteristieken van germanium MOSFET’s werden onderzocht

Extractred interface state density [a.u.]

Figuur 14: Oppervlaktetoestandsdichtheid in functie van de energie

Figuur 16: Electron en gat emissieniveau’s berekend met Boltzmann [4]

Figuur 17: De geëxtraheerde karakteristieken gebruikmakend van een kleinste

Si-passivatie van Ge MOSFETs

Interface trap density [eV cm ]

14 5ML silane 5 ML Silcore

Interface trap density [eV cm ]

14 7ML Silane 7 ML Silcore

Figuur 18: Geëxtraheerde oppervlaktetoestandsdichtheid van Si-gepassiveerde

Een oppervlaktetoestandsmodel is voorgesteld voor de Si-gepassiveerde germa-

PMOS Vt calculated from

Drempelspanningsgedrag in functie van de Si dikte en precursor kan uitgelegd

Figuur 20: De gemeten mobiliteit van de Si-gepassiveerde Ge MOSFET met

Figuur 21: Gatenmobiliteit in functie van de temperatuur en voor verschillende

mobiliteit induceert, wat veroorzaakt wordt door stretch-out door oppervlaktetoe-

Figuur 22: Gatenmobiliteit in functie van de valentiebandhelft oppervlak-

List of Acronyms vii

Nederlandse Samenvatting xiii

2 Admittance Behavior of Ge/III-V MOS Capacitors 17

3 Ge/III-V Interface Trap Extraction Methods 69

4 Pulsed Signal Techniques 105

4.3.2 Theory of DLTS and Fourier Transform DLTS, Devices and

5 Si-passivation of Ge MOSFETs 143

5.6.3 Interface Passivation and Mobility in pMOS Devices . . . . . . 175

The characterization of Ge MOSFETs and capacitors: to evaluate the appli-

Modeling of Ge devices: Models will be composed based on experimental data