Rochester Institute of Technology

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Theses Thesis/Dissertation Collections

1972

Design and Construction of a Digital Pulse

Generator
David Myer

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Myer, David, "Design and Construction of a Digital Pulse Generator" (1972). Thesis. Rochester Institute of Technology. Accessed
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DESIGN MID CONSTRUCTION OF A DIGITAL PULSE GENERATOR

by: David Myer

Technology-
Rochester Institute of

June 1972

Thesis Advisor: Professor J. Carson

 TABLE OF CONTENTS

Page

1 Abstract

2 Introduction

3 Circuit Design

4 Figure 1

6 Figure 2

7 Figure 3

8 Figure 4

9 Table 1

10 Figure 5
12 Summary
13 References

14 Appendix
 ABSTRACT

This pulse generator was built to complement the Stroboscope

501, a high speed multi-flash unit capable of producing up to

6000 flashes per second. The Stroboscope is equipped with a

electro-mechanical frequency generator, however a solid state

pulse generator has the advantages of being highly accurate and

repeatable. The basic design criteria were that the generator

have several selectable frequencies within the limit of the

Stroboscope, be able to count several different amounts of pulses

and then close off automatically and be triggerab^Le from an

exterior source. The unit designed meets all these specifications.

A high speed multi-flash strobe has applications in scientific

photography where any high speed operation must be photographed.

Examples are a photograph of a bullet leaving the barrel of a rifle

or a piece of machinery operating at high speed.

 INTRODUCTION

This research project involved the design and construction of

a digital pulse generator. It was desired that the Stroboscope

'501'
have an exterior and independent triggering device. This
trigger system was to be in addition to the existing internal

trigger of the Stroboscope. An electronic triggering system offers

the advantages of great accuracy and repeatability in terms of

frequency and pulses produced. The generator is essentially an

information handling system, the information being a steady supply

of pulses which are processed in order to obtain a triggering of the

flash in the desired The the the

projec1

manner. core of research and

is therefore in the digital processing section of the generator. It

is in this area that the most extensive research and design was done.

It was necessary to learn the operation of digital intergrated

circuits and the methology of digital processing systems. This

project served to culminate several Electrical Engineering courses

in an electronic; system that has useful application in photography.

 CIRCUIT DESIGN

The circuit construction and operation can be divided into three

distinct sections, the voltage regulator, oscillator and the

frequency synthesizer. Each section will be discussed seperately

with consideration given as how it fits into the whole operation.

1
Voltage Regulator
i
The decision to include a voltage regulator was necessitated

the considerably the inter-

by demanding voltage requirements of

grated circuits which operate in the range of from 4.75 to 525

volts. This regulator effectively isolates the I.C.s from any major

voltage drop in the line input and will also supply a constant volt

age with varying load impedances. A simple zener diode type regulator

would not prove sufficient in that greater stability is desired. Due

to the extensive amount of circuits available for this purpose a pre

designed circuit was chosen and

utilized, (figure l) . In addition to

its regulatory operation this circuit protects the ItC*s from any high

input voltage since the input to the regulator is only 8.5 volts. If

a pass transistor should fail and the total input voltage fall across

the load it would not prove critical to the I.C.s.

This circuit tends to restore a drop in output voltage from the pre

set 5 volts by two mechanisms. The first is as follows; a drop in the

output causes the base of Q3 to see a more positive potential and

thereby causes it to conduct less current. This in turn reduces the

base current to QA, whose reduced collector current allows more base

current to reach Q5 Conduction is thereby increased in Q5 and the

voltage drop from point A to point B increases. The second mechanism

is again started by Q3's reduced conduction allowing more current

from Rl to pass through Q2, This in turn causes Qlb and then Qla to

boost their collector currents and drive more current across the zener

diode which tends to restore any lost output voltage.

1. T.K. Hemingway, British Aircraft Corp., London

Electronics Dec. 21 1970, page 54
 H
O
-P

to
cs
p

I-l
o
>

P4

VO
 Oscillator

This circuit is a conventional emitter-coupled multivibrator

however the usual capacitor has been replaced by a crystal. The

output of transistor Q2 is used to vibrate the crystal which will

oscillate at its frequency of 100 K hz. This forces the whole

circuit to oscillate at that frequency. Square waves are produced

since the output is essentially a clipped sine wave due to the fact
that-
the feedback causes the circuit to be overdriven.

I.C. Circuit

Within this circuit the squarewaves pulses produced in the oscil

lator are programmed according to the desired frequencies and the

number of pulses. The I.C, board and its functions are divided into

two seperate units, the frequency synthesizer and the pulse

counter/

trigger, ( figure 3 ) .

The frequency synthesizer generates all the frequencies by dividing

the primary 1851 Khz, There two
oscillator frequency of are dividing
I.C. components, I.C.I, a four bit binary counter and I.C. 2. a
binary
coded decimal decade counter along with I.C. 3 a B.C.D, to decimal

decoder. The incoming primary frequency passes through I.C. 1 first

where depending on the position of switch SN1 it will be divided by

factors of 4,8 or 16. Following this division the pulses are sent to

I.C. 2 which can divide in B.C.D. from 1 to. 10 and in decimal by decoding
through I.C. 3-. Switch SW2 can select division factors of 6,7,8,9 or 10,
positions 2 through 5 were not used since they would result in repeta-

tive freqencies. The total frequency range is shown in table 1 along

with the appropriate switch positions.

The pulse counter and trigger compose the other half of the I.C.

board. The pulses from the frequency synthesizer must pass through a

gate before they reach the output. This gate in turn is controlled

two I.C.s which constitute the pulse counter. The actual gate
by other

is two nor gates tied together (figure 4) that will pass pulses to

input A is at logical 0. However as soon as it

the output as
long as

goes to logical 1 the nor gate output will remain at zero volts until
 2.2 v

>*70
S k70 <k.7K
< k.?K Xflut.pnt)

Q2 2n706

XI

yQl 2n706
50^1
r

i 100

Figure 2 Oscillator
 0.54 sec.
>*

0 volts

Frequency: I85I.OO KHZ

Risetime = Failtime: 40 nanosec,

Duty cycle:

Figure 3 OSCILLATOR CHARACTERISTICS

 8

From Oscillator

I.C. 2 -* I.C. 3

6 78 9 10

SW1
, - SW2

Trigger Input

I.C. 6 I.C. 5 I.C.fr

clear
Q reset A
preset

24 8

X
SW3
w8*

^ * 5v Output
sw^

Figure 4 I.C. Board

 TABLE 1

SWITCH POSITION FREQUENCY ( KHZ )

SW1 SW2

A 1 723.0469

A 2 803.3854

A 3 903.8086

A 4 1032.9241

A 5 1205.0781

C 1 1446.0938

C 2 1606.7708

C 3 1807.6172

C 4 2065. 8482

C 5 2410.1563

B 1 2892.1875

B 2 3213.5417

B 3 3615-2344

B 4 4131.6964

B 5 4820.3125
 10

from frequency

synthesizer

t output

LOGIC

A INPUT a OUTPUT C
H L r.
'

H H L
L H H
L L I.

L= low H= high

A from I.C. 6

Figure 5 Nor Gate

 11

the circuit is retriggered. Point A's logic is controlled directly

by I.C, 6, a edge triggered JK flip-flop which in turn is controlled

by T.C. 5 , another 4 bit binary counter. Switch SW3 allows I.C. 5 to

count
2,4, 8 pulses or it may be grounded to allow free non operation.

The trigger mechanism operates in the following manner; when the

trigger button is depressed or a pulse is applied to the external

trigger input, the clear input of I.C. 6 goes low. This makes the Q
output to go low and since this is attached to point A of I.C. 4 pulses

will be allowed to pass to the output. Each pulse that goes past the

nor gate is counted by I.C. 5 and when either ?, 4?8 pulses have been

counted, depending on the position of switch SW3, I.C. 5 presents a

a high logic to the JK, preset inputs. I.C. 6. This causes the Q, output

to go high again and since point A also goes high the flow of pulses

is terminated until the circuit is retriggered. To prepare the circuit

to be refired so that the counter is reset to zero the reset switch

SW4 must be momentarily moved to the reset position and then back to

count. While SW4 is in the reset position a low logic is applied to

the reset input of I.C. 5 causing the counter to return to zero and at

the s<-ui.e lime a high logic is applied to the preset input of I.C. 6 to

maintain its Q output high since it might be falsely triggered by the

reset function of I.C. 5. The circuit is now prepared to be fired again.

 12

SUK-IARY

At the last test the operating conditions were as

follows;

Trigger: this circuit is fully operational, both the external trigger

and trigger button are capable of firing the generator in the desired

manner,

Counter: the counter was

operating as desi;ned and along with the Nor

gate was
terminating the flow of pulses after the desired count.

Frequency Synthesizer: Due to the fact that a souree of well shaped

square waves wcs not avaiable it was not possible to exactly determine

if the frequency division was being done as specified. However preliminary

tests did show that divison was taking place at all settings.

Voltage Regulator: this circuit is capable of supplying the full 5

volts under all operating conditions of the I.C. circuit. In addition

up to a 20';^ drop in line voltage was compensated for.

Oscillator: this is the only circuit that is not operational. At the last

test no pulses were being generated.

 11

LIST OF REFERENCES
 1*

LIST OF REFERENCES

1. Thomas Harry. Handbook for Electronic Engineers and

Technicians. Englewood Cliffs: Prentice-Hall, 1965

2. Maley G.A. Manual of Logic Circuits. Englewood Cliffs:

Prentice-Hall, 1970

3. Markus John. Sourcebook of Electronic Circuits. New

York: McGraw Hill, 1968

4. Gillie Angelo. Pulse and Lo;;ic Circuits. New York:

McGraw Hill, 168

5. Morris N.M. Logic Circuits. London: KcGraw Hill,1969

6. Texas Instrument. TTL Intergrated Circuit Data.

Catalog # CC201, 168

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n CIRCUIT TYPES SN5493, SM7493
\ MSI 4-LiIT D1UARY COUiiltHS

MSI TTL HIGH-SPEED RIPPLE-THROUGH COUNTERS

for applications in
Digital Computer Systsms Dat>Handiing Systems o Control Systems
s j on n
TRUTH T"3LE (Sec rm-ts 1. 2. arc 3) FLAT PACKAGE (TOP VIEW)
lOqJC DUAL-IDLINE PACKAGE (TOP VIEW)

-NT I D

1 c I : i
i yl

jr
3
'
1 ~o c ;

[
o

c
1 o
l"l
'
TIlJ I
* : i

5 r> ', i
-\~-

1 i 1 ii 6z6-itJ^ J
G 1

7 0 i
i
0(Dp00
"i'l:i Cr,
mui l '-'cc ^ sc
"'-'

positive lotjic: see trull: table

NC-r:o lntcrn.il Connection

NOTES: 1. Output A connectea t-

incut 5
2. To reset 3(1 outputs to ic:,-a: 0 both

^0(1 ) 3nc*
^0(2) inouts nj:t beat
logics! I.

2. Either (or both) reset ncjt;

^0(1)
ard ^^(2* must be at a logical 0 to count.

description

These high-speed, monolithic 4-bit bins'-/ counters consist of four master-slave flip-flops which are internally intercon
nected to provide a divide-bv-two counter and a dividc-by-eighi Conner. A gated direct reset line is provided which

inhibits the count inpLits a, id simultaneously returns the four flip-flop outputs to a logical 0. As the output from flip-

flop A is not internally connected to the succeeding flip-flops the counter may be operated in two independent modes:

1. When used as a 4-bit rippla-through counter, output A must be externally connected to input B. The input
count pulses are applied to input A. Simultaneous divisions of 2, 4, 8, and 16 are performed at the A, B,
C, and D outputs as shown in the truth table above.

2. V/hen used as a 3-bit ripple-through counter, the input count pulses ore applied to input B. Simultaneous
frequency divisions of 2, 4, and 8 are available at the B, C, and D outputs. Independent use of flip-flop A is
available if the reset function coincides with reset of the 3-bit ripple-through counter.

These circuits are completely compatible with Series 54/74 TTL and DTL logic families. Average power dissipation is
32 mW per flip-fiop (128 mW total).

absolute maximum ratings (over operating temperature range unless otherwise noted)

Supply Voltage Vcc (See Note 4) 7 V

Input Voltaae,Vjn (See Notes 4 and 5) 5.5 V
Operating Cace Temperature Range: SN5493S -55Cto125C

Operating Free-Air Temperature Range: SN5493J, SN5493N . .

-55Cto125C

SN7493 Circuits 0C to 70C

Storage Temperature Range . . .... 65C to 1 50C

NOTES: -1. Thfsu volt.ige wjlucs jre with ruip.'ct to nouvork nround terminal.

5. Inuut sloml* mmr ho zoro or oosilivo with ri.'.;...rt to m-Kvork ground terminal
 CiRCUIT TYi^S $V6m, S:J7193
4-DIT BKJAKY COU;iTE?.S

recommended operating conditions (over operating temperature range)

MIN NOM MAX UNIT

Supply Voltage Vcc (See Note 4): SN5493 Circuits , 4.5 5 5.5 V

SN7493 Circuits . 4.75 5 5.25 V

Normalized Fan-Out From Each Output (See Note 6) 10

Width of Input Count Pulse,
tp(jn) 50 ns

Width of Reset Pulse, tp(rcset) 50 ns

NOTE: 6. Fan-out from ourput A to input 0 and to 10 additional Series 54/74 loads is permitted.

electrical characteristics (over operating temperature range unless otherwise noted)

TEST
PARAMETER TEST CONDITIONS1
MIN TYPf MAX UNIT
FIGURE

Input voltage required to ensure

VCC=
vin(1l . .

logical.,1 at any input terminal

1 MIN 2 V

Input voltage required to ensure

2 Vcc "
MIN 'i 0.8 V
logical 0 at any input terminal

Logical 1 output voltage 2

Vout(1) j VCC MIN. l|02d=-400jjA 2.4 V
=

Vout(Q) Logical 0 output voltage 1

| VK=
dim, l;nk =
16 mA 0.4 V

Logical 1 level input current at

Vcc =
MAX. v:n -
2.4 V 40 UA

'in(l) 3
o o
Rqii) or
P.o[2) inputs
VCC =
MAX, vin =
5.5 V 1 mA

Logical 1 level input current at

VCC
=
MAX, Vin =
2.4 V 30 pA

in<1) 3
A or B inputs VCC
"
MAX, Vin =
5.5 V 1 1 mA

,
.
. - . ..
1
Luyiudi u ifewei input current at
'iii(O) v'cc
=
MAX, Vin
=
0.4 V -1.6 mA
R0(1) or
R0(2) inputs

Logical 0 level input current at

4 VCC= 0.4 V
'in(O) MAX, Vin =
-3.2 mA
A or B inputs

SN5493 -:o -57 mA

os Short-circuit output current 5 VCC "
MAX, Wo
SN7433 -18 -57 mA

St.'5493 32 46 mA
'CC Supply current 3 VCC =
MAX.V n=4.5V

SN7493 32 53 , mA

^ For conditions MIN

shown as or MAX, use the appropriate vafue specified under recommended operating conditions for the applicable
circuit type.

f All typical values are dt

Vcc =
5 V, TA =
25C.
Not mere than one output should be shorted at a time.

=
5 V, =
25C, I\l =
10
switching characteristics, V^q T^
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FIGURE

Maximum frequency of
C[_ =
15pF, RL-400I1 10 18 MHz
'max
input count pulses

Propagation delay time to

logical 1 level from input 6 C|_=15pF. RL

=
400fl 75 135 ns
tpdl
count pulse to output D

Propagation delay time to

logical 0 level from input 6 C|_=15pF, RL400n 75 135 ns

tpdO
count pulse to output 0

8-14 SEE ORDERING INSTRUCTIONS PAGE 1-1 -

 TTL CIRCUIT TYPES St!5490, SN7490
MSI DECADE COUNTERS

MSI TTL HIGH-SPEED DECADE COUNTERS

for applications in
Digital Computer Systems
Data-Handling Systems Control Systems
JORN
logic DUAL-INLINE PACKAGE (TOP VIEW)

TRUTH TABLES
BCD COUNT SEQUENCE
(See Note I RESET, COUNT (See Note 2)
OUTPUT RESET IN'JTS OUTPUT
COUNT
0 c 6 A
0 0 0 0 0 '2'
D C 8 A
0(1) 0'2'i| ?iM
1 0 0 1 0 1 1 1 0 X 0 0 0 c

2 0 0 j, 0 1 1 X 0 oooo

3 0 o ! i 1 X X 1 1 1 00 1
4 0 1 0 0 X 0 X 0 COUNT
5 0
| , 0 1 0 X 0
i X COUNT

6 0 1 1 o ! 0 X X
j 0 COUNT
7 0 i 1
. 1 X r. 1 , COUNT

8 1 0 0 0 NC No Internal Connection
FLAT PACKAGE (TOP VIEW)
9 1 0 0 1

1. Output A connected to input BD for BCD count. <& (b

2. X indicates that either a logical 1 or a logical 0 may
be present.
-i .._*
001
ip kiufi uTika (.ypiCai COuTi i CGf'i i iyui oiiOiiS i-
i \.. r n "4>
-rrr i

These high-speed, monolithic decade counters consist

of four dual-rank, master-slave flio-flops internally

interconnected to provide a divide-by-two counter k-f
_D

and a divide-by-five counter. Gnted direct reset lines

are provided to inhibit count inputs and return all

outputs to lo'jical zero or to

(BCD) count of 9. As the output from flip-flop A is
a binary coded decimal
0
the'

not internally connected to the succeeding stages,

positive logic: see truth table
count may be separated in three independent count

modes:

1. When used as a binary coded decimal decade counter, the BD input must be externally connected to the A
output. The A input receives the incoming count, and a count sequence is obtained in accordance with the
BCD count sequence truth table shown above. In addition to a conventional zero reset, inputs are provided
to reset a BCD count for nine's complement decimal applications.

2. If a symmetrical divide-by-ten count is desired for frequency synthesizers or other applications requiring
division of a binary count by a power of ten, the D output must be externally connected to the A input.
The input count is then applied at the BD input and a divide-by-ten square wave is obtained at output A.

3. For operation as a divide-by-two counter and a divide-by-five counter, no external interconnections are

required. Flip-flop A is used as a binary element for the divide-by-two function. The BD input is used to

obtain bin.iry divide-by-five operation al the B, C, and D outputs. In this mode, the two counters operate

independently; however, all four flip-flops are reset simultaneously.

These circuits aie completely compatible with Series 54/74 TTL and DTL logic families. Average powei dissipation

is 160 m'.V.
 CIRCUIT TYPCS S?;5490, S."I7490
DECADE COUNTERS

absolute maximum ratings (over operating temperature range unless otherwise noted)
'

Supply Voltage Vcc (See Note 3) 7 V

InputVoltage,Vjn (See Notes 3 and 4) 5.5 V
Operating Case Temperature Range: SN5490S -55C to 125C
Operating Free-Air Temperature Range: SN5490J, SN5490N -55Cto125C

SN7490 Circuits 0C to 70C

Storage Temperature Range -65C to 150'C
NOTES: 3. These voltage values are with respect to network ground terminal.

4. Input signals must bo zero or positive with respect to network ground terminal.

recommended operating conditions (over operating temperature range)

MIN NOM MAX UNIT

Supply Voltage Vcc (See Note 3): SN5490 Circuits 4.5 5 5.5 V

SN7490 Circuits 4.75 5 5.25 V

Normalized Fan-Out From Each Output (See Note 5) 10
Width of Input Count Pulse,
tp(in) 50 ns

Width of Reset Pulse, tp(reset) 50 ns

NOTE 5. Fan-out from output A to input BO and to 10 additional Series 54/74 loads is permitted.

electrical characteristics (over operating temperature range unless otherwise noted)

TEST
PARAMETER TEST CONDITIONS*
MIN TYP* MAX UNIT
FIGURE

Input voltage required to ensure

1 VCC =
MIN 2 V
logical 1 at any input terminal

Input voltage required to ensure

'"'
2 '"
-

lotirnl D at anv innut Tprminal

Vcc W.O
1
1

vout(1) Logical 1 output voltage 2 VCC=MIN. I|0.,h--400A 2.4 v

j
vout(0) Logical 0 output voltage 1 VCC =
MIN, lsink=16mA 0.4 V

Logical 1 level input current

Vcc =
MAX. vin =
2-4 V 40 ilA
in(U atR0(1|*R0{2), R9(1). r 3
Vcc =
MAX. Vin =
5.5 V 1 mA

R9<2)
Logical 1 level input current VCc
=
MAX. Vin =
2.4 V SO ,A

'inm 3
input A =
MAX, Vin "
5.5 V 1
at
VCC mA

Logical 1 level input current VCC

"
MAX. V, -
2.4 V 160 PA

,n(1)
3
at input BD VCC =
MAX, Vin -
5.5 V 1 mA

Logical 0 level input current

4 VCC "MAX, Vin=0.4V mA

(in{0> a*R0(1)*R0{2).R9m'or -1.6

R9(2)
Logical 0 level input current
4 VCC -
MAX, Vin -
0.4 V mA
,in,Q1 at input A
-3.2

Logical 0 level input current

4 VCC
"
MAX. Vin -
0.4 V -6.4 mA
linl0) at input BD

0 V SNE4?0 -20 -57 mA

'OS Short-circuit output current^ 5 Vcc
'
MAX, Vout SN7490 -
13 -57 mA

SIM5490 32 46 mA

Supply current 3 VCC-MAX. Vin V

ICC -4.5
SN7490 32 53 mA

* For conditions shown as MIN or MAX, uia the appropriate value speclflad under recommenced operating condition! for the particular

circuit type.

i All typical values are at Vcc -

6 V, TA -
25C
3 Not more than ona output should be shoried ot a time.
\ 8-2
1-1-
-SEE ORDERING INSTRUCTIONS PAGE
 CIRCUIT TYPES SM5442# SN5443, SM5444,
]TTL
SN7442, SN7443, SH7444
nsi
4-Li!:E"TO-IO-LmE DECODERS (l-OF-10)
BCD-to-Decimal o Excess 3-to-Decimal o Excess 3 Gray-to-Decimal

Also for applications as

4-Line to 16-Line Decoders e 3-Line to 8-Line Decoders

featuring diode-clamped inputs
j on n
description DSJAL-lfJ LINE PACKAGE (TOP VIEW)

These monolithic decimal decoders

INPUTS OUTPUTS
consist of eight inverters and ten A
four-input NAND gates. The CC
inverters are connected in pairs to
make BCD input data available for 16 1!i -J
14
~i
13 -
12 -
11 I
h- 10 1
r-i
3 1
decoding by the NAND gates. Full 1
. 1 'jT
decoding of valid input logic
ensures that all outputs remain off \ 1 1 "1 1
for all invalid input conditions. A B CD

The SN5442/SN7442
"3
BCD-to-decimal, SN5443/SN7443
excess 3-to-decimal, and 0123456789
SN5444/SN74M excess 3 o o o n n n n n n n

gray-to-decimal decoders feature

' hi
r1

familiar transistor-transistor logic i , , i

(TTL) circuits with inputs and nl/fr r*
7 1
outputs which are compatible for 12 j 4 D S 7 o
use with other TTL and DTL 0
.

GND
Circuits. D-C noKP marning pro

OUTPUTS
typically one volt and power

dissipation is typically 140

positive logic: see truth t3>jles
milliwatts. Full fan-out of 10 is
available at all outputs.

SN5442/SN7442 SN5443/SN7443 SN5444/SN7444 ALL TYPES

BCD EXCESS 3 EXCESS 3 GRAY DECIMAL
INPUT INPUT INPUT OUTPUT

i 0 ,1 !2.3 4|5,'6 17 8:9

0 | 0 o i o i <y I 0 :1 I
; |
0|l 00
1 1
0 1 0 I
|
0 110

0 I "I \\

10 0 0

10 0 1

4 o i o

10 11

110 0

1
J <i__}_
1 I 0
J li.
1 1
J 1^
J 0 0 l_0

0_ 0 J
I I I 10 0 10
CIRCUIT TYPES SH5442, SN5443, SSI5444,
SK7442, SII7443, SfJ7444
4-LME-T0-10-LME DECODERS (l-OF-10)

absolute maximum ratings (over operating temperature range unless otherwise noted)

Supply Voltage
Vcc (See Note 1) 7V
Input Voltage V;n (See Note 1 ) 5.5 V
Operating Free-Air Temperature Range: SN5442, SN5443, SN5444 Circuits -55C to 1 25C
SN7442, SN7443. SN7444 Circuits 0C to 70C
Storage Temperature Range 65Cto150C

recommended operating conditions (over operating temperature range)

MIN MOM MAX UNIT

Supply Voltage Vcc (See Note 1): SN5442, SN5443, SN5444 Circuits . 4.5 5 5.5 V

SN7442, SN7443, SN7444 Circuits . 4.75 5 5.25 V

Normalized Fan-Out from each Output (N) 10

electrical characteristics (over operating temperature range unless otherwise noted)

TEST
PARAMETER TEST CONDITIONS*
MIN TYPf MAX UNIT
FIGURE
1
v_
Input voltage required to ensure =
M.N
,n'
'
logical 1 at any input terminal
and VCC 2 V
2
1
Input voltage required to ensure 0.8 V
and =
MIN
ln'0'
logical 0 at any input terminal VCC
2

Logical 1 VCC MIN.

=
Vin|||=2V,
vout(1) output voltage 2 2.4 V
Vin(0)=0.8V. lioad'-tOO^A

v--- 1
Vout(0) Logical 0 output voltage 1 0.4 V
Isink= 18
Vin(0)=0.8V. mA

Logical 1 level input current VCC=MAX. Vin =

2.4V 40 pA
10(11 3
(each input) VCC "
MAX. Vin =
5.5 V 1 mA

Logical 0 level input current

in(0) 4 Vcc m
MAX- vin '
0-4 V -1.6 mA
(each input)

VCC=
SN3442, SNS4 43, SN5444 -23 -55 mA

IqS Short-circuit output current 5 MAX. 3N7442. SM7--3. 3.N74-J4 i _-,3 -5 = n-.A

Supply 4 MAX
SN5442. SNS4-13, SN5444 | 28 41 mA
'CC current VCc -

SN74-12.SN7444
SN7442, | 28 5S mA |
25

switching characteristics, Vqq

=
5 V, T^
=
C, N =
10

TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FIGURE
Propagation delay time to
t*'0
6 C|_-15pF. RL-400n 10 22 30 ns
logical 0 level through

two logic levels

Propagation delay time to

tpdO logical 0 level through 6 CL=15pF. RL-400n 23 35 ns

three logic levels

Propagation delay time to

logical 1 level through 6 Ci_*15pF. RL=-400n 10 17 25 ns

tpdf,
two logic levels

Propagation delay time to

tp<jt logical 1 level through 6 C|_-15pF. RL-400n 26 35 ns

three logic levels

* For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for tha

applicable device type.

f All typical values are at VCc

"
5 V, TA -
25C.

Not mora than one output should be shoned at a time.

-SEE ORDERING INSTRUCTIONS PAGE 1-1-

 CIRCUIT TYPES S.N5402, SN7402
QUADRUPLE 2-IMPUT POSITIVE NOR GATES

schematic (each gate) S FLAT PACKAGE J OR N-DUAL-IN-LINE PACKAGE

(TOP VIEW) (TOP VIEW)

4Y 4C 4A GND 313 3A 3Y
4Y 48 4A 3Y 3B 3A
cc

j -=, 66i rQ
~ nifLLMMiJliftir
1Y IA IB 2Y 2A 2B GND

O C-ND
NOTE: Component VElucs sho^vn Lre nominal.
positive logic: Y A + B

recommended operating conditions

MIN NOM MAX UNIT

Supply Voltage Vcc: SN5402 Circuits 4 5 5 5.5 V

SN7402 Circuits 4.75 5 5.25 V
Normalized Fan-Out From Each Output. NJ . . . 10
^: SN5402 Circuits . -55 25 125 C
o
uunui >..i luiu . ...... 0 25 70 - I

electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)

TEST I
PARAMETER
FIGURE
TEST CONDITIONS*
MIN TYPJ MAX UNIT
j
Logical 1 input vol lace required
I
vin(1) 3t either input terminal to ensure 8 VCC= MIN 2 V
logical 0 level at output

Logical 0 input voltoge required

vin!0) at both input terminals to ensure 9 Vcc= MIN 0.8 V

logical 1 level at output

Vcc-r.'IN. Vin-0.EV,
vout(U Logical 1 output voltage 9 2.4 3.3 V
l|oad =
-^00WA

VCC =
MIN, Vin =
2V.
vout(0) Logical 0 output voltage 10 0.22 0.4 V
'sink =
10 mA

Logical p level input current (each

'intOI 11 Vcc =
WAX- vin '
0-4 V -1.6 mA
input)
Logical 1 level input current (each VCC =
MAX, Vjr1 =
2.4 V 40 wA
'Ml) input)
12
VCC' Vin=5.5V
MAX, 1 mA

SN5402 -20 -55

U~ MAX
Ub Short-circuit output currents 13 Vcc mA

SN7402 -18 -55

'CCIOi Logic.il 0 level supply current '

'**
=
5 V
14 4.C. Vin 14 27 mA

'ccdi Logical 1 levil supply curie.m 14 V'cc

-
MAX. V|n
=
0 8 16 mA

=
5 V, T A =
25 C, N =
10
switching characteristics, Vqq
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FIGURE
CL= nL-
rpd0 Propagation deldy tmi"
to logical 0 level 65 15 pF. 400 n 8 15 ns

RL
*pd1 Propagation dcldy tir--.i'
'o to -iraf 1 le.-el G5-
|CL =
15 l-F. 400 11 12 22 ns

t For condition* shown as M[N or MA \r use rho appropriate value specified under recommended operating conditions for the applicable

device type.

\ AM V =
5 V, *
25C.
typical values arc at
Tft
Not mori*
than one output should do shorted at s time.

-SEE ORDERING INSTRUCTIONS PAGE 1-1-

 CIRCUIT TYPES SN5470, SN7470
EDGE-TRIGGERED J-K FLIP-FLOPS

logic
S FLAT PACKAGE J OR N DUAL-INLINE PACKAGE '

(TOP VIEWi (TOP VI El'.')

TRUTH TABLE f
V, P=;tSt CLC

n r~1
J K (lD 1 13 - ni i !~rnj
Q

0 0 Qn
0 1 0 1
1 0 1 1 oE-5
I '6^6
6?^
1 1 Qn "6
\~6r6r-
1
CD
J*
1. J - JI J2 . .

2. K = KI K2 .K*. .

CLOCK P,tr CLEAR NC JI

3. Tn Bit tn-..? before clock Dulse.
= Ki Vcc
4. tn + i = Bit time after deck pulse.
K*
5. If inputs j*
or are not used

they must be grounded. positive logic: Low input to preset sets Q to logical 1

6. NC No Internal Connection Low input to clear sets Q to logical 0

Preset or clear function can occur only
when clock input is low.

description

These monolithic, edge-triggered J-K flip-flops feature gated inputs, direct clear and preset inputs, and ccmplsmertery
Qand Q outputs. Input information is transferred to the outputs on the positive edge of the deck pulse.

Direct-coupled clock triggering occurs at a specific voltage level of the clock pulse, and after the clock input threshold
voltage has been passed, the gated inputs are locked out.

These flip-flops are ideaily suited for medium-

to high-speed applications and can result in a significant saving in system

power dissipation and package count where input gating is required.

recommended operating conditions

MiN NOM MAX UNIT

Supply Voltage Vcc: S.N5470 Circuits 4.5 5 5.5 v

SN7470 Circuits 4.75 5 5.25 V

Operating Free-Air Temperature Range, Ta: SN5470 Circuits -55 25 125 =c

SN7470 Circuits 0 25 70 c
Normalized Fan-Out From Each Output, N 10
5 150 ns
Clock Pulse Transition Time to Logical 1 Level, ti (clock) 'See Figure 68)
Width of Clock Pulss, tp(c|ock) (See Figure C8)
20 ns i
25 ns
Width of Preset Pulse, tp(presetj (See Figure 67)
25 ns I
Width of Clear Pulse, tp(c|ear) (See Figure 67)
CIRCUIT TYPES 5N5470, SII7470
EDGt-TRIGGEHED J-K FLIP-TLO^S

electrical characteristics (over recommended operating free-air temperature range unless otherwise noted)

TtoT
PARAMETER TEST CONDITIONS* MIN TYPt MAX UNIT
FIGUHE
Input voltage required to
36
^in(l) ensure logical 1 at any and Vcc
""
MIN 2 V

input terminal 37

Input voltage required to

36
Vjn(Q) ensure logical 0 at any and
Vcc "
MIN 0.3 V
37
input terminal
"

vout[1) Logical 1 output voltcrje 36 VCc =

MIN, l|0Bd='OOpA 2.4 3.5 V

vout(0) Logical 0 output voltaic 37 Vcc =

WIN. 'sink ="
16 mA C.22 0.4 V

Logical 0 level input current at J1,

l'nl0) 33 Vcc =
MAX, Vin =
0.4V -1.6 mA
J2, J*, J1.K2, K\ or clock

Logical 0 level input current at

38 Vcc =
MAX, Vln =
0.4 V -3 2 mA
preset or clear

Logical 1 level input current at JI, Vcc

=
MAX, Vin
-
2.4 V 40 i pA

mil)
33
i
J2, J*. K1. K2, K*, orclock VCC =
r.'.AX. Vin =
5.5V mA

Logical 1 level input current Vcc

'
MAX, Vin = 2.4 V r.Zs fA
39
at presat or clear VCC -
MAX, Vjn =
5.5 V i rr.A

EN5470 -10 -57

'OS Short-circuit output current^ 40 VCC "MAX, vin

=
mA
SN7470 -18 -37

Supply V; -
5 V 13 ?S mA
'CC current 30 Vrc =
MAX,
rui wOrnJiLiuna E.ujvi, oi tVilN ut Eif\'F., uw mc d^pfopnac-j value spectiiea unaer recomnienaeo operating conditions tor The applicable

device type

% AM tvpic3l values =
5 V, a
25 C.
are at
Vcc Tft
3 Not more than one output should be shorted at e time.
25

switch ng characteristics, Vcc =

5 V, Ta =
Z, N =
10

1
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FIGURE

Maximum frequency 63 C|_ =

15 pF, RL =400n 20 35 MHz
'clock clock

15 pF, = 400 a. 10 20 ns
'setup
Minimum input setup t;me 63 CL =
RL
Minimum input hold time 63 CL'-=-15pF, RL =
4oon 0 5 ns
'hold
Propagation delay time to logical 1

level from clear or preset to 67 CL=15pF, RL=40on 50 ns

ipdl
output

Propagation delay time to logical 0

CL= = 40on 50 ns
tpdO level from clear or preset to 67 15pF, RL
output

Propagation delay time to logical 1

63 CL-15pF, RL
=
400f! 10 27 50 ni
1pd1 level from clock to output

Propagation delay time to logical 0

68 CL 15 pF, RL
-
400 n 10 18 50 ns
'pdO level from clock to output