ENGINEERING A DEVICE FOR
ELECTRON-BEM
WILLIAM T. LEE
Schlumberger Technologies
Integrated circuits are rapidly growing
denser, and features are starting to
shrink below 1 pm. The use of me-
chanical probers on these chips for de-
vice diagnosis is becoming impossible.
Many semiconductor manufacturers
have started using electron-beam
probe stations for critical diagnostic
work. The guidelines presented in this
article will help users of e-beam probe
stations to optimize their IC design
and manufacturing procedures for
e-beam probing.
36
PROBING
A
s device geometries continue to shrink, commercialparts
with submicron features are starting to hit the market in
increasing numbers. High circuit densities and small
linewidths make it increasingly more difficult to probe
these devices with conventional mechanical probing. Mechanical
probes are potentially destructive. They also capacitively load the
device and may alter its behavior. Laser beams have been suc-
cessful in probing ICs and printed-circuit boards to some extent.
They provide good spatial resolution and offer large-bandwidth
channels of acquisition, but they are not applicable to all devices.
Electron-beam probing is fast becoming the preferred technique
for looking at chips that are too dense or complex for mechanical
probers. E-beam probers are no longer limited to R&D labs but
are penetrating IC manufacturing centers all over the world. With
the growing popularity of e-beam probing comes the need for
design and manufacturing engineers to know more about it.
Without information on this technology, they are in danger of
creating complex devices that do not meet the requirements for
e-beam probers. As a result, they will have a device that neither
a mechanical probe nor an e-beam probe can evaluate.
Obviously, this situation would cause a company considerable
financial grief. By following a few guidelines during the device’s
design and manufacturing phases, engineers can avoid this
problem. Design engineers will be able to debug chips faster,
failure-analysis engineers will be able to find faults more quickly,
and product engineers will find it easier to characterize and
improve device performance and yield. All this leads to a reduc-
tion in the time and cost of bringing the device to market,
improved profit margins, and an increased likelihood of success
in the marketplace.
PRINCIPLES OF E-BEAM PROBING
To understand the reasoning behind the guidelines for
designing a device suitable for probing, we first need to under-
stand the basic principles behind e-beam probing itself. There are
many types of electron-beam probe stations in use throughout
industry and academia. 1have chosen to describe a basic system An e-beam probe
that uses the latest-and most advantageous-features.
~ n of y the sources listed in “Further reading” at the end of this station generates
article will provide more information on the general principles of
electron-beam probing. both primary
An electron-beam probe station consists of electrons and lower
0 an electron-beam source

0 a system of lenses for focusing the beam on the target device

energy Secondary
0 an assembly to collect and detect electrons
e1ecb-m.
electronics for waveform acquisition plus a high-speed beam
blanker
The system contains an electron source such as tungsten, LaB6
(lanthanum hexaboride), or a thermal field emitter, which gener-
ates low-energy electrons, called primary electrons. The system
accelerates primary electrons through a potential difference of
anywhere from 500V to 2,500V. It then focuses the beam to a
submicron spot on the target device, where the beam interacts
with the atoms near the surface of the device to generate other
electrons of much lower energy. These electrons, which typically
have energies 0 eV to 20 eV, are called secondary electrons, and
are generated through elastic collisions. A n assembly that con-
sists of an electrostatic or magnetic extractor collects the elec-
trons, and a scintillator and a photomultiplier tube (Figure 1)
detects them.
During image acquisition, the system raster-scans the beam
across the device and feeds the detected secondary-electron
signal into a video monitor. The number of secondary electrons
that escape the surface of the device is a function of the electric
potential in and around the point where the primary beam lands.
If the primary beam lands on a surface metal conductor with a
5V positive potential, fewer secondary electrons will escape than
if the conductor had OV. The metal conductor generates a positive
electric field around itself that draws the low-energy secondary
electrons back into the device. Thus, conductors with positive
potentials look dark in the video monitor image, while negative
potentials look bright. This difference forms the basis for a
process called voltage-contrast imaging.
During waveform acquisition, the system feeds the detected
signal into a waveform display, either in software or on a scope
display. A feedback loop maintains a constant secondary-electron
current at the scintillator in this process. The current is con- Device
trolled by a voltage applied to a filter grid placed between the Photomultiplier Objective
device and the detector. We can use either closed-loop or open-
loop acquisition to capture waveforms. With closed-loop acquisi-
tion, we can capture accurate analog waveforms, but the acqui-
Filter
sition time suffers because the feedback loop takes time to settle.
Open-loop acquisition yields digital waveforms without this lim- Beam
itation because the detected signal is compared against an abso- blanker
lute threshold derived from a user-supplied reference value. Electron
Accelerating source
Both types of waveform acquisition have an upper limit on the anode
measurement bandwidth. This limit is imposed by the integration
time constant of the electronics that builds up the waveform from Figure 1. Basic electron-beam probe
the detected signal. We can remove the limitation by using a beam system

JulvE 1989 37
 ELECTRON-BEAM PROBING

beam blanker: a device used to pulse the beam by sweeping it past a n aperture. This pulsing turns the e-beam
system into a sampling system. Sampling is necessary to overcome the inherent bandwidth limit if the e-beam
is to be used in a continuous, or analog, fashion. By sampling, the system's bandwidth is now limited by the
sampling pulse's size.
collimation: Electrons come off the surface of the die at all angles (a) but end up through a n aligning process
reaching the detector in parallel or at least more parallel (b).This alignment, or collimation, is necessary because
in front of the detector is a filter grid with a retarding voltage applied to reject electrons with too low energy (c).
If electrons arrive off-axis, not in parallel, their energy may be too low to overcome the retarding potential on
the grid. Hence, good data may be rejected, which leads to more noise.

Primary electron0 Secondary

I v9 A
I ,electron

duty cycle: the ratio of timebase to trigger period (reciprocal of the trigger frequency), or the ratio of the part
of the waveform being viewed/acquired to the entire waveform. For example, if the entire test pattern set
(waveform)is 100 ns, and the window for viewing (part of the waveform being viewed) is 10 ns, the duty cycle
is 1:lO.
elastic collision: a collision of objects in which both total energy and momentum are conserved. An example
is the collision of two billiard balls. An example of inelastic collision is putty against a wall.
eV: eV is a measure of energy, specificallya n electron volt, the energy needed to accelerate one electron through
one volt.
inverted QFPs/PGAs/cavity up/cavity down: All these are types of packaging. QFP, for quad flat pack is a
chip whose leads are on the edges. PGA, for pin grid array, is a square array whose leads or pins are on the
bottom. Cavity up is packaging in which the die is on the opposite side of the pins with chip in the middle. In
cavity-down, or inverted, packaging, the die is on the same side as the pins.
passivated part: part with a layer of passivation, which is a protective layer of insulating material (oxide/ni-
tride/polyimide) used to keep the die from damage through corrosion, humidity, or handling by humans.
Unpassivated parts are parts without this insulating layer. Depassivated parts are parts that originally had
this layer but it has been removed.
photocathode: a source of electrons (cathode) that can generate electrons through a process called photoernis-
sion, which is photons generating electrons.
time of flight: the length of time a n electron travels from source to destination. The speed of light is 3xlOe8
m/s. Thus, in 1 n s (10e-9 s), an electron traveling at the speed of light will travel 3xlOe8xlOe-7 = 0.03m or 3
cm. In 1 ps (10e-12), the same electron travels 0.03 mm. If we want nanosecond accuracy, individual secondary
electrons can arrive up to 3 cm apart and this would lead to only a 1-ns error. If secondary electrons that result
from the same primary electron arrive even 1 mm apart they already produce 30 ps of timing error. This error
margin is serious for systems that want to achieve picosecond accuracy. A PSEM is a n example of such a
system, in which the whole idea is to use the fast pulsing capability of the laser/photocathode source. Thus,
secondary electrons must be made to travel together-their paths must be of similar length, etc. If they stray
apart, they will have different times of flight.
trigger frequency: To achieve high measurement bandwidth, most e-beam systems pulse the beam, turning
waveform acquisition into a process analogous to that used in a standard sampling oscilloscope. Sampling
systems require a many repetitions of the measurement process. Thus, the test patterns used to exercise the
device have to run in a loop. To indicate the beginning (or end) of the test loop, the stimulus source must provide
a sync or trigger pulse to the sampling system. The trigger frequency is the frequency of this sync pulse, and
hence determines how often the test loop repeats.
voltage-contrast imaging: method of acquiring scanning electron microscope images from chips. The contrast
variation in the image is caused by a variation in voltage on the surface of the chip being imaged. The voltage
variation is due to variations in the number of secondary electrons that escape the chip's surface from variations
in local electrical fields.

38 IEJ3E DESIGN & TEST OF COlUPLlTERS

blanker to pulse the beam and turn the e-beam probe into a
sampling system. In this way, the measurement bandwidth is
We can use the
limited only by the smallest beam pulse that can be generated. electron beam to
We can place the assembly to detect secondary electrons in frobe the wavejiwms
either a post-lens or a pre-lens position. In a post-lens position,
the assembly is beyond the final lens. In the pre-lens position, it in buried AC signuls
is in the body of the electron-beam column behind the final lens.
The pre-lens scheme leaves more room between the physical end by monitoring the
of the column with detection assembly and the device being electrical behavior
probed. This greater clearance is needed for wafer probing be-
cause most probe cards, especially the high-bandwidth blade or on the surface.
ceramic probe cards, require more than 5 mm of headroom.
We can collect secondary electrons by drawing them away from
the surface of the device. One way to do this is to use an
electrostatic extraction field at the device’s surface, applying a
positive potential of approximately 1 kV. The disadvantage of this
method is that we are placing a high-voltage grid close to device.
This grid can destroy the device; cause surface charging of
dielectrics, which prevents the probing of buried layers: or se-
verely decrease the working distance, which prevents the probing
of wafers.
The alternative to that method of collection is to use a magnetic
extraction/collimating field, which does not require the high-volt-
age grid. Moreover, with this method, electrons are collimated s o
their full velocity component is detected, and the system can
better discriminate their energy levels.
When the primary beam lands on bare metal or other type of
conducting layer, the voltage reading is that of the conductor.
However, if the beam lands on insulation, then the reading is that
of the surface potential. If there is a conductor buried beneath
the surface, the surface is capacitively coupled to the buried
conductor. We can use the electron beam to probe the waveforms
in buried signals by monitoring the electrical behavior on the
surface. However, this approach works only on time-varying (AC)
signals, since the surface charge will inevitably leak away and
reestablish equilibrium. We cannot measure DC signals through
insulation. We can, however, measure both AC and DC signals
on surface conductor layers because the conductor maintains a
definite potential at all times as long as it is not floating.
Before departing from e-beam principles entirely, I’d like to
touch briefly on the photoelectron scanning electron microscope.
The PSEM technique is technically an e-beam probing technique
because image and waveform acquisition are based on the collec-
tion of returning secondary electrons. The microscope generates
ultrashort pulses of electrons via photoemission using a pulsed-
’
laser/photocathode arrangement. The secondary electrons are
typically viewed in picoseconds, vs. the nanoseconds of a pure
e-beam probe. Thus, any time-of-flightvariations induced by local
electric fields have a more pronounced impact on the timing
accuracy and resolution of these electrons. Consequently, if the
device is a high-speed part destined for a PSEM system, the
guidelines presented here are even more critical.

JUNE 1989 39
 ELECTRON-BEAM PROBING

m e primary GUIDELINES
electron beam must These design and manufacturing guidelines fall into three
categories: observability, accuracy, and usability. Observability
have a clear path to guidelines deal with allowing the electron beam unobstructed
access to the signal line being probed. Accuracy guidelines deal
all areas of the die with the shape, amplitude, and timing accuracy of the waveforms
that need to be being acquired. Usability guidelines deal with the practical issues
of using an e-beam probe station.
probed.
OBSERVABILITY
The first set of guidelines ensures that the primary beam can
reach the conductor, or if it encounters an insulating layer, that
the buried conductor has a clear path to the surface. These
guidelines consist of maintaining line of sight, direct vs. indirect
measuring, and using test points.

MAINTAINING LINE OF SIGHT

Guidelines in this category are ior placing bond pads and
routing metal interconnections.

Placing bond pads. The primary electron beam must have a

clear path to all areas of the die that need to be probed. Bond
wires or probe-card pins can block the primary beam’s path.
Since the returning secondary electrons more or less retrace the
path of the primary electrons, the guideline applies to both the
incident beam and the returning beam of electrons:
Do not place bond pads where bond wires or probe card pins
will obscure the areas of the die you want to probe.

Routing metal interconnections. If buried signals are to be

probed via capacitive coupling to the surface, then we must have
a clear line of sight from the buried conductor to the surface of
the insulating layers. Thus, overlying metal-2 lines cannot ob-
scure the metal- 1 lines, poly lines, or diffusion areas that we want
to probe. The same applies to all overlying conductor layers.
Do not obscure access to buried conductors you want to probe.

Power/ground metal planes. For technologies with an overly-

ing metal plane, which is typically used as a ground plane, the
probe must be able to access all buried signals we want to probe.
One way to ensure this is to cut holes in the overlying power or
ground plane.
Provide access ports in overlying powerlground planes.

DIRECT VS. INDIRECT MEASURING

Guidelines in this area involve passivated vs. unpassivated
devices and calibration structures.

Unpassivated devices. Bare conductors give accurate ampli-

tude readings when probed with an electron beam. Also, we can

40 JEEE DESZGN & TEST OF COMPUTERS

observe DC levels on bare conductors. Surface measurements on
buried conductors suffer from signal attenuation as the insula-
When accurate
tion thickness increases. Moreover, the measured signal is always voltage i@vrm.ution
AC coupled, so we cannot observe DC levels. Thus, an un-
passivated device will yield clearer results. is required about
Probe devices without passivation whenever possible. buried signals, the
Passivation thickness. In many instances, especially in failure best solution is to
analysis, we may not be able to remove passivation because it is bring a test point up
too difficult, it will destroy the device, or it will alter device
behavior. In such cases, we can partially remove the passivation to the suqace.
layer or put on a thinner layer when manufacturing the device.
We can also reduce the thickness of the intermetal/poly insula-
tion as long as we are not sacrificing functionality or reliability.
Either of these actions will improve the capacitive couplingeffect,
which is inversely proportional to the buried conductor’sdepth.
Use the thinnest insulation and passivation layers necessary,
preferably no greater than the linewidth

Calibration structures. We can use a simple surface-conduc-

tor-to-buried-conductor structure to compensate for the signal
attenuation when taking measurements over buried conductors.
Suppose we know that the metal- 1 /metal-2 insulating layer has
little variation in thickness across the die and a 5V-amplitude AC
signal in the buried metal- 1 line measures 5V on the bare metal-2
portion but only 3V on the insulation directly above the metal-1
portion of the same electrical net. We can then apply a correction
factor of 5 / 3 in general to other metal-1 measurements. This
approach will give voltages in buried signals to a first approxima-
tion.
We can use the simple structure in Figure 2 to obtain the
attenuation factor as long as we add it to the device in some
unused area of the die. The waveform we observe comes from the
convolution of the sampling pulse and the actual signal. We can
also use deconvolution algorithms2 to reconstruct the original
waveform by approximating the sampling-pulse profile and the
effects of attenuation through the insulation.

USING TEST POINTS

Guidelinesin this area include how to place test points and the
characteristics of test points.

Placing test points. When accurate voltage information is

required about buried signals, the best solution is to bring a test
point up to the surface. Test points are either electrically con-
nected to the buried conductor, with a simple via, for example, or
they are not. Connected test points provide the most accurate Surface swing
conductor
waveform readings on the surface as long as they do not add too 5V swing
much capacitance to the conductor they are attached to. A direct Buried conductors
connection is not always feasible or harmless, though, so the
unconnected test point is the next best thing. A surface pad of Figure 2. Structure for calibrating the
metal increases the capacitive coupling effect and provides a attenuationfactor.

JUlVE 1989 41
 ELECTRON-BEAM PROBING
better reading than the surface charge off the insulating layer.
The center of the Figure 3 illustrates.
c d u c t q where it is Add via test points ifpossible or else use surface pads to
enhance signal accessibility.
most likely to be
flattest and where Test-point characteristics. The test points should be on the
die surface, not buried, s o the electron beam can read them
most of the beam can directly. They should be at least three times the beam’s rated spot
size, which is typically the beam’s width at half maximum bright-
land, is the best ness. This size ensures that the beam does not stray off the test
place to take point when its axis is centered on the test point. The surface of
the test point should be flat. Any angled surfaces will generate
measurements. secondary electrons that are at large angles to the primary beam’s
axis, which may affect voltage accuracy.
Use large, jlat test points.

ACCURACY
These guidelines concern how to maximize the accuracy of the
waveforms acquired from the device, including how to maximize
the strength of the signal to be measured, how to minimize the
attenuation from intervening materials, and how to reduce noise
and crosstalk.

IMPROVING SIGNAL- TO-NOISERATIO

Guidelines in this area deal with conductor width and topogra-
phy and the type of dielectric material.

Conductor width. Exposed surface conductors have to be large

enough for the primary beam to land on. A ratio of conductor
width to the size of the beam spot of at least 3:1 ensures that 98%
of the beam lands on the conductor (assuming a Gaussian
distribution for the intensity profile of the brightness across the
spot). For buried conductors, we should maximize the conductor
width to increase the capacitive coupling effect to the surface. We
do not have to maintain the large width throughout the buried
conductor’s path through the chip. Widening the line at selected
probe points is sufficient. Figure 4 illustrates.
Widen buried conductor lines at selected probe points to increase
capacitive coupling to the surface, aiming for a width-to-depth
ratio of at least 1:l.

Conductor topography. A 2-pm metal line may look pretty flat

to a 1 -pm beam, but not to a 0.1-pm beam, which will be affected
by surface microstructures. Some e-beam probes scan lines to
turn the probe spot into a probe line. This allows the beam to
average the microstructures and not produce anomalous read-
ings because the landing surface is at strange angles.
M a k e the exposed probe points as smooth as possible.

Even with relatively large spot sizes, surface planarity affects

measurements significantly. The center of the conductor, where
it is most likely to be flattest and where most of the beam can

42 IEEE DESIGN & TEST OF COiUlJUTERS

 ALTERNATIVES TO E-BEAM PROBING
Other than e-beam probes, the two most popular
kinds of probes are mechanical and laser probes.
Other types of radiation have been used in probing
devices, but primarily for structural and material
analysis, not for signal measurement.
Mechanical probes. Mechanical probers are fast
becoming obsolete for next-generation VLSI/ULSI
devices, primarily because the technique is invasive
and potentially destructive. I t is not uncommon for
a device to survive a few probe sessions before failing
completely because the probe has severed a metal
line or has displaced conductive material causing the
device to short. Another disadvantage is that the light
optics used to image the area being probed limit the
user’s ability to place the probe on a submicron
feature. Optical microscopes are inherently re-
stricted to spatial resolutions of a micron or more, so
we do not get a precise image of the point being
probed. In addition, optical microscopes have a very
limited depth of field, which makes it impossible to
view both the probe tip and the die surface simulta-
neously until just before contact.
Another drawback to mechanical probes is that the
probe itself is capacitively loading and can easily alter
the signal-behavior measurement. The addition of
this parallel capacitive load to the node being probed
increases the RC time constant and tends to increase
rise/fall times and mask out the high-frequency
components in the signal.
Finally, it is very diff‘icult to probe more than a few
points at a time because there is so much hardware
around the die. We cannot, for example, simulta-
neously probe all signals on a 32-bit bus. Hence, we
cannot make a n easy comparison of all the related
signals.
The only advantage of mechanical probing over
other techniques it that it can force signals at select
nodes in the device. Forcing signals is a must for
certain situations, and there is no substitute for a
mechanical probe in those cases. This does not mean
that e-beam or laser probe stations could not have
mechanical probes inside the chamber injecting sig-
nals into the part. However, this hybrid approach is
possible but not practical.
Another possibility not yet in the realm of the
practical is a technique called EBIC (electron-beam
induced current) that can force small currents into
devices. The difficulty in controlling the current is
what makes this technique impractical.
Laser probes. Of the types of laser probing avail-
able, three are the best understood and the most
likely to appear on the market: the photoexcitation
probe, the electro-optic probe, and the electro-optic
crystal probe. Other laser-based probing techniques
show some promising results in the research lab but
are further from commercial application.
JUNE 1989
The photoexcitation probe shines a laser beam
through the active region of a transistor and monitors
the power-supply current. The beam generates elec-
tron-hole pairs, which contribute to the current
through the transistor when it is on but make no
contribution when the transistor is off. Thus, the
power-supply current shows a small but detectable
change when the beam passes through a transistor
that is on versus no change when the transistor is
off.
The advantage of this technique is that the user can
perform a digital (logic-analyzer-style)analysis of the
device. The major drawbacks are that it works only
for CMOS devices, since the power-supply current
being drawn must be small for these perturbations
to show through. NMOS is very difficult to probe, and
ECL devices are impossible. Again, the spatial reso-
lution achievable by this technique is limited by the
inherent limit of light optics.
The electro-optic probe shines a laser beam through
or bounces the beam off a conductive region of the
device and measures the phase change it undergoes.
This phase change is proportional to the electric field
in the material and can be used to determine the
on/off state of that region. This direct electro-optic
technique can be used to probe 111-V materials, such
as GaAs, with good temporal resolution.
A related technique, called plasma-optic probing,
can be used to detect similar effects in symmetric
atomic structures, such a s silicon.2 The phase
change is proportional to the volume of material the
beam passes through in addition to the material‘s
potential. Thus, the technique gives a reading of the
space-charge density in the material and not a direct
reading of the conductor voltage.
The electro-optic crystal probe shines a laser beam
down a thin rod towards the surface of a device and
reflects it back up the rod via an electro-optic crystal.
such a s LiNbOs (lithium niobate). This crystal and
rod are placed in proximity to the surface of the
device and the beam passes through the electric
fields above the surface of the device around the
conductive features. The electric field influences the
phase change of the beam by affecting the phase-re-
tardation characteristic of the crystal. The primary
disadvantage of this technique is the low spatial
resolution afforded by the system, which is limited
by the size of the crystal. The crystal must be a s small
as possible, but still have facets that can reflect the
beam properly.
REFERENCES
1. K. Weingarten et al., “Direct Electro-optic Sampling of
GaAs Integrated Circuits.” Electronic Letters, Vol. 2 1,
1985, p. 765.
2. H. Heinrich. A Non-Invasive Optical Probe for Detecting
Electrical Signals in Silicon Integrated Circuits,G L report
4190, Stanford Univ.,Stanford, Calif., 1987.
43
 ELECTRON-BEAM PROBING

Exposed surface test pads
Figure 3. Directly connected buried con-
ductor (4and capacitively coupled bur-
ied conductor &).
land, is the best place to take measurements. Placing the beam
on the conductor edge causes more secondary electrons to be
generated because of the sharper curvature, and results will be
unpredictable. Having less of the beam land on the conductor will
also cause a different yield of secondary electrons in the sur-
rounding insulator and give incorrect readings3
Make the surface of exposed probe points as p h a r as possible.
Dielectric material. From the relation, q =CY the change in q
is larger for a given change in V if capacitance C is larger. C
increases with the dielectric constant k of the dielectric material.
To maximize the change in the surface charge for a voltage swing
in a buried conductor, the insulating material should have as high
a dielectric constant as possible.
Select materials with a high dielectric constantfor insulation
between conductors.

REDUCING CROSSTALK
Guidelines in this area concern dielectric thickness and the
E-beam

in
spacing between conductors.

Dielectric thickness. The capacitive coupling effect is directly

Jog to provide proportional to the conductor’s width and inversely proportional
to its depth from the surface. At the same time, deeply buried
conductors are more difficult to probe without picking up cross-
talk from neighboring surface and buried conductors. Figure 5
conductors illustrates.
Minimize the depth of the buried conductor at selected probe points.
Figure 4. Widening conductors at test
points. Interconductor spacing. We also need to increase the distance
to neighboring conductors to lessen their influence at the mea-
surement point.
Maximize lateral spacing to neighboring conductors at selected
probe points.

MAINTMNING A CONSISTENT ENVIRONMENT

Guidelines in this area include how to make the layout asym-
metric and where to place ground rings.

Asymmetric layout. As the primary beam approaches the

target probe point, it travels through and is influenced by all the
local fields from the die. We need to minimize the effect from this
sum so that the primary electrons can land accurately on the
Nearby device surface. The returning secondary electrons are influenced
conductors
to a greater extent because their energies are much lower. Inter-
ference along their path to the detector will increase amplitude
and timing errors and increase background noise. This global
field effect is strongest when large areas of the die switch in
Conductor being probed unison, creating macro-sized shifts in their combined fields.
We can minimize these shifts by spreading out the blocks of
Figure 5. Crosstalk from neighboring logic or interconnections that switch in unison. Changing the
conductors. placement of logic elements creates a more random distribution

44 IEEE DESIGN & TEST OF COMPUTERS

of a particular macro function across more die area. This tech-
nique minimizes the strength of the changes in the global field.
Making a device
Increase the asymmetry of the layout to minimize the effectsfrom physically suitable
the sum of all localfilds.
for e-beamprobing is
Ground rings. We can further stabilize the local fields around only part of the tusk.
selected probe points by surrounding the probe point with a
stable potential. The greatest electric field influence on the re- We must also
turning secondaries occurs within the first few microns of the die
surface. By placing ground lines adjacent to surface conductors consider how
and ground rings around test points from buried conductors, we practical it is to use
can reduce crosstalk.
Place ground planes/lines/rings around probe points. an e-beamprobe.
USABILITY
Making a device physically suitable for e-beam probing is only
part of the task. We must also consider how practical it is to use
an e-beam probe. Acquired waveforms and images are inherently
noisy. We can compensate for these effects through some form of
signal averaging, but the time it takes to get a decent, usable
waveform or image depends on many factors. The length of the
test program, for example, determines the trigger frequency and
the duty cycle, which affect waveform-acquisition time. The
voltage resolution required also determines acquisition time.

REDUCING ACQUISITION TIME

Guidelines on reducing acquisition time include how to deal
with voltage swings, the length and speed of the test program,
and the trigger frequency vs. timebase.

Voltage swings. Most systems have a white noise component

that has to be averaged out. This noise is greater when measuring
on insulation. The smaller the voltage swing to be seen, the more
averaging is necessary to filter out the noise and expose the
underlying signal. Averaging takes time, but we can minimize it
by planning large swings at the probe points. Although we can
look for a voltage swing through thick passivation, it is generally
impractical to try to look for a 50-mV difference in adjacent
memory cells at the diffusion level, for example. If we know ahead
of time that the points we want to probe have very small swings,
we can bring these signals closer to the die surface, where we can
capture a larger voltage swing.
Maximize the voltage swings at all probe points.

Test program length and speed. The rate of waveform acqui-

sition is strictly controlled by the frequency of the synchroniza-
tion signal provided to the e-beam probe system. A trigger that
occurs often allows the e-beam to pass over the probe point many
more times per second and therefore build up waveforms more
quickly. When a test program is running, it generates a synchro-
nization pulse once per complete test cycle, typically at the
beginning of the cycle. Thus, the longer the test program, the

amm3 1989 45
 ELECTRON-BEAMPROBING

slower the trigger and hence the longer the time to acquire
Without adequate waveforms.
forethought, we can The obvious solution is to use shorter test programs for e-beam
diagnostic sessions. However, this is difficult in real life once a
easily make test test program has been designed and debugged and has been on
the production floor for some time. The time to think about this
pograms so large problem is when the original test program is designed. The whole
that their slow test strategy has to be rethought if e-beam diagnostics are to be
an integral part of getting the device to market. Without adequate
trigger rate makes forethought, we can easily make test programs so large that their
slow trigger rate makes them unsuitable for e-beam systems.
them unsuitablefor These design considerations should become less critical as more
e-beam systems. designs incorporate scan-path or other design-for-test features
that reduce the number of vectors needed to initialize a device to
a desired state.
Incorporate limitations imposed by e-beamprobing into test
strategies from inception.

Trigger frequency vs. timebase. The smaller the time window

used to view the waveforms for a given trigger frequency, the
larger the ratio between the e-beam scope's timebase and the
trigger period. Most systems cannot exceed a ratio of approxi-
mately 1: 10,000.Beyond this ratio, the integration electronics in
the system that build u p the waveforms can no longer hold the
tiny amount of charge generated by the detector. The result is
that waveforms fade away before they can be built up. Thus, we
may not be able to view a waveform in a 1 0-ns window if the trigger
period is 1 ms at 1 kHz. In addition, this ratio depends on the
brightness of the electron source, so systems with high brightness
guns will have larger ratios.
Keep the target e-beam system's timebase-to-triggerratio (or
duty-cycle) limit in mind when designing test programs.

PACKAGING
Guidelines for packaging concern whether to use cavity-up or
cavity-down packaging and how to control heat dissipation and
temperature.

Cavity-up vs. cavity-down. The latest change in the design of

e-beam probe stations is to invert the column and have the beam
travel u p towards the device, while providing stimulus access to
the device from above through the specimen chamber lid. This
approach vastly simplifies the set-up required for devices in DIPS,
PGAs, and other packages, where pins point one way and the die
faces the other way. What is good for cavity-up devices, however,
makes life difficult for cavity-down devices such a s cavity-down
PGAs and inverted QFPs. Thus, if a part destined for a n e-beam
probe station is to be mass-produced in a n inverted-cavity pack-
age, we need to mix the packaging between cavity-up and cavity-
down.
Package some dice in cavity-up equivalent packages for
easy mounting.

46 IEEE DESIGN & TEST OF COMPUTERS

 Heat dissipation/temperature control. Heat dissipation be- The latest
comes a severe problem in a vacuum, especially with ECL tech-
nologies. We must plan how to shunt heat away from the device time-saving
through conduction, either into a heat reservoir such as a large
aluminum block, or into coolant fluid pumped past the device. d e v e l ~ m e nin
t
An example of a coolant plan is to place a hollow metal jacket that
contains forced cold air around the device. Temperature control
e-beam probing is to
is a difficult problem but not insurmountable, since some e-beam link the
probers now have options that take care of the problem. Certain
package types are more efficient at conducting heat away from uoltagecontrast
the die. Ceramics are better than plastics, for example, and
inverted PGAs with heat-sink mounts are better than cavity-up image with the
PGAs . layout database P o m
Use packages that can be easily cooled in the target e-beam
system whenever possible. the design
WOrkStatiOn.
LINKING WITH CAD /CAE DATABASES
The latest time-saving development in e-beam probing is to link
the voltage-contrast image with the layout database from the
design workstation. This link enables u s to control movement
around the device from the layout display. The advantage is that
the layout display has colors and symbols that aid in locating nets
and devices in the physical device. Another link from the layout
to either the textual netlist or the schematic (logic diagram) can
further cut down on navigation time. We can then select nets and
devices, locating them by name or logic symbol. Most engineers
find it easier to read a schematic, netlist, or layout than a
voltage-contrast image.
To accomplish this link, we need to properly mark the device
parts to orient them to the layout display and we need to archive
certain design information for retrieval during debugging or
failure analysis.

Alignment marks. Alignment marks and orientation symbols

are especially useful for passivated parts. Unpowered passivated
parts typically show no distinguishing marks that can help orient
the image relative to the layout display. Putting an exposed logo
or special mark in one corner will do.
We can link the voltage-contrast image and the layout image by
selecting and aligning three features that exist on both images.
These could be the inner corner of three of the four corner bond
pads, for example, or other exposed alignment marks. We use
three points instead of one or two to take care of differences in
position, scale, and orientation.
Using arbitrary features on the die will lead to alignment and
positioning errors. The 2-pm line the layout display shows may
end up to be a 1.7-pm line, either on purpose because of process
scaling or through the manufacturer’s inability to make what is
intended. Using comers of bond pads and aligning the two images
at low magnification is another way to introduce errors in the
image lock. We can avoid these errors by laying down fine
alignment marks, preferably labeled crosshairs.

JUNE 1989 47
 ELECTRON-BEAM PROBZNG
FURTHER READING
The following resources are good
general reading on electron-beam
probing. Additional sources include
the proceedings of the International
Symposium on Testing and Failure
Analysis also offer good information
on e-beam probing. Contact ASM
International, Metals Park, OH
44073: (216)338-5151. Also V ~ U -
able sources are the proceedings of
the International Symposium on
Electron, Ion. and Photon Beams,
which are published by the Ameri-
can Institute of Physics, 335 E.
45th St., New York, NY 10017.Fi-
nally, there are the Critical Reviews
of Optical Science and Technology
published by the International So-
ciety for Optical Engineering, PO
10, Bellingham, WA 98227-0010;
(206)676-3290.
Brust, H., et al., “Logic-StateTracing:
Electron Beam Testing by Correlation,”
Microelectronic Engineering, Vol. 3,
1985, p. 191.
Feuerbaum, H., “ElectronBeam Testing:
Methods and Applications,” Scanning,
Vol. 5. 1983. p. 14.
Fujioka, H., et al.. “Electron Beam
Blanking Systems,” Scanning. Vol. 5,
1983. p. 3.
May, T., et al.. “Dynamic Fault Imaging
of VLSI Random Logic Devices,” Proc.
Int’l Reliability Physics Symp., 1984, p.
95.
Menzel. E., et al., “Secondary Electron
Detection Systems for Quantitative
Voltage Measurements,” Scanning, Vol.
5, 1983,p. 151.
Menzel, E., et al., “Electron Beam Prob-
ing of Integrated Circuits,” J. Solid State
Technology, Dec. 1985. p. 63.
Reimer. L.. Scanning Electron Micros-
copy, Springer Series in Optical Sci-
ences, Vol. 45, P. Hawkes, ed.,
Springer-Verlag.New York, 1988.
Richardson, N., “E-Beam Probing for
VLSI Circuit Debug,” VLSI Systems De-
sign, Aug. 1987, p. 24.
, Stivers, A., et al.. “Fault Contrast: A New
Voltage Contrast VLSI Diagnosis Tech-
nique,” Proc. Int’l Reliability Physics
Symp., 1986, p. 109.
~ Willis. K., et al., “Electron-BeamTesting
and Its Applications to VLSI Technol-
ogy,’’ Characterization of Very High
Speed SemiconductorDevices and Inte-
~ grated Circuits, R. Jain. ed.. Critical
Reviews of Optical Science and Tech-
nology, Vol. 795, SPIE, Bellingham.
Wash., 1987. p. 166.
48
Lay down exposed orientation and alignment marks that are
of known size.
Design data to archive. The design data files for archiving will
vary from system to system but will typically be the
full netlist, such as the SPICE file
full schematic file, such as the EDIF file
full layout file, such as the Calma file
label file for layout if labels are not in layout file
layer coloring information for layout file
process-technology description
test vectors or simulation data, such as Zycad files
The software uses the process-technology description to recog-
nize devices and nets in the layout. I t can then extract a netlist
from the layout that it can compare with the simulation netlist
or schematic file. This comparison is a precursor to establishing
the links across different domains of information, such as from
the signal name in the schematic to the polygons representing
the net in the layout to the physical coordinates in the voltage-
contrast image. We can then use the simulation data to compare
actual vs. expected waveforms. We need the layer coloring infor-
mation to display the mask layers in the layout.
Archive the necessary information [inpreceding bulleted list) during
the design process so it can be used later for guided probing.
T
he guidelines described here can be implemented during
the design and manufacturing stages. By following these
guidelines, engineers are assured of being able to place
new devices in a n electron-beam probe station for effi-
cient diagnosis during design debug, product engineering, and
failure analysis. Consequently, the product may get to market
more quickly and be more reliable.
Compared with laser probes, e-beam probes offer more advan-
tages. Laser probes provide good temporal resolution and very
high measurement bandwidth with good sensitivity, but they
have much poorer spatial resolution than e-beam probes. Laser
probers may well be excellent tools in the future, but there are
many obstacles yet to overcome before these techniques become
practical.
Perhaps, the answer is to take the best of both techniques,
combining the high temporal resolution of the laser beam with
the high spatial resolution of the electron beam. We would need
much more research to develop such a system, however. To meet
today’s needs, as well as those in the near future, e-beam probers
are the best choice. @D
ACKNOWLEDGMENTS
I thank Andrew Muray who worked with me on the original draft of this article.
The idea on asymmetric layout comes from Chris Talbot. Thanks also to Steve
Harari, Neil Richardson, Jeanie Lawrence, and Eileen Algaze who proofread earlier
drafts of this article.
IEEE DESIGN & TEST OF COMPUTERS
REFERENCES
1. P. May , et al..“PhotoelectronScanning Electron Microscope (PSEM)for High
Speed Noncontact Testing,” Characterization of Very High Speed Semicon-
ductor Devices and Integrated Circuits, 795, 201, 1987.
2. E. Plies, et al., ‘TestingDifferent Methods of Deconvolution for Electron Beam
Measured Waveforms,” 1st European Conference on Electron and Optical
Beam Testing of Integrated Circuits, 47, 1987.
3. J. L. de Song, et al., “Effects of Local Fields on Electron Beam Voltage
Measurement Accuracy,” Scanning Electron Micros. , 111, 933, 1986.

in the ATE Division, where he started as a software engineer working on test-gen-

eration software and software for the IDS 5000 electron-beam probe station. He
then became an applications engineer working on the IDS product line.
He holds a BS in computer science and an M S in electrical engineering and
computer science, both from the Massachusetts Institute of Technology. He is a
member of the IEEE. His address is Schlumberger Technologies ATE, 1601
Technology Dr., San Jose. CA 95 110-1397.

The European Design Automation Conference

Glasgow, Scotland 12-15 March 1990

The European Design Automation Conferencewill be held in Glasgow,

Scotland from 12 - 15March 1990.
Run by EDAC, a non profit association, the conference is intended for De-
sign Automation professionals and is co-sponsored by CAVE and UKDA
in association with IEEE/DATC, ACM/SIGDA, IEE and other European
CALL technical societies.
The conferencewill cover all areas of the design process of electronic cir-
FOR cuits and systems from concept to manufacture and includes CAD and
DA tools for analog, digital, VLSI, microwave and high-speed electronics.

PAPERS The deadline for receipt of papers is 4 September and intending authors
should contact the Secretariat for instructions for submission.
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EDAC 90
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