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    Catalin Badea
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    1. The document outlines the 14-week timetable for the first semester of Project 1, which involves the design, simulation, and layout of electronic devices and circuits. 2. Key activities include design presentations, setting up the CAD environment, schematic design, analytical calculations, simulation, layout design, tape-out, verification, and preparation for manufacturing. 3. Contact information is provided for instructors overseeing circuit design issues and CAD issues.

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    1. The document outlines the 14-week timetable for the first semester of Project 1, which involves the design, simulation, and layout of electronic devices and circuits. 2. Key activities include design presentations, setting up the CAD environment, schematic design, analytical calculations, simulation, layout design, tape-out, verification, and preparation for manufacturing. 3. Contact information is provided for instructors overseeing circuit design issues and CAD issues.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    2 views2 pages

    PR1 Schedule

    Uploaded by

    Catalin Badea
    1. The document outlines the 14-week timetable for the first semester of Project 1, which involves the design, simulation, and layout of electronic devices and circuits. 2. Key activities include design presentations, setting up the CAD environment, schematic design, analytical calculations, simulation, layout design, tape-out, verification, and preparation for manufacturing. 3. Contact information is provided for instructors overseeing circuit design issues and CAD issues.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    of 2

    Project 1 –Electronic Devices and Circuits Timetable / academic year 2023-2024

    Timetable for the first semester – Project 1 - design, simulation and layout
    Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14
    Theme Design Design Design Design Design Evaluation I - Schematic - Schematic TAPE-OUT - Layout - Layout - Layout - Layout
    presentation (circuit (circuit (circuit (circuit (circuit - analytical redesign redesign -SMT version: verification verification verification verification
    design, design,sche design,sche design,sche design,sche calculations - layout design - layout design - final schematic -penalization -penalization -penalization -penalization
    schematic, matic, matic, matic, matic, - simulation -preparing for -preparing for -preparing for -preparing for
    - layout
    setting CAD setting CAD setting CAD setting CAD setting CAD manufacturing manufacturing manufacturing manufacturing
    environment environmen environment environment environment - Gerber files for
    -BOM SMT -BOM SMT
    for the t for the for the for the for the SMT -BOM SMT -BOM SMT -BOM THT -BOM THT
    given given given given given - BOM -BOM THT -BOM THT
    technology) technology) technology) technology) technology) – mark 8-10
    Evaluation Evaluation
    - THT version:
    - final schematic
    - mounting map
    -BOM
    – mark: 5-7
    Points Maximum 80-100 pts SMT Final grade Final grade
    50 points 50-70 pts THT
    0-49pts FAIL

    Contacts:
    Dr. Laurentiu Teodorescu, email: laurentiu.teodorescu@upb.ro (A411a) for the circuit design issues (circuit design, schematic, simulations, analytical calculations, Schematic redesign, mounting map for THT)

    Dr. Cristina Marghescu, email: cristina.marghescu@cetti.ro (B305a) for the CAD issues (setting CAD environment for the given technology, layout design, Gerber files for SMT,BOM SMT, BOM THT,layout verification, penalization, preparing for manufacturing)

    Timetable for the second semester – Project 1 - practical implementation and commissioning
    Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14
    Equipping Equipping
    Testing and Testing and Testing and
    troubleshooting troubleshooting troubleshooting
    Evaluation Evaluation Evaluation Evaluation Evaluation Supplementary evaluation for students
    +Presentation +Presentation +Presentation +Presentation +Presentation
    who dropped the exam in the first
    stage
    Evaluation Pass/Fail Pass/Fail Pass/Fail Pass/Fail Pass/Fail Pass Pass Pass Pass Pass/Fail

    Contacts:
    Equipping- Dr. Cristina Marghescu, email: cristina.marghescu@cetti.ro (B305a)
    Testing and troubleshooting – Dr. Laurentiu Teodorescu, email: laurentiu.teodorescu@upb.ro (A411a) for the circuit design issues, Dr. Cristina Marghescu, email: cristina.marghescu@cetti.ro for the CAD (layout/board) issues (B305a)

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