Part - 5

Processor Buses and Memory

 Processor Buses
What is a bus?
The address line, data line and control line together to
memory from CPU and peripherals is called bus
What are the different types of buses?
On-chip buses
1. Program bus
2. Data bus
3. Peripheral bus
Off-chip buses
1. External bus

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Processor Buses cont…
On-chip buses
Program bus – PAB & PDB
• The bus connected between CPU and on-chip
program memory
• All processor architectures have only one program
bus because there is only one PC
Data bus – DAB & DDB
• The bus connected between CPU and on-chip data
memory
• In all DSP architectures, only the number on-chip
data buses will increase.
• Harvard architecture – 1
• Modified Harvard architecture – 2 DAB and 1DDB
• Advanced Harvard architecture – 2 read buses & 1 write bus

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Processor Buses cont…
On-chip buses
Peripheral bus
• The bus connected between on-chip peripheral, CPU
and on-chip memory
• Peripherals such as on-chip DMA controller, EMIF
etc have individual peripheral buses
Off-chip buses
External bus
• The bus connected between on-chip memory and
CPU to external off-chip devices.
• All processor architectures have only one external
bus

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Processor Buses cont…
Harvard architecture - `C5X – 1 PB & 1 DB

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Processor Buses cont…
Modified Harvard architecture - `C3X – 1 PB & 2 DAB, 1 DDB

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Processor Buses cont…
Advance Modified Harvard architecture - `C54X – 1 PB & 3 DB
2 read buses & one write bus

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Processor Buses cont…
`C55X – 1 PB & 5 DB 3 read buses & 2 write buses
Three Data-read data buses-BDB, CDB & DDB (each of 16 – bits)

Three Data-read address buses-BAB, CAB & DAB (each of 23 – bits)

Program-read data bus-PDB (32 – bits)

Program-read address bus-PAB (24 – bits)

CPU

Instruction Program Address Data

data computation
Buffer unit Flow unit unit
flow unit
(I-unit) (P-unit) (A-unit) (D-unit)

Two Data-write data buses- EDB & FDB (each of 16 – bits)

Two Data-write address buses- EAB & FAB (each of 23 – bits)

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory
Classification of memory
On-chip memory
Off-chip memory
What are the different types of memories?
Read only memory (ROM)
EPROM, EEPROM, Flash etc
Random Access Memory (RAM)
SARAM – Single access RAM
DARAM – Dual access RAM

Off-chip memory is only SARAM

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15
 On-chip Memory details in `C54X
Memory `C541 `C542 & `C545 & `C548 `C549 `C5402 `C5410 `C5420
type `C543 `C546

ROM 28K 2K 48K 2K 16K 4K 16K 0

Program 20K 2K 32K 2K 0 0 0 0

ROM

Program / 8K 0 16K 0 16K 4K 16K 0

Data
ROM

SARAM 0 0 0 24K 24K 0 56K 128K

DARAM 5K 10K 6K 8K 8K 16K 8K 32K

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory space
➢ Memory is organized into three individually selectable spaces:
Program, Data, and I/O.
➢ Within any of these spaces, RAM, ROM, EPROM, EEPROM, or
memory-mapped peripherals can reside either on-chip or
off-chip.
➢ Together, these three spaces provide a total address range of
192K words
Use of Memory spaces
▪ Program memory space
Contains the instructions to execute, as well as tables used in
execution (e.g. coefficient tables).
▪ Data-memory space
Stores data used by instructions.
▪ I/O memory space
Interfaces to external memory-mapped peripherals and can also
serve as extra data storage space
Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15
 Memory Mapping
➢ DSPs have different on-chip memory resources like SARAM,
DARAM and ROM
➢ These on-chip memories are mapped to Program space, Data
space using three bits (MP/MC, DROM and OVLY) in status and
control register.
MP/MC bit
▪ Set to 0 - the on-chip ROM is mapped into program space.
▪ Set to 1 - the on-chip ROM is not mapped into program space.
DROM bit
▪ Set to 0 - the on-chip ROM is not mapped into data space.
▪ Set to 1 - a part of the on-chip ROM is mapped into data
space.
▪ The use of DROM is independent of the state of MP/MC.
OVLY bit
▪ Set to 0 - the on-chip RAMs are mapped only into data space.
▪ Set to 1 - the on-chip RAMs are mapped into program and
data space.
Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15
 Memory Mapping cont…
Memory mapping for `C541 - 28 K words ROM, 5K words DARAM
ROM 28 K words – 20K Program ROM, 8 K Program/Data ROM selected by
DROM bit
DARAM 5 K words – 5K for data space or 5 K for both Program and Data space
selected by OVLY bit
64K x16 64K x16
Program Memory Data Memory space
64K x16 space
Memory space 0000h 0000h
0000h
5Kx16 on-chip
DARAM
13FFh 13FFh
13FFh 1400h 1400h
1400h
31Kx 16
External memory
(SARAM)

8FFFh 8FFFh
8FFFh
9000h 9000h 9000h
28Kx16 on-chip
ROM
FFFFh FFFFh FFFFh

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory Mapping cont…
Microprocessor Mode of operation MP/MC = 1
On-chip ROM neither in PM space or DM space (DROM = 0)
On-chip DARAM for DM space (OVLY = 0)

64K x16 64K x16

64K x16 Program Memory Data Memory space
Memory space space
0000h 0000h 0000h 5Kx16 on-chip
5Kx16 on-chip DARAM
DARAM 0000h–005Fh MMREGS
0060h–007Fh Scratch-pad
13FFh 13FFh 13FFh 0080h–13FFh On-chip DARAM
1400h 1400h 1400h
31Kx 16 59Kx 16
64K x 16
External memory External memory
External memory
(SARAM) (SARAM)
(SARAM)

8FFFh 8FFFh DFFFh

9000h
9000h E000h
28Kx16 on-chip
ROM
FFFFh
FFFFh FFFFh

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory Mapping cont…
Microprocessor Mode of operation MP/MC = 1
On-chip ROM neither in PM space or DM space (DROM = 1)
On-chip DARAM for DM space (OVLY = 0)

64K x16 64K x16

64K x16 Program Memory Data Memory space
Memory space space
0000h 0000h 0000h 5Kx16 on-chip
5Kx16 on-chip DARAM
DARAM 0000h–005Fh MMREGS
0060h–007Fh Scratch-pad
13FFh 13FFh 13FFh 0080h–13FFh On-chip DARAM
1400h 1400h 1400h
31Kx 16 51Kx 16
64 K x 16
External memory External memory
External memory
(SARAM) (SARAM)
(SARAM)

8FFFh 8FFFh DFFFh

9000h
9000h E000h
28Kx16 on-chip 8Kx16 on-chip
ROM ROM
FF00h–FFFFh - Reserved
FFFFh
FFFFh FFFFh

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory Mapping cont…
Microprocessor Mode of operation MP/MC = 1
On-chip ROM neither in PM space or DM space (DROM = 1)
On-chip DARAM for DM space (OVLY =1)

64K x16 64K x16

64K x16 Program Memory Data Memory space
Memory space space
0000h 0000h 5Kx16 on-chip 0000h 5Kx16 on-chip
5Kx16 on-chip DARAM DARAM
DARAM 0000h–007Fh Reserved 0000h–005Fh MMREGS
0080h–13FFh On-chip DARAM 0060h–007Fh Scratch-pad
13FFh 13FFh 13FFh 0080h–13FFh On-chip DARAM
1400h 1400h 1400h
31Kx 16 51Kx 16
59Kx 16
External memory External memory
External memory
(SARAM) (SARAM)
(SARAM)

8FFFh 8FFFh DFFFh

9000h
9000h E000h
28Kx16 on-chip
8Kx16 on-chip
ROM
ROM
FFFFh FF00h–FFFFh - Reserved
FFFFh FFFFh

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory Mapping cont…
Microcomputer Mode of operation MP/MC = 0
On-chip ROM neither in PM space or DM space (DROM = 0)
On-chip DARAM for DM space (OVLY =0)

64K x16 64K x16

64K x16 Program Memory Data Memory space
Memory space space
0000h 0000h 0000h 5Kx16 on-chip
5Kx16 on-chip DARAM
DARAM 0000h–005Fh MMREGS
0060h–007Fh Scratch-pad
13FFh 13FFh 13FFh 0080h–13FFh On-chip DARAM
1400h 1400h 1400h
31Kx 16 36K x 16 59Kx 16
External memory External memory External memory
(SARAM) (SARAM) (SARAM)

8FFFh 8FFFh DFFFh

9000h
9000h 28Kx16 on-chip E000h
28Kx16 on-chip
ROM
ROM
FF00h–FF80h BIST
FFFFh FF80h–FFFFh Interrupt
FFFFh Vectors FFFFh

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory Mapping cont…
Microcomputer Mode of operation MP/MC = 0
On-chip ROM neither in PM space or DM space (DROM = 1)
On-chip DARAM for DM space (OVLY =0)

64K x16 64K x16

64K x16 Program Memory Data Memory space
Memory space space
0000h 0000h 0000h 5Kx16 on-chip
5Kx16 on-chip DARAM
DARAM 0000h–005Fh MMREGS
0060h–007Fh Scratch-pad
13FFh 13FFh 13FFh 0080h–13FFh On-chip DARAM
1400h 1400h 1400h
31Kx 16 36K x 16 51Kx 16
External memory External memory External memory
(SARAM) (SARAM) (SARAM)

8FFFh 8FFFh DFFFh

9000h
9000h 28Kx16 on-chip E000h
28Kx16 on-chip 8Kx16 on-chip
ROM
ROM ROM
FF00h–FF80h BIST
FF80h–FFFFh Interrupt FF00h–FFFFh - Reserved
FFFFh
FFFFh Vectors FFFFh

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Memory Mapping cont…
Microcomputer Mode of operation MP/MC = 0
On-chip ROM neither in PM space or DM space (DROM = 1)
On-chip DARAM for DM space (OVLY =1)

64K x16 64K x16

64K x16 Program Memory Data Memory space
Memory space space
0000h 0000h 0000h 5Kx16 on-chip
5Kx16 on-chip 5Kx16 on-chip DARAM
DARAM DARAM 0000h–005Fh MMREGS
0000h–007Fh Reserved 0060h–007Fh Scratch-pad
13FFh 13FFh 0080h–13FFh On-chip DARAM 13FFh 0080h–13FFh On-chip DARAM
1400h 1400h 1400h
31Kx 16 31K x 16 51Kx 16
External memory External memory External memory
(SARAM) (SARAM) (SARAM)

8FFFh 8FFFh DFFFh

9000h
9000h 28Kx16 on-chip E000h
28Kx16 on-chip 8Kx16 on-chip
ROM
ROM ROM
FF00h–FF80h BIST
FF80h–FFFFh Interrupt FF00h–FFFFh - Reserved
FFFFh
FFFFh Vectors FFFFh

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

 Extended Program memory space (only in`C54X)
The Program memory space can be extended to 23 address lines
Maximum Program memory space – 8 M words ( 8M x 16 bits)
Processors having extended PM space
`C548, `C549, `C5402, `C5410 and `C5420
`C5420 – 18 address lines
`C5402 – 20 address lines
`C548, `C549 and `C5410 - 23 address lines

Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15

End of Part-5